Chip full life cycle performance monitoring and evaluation method and system based on big data

Abstract

This invention relates to the field of chip performance monitoring technology, and discloses a method for monitoring and evaluating the performance of chips throughout their entire lifecycle based on big data. This method first extracts key physical characteristics of each bare die at the manufacturing stage, generates individual chip quality factors, and writes them into a one-time programmable memory area. Then, at the application stage, it collects the junction temperature of each layer in real time, calculates the vertical temperature gradient vector and local absolute temperature, and constructs a thermo-coupled instantaneous interface mechanical damage rate model based on the quality factors to quantify the instantaneous interface mechanical damage rate. Furthermore, it introduces a business weight coefficient to couple electrical wear with cumulative thermo-mechanical fatigue damage, calculating the chip's remaining health. Finally, based on the health warning threshold, it executes a vertical wear balancing strategy to migrate the data of damaged layers to a safe level. This invention solves the problem that traditional chip performance monitoring cannot detect the risk of microscopic thermal mismatch within the stacked structure, and avoids sudden physical failures of the chip through proactive physical load redistribution.

Description

Technical Field

[0001] This invention relates to the field of chip performance monitoring technology, specifically to a method and system for monitoring and evaluating chip performance throughout its entire lifecycle based on big data. Background Technology

[0002] As Moore's Law slows down, the semiconductor industry has widely adopted System-in-Package (SiP) and 3D-IC technology. This involves high-density vertical integration of dies of different materials, such as controller chips and memory chips (DRAM / NAND), to break through the performance limits of single chips. These chips contain thousands of microbumps and multiple layers of underfill adhesive, forming a complex interface between heterogeneous materials, which is crucial for ensuring the integrity of the chip's physical structure.

[0003] Existing monitoring technologies for such chips primarily focus on electrical performance and macroscopic thermal management. For example, the common SMART technology estimates memory lifespan by counting the number of erase and write cycles; or it uses a temperature sensor placed on the chip surface to monitor the average temperature, triggering frequency reduction protection when the temperature exceeds an absolute threshold. Some advanced solutions attempt to indirectly infer the chip's aging level by monitoring the power consumption curve of the entire chip.

[0004] However, the aforementioned existing technologies have some shortcomings in addressing the interlayer thermomechanical failure problem unique to stacked structures. Specifically, due to the significant differences in the thermal expansion coefficients of different layer materials, when a vertical temperature gradient exists within the chip, enormous shear stress is generated at the interlayer interfaces. Existing average temperature monitoring masks localized micro-temperature gradients and cannot detect the risk of internal mechanical tearing caused by uneven thermal expansion and contraction. Especially under conditions of low temperature difference but high absolute temperature, or high-frequency thermal shock, existing electrical or average temperature models cannot quantify the fatigue accumulation at the interlayer interfaces, leading to sudden physical failures of the chip often occurring despite normal electrical function due to internal interlayer delamination or bump fracture. Therefore, there is an urgent need for chip lifecycle performance monitoring and evaluation methods and systems based on big data to solve these problems. Summary of the Invention

[0005] To address the problems in related technologies, this invention provides a big data-based method for monitoring and evaluating the performance of chips throughout their entire lifecycle, thereby overcoming the aforementioned technical problems in existing related technologies.

[0006] To solve the aforementioned technical problem, the present invention is achieved through the following technical solution: In a first aspect, embodiments of the present invention provide a chip lifecycle performance monitoring and evaluation method based on big data, specifically including: during the wafer testing and packaging testing stages, extracting key physical characteristic data of each bare die of the chip, establishing a multi-factor weighted evaluation model, normalizing the key physical characteristic data into chip-specific quality factors, and writing the chip-specific quality factors into the chip's one-time programmable memory area; during chip operation, collecting real-time junction temperature data of each layer in the stacked structure, calculating the vertical temperature gradient vector between adjacent layers of the chip and the local absolute temperature of the interface between adjacent layers; based on the principles of solid mechanics and the Arrhenius equation, combined with the chip-specific quality factors... A quality factor is used to construct a thermo-mechanically coupled instantaneous interface mechanical damage rate model, and the instantaneous interface damage rate is calculated using the vertical temperature gradient and local absolute temperature. A business importance weighting coefficient is introduced to calculate the electrical wear term characterizing read / write wear, and the cumulative thermo-mechanical fatigue damage term is calculated based on the instantaneous interface damage rate. The remaining health of the chip is calculated using a cumulative health assessment model. A health warning threshold is set; when the remaining health of the chip is lower than the health warning threshold, a vertical wear leveling strategy is executed to migrate the data of the damaged layer to the safe level and perform downgrading processing. The key physical characteristic data includes wafer location characteristics, leakage current characteristics, and wire bonding strength characteristics.

[0007] As a preferred embodiment of the chip lifecycle performance monitoring and evaluation method based on big data described in this invention, the expression of the multi-factor weighted evaluation model is as follows: ; In the formula, For individual physical factors of the chip, As a standard physical fitness baseline, For wafer position features, This represents the average leakage current of the wafer. The average bond pull force of the wafer. Leakage current characteristics Characteristics of wire bonding strength. Risk coefficient for edge locations This is the leakage current weighting coefficient. This is the mechanical strength weighting coefficient. This is a function that maximizes the value.

[0008] As a preferred embodiment of the chip lifecycle performance monitoring and evaluation method based on big data described in this invention, the formula for calculating the vertical temperature gradient vector is: ; In the formula, This represents the vertical temperature gradient vector between adjacent layers of the chip. for Time of the first Real-time junction temperature of the chip in the current analysis layer. for Time and the The next layer chip that is vertically adjacent to the next layer chip (i.e., Real-time junction temperature of the layer. This refers to the physical layer spacing between two adjacent chip layers.

[0009] As a preferred embodiment of the chip lifecycle performance monitoring and evaluation method based on big data described in this invention, the formula for calculating the local absolute temperature is as follows: ; In the formula, This represents the local absolute temperature at the interface between adjacent layers of the chip.

[0010] As a preferred embodiment of the chip lifecycle performance monitoring and evaluation method based on big data described in this invention, the expression for the instantaneous interface mechanical damage rate model is as follows: ; In the formula, for Instantaneous interface damage rate at any given moment For effective length of action, This represents the absolute difference in the coefficients of thermal expansion between the two layers of material. The fatigue ductility index, The frequency factor is constant. For fatigue thermal sensitivity, is the Boltzmann constant.

[0011] As a preferred embodiment of the chip lifecycle performance monitoring and evaluation method based on big data described in this invention, the expression for the electrical wear term is: ; In the formula, for Electrical wear and tear items at all times The number of stacking layers, For the first The current erase / write / cycle count of the layer. To design rated life, For importance weights.

[0012] As a preferred embodiment of the chip lifecycle performance monitoring and evaluation method based on big data described in this invention, the expression for the cumulative thermomechanical fatigue damage term is: ; In the formula, For a moment Cumulative thermomechanical fatigue damage term, This is the normalization coefficient for mechanical damage.

[0013] As a preferred embodiment of the chip lifecycle performance monitoring and evaluation method based on big data described in this invention, the expression of the cumulative health assessment model is as follows: ; In the formula, for The remaining health status of the time chip. This indicates the remaining health of the chip in its initial perfect state.

[0014] As a preferred embodiment of the chip lifecycle performance monitoring and evaluation method based on big data described in this invention, the vertical wear leveling strategy includes: the system forcibly stopping write operations on chip layers whose health has dropped to a dangerous range, migrating data hotspots to chip layers with better health or lower temperatures, and marking the original damaged layer as a derated usage area used only for storing cold data.

[0015] Secondly, embodiments of the present invention provide a system for chip lifecycle performance monitoring and evaluation based on big data, comprising: a manufacturing-end data extraction and feature implantation module, used to extract key physical feature data of each bare die of the chip during the wafer testing and packaging testing stages, establish a multi-factor weighted evaluation model, normalize the key physical feature data into chip-specific quality factors, and write the chip-specific quality factors into the chip's one-time programmable memory area; an application-end interlayer micro-area monitoring module, used to collect real-time junction temperature data of each layer in the stacked structure during chip operation, calculate the vertical temperature gradient between adjacent layers and the local absolute temperature of the interface between adjacent layers; and an instantaneous interface mechanical damage rate calculation module, used for... Based on the principles of solid mechanics and the Arrhenius equation, combined with the chip's individual physical properties, a thermo-mechanically coupled instantaneous interface mechanical damage rate model is constructed, and the instantaneous interface damage rate is calculated using the vertical temperature gradient and local absolute temperature. The cumulative health assessment module is used to introduce business importance weight coefficients, calculate the electrical wear term representing read / write wear, and calculate the cumulative thermo-mechanical fatigue damage term based on the instantaneous interface damage rate. The remaining health of the chip is calculated through the cumulative health assessment model. The vertical wear leveling control module is used to set a health warning threshold. When the remaining health is lower than the health warning threshold, the vertical wear leveling strategy is executed to migrate the data of the damaged layer to the security level and perform degradation processing.

[0016] The present invention has the following beneficial effects: 1. This invention extracts wafer location features, static leakage current features, and wire bonding strength features of chips during wafer testing and packaging testing. By constructing manufacturing characteristic factors that reflect individual physical quality and embedding them into the chip, the theoretical lifetime model can be corrected using these manufacturing characteristic factors during application evaluation. This solves the data gap problem caused by the failure to transmit key process parameters from the manufacturing end to the application end, making the health assessment of edge dies or chips with minor process defects more consistent with objective physical facts.

[0017] 2. This invention abandons the traditional surface average temperature monitoring mode. By calculating the vertical temperature gradient and local absolute temperature between adjacent layers and combining the fatigue ductility index of the material, a thermo-mechanically coupled instantaneous interface mechanical damage rate model is established. This model senses and quantifies the thermal mismatch shear stress caused by the micro temperature difference gradient and the catalytic amplification effect of the high temperature environment on mechanical fatigue. This effectively detects physical hazards such as interlayer delamination and micro-bump fracture that cannot be detected when the electrical function is normal, thus making up for the shortcomings of single electrical read / write wear monitoring.

[0018] 3. This invention employs a variable frequency sampling strategy. When the temperature is stable, low-frequency sampling is used to save system resources. When the temperature change rate is drastic, high-frequency sampling is automatically switched to capture transient thermal shocks, ensuring accurate capture of extreme operating conditions that may cause damage even with low bus occupancy. Simultaneously, by constructing a cumulative health assessment model and introducing a business importance weighting coefficient, the electrical damage item representing read / write wear is quantitatively coupled with the thermomechanical fatigue damage item representing interlayer delamination risk. This outputs a visualized digital remaining health index, thereby achieving quantitative evaluation and performance monitoring of the chip from the data logic level to the physical structure level.

[0019] 4. This invention implements a vertical wear leveling strategy based on the remaining health status and early warning threshold. When the physical health status of a certain layer is detected to drop to a dangerous range, the system can proactively and forcibly stop the write operation of that layer, migrate the data hotspot to a safer layer with better physical condition or lower temperature, and downgrade the damaged layer to a cold data storage area. This helps to reduce the subsequent damage rate of high-risk areas, delay the complete failure of the chip, and improve the overall reliability and service life of the system.

[0020] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, the drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 The flowchart illustrates a chip lifecycle performance monitoring and evaluation method based on big data, as provided in Embodiment 1 of the present invention.

[0023] Figure 2 This is a schematic diagram of a chip lifecycle performance monitoring and evaluation system based on big data, provided in Embodiment 2 of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Example 1 Existing life monitoring methods mainly focus on electrical read / write wear. When faced with the unique physical reliability issues of stacked structures, data gaps often occur because key process parameters at the manufacturing end are not transmitted to the application end. Furthermore, the application end is limited to monitoring the macroscopic average temperature of the package surface and cannot detect the microscopic cyclic shear stress induced by material thermal mismatch inside the stack. This leads to the failure to detect hidden thermomechanical damage such as interlayer delamination and microbump fracture, posing a risk of sudden physical failure.

[0026] To solve the above technical problems, such as Figure 1 As shown, Embodiment 1 of the present invention provides a method for monitoring and evaluating the full lifecycle performance of chips based on big data. Specifically, Embodiment 1 takes an 8-layer stacked SiP memory chip used in industrial control as an example: this chip vertically integrates a main control chip (Layer 1) and multiple layers of NAND Flash chips (Layer 2-8). It is necessary to... It can operate for a long time under extreme temperature variations.

[0027] In the specific implementation of Example 1: First, during the wafer testing and packaging testing stages, key physical characteristic data of each bare die of the chip are extracted, a multi-factor weighted evaluation model is established, the key physical characteristic data is normalized into chip-specific quality factors, and the chip-specific quality factors are written into the chip's one-time programmable memory area. This method fills the gap in the application end's inability to obtain wafer-level raw data by quantifying the process discreteness at the manufacturing end into unified digital characteristics, enabling the subsequent evaluation model to identify and adapt to the individual differences in the chip's "inherent quality," avoiding misjudgment of defective individuals by the general model. Second, during chip operation, real-time junction temperature data of each layer in the stacked structure are collected, and the vertical temperature gradient vector between adjacent layers and the local absolute temperature of the interface between adjacent layers are calculated. This method breaks through the limitations of traditional surface average temperature monitoring, by capturing the vertical heat flow gradient and micro-region high temperature, locking the source of interlayer thermal stress shear and material chemical aging, solving the problem that the hidden danger of thermal mismatch inside the stacked structure cannot be detected. Then, based on the principles of solid mechanics and the Arrhenius equation, combined with the chip's individual quality factor, a thermo-mechanically coupled instantaneous interface mechanical damage rate model is constructed, and the instantaneous interface damage rate is calculated using the vertical temperature gradient and local absolute temperature. This method uses physical equations to calculate the thermo-mechanically coupled instantaneous interface mechanical damage rate, considering both the catalytic amplification effect of ambient temperature on material fatigue and dynamically correcting the theoretical model using the quality factor. This allows for real-time output of the microscopic physical damage rate consistent with the objective entity of the chip without the need for destructive testing. Next, a business importance weighting coefficient is introduced to calculate the electrical wear term characterizing read / write wear, and the cumulative thermo-mechanical fatigue damage term is calculated based on the instantaneous interface damage rate. The remaining health of the chip is then calculated using a cumulative health assessment model. This method quantitatively integrates the read / write lifetime consumption at the logic level with the structural fatigue accumulation at the physical level, and weights the impact of different dies on the business system, achieving a comprehensive digital quantitative assessment and performance monitoring of the chip from functional integrity to structural reliability. Finally, a health warning threshold is set. When the remaining health of the chip is lower than the health warning threshold, a vertical wear leveling strategy is executed to migrate the data of the damaged layer to the safe layer and perform degradation processing. This method blocks the vicious damage cycle of the weak layer interface by performing load migration and hotspot dissipation before the physical failure critical point, and maximizes the effective service life of the chip while ensuring data integrity.

[0028] Furthermore, to better illustrate the technical solution of Embodiment 1 of the present invention, a detailed description is provided of the chip lifecycle performance monitoring and evaluation method based on big data, specifically including the following: S1. Manufacturing data extraction and feature implantation, specifically including the following sub-steps: S11. First, during the wafer testing (CP) and packaging testing (FT) stages, the system extracts key physical characteristic data for each die, including wafer location characteristics. Leakage current characteristics and wire bonding strength characteristics .

[0029] Specifically, the wafer location features This indicates the physical coordinates of the die on the wafer. If it is located in the wafer edge region, it is marked. If it is located in the central area, then mark it. The leakage current characteristic The static leakage current value is obtained through IV curve testing; the wire bonding strength characteristics are... This refers to the lead pull force value measured by sampling during the wire bonding process.

[0030] S12. Based on statistical principles, the system establishes a multi-factor weighted evaluation model, normalizing the above three key physical characteristics into chip-based individual physical factors. The specific calculation steps are as follows: S121. Determine batch baseline value: The system calculates the average leakage current of the current batch of wafers. and average bond tension This serves as a reference baseline for standard physical condition.

[0031] S122. Define the deviation penalty function: apply a penalty weight to parameters that are worse than the benchmark value, and do not reward parameters that are better than the benchmark value, keeping the weight of 0, to ensure that the physical factors only reflect the risk increment. Construct the multi-factor weighted assessment model as follows: ; In the formula, This is the standard physical fitness baseline; The edge location risk coefficient is used to characterize the increased thermal sensitivity of edge wafers due to lattice defects; This is the leakage current weighting coefficient, which characterizes the direct contribution of leakage current to heat generation; This is the mechanical strength weighting coefficient, which characterizes the effect of bond strength on thermal stress fatigue. The function ensures that the leakage current is above average or the pull force is below average only when the leakage current is above average or the pull force is below average. That's when it will increase.

[0032] For example, in this embodiment 1, the risk coefficient of the edge location Leakage current weighting coefficient and mechanical strength weighting coefficient The method for determining it is as follows: First, the system retrieves data from the historical production database that has completed the entire lifecycle closure. Data on individual sample chips, such as chips manufactured within the past three years that have failed or been retired. Construct training set .in: For the first The manufacturing feature vector of a historical chip includes: whether it is an edge ( Standardized leakage current deviation () Standardized tensile deviation () ); For the first The true lifetime acceleration factor of a historical chip is defined as... , This refers to the mean time between failures (MTBF) of this batch of chips. For the first The actual failure time of each chip. If This indicates that the chip has a shorter lifespan than average, and its quality factor should be greater than 1.

[0033] Then, based on the chip's individual physical constitution factors Based on the formula structure, the following regression equation is established: ; In the formula, The term represents the random residual. This equation characterizes the reduction factor in the actual lifespan of a chip by fitting the deviation of manufacturing parameters.

[0034] Then, the coefficients are solved using the least squares method, and the regression equation is solved using the least squares method, with the objective function being the minimization of the sum of squared residuals. ; The optimal solution is obtained through matrix operations. : ; in, For the feature matrix of the training set, This indicates the matrix transpose.

[0035] Finally, a t-test was performed on the calculated coefficients: If a certain coefficient (such as...) If the p-value of the physical characteristic is greater than 0.05, it indicates that the physical characteristic is not statistically significantly correlated with lifespan decline. Therefore, the coefficient is set to 0, i.e., the characteristic is removed. If the P-value is less than 0.05, the calculated value is retained as the weight parameter fixed in the system.

[0036] Specifically, for example, in this embodiment 1, the system selects a sample size. The previous generation of SiP products was used for training. Data shows that chips located at the wafer edge have an average lifespan only that of the center chips. Life acceleration factor Therefore, the calculation is For every increase in leakage current Lifespan shortened by approximately ,Right now Increase by 1.0, therefore the calculation is... The bond pull force showed a weak correlation with early failure, but the pull force was below the mean. The risk increases significantly during regression calculations. Through the regression calculations of the aforementioned big data, this invention determines the parameters in the formula. .

[0037] S13, the calculated results The manufacturing characteristic factors are written into the one-time programmable memory area of ​​the SiP master control chip, forming a manufacturing characteristic factor that the chip carries throughout its life.

[0038] Specifically, for example: performing calculations on the 4th layer Flash die, assuming the die is located at the wafer edge, wafer position characteristics... Measured leakage current characteristics The average leakage current of the current batch of wafers Bond strength characteristics Average bond pull of the current batch of wafers There is no deviation. Then substitute it into the formula to calculate. This result quantifies the combined physical risks posed by the die's edge location and excessive leakage current.

[0039] In this embodiment 1, multi-dimensional manufacturing process parameters such as wafer location, leakage current, and bonding strength are normalized into individual chip quality factors. Furthermore, it is embedded in the chip's OTP region, enabling the cross-temporal and spatial transmission of manufacturing quality data to the application-side reliability model. This bridges the data gap between upstream and downstream sectors of the industry chain, allowing application-side monitoring systems to accurately perceive the inherent differences in the "congenital constitution" of individual chips by reading this factor without needing to access the wafer fab's original database; particularly regarding the aforementioned calculation results. For defective individuals, the system can use the calculation results to make targeted corrections to the theoretical damage rate in the subsequent instantaneous interface mechanical damage rate model, thereby avoiding reliability misjudgments caused by the traditional general model ignoring individual process fluctuations.

[0040] S2. Application-side inter-layer micro-area monitoring, specifically including the following sub-steps: S21. During chip operation, the main control chip calls the built-in temperature sensors in each layer of the stacked structure to collect real-time junction temperature data. To avoid high-frequency polling consuming internal bus bandwidth, this embodiment adopts a variable-frequency sampling strategy: that is, by default, it polls at a low frequency (e.g., 0.1Hz); when the temperature change rate of any layer exceeds a threshold (e.g., ... When the transient thermal shock occurs, it automatically switches to a high-frequency sampling mode (such as 10Hz) to accurately capture the transient thermal shock.

[0041] S22. The system calculates the vertical temperature gradient vector between adjacent layers. Used to characterize heat flux density and thermal resistance properties: ; In the formula, for Time of the first Real-time junction temperature of the chip in the current analysis layer; for Time and the The next layer chip that is vertically adjacent to the next layer chip (i.e., Real-time junction temperature of the layer; The physical layer spacing between two adjacent chip layers is obtained by imaging and measuring the stacked cross-section using a scanning electron microscope.

[0042] S23. The system calculates the local absolute temperature at the interface between adjacent layers. The ambient temperature used to characterize thermochemical aging: .

[0043] Specifically, for example: assuming the measurement is (Right now During the high-load phase following a low-temperature start-up, the equipment monitored a temperature rise to [temperature value missing] on layer 4 (hotspot). ( ), the 5th layer is maintained ( At this point, the system calculates the vertical temperature gradient. Local absolute temperature .

[0044] In this embodiment 1, the system utilizes a frequency conversion sampling strategy to automatically switch to high-frequency mode when drastic temperature fluctuations are detected, ensuring that no transient thermal shock process is missed. Subsequently, the discrete single-layer junction temperature data is converted into a vertical temperature gradient. With local absolute temperature Through vertical temperature gradient The shear stress driving source leading to interlaminar mechanical tearing was characterized, while utilizing local absolute temperature. The thermochemical environmental parameters affecting the aging rate of materials were identified, thus providing key input variables for the subsequent construction of a thermo-mechanically coupled instantaneous interfacial mechanical damage rate model, solving the problem that existing technologies mask the risk of local interlayer thermal mismatch by focusing only on average temperature.

[0045] S3. Construct a thermo-coupling instantaneous interface mechanical damage rate model to calculate the interlayer micro-area monitoring and instantaneous damage at the application end. This includes the following sub-steps: S31. First, based on the principles of solid mechanics, analyze the stress state at the interlayer interface. When there is a temperature difference between two adjacent chip layers and their materials (such as silicon and the underfill adhesive) have different coefficients of thermal expansion, thermal mismatch will cause shear deformation at the interlayer interface. Define engineering shear strain. This is the ratio of horizontal thermal deformation to vertical interlayer spacing. ; in, The amount of horizontal thermal deformation depends on the temperature difference. The absolute difference in the coefficients of thermal expansion of the two layers of materials and effective length of action (i.e., the distance from the neutral point).

[0046] Therefore, the formula for engineering shear strain is derived as follows: .

[0047] For example, in this embodiment 1, the absolute difference in the coefficients of thermal expansion of the two layers of materials The calibration method is as follows: Step 1: Take samples of two key materials from the chip production line: Substrate sample: Excerpt The single-crystal silicon wafers used for the bare wafers are fabricated into test strips of standard size, such as... ; Medium sample: cut for filling the first Layer and First The gaps between the layers are filled with adhesive, which is then completely cured to prepare pure colloidal samples of the same size.

[0048] Step 2: Using a thermomechanical analyzer (TMA), and following the industry standard IPC-TM-6502.4.24, perform temperature scans on both types of samples. The scan temperature range covers the chip's rated operating range, such as... Record the dimensional expansion curve of the material as a function of temperature.

[0049] Step 3: Perform polynomial regression fitting on the curves obtained from the TMA scan to establish the thermal expansion coefficients of the two materials as a function of temperature. The functional relationship is: Silicon chip CTE function: (Since the thermal expansion of silicon is stable, it can be considered a constant or a linear function). Filling medium CTE function: .

[0050] Step 4: Calculate the key coefficients obtained from the fitting (e.g., ...) As inherent parameters of the system, they are written into the non-volatile memory of the intelligent management and control layer throughout the entire lifecycle.

[0051] Step 5: Definition The dynamic calculation formula is provided for the chip to call during runtime: .

[0052] During actual use, the chip reads the local absolute temperature in real time. Substituting the values ​​into the function above, we can obtain the absolute difference in the thermal expansion coefficients of the two layers of materials. .

[0053] Specifically, for example: in this embodiment 1, the wafer and the underfill adhesive used are subjected to TMA full-temperature range (T / T) treatment. (Scanning measurement) The measured CTE of the single-crystal silicon chip is stable within the operating temperature range and is fitted as a constant. The CTE of the cured bottom filler was found to change non-linearly with temperature. Polynomial regression fitting was used to obtain its temperature-dependent properties. The functional relationship is: The system extracts the above fitting coefficients ( , , , This is then written to the chip's memory area as an inherent parameter. During chip operation, assume the system monitors a local absolute temperature at a certain moment. (Right now If so, the above parameters will be automatically invoked for dynamic calculation: First, the medium CTE will be calculated: Therefore, the difference in dynamic thermal expansion coefficients at that moment can be obtained: .

[0054] S32. According to the Coffin-Manson empirical formula in materials fatigue physics, the plastic fatigue life of a material has a power-law relationship with the experienced plastic strain amplitude. Define the mechanical fatigue driving term. This is used to characterize the lattice dislocation slip and microcrack initiation rate directly caused by geometric deformation. This mechanical fatigue driving term... Engineering shear strain of The power is directly proportional to: ; In the formula, This refers to the fatigue ductility index. For example, for lead-free solders and polymer adhesives, the fatigue ductility index is... The calibration steps are as follows: Step 1: During the product reliability verification phase, select two groups of SiP chip samples from the same batch (number of samples per group). Each particle was subjected to accelerated aging (ATC) tests under two different temperature differential cyclic stress conditions. Operating Condition A, Low Stress Group: Set Temperature Difference Range ,For example ,Right now ; Condition B, High Stress Group: Set Temperature Difference Range ,For example ,Right now .

[0055] Step 2: Record the number of failure cycles for the two sets of samples under their respective operating conditions, and calculate their characteristic lifetime based on the Weibull distribution, i.e. Number of cycles at sample failure: The characteristic lifetime measured under operating condition A is The characteristic life under operating condition B was measured as follows: Second-rate.

[0056] Step 3: Based on the generalized Coffin-Manson fatigue equation And engineering shear strain With temperature difference They are directly proportional, and the following equation can be established: Taking the natural logarithm of both sides of the above equation, we can derive... The calculation formula is as follows: .

[0057] Step 4: Calculate the results The value is used as an inherent material property parameter of this SiP chip model and written into the database of the control system or the chip firmware.

[0058] Specifically, for example: in this embodiment 1, the 8-layer stacked SiP chip was calibrated by actual measurement: Under the conditions, the characteristic lifetime was measured. Next; in Under the condition, the characteristic lifetime was measured. Next. Substitute into the formula to calculate: Therefore, in this embodiment, the fatigue ductility index... Determined as .

[0059] S33. Considering that high-temperature environments exacerbate atomic diffusion and creep within materials, leading to a decrease in yield strength and thus accelerating fatigue crack propagation, the fatigue weakening coefficient of the material is constructed using the Arrhenius equation. The formula is used to characterize the catalytic amplification effect of ambient temperature on mechanical fatigue, and is as follows: ; In the formula, This is a frequency factor constant used to adjust the damage magnitude; It is a fatigue thermal sensitive energy, which characterizes the rate at which the fatigue resistance of a material decreases with increasing temperature; This is the Boltzmann constant, quoted from the standard value published by the International Committee on Data for Science and Technology (ICS). This is the fatigue weakening coefficient of the material. Characterized by local absolute temperature Below, the chemical reaction rate constant of the damage reaction.

[0060] For example: In this embodiment 1, fatigue thermal sensitivity energy With frequency factor constant The combined measurement was conducted using the "Multi-temperature Point High-Temperature Operating Life Test" conforming to the JEDEC JESD22-A108 standard. The specific steps are as follows: Step 1: Select SiP chip samples from the same batch of production, totaling... The particles were randomly divided into three groups and subjected to accelerated failure tests under three different constant junction temperature stresses: Group 1: Low-temperature accelerated group, junction temperature (like ); Group 2: Medium-temperature accelerated group, junction temperature (like ); Group 3: High-temperature accelerated group, junction temperature (like ).

[0061] Step 2: Record the time when delamination or fracture failure occurred in each group of samples, and calculate the average failure time for each group, denoted as follows: The corresponding damage response rate Defined as the reciprocal of the failure time, i.e. .

[0062] Step 3: Take the natural logarithm of both sides of the Arrhenius equation to transform it into a linear regression form: ;by x-axis ,by y-axis Construct coordinate points , , .

[0063] Step 4: Use the least squares method to perform a linear fit on the above scattered points to obtain the equation of the straight line. .Sure The slope of a straight line The corresponding physical meaning is ,therefore .Sure : intercept of the line The corresponding physical meaning is ,therefore .

[0064] Specifically, for example, in this embodiment 1, the interlayer bottom filler material of the SiP chip was measured and calibrated. The measured data is as follows: At that time, average lifespan Hours; Rate .exist At that time, average lifespan Hours; Rate .exist At that time, average lifespan Hours; Rate .

[0065] Linear fitting: x-axis They are respectively The slope is obtained by fitting. ,intercept .

[0066] Calculate the activation energy: Calculate the frequency factor: .

[0067] S34. Existing theoretical models are all based on the assumption of ideal materials and ignore manufacturing process fluctuations. This invention utilizes the chip individual quality factor obtained in step S1. As a correction factor, the theoretical model is mapped to a specific chip: if This indicates that the individual has manufacturing defects, and the damage rate under the same stress will be amplified.

[0068] S35. Damage at the interlayer interface originates from cyclic thermal stress, while ambient temperature acts as a catalyst; for example, high temperatures reduce the material's yield strength and accelerate crack propagation. Therefore, the individual chip quality factor... Mechanical fatigue drive item With the material's fatigue weakening coefficient The product coupling of these three factors determines the total instantaneous interface damage rate. The instantaneous interface mechanical damage rate model is constructed as follows: .

[0069] Specifically, for example, in this embodiment 1, , , , , Chip individual physical factors interlayer temperature difference Local absolute temperature Assuming the chip's effective operating length... (Right now ), calculate the engineering shear strain at this time. Subsequently, the instantaneous interface mechanical damage rate model was substituted into the calculation. The calculation results quantify the rate of mechanical damage accumulation at the interlayer interface under the current low load and low temperature difference conditions.

[0070] In this embodiment 1, the system will characterize the individual chip quality factor that represents the manufacturing process deviation. Substituting the instantaneous interface mechanical damage rate model of thermo-coupling with the mechanical fatigue driving term calculated based on real-time temperature difference... and the material fatigue weakening coefficient calculated based on absolute temperature By performing nonlinear coupling, the instantaneous interface damage rate under the current low-load condition is finally quantified. This method quantifies the synergistic effect of thermal mismatch shear force and high-temperature aging on interface lifetime through a model, and uses a bulk factor to correct the theoretical model's assessment bias on defective individuals. This ensures that even in the early stages when electrical parameters are normal, the fatigue accumulation trend of the microscopic physical interface inside the stacked structure can be sensitively captured.

[0071] S4. Construct a cumulative health assessment model to evaluate the physical health of the chip, specifically including the following steps: S41. Based on the traditional SMART monitoring principle, a linear cumulative damage theory is adopted. Considering the different service importance carried by different dies within the SiP (System-on-a-Package), for example, the failure of the main controller die results in total disk failure, while the failure of a single flash die only leads to a reduction in capacity, a weighting factor is introduced. Define electrical wear term. for: ; In the formula, The number of stacking layers; For the first The current erase / write / cycle count for the layer; Designed for rated life; For importance weights, satisfying .

[0072] For example, in this embodiment 1, the importance weight The steps for determining this are as follows: Step 1: Construct the data interaction topology diagram inside the chip .in, Represents the set of bare die nodes for each layer of the stack. This represents the data transmission channel between layers, such as a bonding wire. The node connecting to the external host interface is defined as the root node (usually the master control layer).

[0073] Step 2: Calculate the data blocking loss value for each layer node. Simulation 1 A layer node becomes invalid, which means a node is removed from the graph. And its connecting edges, calculate the remaining storage address space capacity in the system that can still be accessed through the root node, denoted as . The total design capacity of the system is denoted as... Definition of the first The failure loss value of the layer is: ; This formula indicates that when the first... When a layer is physically damaged, the system loses its total capacity either directly (due to the damage to the layer itself) or indirectly (due to the interruption of the layer as a transmission path, making subsequent layers inaccessible).

[0074] For the main control layer (Layer 1): as the essential routing node for data transmission, if it fails, all storage granules become unreachable. ,but .

[0075] For independent storage layers (Layer 2-N): as a leaf node, if the... A layer failure only renders the capacity of that layer unavailable; it does not affect other layers. ,but , For the first The capacity of a single layer.

[0076] Step 3: Define the proportion of the loss value of each layer to the total potential loss risk of the system as the weight, as shown in the following formula: .

[0077] S42. Define the cumulative thermomechanical fatigue damage term. This is used to characterize the probability of irreversible physical delamination in the packaging structure. ; In the formula, This is the normalization coefficient for mechanical damage.

[0078] For example, in this embodiment 1, the mechanical damage normalization coefficient The method for determining it is as follows: First, from the test data in step S32, select the high-stress condition (condition B: temperature difference range). Characteristic lifetime under ) As an objective truth value of physical failure, it represents the chip's ultimate tolerance capability under specific physical stress. Then, using the instantaneous interface mechanical damage rate model, the temperature curve of condition B is... Substitute the values ​​and calculate the definite integral of the theoretical damage rate within a single temperature cycle under this operating condition, denoted as the theoretical damage amount per cycle. : ; In the formula, This is the time required to complete one temperature cycle in operating condition B. Take the average body mass factor of the test samples.

[0079] Then, the theoretical damage amount per week was calculated. Multiply by the number of characteristic lifetimes This yields the theoretical cumulative damage value calculated by the model when the chip experiences physical failure, i.e., the critical threshold. Critical threshold This means that when the model's accumulated calculated value reaches this value, the chip will objectively experience physical failure.

[0080] Finally, according to the boundary conditions defined by normalization, that is, when failure occurs, Constructing equations Therefore, the normalized coefficient of mechanical damage can be obtained. .

[0081] S43, Based on electrical wear item With cumulative thermomechanical fatigue damage Calculate the total damage amount, and determine the chip's remaining health by subtracting the calculated total damage amount from the initial perfect state. The cumulative health assessment model is constructed as follows: ; In the formula, This indicates the remaining health of the chip in its initial perfect state.

[0082] Specifically, for example: assuming the system runs to The SiP chip is configured to consist of a single controller chip (Layer 1) and seven layers of NAND Flash (Layers 2-8). Considering that a failure of the controller chip would lead to system paralysis, its weight is set accordingly. The remaining 7 Flash layers have their weights evenly distributed, i.e. Set the rated erase / write life of the Flash chip. At this time, the main control chip has no erase / write wear ( The fourth layer, being located in a hotspot area, has already been written. One pass (50% loss); the remaining 6 layers of Flash were written evenly. Secondary wear (20% loss). System calculates electrical wear item. Based on the instantaneous interface damage rate calculated in step S35, the system... Integrate the maximum damage rate within one hour. Assume a mechanical damage normalization coefficient. The cumulative mechanical damage integral is calculated as follows: The system calculates the cumulative thermomechanical fatigue damage term. Substitute into the cumulative health assessment model to calculate the remaining health. The result indicates that the chip's overall remaining health has decreased to 75%.

[0083] In this embodiment 1, the system is based on preset business importance weights. Calculate the electrical wear term The normalized cumulative thermomechanical fatigue damage term is obtained by combining the integral calculations based on historical operating conditions. Ultimately, the remaining health of the chip is determined by superimposing multidimensional damage. This method overcomes the blind spot of traditional methods that only count the number of erase and write cycles while ignoring the mechanical fatigue between layers. Furthermore, it reflects the differentiated impact of failures of different dies, such as the main control chip and memory chips, on the overall availability of the system through weight allocation. This provides quantitative decision indicators for triggering precise proactive maintenance based on the actual health status.

[0084] S5, Based on Remaining Health Vertical wear balancing control specifically includes the following steps: S51. Set health status warning threshold If the system compares and finds the chip's remaining health... If the chip is found to have a physical defect, a vertical wear leveling strategy is executed; otherwise, the chip is considered to be normal.

[0085] For example, in this embodiment 1, the health warning threshold The calibration method is as follows: First, using the data established in step S12, including... Training set of historically failed chips The system backtracks and inputs the historical operating data (temperature, erase / write operations) of these failed chips into the cumulative health assessment model to calculate the time of actual physical failure for each chip (i.e., the time of failure). The theoretical residual health calculated by the model is denoted as the residual sample. .

[0086] Then, on the residual dataset Perform statistical analysis and calculate its mean residual value. and standard deviation .

[0087] Introducing the standard normal distribution Coverage principle, determine the early warning threshold: ; in, The physical security margin for data migration is calculated based on the physical transmission rate. ; In the formula, For single-level storage capacity; Minimum write migration speed; The maximum instantaneous interface mechanical damage rate observed in historical data from step S35.

[0088] Specifically, for example, in the training set of this embodiment 1, backtesting revealed that the model calculated the average health of historical chips when they failed. Standard deviation The single-layer capacity is 128GB, the minimum migration speed is 50MB / s, and the complete migration takes approximately 2560 seconds (0.71 hours). The historically observed maximum damage rate is... Then the physical security margin for data migration. The final calculated objective threshold is: The result indicates that when the system calculates a remaining health level below 6.7%, considering historical limitations of the model... Given the statistical error range and the physical time required for data migration, the system must immediately initiate vertical wear equalization; otherwise, it will face an extremely high risk of unpredictable failure.

[0089] S52. When a physical defect is detected in the chip, a vertical wear leveling strategy is executed: the system forcibly stops write operations at layer 4 and migrates data hotspots to areas with lower temperatures (smaller Arrhenius values) and lower chip individual quality factors. The first layer is designated as the "derating zone," and the fourth layer is marked as such, used only for storing cold data. This reduces the subsequent instantaneous interface damage rate of this layer. delay Further decline.

[0090] In this embodiment 1, the system sets a hard health warning threshold based on the statistical distribution of historical failure data and the physical time required for data migration. When the remaining health of the chip is detected When the temperature drops below this threshold, a vertical wear leveling strategy is automatically triggered. This dynamically relocates high-frequency read / write operations from the high-risk area where damage accumulates fastest to a safe area that is in good condition and at low temperatures. The high-risk area is then locked as a cold data area for read-only or low-frequency write operations. This method preemptively redistributes the internal thermal load before the critical point of physical failure, cutting off the fatigue acceleration source at weak interlayer interfaces. It not only ensures the integrity of core user data using reserved safety margins but also delays the complete disintegration of the chip's physical structure by reducing local thermal stress.

[0091] Example 2 As a second embodiment of the present invention, such as Figure 2 As shown in Example 1, this example also discloses a chip lifecycle performance monitoring and evaluation system based on big data. The specific architecture includes: a manufacturing end physical mapping layer, an application end sensor network layer, and a lifecycle intelligent management and control layer.

[0092] The manufacturing-side physical mapping layer is primarily deployed on wafer fabrication and packaging / testing production lines. Its core hardware includes industrial-grade automated test equipment (ATE) and one-time programmable memory (OTP) within the chip. The ATE equipment is equipped with precision probe cards to perform wafer-level electrical scanning and finished-product mechanical tensile testing, aiming to obtain information including wafer position coordinates. Static leakage current and wire bonding pull The original physical characteristics, including the chip's physical characteristics, are permanently fixed to the chip's one-time programmable memory area through a programming interface.

[0093] The application-side sensing network layer is integrated within the SiP chip package. It includes miniature embedded temperature sensors distributed across key hot spots on each stacked die. These sensors are interconnected via an internal stacking bus, enabling them to capture junction temperature data from each layer in real time at a sampling rate of up to 100Hz, providing dynamic input for thermodynamic calculations.

[0094] The full lifecycle intelligent management and control layer is an intelligent algorithm module running in the main control chip firmware. When computer-readable instructions are executed by the processor, the following functional modules are run: Manufacturing Data Extraction and Feature Implantation Module: This module is mainly used in the chip manufacturing stage to read the raw data from the ATE testing equipment, establish a multi-factor weighted evaluation model, and normalize discrete manufacturing process parameters into single chip-specific quality factors. This solves the error problem of traditional models assuming that all chips have the same quality.

[0095] Application-side interlayer micro-area monitoring module: During chip operation, this module executes a frequency conversion sampling strategy and uses differential operations to calculate the vertical temperature gradient. With local absolute temperature This is used to overcome the shortcomings of traditional surface temperature uniformity monitoring that masks the internal thermal gradient.

[0096] Instantaneous interface mechanical damage rate calculation module: This module combines solid mechanics and the Arrhenius equation, and introduces chip individual physical factors. The theoretical model is modified, and the instantaneous interface mechanical damage rate caused by thermal mismatch at the interlayer interface is calculated in real time, thereby identifying potential areas where the electrical function is normal but the physical structure is on the verge of fatigue.

[0097] Cumulative Health Assessment Module: This module is responsible for calculating the number of routine P / E erase / write cycles and the electrical wear item. The instantaneous mechanical damage rate is integrated over time to calculate the cumulative thermomechanical fatigue damage term. By introducing business importance weights Calculate the remaining health of the chip.

[0098] Vertical wear leveling control module: This module is used to compare the chip's remaining health status with the warning threshold in real time. When detected When this happens, the module immediately triggers a vertical wear leveling strategy: it forcibly suspends write operations on the damaged layer, calls the DMA controller to move hot data to a safer layer with a better chip quality factor or a lower temperature, and marks the original damaged layer as a "cold data area," thereby blocking the damage accumulation process before physical failure occurs.

[0099] Furthermore, in order to verify the actual effect of the method described in Embodiment 1 of the present invention in solving the problem of monitoring latent physical failures, a comparative experiment was constructed in this embodiment.

[0100] Experimental subjects: 200 8-layer stacked 3D NAND Flash SiP chips from the same batch. Of these, 100 chips located at the wafer edge and exhibiting relatively high leakage current were specifically selected. To eliminate selection bias, these 100 high-risk chips were randomly divided into two groups of 50 each.

[0101] Temperature cycling tests conforming to JEDEC JESD22-A104 standards were employed. The experimental equipment included an automated aging chamber with high and low temperature shock capabilities, and a matching read / write pressure test board. To simulate extreme operating conditions, the aging chamber temperature was set at [temperature range missing]. Rapid cycling between them, temperature change rate The chip was kept at both high and low temperatures for 15 minutes each. During the temperature change process, a high-frequency random read / write load (4KB Random Write, QD=32) was continuously applied to the chip using a read / write stress test board to induce shear stress caused by thermal mismatch in the material.

[0102] This experiment included a control group and an experimental group, with each group containing 50 normal samples and 50 defective samples. Control group (using existing technology): Monitoring of P / E erase / write cycles is based solely on SMART technology. An alarm is triggered when the number of erase / write cycles reaches 90% of the rated value (3000 times), and there is no thermomechanical damage assessment function.

[0103] Experimental group (using the scheme of this invention): A big data-based full lifecycle monitoring system was implemented. A health status early warning threshold was set. Enable manufacturing-side characteristic factor correction and vertical wear equalization strategies.

[0104] During the experiment, aging tests were continuously run until the chips failed. The physical failure time of each chip and whether the system successfully issued an early warning before failure were recorded. A two-sample t-test was used to assess the significance of the differences in lifespan, and a chi-square test was used to assess the differences in early warning accuracy. The experimental statistics are shown in Table 1 below: Table 1 Conclusion: The 95% confidence interval for the lifespan of the control group was [1920, 2180] hours, while that of the experimental group was [2510, 2850] hours. The two intervals did not overlap, providing strong statistical evidence that the 30.7% increase in lifespan in the experimental group was not due to random sample error, but rather a genuine physical improvement resulting from the vertical wear equalization strategy described in this invention. Furthermore, the average lifespan of the control group was 2,050 hours, with 6 chips triggering SMART alarms before complete failure. Analysis revealed that this was due to interlayer microcracks causing a decrease in signal integrity, leading to a surge in ECC error correction rate. Although existing technology captured these 12% anomalies, the lack of direct monitoring of the stress mechanism resulted in the remaining 88% of chips experiencing sudden physical fractures without any electrical warning signs, leading to data loss. Correspondingly, due to the extremely short warning window, only 5 chips in the control group completed data migration, resulting in a migration success rate of 10%. The average lifespan of the experimental group was extended to 2,680 hours. By monitoring the instantaneous interface damage rate, the system successfully identified the fatigue risk of 48 chips in advance and reduced the proportion of sudden failures to 4%. This result shows that downgrading the damaged layer to a cold data area can effectively slow down the crack propagation rate, thereby extending the effective service time of the chip under the critical state of physical damage.

[0105] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0106] The preferred embodiments of the invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention.

Claims

1. A chip lifecycle performance monitoring and evaluation method based on big data, characterized in that, include: During the wafer testing and packaging testing stages, key physical characteristic data of each bare die of the chip are extracted, a multi-factor weighted evaluation model is established, the key physical characteristic data is normalized into chip individual quality factors, and the chip individual quality factors are written into the chip's one-time programmable memory area. During chip operation, real-time junction temperature data of each layer in the stacked structure are collected, and the vertical temperature gradient vector between adjacent layers and the local absolute temperature of the interface between adjacent layers are calculated. Based on the principles of solid mechanics and the Arrhenius equation, combined with the chip's individual physical factors, a thermo-mechanically coupled instantaneous interface mechanical damage rate model is constructed, and the instantaneous interface damage rate is calculated using the vertical temperature gradient and the local absolute temperature. By introducing a business importance weighting coefficient, an electrical wear item representing read / write wear is calculated, and a cumulative thermomechanical fatigue damage item is calculated based on the instantaneous interface damage rate. The remaining health of the chip is then calculated using a cumulative health assessment model. A health warning threshold is set. When the remaining health of the chip is lower than the health warning threshold, a vertical wear leveling strategy is executed to migrate the data of the damaged layer to the security level and perform degradation processing. The key physical characteristics data include wafer location characteristics, leakage current characteristics, and wire bond strength characteristics.

2. The chip lifecycle performance monitoring and evaluation method based on big data according to claim 1, characterized in that, The expression for the multi-factor weighted evaluation model is as follows: ； In the formula, For individual physical factors of the chip, As a standard physical fitness baseline, For wafer position features, This represents the average leakage current of the wafer. The average bond pull force of the wafer. Leakage current characteristics Characteristics of wire bonding strength. Risk coefficient for edge locations This is the leakage current weighting coefficient. This is the mechanical strength weighting coefficient. This is a function that maximizes the value.

3. The chip lifecycle performance monitoring and evaluation method based on big data according to claim 2, characterized in that, The formula for calculating the vertical temperature gradient vector is: ； In the formula, This represents the vertical temperature gradient vector between adjacent layers of the chip. for Time of the first Real-time junction temperature of the chip in the current analysis layer. for Time and the The next layer chip that is vertically adjacent to the next layer chip (i.e., Real-time junction temperature of the layer. This refers to the physical layer spacing between two adjacent chip layers.

4. The chip lifecycle performance monitoring and evaluation method based on big data according to claim 3, characterized in that, The formula for calculating the local absolute temperature is: ； In the formula, This represents the local absolute temperature at the interface between adjacent layers of the chip.

5. The chip lifecycle performance monitoring and evaluation method based on big data according to claim 4, characterized in that, The expression for the instantaneous interface mechanical damage rate model is: ； In the formula, for Instantaneous interface damage rate at any given moment For effective length of action, This represents the absolute difference in the coefficients of thermal expansion between the two layers of material. The fatigue ductility index, The frequency factor is constant. For fatigue thermal sensitivity, is the Boltzmann constant.

6. The chip lifecycle performance monitoring and evaluation method based on big data according to claim 1, characterized in that, The expression for the electrical wear term is: ； In the formula, for Electrical wear and tear items at all times The number of stacking layers, For the first The current erase / write / cycle count of the layer. To design rated life, For importance weights.

7. The chip lifecycle performance monitoring and evaluation method based on big data according to claim 5, characterized in that, The expression for the cumulative thermomechanical fatigue damage term is: ； In the formula, For a moment Cumulative thermomechanical fatigue damage term, This is the normalization coefficient for mechanical damage.

8. The chip lifecycle performance monitoring and evaluation method based on big data according to claim 6 or 7, characterized in that, The expression for the cumulative health assessment model is: ； In the formula, for The remaining health status of the time chip. This indicates the remaining health of the chip in its initial perfect state.

9. The chip lifecycle performance monitoring and evaluation method based on big data according to claim 1, characterized in that, The vertical wear leveling strategy includes: the system forcibly stopping write operations on chip layers whose health has dropped to a dangerous range, migrating data hotspots to chip layers with better health or lower temperatures, and marking the original damaged layers as derated usage areas used only for storing cold data.

10. A system for monitoring and evaluating chip lifecycle performance based on big data, employing the chip lifecycle performance monitoring and evaluation method based on big data as described in any one of claims 1 to 9, characterized in that, include: The manufacturing end data extraction and feature implantation module is used to extract key physical feature data of each bare die of the chip during the wafer testing and packaging testing stages, establish a multi-factor weighted evaluation model, normalize the key physical feature data into chip individual quality factors, and write the chip individual quality factors into the chip's one-time programmable memory area. The application-side interlayer micro-region monitoring module is used to collect real-time junction temperature data of each layer in the stacked structure during chip operation, and to calculate the vertical temperature gradient between adjacent layers and the local absolute temperature of the interface between adjacent layers. The instantaneous interface mechanical damage rate calculation module is used to construct a thermo-mechanically coupled instantaneous interface mechanical damage rate model based on solid mechanics principles and the Arrhenius equation, combined with chip individual quality factors, and to calculate the instantaneous interface damage rate using vertical temperature gradient and local absolute temperature. The cumulative health assessment module is used to introduce business importance weight coefficients, calculate electrical wear items that characterize read and write wear, calculate cumulative thermomechanical fatigue damage items based on instantaneous interface damage rate, and calculate the chip's remaining health through the cumulative health assessment model. The vertical wear leveling control module is used to set a health warning threshold. When the remaining health is lower than the health warning threshold, the vertical wear leveling strategy is executed to migrate the data of the damaged layer to the safe layer and perform degradation processing.

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