A printed circuit layout implementation method for LED display glass substrate

Abstract

This invention discloses a method for implementing printed circuit layout on LED display glass substrates, specifically relating to the field of printed circuit layout. It addresses the problem in existing technologies where printed circuit wiring in glass substrate splicing structures struggles to balance local overheat control and visual consistency. The method involves constructing a two-dimensional equivalent thermal resistance distribution map and a visual transmission path offset vector field, dividing the area adjacent to the splice seam into a grid, and determining the trace area ratio based on the coupling relationship between thermal characteristics and optical offset. This generates a multi-branched interwoven mesh circuit structure. Furthermore, thermal characteristic parameters are obtained through steady-state current field simulation. In areas exceeding thermal limits, circuit topology splitting is performed to disperse current density. Simultaneously, the circuits are discontinuously and staggered according to visual offset, thereby achieving a synergistic improvement in both thermal distribution balance and visual effect optimization of the printed circuit, and enhancing structural reliability and long-term stability.

Description

Technical Field

[0001] This invention relates to the field of printed circuit layout technology, and more specifically, to a method for implementing printed circuit layout on an LED display glass substrate. Background Technology

[0002] With the development of ultra-large-size splicing displays and high-resolution display technologies, LED display glass substrates have gradually become an important carrier for high-end display modules, and are widely used in applications such as splicing displays, transparent displays, and fine-pitch displays. In this type of structure, the driver chip is usually directly integrated on the surface of the glass substrate, and power supply and signal distribution are realized through printed circuits. Due to the limited thermal conductivity of the glass material itself and the discontinuity of the splicing structure, local heat accumulation is easily formed near the driver chip pads and in the adjacent area of ​​the splicing seam, which can lead to risks such as uneven temperature rise, stress concentration, and even microcrack propagation.

[0003] Meanwhile, during actual viewing, the combined effect of the viewing angle and the thickness of the glass substrate causes light to refract and shift within the substrate, resulting in visual misalignment or stripes in the seam area and surrounding circuitry, affecting overall display consistency. Against this backdrop, traditional printed circuit layout methods primarily rely on uniform or simple gradient wiring, focusing mainly on electrical connectivity and fabrication feasibility, lacking a comprehensive consideration of the coupled effects of thermal distribution and visual shift. This makes it difficult to effectively suppress localized overheating and eliminate visual discontinuities in the seam area under high-density wiring conditions. Therefore, there is an urgent need for a printed circuit layout method for LED display glass substrate applications that can simultaneously address thermal safety and visual consistency. Summary of the Invention

[0004] In order to overcome the above-mentioned defects of the prior art, embodiments of the present invention provide a method for implementing printed circuit layout of LED display glass substrate to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for implementing printed circuit layout on an LED display glass substrate includes the following steps: S1. Under the unloaded state of the glass substrate, inject a preset calibration heat power into the pad position of the driver chip, collect the steady-state temperature distribution on the surface of the glass substrate and construct a two-dimensional equivalent thermal resistance distribution map. S2. Based on the observation distance and glass substrate thickness parameters, calculate the lateral offset generated when incident light from the back of the glass substrate passes through the front of the glass substrate, and construct the visual transmission path offset vector field. S3. Taking the edge of the glass substrate seam as the starting boundary, a gradual transition zone with a width that overlaps with the thermal influence radius in the two-dimensional equivalent thermal resistance distribution diagram is defined along the vertical seam direction. The gradual transition zone is divided into a sequence of grid cells arranged along the direction. S4. Assign an initial value to the trace area ratio of the grid cell sequence by coupling the two-dimensional equivalent thermal resistance distribution of the corresponding region of the grid cell and the visual transmission path offset vector field, and generate a geometric description of the interwoven mesh line with a multi-branch intersection shape within the grid cell. S5. Using the two-dimensional equivalent thermal resistance distribution map as the thermal characteristic constraint parameter, perform steady-state current field simulation on the geometric description of the interwoven mesh line, and extract the Joule thermal power surface density value corresponding to each mesh unit as the unit thermal characteristic parameter. S6. Compare the unit thermal characteristic parameters with the thermal power surface density threshold corresponding to the allowable thermal stress of the glass substrate, and perform circuit topology splitting operation on the grid units that exceed the threshold. S7. The topology-adjusted interwoven mesh lines are transformed into a discontinuous line segment array according to the visual transmission path offset vector field, and the line segment arrays in all grid cells are merged to generate printed circuit graphic data for photoplotting exposure.

[0007] As a further aspect of the present invention, in step S1, constructing the two-dimensional equivalent thermal resistance distribution map specifically includes: In a static environment where the glass substrate is without a driving signal, a preset constant thermal power is injected into the pad position of the driver chip. Full-frame temperature images of the glass substrate surface are acquired at fixed time intervals. When the maximum temperature difference between adjacent frames is lower than the preset fluctuation threshold, the current frame is taken as the steady-state temperature distribution image. Based on the difference between the temperature value of each pixel in the steady-state temperature distribution image and the preset ambient reference temperature, as well as the injected calibration heat power value, the equivalent thermal resistance value is calculated pixel by pixel and summarized to generate a two-dimensional equivalent thermal resistance distribution map indexed by the plane coordinates of the glass substrate.

[0008] As a further aspect of the present invention, in step S2, constructing the visual transmission path offset vector field specifically includes: The vertical distance from the set observation position to the front of the glass substrate is extracted as the observation distance parameter, and the glass substrate forming thickness is extracted as the glass substrate thickness parameter. Based on the calibrated refractive index constant, combined with the observation distance parameter and the glass substrate thickness parameter, the lateral offset distance between the propagation path of the incident light from the back of the glass substrate inside the glass substrate and the path of the light emitted to the observation position is calculated. The glass substrate plane is divided into discrete coordinates. For each coordinate point, the lateral offset distance and offset direction are calculated to generate a visual transmission path offset vector field indexed by the coordinates of the glass substrate plane and containing two components: offset distance and offset direction.

[0009] As a further aspect of the present invention, in S3, the gradually transitioning region whose width overlaps with the thermally affected radius in the two-dimensional equivalent thermal resistance distribution diagram specifically includes: Extract the attenuation curve of the equivalent thermal resistance value located at the edge of the glass substrate seam and extending along the direction perpendicular to the seam from the two-dimensional equivalent thermal resistance distribution map. Identify the spatial position of the equivalent thermal resistance value from the peak value at the seam edge to the specified attenuation ratio on the attenuation curve and determine the straight-line distance from the position to the seam edge as the thermal influence radius. Using the edge of the glass substrate seam as the starting boundary, a region with a length equal to the heat-affected radius is cut along the direction perpendicular to the seam as a gradient transition zone. The gradient transition zone is discretized into strips of equal width along the direction parallel to the seam, and each strip is then divided at equal intervals along the direction perpendicular to the seam to form a grid unit sequence arranged in rows and columns.

[0010] As a further aspect of the present invention, in step S4, generating the geometric description of the interwoven network line with a multi-branch intersection shape specifically includes: The average equivalent thermal resistance within the coverage area of ​​each grid cell is extracted from the two-dimensional equivalent thermal resistance distribution map, and the offset distance of the corresponding spatial position of each grid cell is extracted from the visual transmission path offset vector field. The coupling characteristic quantity of the grid cell is calculated by nonlinearly correlating the average equivalent thermal resistance with the offset distance. The proportion of the coupling characteristic quantity of a mesh cell to the total coupling characteristic quantity of all mesh cells in the gradient transition region is determined as the initial value of the trace area ratio of that mesh cell. Within a single grid cell, at least two main trunk lines are laid out along the main direction of current conduction, and cross-bridging lines with non-zero angles to the main trunk lines are added between adjacent main trunk lines. The number of cross-bridging lines laid out is positively correlated with the initial value of the percentage of the grid cell's wiring area. The distribution of main lines and cross-bridging lines within all grid cells is summarized to form a geometric description of an interwoven network with multiple branching and crossing patterns.

[0011] As a further aspect of the present invention, in step S5, performing steady-state current field simulation on the geometric description of the interwoven network circuit specifically includes: The equivalent thermal resistance value within the coverage area of ​​each grid cell in the two-dimensional equivalent thermal resistance distribution map is extracted and used as the thermal characteristic constraint parameter of the corresponding grid cell. A numerical model of a conductive network, including the topology and geometric dimensions of the circuit, is constructed based on the geometric description of the interwoven mesh circuit. An equivalent driving current load corresponding to the calibrated thermal power is applied to the mesh nodes corresponding to the pads of the driver chip. Solve the potential distribution of each branch node and the current density vector flowing through each line segment in the conductive network model. Calculate the Joule thermal power surface density value based on the current density modulus of each line segment, the conductivity of the line material, and the geometric area of ​​the grid cell containing that line segment. Then, correct the Joule thermal power surface density value by combining it with the thermal characteristic constraint parameters of the corresponding grid cell, and use it as the element thermal characteristic parameter.

[0012] As a further aspect of the present invention, in step S6, performing the line topology splitting operation specifically includes: The allowable temperature difference threshold of the glass substrate without crack propagation is calculated based on the allowable thermal stress value, coefficient of thermal expansion and elastic modulus of the glass substrate material. The thermal power surface density threshold is obtained by using the allowable temperature difference threshold, the thermal conductivity of the glass substrate and the thickness of the glass substrate. Traverse all mesh cells and compare the element thermal characteristic parameters of each mesh cell with the thermal power surface density threshold. Mark mesh cells whose element thermal characteristic parameters exceed the thermal power surface density threshold as thermal over-limit cells. For the main trunk line in the current interwoven mesh line geometry description within the grid cell marked as thermal overlimit cell, perform symmetrical splitting, replace the original single main trunk line with at least two sub-main trunk lines that are equally spaced and connected in parallel, and the total cross-sectional area of ​​the split sub-main trunk lines is equal to the cross-sectional area of ​​the original main trunk line. Update the line geometry description corresponding to the thermal over-limit unit to obtain the interwoven mesh line geometry description after topology split correction.

[0013] As a further aspect of the present invention, in step S7, generating the printed circuit pattern data for photoplotting exposure specifically includes: The offset vector at the corresponding spatial position of each grid cell is extracted from the visual transmission path offset vector field. The maximum continuous length of the line segment in the grid cell is determined by the magnitude of the offset vector, and the misalignment distance between adjacent line segments in the vertical splice direction is determined by the direction of the offset vector. Based on the maximum continuous length, all continuous lines in the topology-adjusted interwoven network are cut into discontinuous segments, and the start and end positions of the discontinuous segments are staggered between adjacent grid cells according to the staggered spacing. The geometric coordinates of the discontinuous line segments after all grid cells have been truncated and misaligned are arranged in a format readable by a photoplotter and then output as printed circuit graphic data for photoplotting exposure.

[0014] The technical effects and advantages of the printed circuit layout method for an LED display glass substrate of the present invention are as follows: This invention addresses the issues of localized overheating and visual discontinuity in high-density integration and splicing displays of printed circuits on LED display glass substrates. By constructing a two-dimensional equivalent thermal resistance distribution map and a visual transmission path offset vector field, it achieves synergistic analysis of thermal and optical characteristics. Based on this, it couples and controls the wiring area ratio, generating a multi-branched interwoven mesh circuit structure to effectively disperse current paths, reduce local current density, and thus homogenize Joule heat distribution and suppress hotspot formation. Simultaneously, by setting a thermal power surface density threshold based on the material's allowable thermal stress and triggering circuit topology splitting, the wiring structure can adaptively adjust in thermally over-limit areas, avoiding structural damage caused by stress concentration. At the visual level, transmission path offset information is used to discontinuously and misalign the circuits, effectively reducing visual stripes and misalignment in splicing areas and improving display consistency. The overall solution achieves simultaneous optimization of thermal management capabilities and visual effects without increasing the total conductive cross-sectional area, balancing engineering feasibility and performance improvement, and has significant application value. Attached Figure Description

[0015] Figure 1 This is a schematic diagram illustrating a method for implementing the printed circuit layout of an LED display glass substrate according to the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0017] Example 1 Figure 1 The present invention provides a method for implementing printed circuit layout on an LED display glass substrate, which includes the following steps: S1. Under the unloaded state of the glass substrate, inject a preset calibration heat power into the pad position of the driver chip, collect the steady-state temperature distribution on the surface of the glass substrate and construct a two-dimensional equivalent thermal resistance distribution map. S2. Based on the observation distance and glass substrate thickness parameters, calculate the lateral offset generated when incident light from the back of the glass substrate passes through the front of the glass substrate, and construct the visual transmission path offset vector field. S3. Taking the edge of the glass substrate seam as the starting boundary, a gradual transition zone with a width that overlaps with the thermal influence radius in the two-dimensional equivalent thermal resistance distribution diagram is defined along the vertical seam direction. The gradual transition zone is divided into a sequence of grid cells arranged along the direction. S4. Assign an initial value to the trace area ratio of the grid cell sequence by coupling the two-dimensional equivalent thermal resistance distribution of the corresponding region of the grid cell and the visual transmission path offset vector field, and generate a geometric description of the interwoven mesh line with a multi-branch intersection shape within the grid cell. S5. Using the two-dimensional equivalent thermal resistance distribution map as the thermal characteristic constraint parameter, perform steady-state current field simulation on the geometric description of the interwoven mesh line, and extract the Joule thermal power surface density value corresponding to each mesh unit as the unit thermal characteristic parameter. S6. Compare the unit thermal characteristic parameters with the thermal power surface density threshold corresponding to the allowable thermal stress of the glass substrate, and perform circuit topology splitting operation on the grid units that exceed the threshold. S7. The topology-adjusted interwoven mesh lines are transformed into a discontinuous line segment array according to the visual transmission path offset vector field, and the line segment arrays in all grid cells are merged to generate printed circuit graphic data for photoplotting exposure.

[0018] In S1, a two-dimensional equivalent thermal resistance distribution map is constructed.

[0019] Before powering on, the glass substrate under test undergoes environmental stabilization treatment. The substrate is placed in a constant-temperature chamber, maintaining the ambient temperature at 25°C for at least 30 minutes to eliminate initial temperature differences. After confirming the glass substrate is in a static state without any drive signal input, constant thermal power is injected into the corresponding area through heating leads pre-positioned at the driver chip pads. This constant thermal power is achieved through a regulated power supply and a current-limiting module. A fixed DC power supply output voltage is converted into a stable heat source through a precision resistive load to ensure the injected power remains constant throughout the acquisition process. For example, a calibration thermal power of 0.8W is selected, or other power values ​​determined through prior experiments, ensuring a measurable temperature rise on the substrate surface without causing material damage. To ensure heat input is concentrated in the driver chip pad area, a low thermal conductivity insulating material is applied around the pads to prevent rapid heat diffusion along the surface from affecting measurement accuracy. During heating, the power supply output voltage and current are continuously monitored, and the input power deviation is checked in real time through a power monitoring module to ensure power fluctuations do not exceed ±2%.

[0020] An infrared thermal imaging device was used to collect the full-frame temperature of the glass substrate surface, with an acquisition interval of 1 second, continuously acquiring at least 120 frames of temperature images. To address the steady-state determination issue, a continuous frame comparison method was used to process the acquisition results. The maximum temperature difference between the current frame and the previous frame was calculated. A steady-state state was determined when this maximum temperature difference was less than a preset fluctuation threshold for five consecutive frames. The fluctuation threshold was set to 0.2℃, or other thresholds obtained through statistical analysis of multiple batches of experiments, effectively avoiding misjudgments of a steady state due to short-term disturbances. After determining the steady-state frame, the temperature image of that frame was processed pixel by pixel. For each pixel, the temperature value at that point was first read, and then subtracted from the pre-calibrated ambient reference temperature during actual operation, such as 25℃, to obtain the temperature rise value at that location. The temperature rise value is then correlated with the aforementioned injected constant heat power. To avoid distortion caused by directly applying the total power to a single pixel, the temperature rise values ​​of all pixels in the entire temperature image are accumulated, the overall temperature rise distribution weight is calculated, and then the total power is allocated according to the proportion of each pixel's temperature rise to the overall temperature rise, thus obtaining the local equivalent heat flux contribution corresponding to each pixel. Based on this, the temperature rise value of the pixel is converted to its corresponding local heat flux to obtain the equivalent thermal resistance value of the pixel. To reduce the influence of noise, the calculated equivalent thermal resistance value is subjected to local neighborhood smoothing, specifically using a 3×3 window centered on the pixel for averaging, making the thermal resistance distribution more continuous and stable. Finally, the equivalent thermal resistance values ​​of all pixels are mapped according to their spatial coordinates in the glass substrate plane to form a two-dimensional equivalent thermal resistance distribution map.

[0021] In S2, a visual transmission path offset vector field is constructed.

[0022] Parameters of the actual viewing environment of the display device are acquired, and the observation position is defined as the equivalent observation point of the human eye or the camera acquisition device. This observation point is positioned along a direction perpendicular to the plane of the glass substrate to ensure a stable normal relationship with the front surface of the glass substrate. The vertical distance from this observation point to the front surface of the glass substrate is directly measured using a ranging device. The ranging device is a fixedly installed laser ranging module with a measurement accuracy controlled within ±1mm to ensure the stability of subsequent offset calculations. To avoid errors introduced by environmental changes, the device is zero-point calibrated before measurement, and three consecutive measurements are taken, with the average value used as the final observation distance parameter. Simultaneously, the thickness of the glass substrate is measured. A contact thickness gauge is used to collect thickness values ​​at the four corners and center of the substrate, and the consistency of the collected results is judged. When the thickness deviation at each point is less than 0.05mm, the average value is taken as the glass substrate thickness parameter. If there is significant unevenness in local thickness, the thickness information is recorded separately according to the area, and the corresponding thickness value is called according to the area in subsequent calculations. To ensure parameter stability, the glass substrate is fixed on a horizontal support platform during the measurement process to avoid tilting and introducing additional optical path deviations.

[0023] Based on the physical law that the direction of light propagation changes in different media, the propagation path of light at the air-glass interface is analyzed in segments. The incident light is assumed to enter the glass substrate from the back side along the normal direction, a setting derived from the structural characteristic of LED light-emitting units typically emitting light perpendicularly in actual display scenarios. After entering the glass, due to the higher refractive index of the glass material compared to air, the light is refracted at the glass interface, changing its propagation direction and forming a propagation path deviating from the original incident direction within the glass. The refractive index constant is calibrated by performing refraction tests on a sample of the glass material used. The light propagates along the refractive direction inside the glass to the front interface and then re-enters the air. Here, due to the change in the refractive index of the medium, it is refracted again and finally propagates towards the observation position. To determine the lateral offset distance, an ideal straight line is geometrically constructed connecting the incident point and the observation point. The actual refraction path is compared with this ideal straight line, and the horizontal deviation between the two at the projected position on the front side of the glass substrate is calculated. First, the path ratio of light in the air segment and the glass segment is determined based on the observation distance and glass thickness. Then, the degree of inclination of the light in the glass is determined by combining the refractive index, and the tendency of the light to deflect relative to the vertical direction when it exits the glass is calculated. The lateral offset distance obtained through this process reflects the amount of light deflection on the plane due to the refraction effect.

[0024] The offset calculation is extended to the spatial distribution across the entire glass substrate, and the glass substrate plane is discretized. The glass substrate is divided into a two-dimensional coordinate grid with a fixed spacing of 1 mm to balance computational accuracy and efficiency. Each grid intersection is a discrete coordinate point, corresponding to a specific spatial location on the glass substrate. For each coordinate point, the lateral offset distance corresponding to that location is calculated using the ray path calculation method, and the directional component of the offset vector is determined by combining the ray offset direction information. The direction is determined by using the seam direction as a reference axis and decomposing the offset direction into a component along the perpendicular seam direction, so that the offset result can be directly reflected in the subsequent wiring layout direction. For areas where the offset distance is close to zero, its vector length is limited to the minimum resolution range to avoid directional misjudgment due to numerical instability. After all coordinate points are calculated, the offset distance and direction of each point are combined to form a two-dimensional vector data unit, which is stored according to its actual coordinate position in the glass substrate plane to construct a complete visual transmission path offset vector field.

[0025] In S3, a gradual transition zone is defined whose width overlaps with the thermal influence radius in the two-dimensional equivalent thermal resistance distribution diagram.

[0026] Spatial positioning processing is performed on the generated two-dimensional equivalent thermal resistance distribution map to determine the specific location of the glass substrate seam in the plane coordinate system. The seam edge is abstracted as a continuous linear boundary, and multiple sampling points are selected at fixed intervals on this boundary. The sampling interval is set to 1 mm, and uniform point selection ensures that all positions of the seam are covered. For each sampling point, a sampling path is established along the direction perpendicular to the seam. This path corresponds to a sequence of grid points arranged continuously in rows or columns in the discrete coordinate grid. The equivalent thermal resistance value is read point by point along this path, forming a thermal resistance data sequence that varies with spatial position. To eliminate the influence of measurement noise on the curve shape, local smoothing processing is performed on the data sequence. A first filtering is performed using the moving average of three adjacent points to make the curve exhibit a stable monotonically decreasing trend. Subsequently, the peak point at the seam edge is identified in the smoothed thermal resistance sequence. This peak point usually corresponds to the maximum value of the thermal resistance distribution. A thermal resistance attenuation ratio threshold is set based on this peak point. For example, this ratio is set to 0.3, meaning that when the thermal resistance drops to 30% of the peak value, it is considered a boundary position where the thermal effect is significantly reduced. This ratio was obtained through statistical analysis of multiple batches of samples and remains stable and applicable across glass substrates of different sizes and materials. The sampling process compares points outward from the peak point along the sampling path. When the thermal resistance value is detected to be lower than the value corresponding to this attenuation ratio for the first time, that point is taken as the thermally affected boundary point, and the straight-line distance between that point and the seam edge is calculated as the thermally affected radius.

[0027] Using the defined seam edge as the starting boundary, the glass substrate is divided into regions along the direction perpendicular to the seam. Starting from the seam edge, a region with a length equal to the heat-affected radius is intercepted outward along the vertical direction, and this region is defined as the gradient transition zone. This region is spatially distributed in a strip shape, and its width is directly determined by the heat-affected radius, thus covering the entire range of significant changes in thermal resistance. To achieve subsequent fine wiring control, the gradient transition zone is further discretized. First, the region is divided into several strips of equal width along the direction parallel to the seam. The default strip width is set to 2mm, which is determined based on a combination of wiring accuracy and computational scale, ensuring spatial resolution while avoiding an excessive number of units. Each strip remains continuous along its length, forming several parallel strip-shaped regions on the plane. Then, for each strip, it is equally divided along the direction perpendicular to the seam into several rectangular units, with a division spacing of 1mm, consistent with the aforementioned thermal resistance sampling spacing, thereby ensuring data consistency and correspondence. Through the aforementioned bidirectional partitioning, the entire gradient transition zone is subdivided into regularly arranged grid cells, each corresponding to a defined spatial range and corresponding to the data in the equivalent thermal resistance distribution map. To ensure the stability of the grid partitioning, the boundary positions are aligned during the partitioning process to keep the grid boundaries parallel to the seam edges. Additionally, edge regions that are smaller than the complete cell size are truncated to avoid generating irregular cells.

[0028] In step S4, a geometric description of an interwoven network with multiple branch intersections is generated.

[0029] Feature extraction is performed on each of the pre-defined grid cells. For each grid cell, the equivalent thermal resistance values ​​of all pixels within its coverage area are read from the 2D equivalent thermal resistance distribution map, and these values ​​are statistically processed. The average equivalent thermal resistance of the grid cell is obtained by direct averaging. This method ensures computational simplicity while eliminating local noise, allowing the result to reflect the overall heat dissipation characteristics of the cell. For cells with significant outliers, a neighborhood mean replacement process is first performed, replacing outliers deviating more than 20% from the neighborhood mean with the neighborhood mean, thus avoiding interference from local measurement errors on the overall average. Subsequently, the offset distance corresponding to the center position of the grid cell is extracted from the visual transmission path offset vector field. This center position is obtained by averaging the coordinates of the four vertices of the grid cell, ensuring its spatial representativeness. To ensure comparability of data with different dimensions, the average equivalent thermal resistance and the offset distance are normalized, converting them into dimensionless values ​​between 0 and 1. In this embodiment, normalization is achieved by dividing the current value by the maximum value within the corresponding region. After normalization, a nonlinear enhancement operation is performed on the superposition result of the two according to the pre-set nonlinear association rules. For example, the sum of squares is used to enhance the larger input value in the result, while the influence of the smaller value is suppressed, thereby highlighting the comprehensive influence of the region with large thermal resistance and significant visual offset.

[0030] The coupling characteristics of all grid cells within the gradient transition zone are summarized. This involves traversing all grid cells and summing the coupling characteristics of each cell to obtain the total coupling characteristic value for that region. Then, for each grid cell, its own coupling characteristic value is proportional to the total coupling characteristic value to obtain its proportion within the whole. This proportion is directly used as the initial value for the routing area proportion of that grid cell, thus achieving differentiated allocation between different regions. To avoid individual cells having extremely small coupling characteristics that cause their proportions to approach zero, a lower limit constraint is set on the proportion results, limiting the minimum proportion to 0.02, meaning each cell must be allocated at least 2% of the basic routing area. This lower limit was determined through multiple routing experiments to ensure minimum conductivity without introducing excessive redundant lines. Simultaneously, an upper limit constraint is set on cells with excessively large proportions; in this embodiment, the maximum proportion is limited to no more than 0.25 to prevent overly dense routing in local areas from causing processing difficulties. After applying upper and lower limit constraints to the proportions of all cells, a normalization process is performed again to restore the sum of the proportions of all grid cells to 1, thereby ensuring that the total routing area remains unchanged.

[0031] Based on the initial value of the determined trace area ratio, the wiring is laid out within each grid cell. The main direction of current conduction is determined, which is determined by the connectivity between the driver chip pads and the target connection area, and remains consistent throughout the entire gradient transition zone. At least two main traces are laid out along this main direction within a single grid cell. The main traces are parallel and evenly spaced, and their spacing is adjusted according to the initial trace area ratio of the cell; the larger the ratio, the more main traces or their width are increased accordingly. In this embodiment, when the ratio exceeds 0.15, the number of main traces is increased; when the ratio is below 0.15, two main traces are maintained, but the trace width is appropriately reduced. Subsequently, cross-bridging traces are laid between adjacent main traces. The bridging traces form a non-zero angle with the main traces. In this embodiment, the angle is set to 45°, an angle determined experimentally to achieve good current dispersion without increasing wiring complexity. The number of bridging lines is set in stages based on the initial value of the line area ratio. For example, one bridging line is laid when the ratio is between 0.05 and 0.10, and two bridging lines are laid when the ratio is between 0.10 and 0.20, thus forming a stable increasing relationship. All bridging lines are spatially staggered to avoid forming local concentrated structures. After the line layout of a single grid cell is completed, its geometric description is recorded, including the location of the main line, the connection relationship of the bridging lines, and the size parameters of each line segment. Finally, the geometric descriptions of the lines of all grid cells are summarized and spliced ​​to form an interwoven network line structure covering the entire gradient transition zone.

[0032] In S5, steady-state current field simulation is performed on the geometric description of the interwoven network circuit.

[0033] For the already divided grid cells, a region mapping process is performed on the two-dimensional equivalent thermal resistance distribution map. The coverage area of ​​each grid cell in the planar coordinates is matched with the corresponding region in the equivalent thermal resistance distribution map, and the set of equivalent thermal resistance values ​​of all pixels in that region is read. To ensure the stability and representativeness of this set of data, statistical processing is performed on it, using a combination of mean and median. That is, the average value of all pixels in the region is first calculated, and then compared with the median value of the region. When the deviation is less than 10%, the average value is directly taken as the equivalent thermal resistance value of the grid cell; when the deviation exceeds 10%, the median value is used instead, thereby avoiding interference from local outliers. The value obtained after this processing is used as the thermal characteristic constraint parameter of the grid cell and is bound to the spatial coordinates of the grid cell for storage. Subsequently, a numerical model of the conductive network is constructed based on the geometric description of the interwoven mesh circuit. Each main trunk line and bridging line is abstracted as a conductive branch, and the intersection points of each line are defined as nodes. The topology between nodes and branches is established according to the actual connection relationship, and the length, width, and thickness information of each branch are recorded as geometric dimension parameters. For the location of the driver chip pads, the mesh node closest to it in space is selected as the input node, and an equivalent drive current load is applied at this node. This load is determined by maintaining the total input power consistent with the aforementioned calibrated thermal power, and by comprehensively matching a pre-set voltage value with the equivalent conductive path, ensuring that the input current forms an energy input state in the conductive network corresponding to the calibrated thermal power. By gradually adjusting the input current and monitoring the total power consumption of the network, it is stabilized near the calibrated value of 0.8W, with an allowable deviation of no more than ±2%, thus completing the application of the equivalent drive current load.

[0034] After constructing the conductive network model and setting the input conditions, the current distribution within the network is solved. All nodes in the conductive network are numbered, and the connection relationships between each node and its neighboring nodes, as well as the geometric dimensions and material properties of the corresponding branches, are recorded. For each node, information from all its neighboring branches is read, and the conductivity between the node and its neighboring nodes is comprehensively searched according to the branch width, thickness, and material conductivity in a preset lookup table to obtain the conductivity weight value in each connection direction. During the initialization phase, the potential of the node corresponding to the driver chip pad is set to a fixed input potential, while the potentials of the remaining nodes are uniformly set to the initial value of 0. Subsequently, the potential value of each node is updated sequentially according to the node number order. For the current node, the potentials of its neighboring nodes are weighted and averaged according to the conductivity weight of the corresponding branches, and the result is used as the new potential value of the node, thus ensuring that the potential update process satisfies the current distribution relationship at the nodes. After completing one round of updating all nodes, the difference between the old and new potentials of all nodes is statistically analyzed. When the maximum difference is greater than a preset convergence threshold, the next round of updates continues; when the maximum difference is less than the preset convergence threshold, the iteration stops. In this embodiment, the convergence threshold is set to 0.001V. This value was determined through multiple tests to ensure stable solution results and controllable computation time. To avoid local oscillations, a partial retention method is used for the newly calculated node potentials during the update process. That is, the potentials from the previous round are merged with the calculated values ​​in the current round at a ratio of 7:3, thereby improving the overall convergence stability. Through the above node-by-node update and convergence judgment process, the stable potential distribution of each node in the entire conductive network is finally obtained.

[0035] After obtaining a stable node potential distribution, the potential difference between the two nodes of each branch is calculated. The current magnitude of the branch is determined by combining the branch's geometry and material conductivity, and the corresponding current density is calculated based on the branch's cross-sectional area. Subsequently, the current density is correlated with the material's conductivity, and the heating intensity of each branch is calculated segment by segment. Specifically, the current density modulus and material conductivity are combined, the current density modulus is squared, and then divided by the material conductivity to obtain the heating intensity per unit volume. This heating intensity is then multiplied by the volume of the line segment to obtain the total heating power of that segment. This heating power is then aggregated according to the grid cell to which the line belongs; that is, the heating power of all line segments located in the same grid cell is accumulated to obtain the total heating power of that grid cell. This total heating power is then divided by the area of ​​that grid cell to obtain the Joule heat power surface density value of that cell. To further reflect the differences in heat dissipation capacity in different regions, this result is coupled and corrected with the thermal characteristic constraint parameters of the corresponding grid cell. In this embodiment, a tiered adjustment method is adopted: when the equivalent thermal resistance of a certain grid cell is higher than the overall average, its Joule thermal power surface density is increased by 10% to 20% proportionally; when it is lower than the average, the original value is maintained or appropriately reduced by no more than 10%. This proportional range is determined through sample testing, which can enhance the risk expression of high thermal resistance regions without introducing abrupt changes. Finally, the corrected Joule thermal power surface density value is used as the unit thermal characteristic parameter of that grid cell.

[0036] In step S6, a line topology splitting operation is performed.

[0037] The mechanical and thermal parameters of the glass substrate material used were obtained, specifically including the allowable thermal stress value, coefficient of linear expansion, and elastic modulus. The allowable thermal stress value was obtained from the material's factory inspection report, the coefficient of linear expansion was obtained from the official material parameter table, and the elastic modulus was determined from standard tensile test data. Subsequently, based on the mechanism of thermal stress generation, the thermal expansion caused by temperature changes was matched with the material's elastic recovery capacity for calculation. Specifically, the allowable thermal stress value and elastic modulus were proportionally converted to obtain the upper limit of unit strain. Then, combined with the coefficient of linear expansion, this upper limit of strain was used to extrapolate the temperature change range, thus obtaining the maximum temperature difference that the glass substrate could withstand without crack propagation. To ensure a safety margin, this value was reduced by a safety factor of 0.8 to finally determine the allowable temperature difference threshold. After obtaining the temperature difference threshold, it was correlated with the thermal conductivity characteristics of the glass substrate. Specifically, the thermal conductivity of the glass substrate was obtained from the official material parameter table, and the measured substrate thickness was also obtained. The distribution of the temperature difference in the thickness direction was converted into the heat flux intensity per unit area. The operation method is as follows: the allowable temperature difference is evenly distributed in the thickness direction of the substrate, the temperature gradient corresponding to the unit thickness is calculated, and then the maximum heat flow allowed to pass through the unit area is obtained by combining the thermal conductivity, thereby obtaining the heat power surface density threshold.

[0038] The entire grid cell within the gradual transition zone is traversed, and the corresponding Joule thermal power surface density value is read for each cell. This value is derived from the aforementioned current distribution calculation and has undergone thermal characteristic constraint correction. The thermal characteristic parameter of this cell is then directly compared with the determined thermal power surface density threshold. When the thermal characteristic parameter of a grid cell exceeds the thermal power surface density threshold, the cell is determined to be in a thermal over-limit state and marked as a thermal over-limit cell. To avoid misjudgments caused by boundary fluctuations during the marking process, this embodiment sets a buffer zone. When the thermal characteristic parameter is between 95% and 100% of the threshold, this region is marked as a critical cell and processed together with thermal over-limit cells in subsequent processing. This zone is determined through analysis of multiple batches of sample test results, effectively improving the stability of the judgment.

[0039] For marked thermal overrun units, topology splitting is performed on their internal wiring structures. The geometric description of the current interwoven mesh wiring within the grid unit is read to identify the main trunk lines responsible for primary current conduction. Then, a symmetrical splitting operation is performed on each main trunk line, replacing it with two or more parallel sub-main trunk lines using the main trunk line's centerline as the axis of symmetry. In this embodiment, it is initially split into two sub-main trunk lines, which are spatially spaced at equal intervals. The spacing is determined proportionally by the grid unit size; for example, when the grid unit width is 2mm, the sub-main trunk line spacing is set to 0.6mm to ensure wiring uniformity. During the splitting process, the total cross-sectional area of ​​the original main trunk line is maintained; that is, the width of the sub-main trunk lines is adjusted so that their total cross-sectional area equals the original main trunk line area. For example, if the original main trunk line width is 0.2mm, it is split into two sub-main trunk lines each with a width of 0.1mm. After the main trunk is split, the connections of the original cross-bridging routes are rematched, so that the bridging routes connect to the respective sub-main trunk routes, thus forming a new multi-path conduction structure. The updated line geometry is then recorded, and the corresponding structure of the original mesh cells is replaced. To ensure the adjustment effect, the thermal characteristic parameters of the mesh cell are recalculated after each split. If they are still higher than the threshold, the next round of splitting continues until the threshold requirement is met. The final interwoven mesh line structure achieves spatial dispersion of current paths while maintaining the total conductivity, thereby reducing the local thermal power surface density and eliminating the risk of thermal overshoot.

[0040] In step S7, printed circuit pattern data for photoplotting exposure is generated.

[0041] For the constructed visual transmission path offset vector field, each grid cell is processed individually. Based on the spatial location of the grid cell, its center coordinates are determined, and the corresponding offset vector information is extracted from the offset vector field. This vector consists of two parts: offset distance and offset direction. To ensure data stability, the offset vectors within the surrounding neighborhood of this location are averaged. In this embodiment, a nine-point region centered on the grid cell center and covering eight adjacent grid points is selected, and the average offset distance is taken as the representative offset distance of this grid cell, thus avoiding fluctuations caused by single-point measurement errors. Subsequently, the maximum continuous length of the line segment is determined based on the offset distance. The offset distance is normalized to map its range to between 0 and 1, and then converted into the corresponding continuous length ratio according to a preset mapping rule. In this embodiment, the maximum continuous length is set to 2mm, and the minimum is 0.5mm. When the normalized offset distance value is close to 1, the continuous length is 0.5mm; when the normalized value is close to 0, the continuous length is 2mm. The intermediate value is determined by linear interpolation, thus ensuring that the larger the offset, the shorter the line, avoiding visual overlap. Simultaneously, the misalignment spacing is determined based on the offset vector direction. The offset direction is projected onto the direction perpendicular to the seam, and its component in that direction is calculated. This component is then used as the base value for the misalignment spacing. The misalignment spacing is limited to the range of 0.2 mm to 1 mm. The maximum spacing is taken when the offset direction is consistent with the direction perpendicular to the seam, and it is reduced proportionally when the offset direction deviates. Through the above processing, each mesh cell obtains its corresponding maximum continuous length and misalignment spacing parameters, forming a continuously varying distribution in space.

[0042] Based on the obtained maximum continuous length, all continuous traces in the interwoven mesh network are segmented. Specifically, for each continuous trace, it is divided along the line direction according to the maximum continuous length, starting from its starting point. When this length is reached, it is truncated, leaving blank segments at fixed intervals at the truncated positions. In this embodiment, the blank segment length is set to 0.2mm by default. This value is determined by the photoplotting processing capability to ensure the manufacturability of the graphic. This operation is repeated for the entire line until it is completely divided into several discontinuous segments. After completing the truncation within a single grid cell, the adjacent grid cells are staggered. According to the obtained staggering distance, the starting positions of the discontinuous segments in adjacent grid cells are translated and adjusted so that the discontinuous segments of adjacent cells are staggered in the vertical seam direction. For example, when the starting point of the discontinuous segment of the current grid cell is at position 0, the starting point of the adjacent cell is offset by 0.5mm in the vertical direction, thereby avoiding the visual alignment and superposition of discontinuous segments. After completing the discontinuity and misalignment processing of all grid cells, the geometric coordinates of all line segments are uniformly organized. The start-point coordinates, end-point coordinates, and line width information of each line segment are encoded according to the format required by the photoplotting equipment. Using a standard vector path description method, each line segment is represented as a coordinate sequence with attached line width attribute information. Finally, the line segment data within all grid cells are summarized to form a complete printed circuit board graphic data file. This file is directly used by the photoplotting exposure equipment to perform graphic transfer, thereby achieving circuit layout based on visual offset compensation.

[0043] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0044] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0045] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0046] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0047] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0048] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0049] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0050] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0051] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for implementing printed circuit layout on an LED display glass substrate, characterized in that, Includes the following steps: S1. Under the unloaded state of the glass substrate, inject a preset calibration heat power into the pad position of the driver chip, collect the steady-state temperature distribution on the surface of the glass substrate and construct a two-dimensional equivalent thermal resistance distribution map. S2. Based on the observation distance and glass substrate thickness parameters, calculate the lateral offset generated when incident light from the back of the glass substrate passes through the front of the glass substrate, and construct the visual transmission path offset vector field. S3. Taking the edge of the glass substrate seam as the starting boundary, a gradual transition zone with a width that overlaps with the thermal influence radius in the two-dimensional equivalent thermal resistance distribution diagram is defined along the vertical seam direction. The gradual transition zone is divided into a sequence of grid cells arranged along the direction. S4. Assign an initial value to the trace area ratio of the grid cell sequence by coupling the two-dimensional equivalent thermal resistance distribution of the corresponding region of the grid cell and the visual transmission path offset vector field, and generate a geometric description of the interwoven mesh line with a multi-branch intersection shape within the grid cell. S5. Using the two-dimensional equivalent thermal resistance distribution map as the thermal characteristic constraint parameter, perform steady-state current field simulation on the geometric description of the interwoven mesh line, and extract the Joule thermal power surface density value corresponding to each mesh unit as the unit thermal characteristic parameter. S6. Compare the unit thermal characteristic parameters with the thermal power surface density threshold corresponding to the allowable thermal stress of the glass substrate, and perform circuit topology splitting operation on the grid units that exceed the threshold. S7. The topology-adjusted interwoven mesh lines are transformed into a discontinuous line segment array according to the visual transmission path offset vector field, and the line segment arrays in all grid cells are merged to generate printed circuit graphic data for photoplotting exposure.

2. The method for implementing printed circuit layout on an LED display glass substrate according to claim 1, characterized in that, In step S1, constructing the two-dimensional equivalent thermal resistance distribution map specifically includes: In a static environment where the glass substrate is without a driving signal, a preset constant thermal power is injected into the pad position of the driver chip. Full-frame temperature images of the glass substrate surface are acquired at fixed time intervals. When the maximum temperature difference between adjacent frames is lower than the preset fluctuation threshold, the current frame is taken as the steady-state temperature distribution image. Based on the difference between the temperature value of each pixel in the steady-state temperature distribution image and the preset ambient reference temperature, as well as the injected calibration heat power value, the equivalent thermal resistance value is calculated pixel by pixel and summarized to generate a two-dimensional equivalent thermal resistance distribution map indexed by the plane coordinates of the glass substrate.

3. The method for implementing printed circuit layout on an LED display glass substrate according to claim 1, characterized in that, In step S2, constructing the visual transmission path offset vector field specifically includes: The vertical distance from the set observation position to the front of the glass substrate is extracted as the observation distance parameter, and the glass substrate forming thickness is extracted as the glass substrate thickness parameter. Based on the calibrated refractive index constant, combined with the observation distance parameter and the glass substrate thickness parameter, the lateral offset distance between the propagation path of the light rays incident from the back of the glass substrate inside the glass substrate and the path of the light rays emitted to the observation position is calculated. The glass substrate plane is divided into discrete coordinates. For each coordinate point, the lateral offset distance and offset direction are calculated to generate a visual transmission path offset vector field indexed by the coordinates of the glass substrate plane and containing two components: offset distance and offset direction.

4. The method for implementing printed circuit layout on an LED display glass substrate according to claim 1, characterized in that, In S3, the gradually transitioning region whose width overlaps with the thermal influence radius in the two-dimensional equivalent thermal resistance distribution diagram specifically includes: Extract the attenuation curve of the equivalent thermal resistance value located at the edge of the glass substrate seam and extending along the direction perpendicular to the seam from the two-dimensional equivalent thermal resistance distribution map. Identify the spatial position of the equivalent thermal resistance value from the peak value at the seam edge to the specified attenuation ratio on the attenuation curve and determine the straight-line distance from the position to the seam edge as the thermal influence radius. Using the edge of the glass substrate seam as the starting boundary, a region with a length equal to the heat-affected radius is cut along the direction perpendicular to the seam as a gradient transition zone. The gradient transition zone is discretized into strips of equal width along the direction parallel to the seam, and each strip is then divided at equal intervals along the direction perpendicular to the seam to form a grid unit sequence arranged in rows and columns.

5. The method for implementing printed circuit layout on an LED display glass substrate according to claim 1, characterized in that, In step S4, generating the geometric description of the interwoven network with multi-branch intersections specifically includes: The average equivalent thermal resistance within the coverage area of ​​each grid cell is extracted from the two-dimensional equivalent thermal resistance distribution map, and the offset distance of the corresponding spatial position of each grid cell is extracted from the visual transmission path offset vector field. The coupling characteristic quantity of the grid cell is calculated by nonlinearly correlating the average equivalent thermal resistance with the offset distance. The proportion of the coupling characteristic quantity of a mesh cell to the total coupling characteristic quantity of all mesh cells in the gradient transition region is determined as the initial value of the trace area ratio of that mesh cell. Within a single grid cell, at least two main trunk lines are laid out along the main direction of current conduction, and cross-bridging lines with non-zero angles to the main trunk lines are added between adjacent main trunk lines. The number of cross-bridging lines laid out is positively correlated with the initial value of the percentage of the grid cell's wiring area. The distribution of main lines and cross-bridging lines within all grid cells is summarized to form a geometric description of an interwoven network with multiple branching and crossing patterns.

6. The method for implementing printed circuit layout on an LED display glass substrate according to claim 1, characterized in that, In step S5, performing steady-state current field simulation on the geometric description of the interwoven network circuit specifically includes: The equivalent thermal resistance value within the coverage area of ​​each grid cell in the two-dimensional equivalent thermal resistance distribution map is extracted and used as the thermal characteristic constraint parameter of the corresponding grid cell. A numerical model of a conductive network, including the topology and geometric dimensions of the circuit, is constructed based on the geometric description of the interwoven mesh circuit. An equivalent driving current load corresponding to the calibrated thermal power is applied to the mesh nodes corresponding to the pads of the driver chip. Solve the potential distribution of each branch node and the current density vector flowing through each line segment in the conductive network model. Calculate the Joule thermal power surface density value based on the current density modulus of each line segment, the conductivity of the line material, and the geometric area of ​​the grid cell containing that line segment. Then, correct the Joule thermal power surface density value by combining it with the thermal characteristic constraint parameters of the corresponding grid cell, and use it as the element thermal characteristic parameter.

7. The method for implementing printed circuit layout on an LED display glass substrate according to claim 1, characterized in that, In step S6, the specific steps of performing the line topology splitting operation include: The allowable temperature difference threshold of the glass substrate without crack propagation is calculated based on the allowable thermal stress value, coefficient of thermal expansion and elastic modulus of the glass substrate material. The thermal power surface density threshold is obtained by using the allowable temperature difference threshold, the thermal conductivity of the glass substrate and the thickness of the glass substrate. Traverse all mesh cells and compare the element thermal characteristic parameters of each mesh cell with the thermal power surface density threshold. Mark mesh cells whose element thermal characteristic parameters exceed the thermal power surface density threshold as thermal over-limit cells. For the main trunk line in the current interwoven mesh line geometry description within the grid cell marked as thermal overlimit cell, perform symmetrical splitting, replace the original single main trunk line with at least two sub-main trunk lines that are equally spaced and connected in parallel, and the total cross-sectional area of ​​the split sub-main trunk lines is equal to the cross-sectional area of ​​the original main trunk line. Update the line geometry description corresponding to the thermal over-limit unit to obtain the interwoven mesh line geometry description after topology split correction.

8. The method for implementing printed circuit layout on an LED display glass substrate according to claim 1, characterized in that, In step S7, generating the printed circuit pattern data for photoplotting exposure specifically includes: The offset vector at the corresponding spatial position of each grid cell is extracted from the visual transmission path offset vector field. The maximum continuous length of the line segment in the grid cell is determined by the magnitude of the offset vector, and the misalignment distance between adjacent line segments in the vertical splice direction is determined by the direction of the offset vector. Based on the maximum continuous length, all continuous lines in the topology-adjusted interwoven network are cut into discontinuous segments, and the start and end positions of the discontinuous segments are staggered between adjacent grid cells according to the staggered spacing. The geometric coordinates of the discontinuous line segments after all grid cells have been truncated and misaligned are arranged in a format readable by a photoplotter and then output as printed circuit graphic data for photoplotting exposure.

Images