Read circuit for magnetic memory chip and MRAM

Abstract

This application provides a read circuit for a magnetic storage chip and an MRAM. The read circuit includes: a storage circuit, including a memory bit under test and a first transistor, the memory bit under test including a first free layer and a first reference layer; a reference circuit, including a reference memory bit and a second transistor, the reference memory bit including a second free layer and a second reference layer; a first interconnect line, including a first sub-connection line and a second sub-connection line, the first sub-connection line being connected to the first free layer; a second interconnect line, including a third sub-connection line and a fourth sub-connection line, the third sub-connection line being connected to the first reference layer through the first transistor; a first interconnect line, the second sub-connection line being connected to the second reference layer through the first interconnect line and the second transistor; and a second interconnect line, the fourth sub-connection line being connected to the second free layer through the second interconnect line. This application solves the problem in the prior art where designing two sets of read logic circuits in a single chip results in an excessively large chip area and high read power consumption.

Description

Technical Field

[0001] This application relates to the field of magnetic random access memory (MRAM) chip technology, and more specifically, to a read circuit for a magnetic memory chip and MRAM. Background Technology

[0002] Magnetic Random Access Memory (MRAM) chips utilize magnetic tunnel junctions (MTJs) to store information. MRAMs store data using the relative magnetic moments of two layers of magnetic materials. When the magnetic moments are in the same direction, the resistance is low, typically represented as "0". When the magnetic moments are in opposite directions, the resistance is high, typically represented as "1". To read stored data, the resistance of the stored bit needs to be known. A common method is to set an additional reference resistor, whose resistance value is between "0" and "1", and then compare the reference resistor with the resistance of the bit.

[0003] The read error rate is lowest when the reference resistor value is between the "0" and "1" states. Therefore, the reference resistor value of MRAM is adjusted to be between the "0" and "1" states before leaving the factory. However, as the temperature rises, the resistance of the "1" state will continuously decrease, causing the constant reference resistor value to fail to meet the requirement of always being between the "0" and "1" states at high and low temperatures. An effective solution is to use a reference resistor array composed of a "1" state MTJ and a constant reference resistor. As the temperature changes, the resistance of the AP state MTJ in the reference resistor also changes accordingly, and a special circuit can ensure that the reference resistor value is always between "0" and "1". However, this method has a major drawback: the "1" state reference MTJ is not stable enough under external conditions and may flip to the "0" state due to repeated readings, temperature, magnetic fields, etc., leading to read errors.

[0004] In conventional STT-MRAM (Spin-Transfer Torque Magnetoresistive Random Access Memory) read circuit design, the read current typically flows from the free layer to the reference layer, consistent with the current direction for writing "0". This can lead to "1" flipping to "0", a phenomenon known as RDR (Read Disturbance). This effect is clearly detrimental to the scheme described above, which uses the "1"-state MTJ as the reference resistor. Therefore, the patent "A Read Circuit and Method for MRAM, Temperature-Adaptive MRAM" proposes an improved read circuit design: the read current at the array flows from the free layer to the reference layer, while the read current of the reference resistor flows from the reference layer to the free layer. The advantage is that when the current of the reference resistor flows from the reference layer to the free layer, only the "0" flipping to "1" RDR effect occurs, while the reference resistor MTJ is in the "1" state and therefore this effect does not occur. Conversely, the current during read operation actually helps improve the stability of the "1" state. Therefore, this design can significantly improve the stability of the reference. The aforementioned patent proposes a circuit design but does not disclose specific implementation methods. One obvious approach is to design different read logic circuits for the array and the reference resistor to reverse the read current. However, designing two sets of read circuits in one chip would obviously increase the chip area and read power consumption, which is not the optimal solution.

[0005] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0006] The main objective of this application is to provide a read circuit and MRAM for a magnetic storage chip, so as to at least solve the problem in the prior art that designing two sets of read logic circuits in one chip to achieve reverse read current results in excessive chip area and high read power consumption.

[0007] To achieve the above objectives, according to one aspect of this application, a read circuit for a magnetic storage chip is provided, comprising: a storage circuit including a storage bit to be tested and a first transistor, the storage bit to be tested including a first free layer and a first reference layer, a first terminal of the first transistor being electrically connected to the first reference layer; a reference circuit including a reference storage bit and a second transistor, the reference storage bit including a second free layer and a second reference layer, a first terminal of the second transistor being electrically connected to the second reference layer; a first connection line located in a first plane, the first connection line including a first sub-connection line and a second sub-connection line, the first sub-connection line being electrically connected to the first free layer, the first connection line being a bit line or a source line; and a second connection line located in a second plane, the second connection line including a third sub-connection line. The third interconnect is a line and a fourth sub-connection line, the third sub-connection line being electrically connected to the second end of the first transistor, the second plane being parallel to the first plane, the second interconnect being the source line when the first interconnect is the bit line, and the second interconnect being the bit line when the first interconnect is the source line; a first interconnect located on the third plane, the first end of the first interconnect being electrically connected to the second sub-connection line, the second end of the first interconnect being electrically connected to the second end of the second transistor, the third plane being perpendicular to the first plane; a second interconnect located on the fourth plane, the first end of the second interconnect being electrically connected to the fourth sub-connection line, the second end of the second interconnect being electrically connected to the second free layer, the fourth plane being perpendicular to the first plane.

[0008] Optionally, the first interconnect includes: a first sub-interconnect and a second sub-interconnect that are perpendicular to each other, the first sub-interconnect being perpendicular to the first plane, a first end of the first sub-interconnect being the first end of the first interconnect, a second end of the first sub-interconnect being electrically connected to the first end of the second sub-interconnect, and a second end of the second sub-interconnect being the second end of the first interconnect. The second interconnect includes: a third sub-interconnect and a fourth sub-interconnect that are perpendicular to each other, the third sub-interconnect being perpendicular to the first plane, a first end of the third sub-interconnect being the first end of the second interconnect, a second end of the third sub-interconnect being electrically connected to the first end of the fourth sub-interconnect, and a second end of the fourth sub-interconnect being the second end of the second interconnect.

[0009] Optionally, the read circuit further includes: a third connection line, including a fifth sub-connection line and a sixth sub-connection line, wherein the fifth sub-connection line is electrically connected to the control terminal of the first transistor, the sixth sub-connection line is electrically connected to the control terminal of the second transistor, the third connection line is parallel to the first plane, and the third connection line is a word line.

[0010] Optionally, the reading circuit further includes: a reading logic circuit, a first terminal of which is electrically connected to the first connecting line, a second terminal of which is electrically connected to the second connecting line, the reading logic circuit being used to provide positive voltage to the first connecting line, and the reading logic circuit being used to provide negative voltage to the second connecting line.

[0011] Optionally, the reference storage bit is in an antiparallel state.

[0012] Optionally, both the first connecting wire and the second connecting wire are made of metal.

[0013] Optionally, both the first connecting wire and the second connecting wire are made of copper.

[0014] Optionally, the material of the third connecting line is metal.

[0015] Optionally, the material of the third connecting wire includes copper.

[0016] According to another aspect of this application, an MRAM is provided, including a read circuit for any of the magnetic storage chips described above.

[0017] Using the technical solution of this application, the read circuit of the magnetic storage chip includes a storage circuit, a reference circuit, a first connection line, a second connection line, a first interconnect line, and a second interconnect line. The storage circuit includes a storage bit under test and a first transistor. The storage bit under test includes a first free layer and a first reference layer. The first terminal of the first transistor is electrically connected to the first reference layer. The reference circuit includes a reference storage bit and a second transistor. The reference storage bit includes a second free layer and a second reference layer. The first terminal of the second transistor is electrically connected to the second reference layer. The first connection line includes a first sub-connection line and a second sub-connection line. The first sub-connection line is electrically connected to the first free layer. The second connection line includes a third sub-connection line and a fourth sub-connection line. The third sub-connection line is electrically connected to the second terminal of the first transistor. The first terminal of the first interconnect line is electrically connected to the second sub-connection line. The second terminal of the first interconnect line is electrically connected to the second terminal of the second transistor. The first terminal of the second interconnect line is electrically connected to the fourth sub-connection line. The second terminal of the second interconnect line is electrically connected to the second free layer. Compared to existing technologies that design two sets of read logic circuits within a single chip to achieve reverse read current, resulting in excessive chip area and high read power consumption, this application addresses the issue in the memory array region (i.e., the region where the memory circuit is located). In this application, the first sub-connection line connects to the first free layer, and the third sub-connection line connects to the first reference layer via a first transistor. During read operations, a positive voltage is applied to the first connection line (i.e., the first sub-connection line is positive voltage), and a negative voltage is applied to the second connection line (i.e., the third sub-connection line is negative voltage). The read current flows from the first free layer to the first reference layer. In the reference region (i.e., the region where the reference circuit is located), the second sub-connection line is electrically connected to the second transistor via a first interconnect line. The second transistor is electrically connected to the second reference layer. Therefore, the second sub-connection line is equivalent to… Electrically connected to the second reference layer, the fourth sub-connector is electrically connected to the second free layer via the second interconnect. During reading, the first connection is positively charged (i.e., the second sub-connector is positively charged), and the second connection is negatively charged (i.e., the fourth sub-connector is negatively charged). At this time, the read current flows from the second reference layer to the second free layer, ensuring that the read current of the reference circuit and the memory circuit are opposite. Only one set of read logic circuit needs to be designed, such that the read logic circuit applies positive voltage to the first connection and negative voltage to the second connection. This ensures that, with the same read logic circuit, the read current is reversed only by a small-scale modification of the metal traces (i.e., the first interconnect and the second interconnect), ensuring low read power consumption and a small chip area. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1A schematic diagram of the circuit structure of a read circuit for a magnetic storage chip provided in an embodiment of this application is shown.

[0020] The above figures include the following reference numerals:

[0021] 11. Memory bit under test; 12. First transistor; 13. Reference memory bit; 14. Second transistor; 15. First interconnect; 151. First sub-interconnect; 152. Second sub-interconnect; 16. Second interconnect; 161. Third sub-interconnect; 162. Fourth sub-interconnect; 17. First interconnect; 18. Second interconnect; 171. First sub-interconnect; 172. Second sub-interconnect; 181. Third sub-interconnect; 182. Fourth sub-interconnect; 19. Third interconnect; 191. Fifth sub-interconnect; 192. Sixth sub-interconnect; 20. First metal via; 21. Second metal via; 22. Third metal via; 23. Fourth metal via; 24. Fifth metal via. Detailed Implementation

[0022] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0024] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0025] As described in the background section, the prior art involves designing two sets of read logic circuits in a single chip to achieve reverse read current, resulting in an excessively large chip area and high read power consumption. To address these issues, embodiments of this application provide a read circuit for a magnetic storage chip and an MRAM.

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] This application provides a read circuit for a magnetic storage chip, such as... Figure 1 As shown, it includes:

[0028] The storage circuit includes a storage bit under test 11 and a first transistor 12. The storage bit under test 11 includes a first free layer and a first reference layer. The first terminal of the first transistor 12 is electrically connected to the first reference layer.

[0029] The reference circuit includes a reference storage bit 13 and a second transistor 14. The reference storage bit 13 includes a second free layer and a second reference layer. The first terminal of the second transistor 14 is electrically connected to the second reference layer.

[0030] The first connection line 15 is located in the first plane (not shown). The first connection line 15 includes a first sub-connection line 151 and a second sub-connection line 152. The first sub-connection line 151 is electrically connected to the first free layer. The first connection line 15 is a bit line or a source line.

[0031] The second connection line 16 is located in the second plane (not shown). The second connection line 16 includes a third sub-connection line 161 and a fourth sub-connection line 162. The third sub-connection line 161 is electrically connected to the second terminal of the first transistor 12. The second plane is parallel to the first plane. When the first connection line 15 is the bit line, the second connection line 16 is the source line. When the first connection line 15 is the source line, the second connection line 16 is the bit line.

[0032] The first interconnect line 17 is located in the third plane (not shown). The first end of the first interconnect line 17 is electrically connected to the second sub-connection line 152, and the second end of the first interconnect line 17 is electrically connected to the second end of the second transistor 14. The third plane is perpendicular to the first plane.

[0033] The second interconnect line 18 is located in the fourth plane (not shown). The first end of the second interconnect line 18 is electrically connected to the fourth sub-connection line 162, and the second end of the second interconnect line 18 is electrically connected to the second free layer. The fourth plane is perpendicular to the first plane.

[0034] According to the above embodiments, the read circuit of the magnetic storage chip includes a storage circuit, a reference circuit, a first connection line, a second connection line, a first interconnect line, and a second interconnect line. The storage circuit includes a storage bit under test (DUT) and a first transistor. The DUT includes a first free layer and a first reference layer. The first terminal of the first transistor is electrically connected to the first reference layer. The reference circuit includes a reference storage bit and a second transistor. The reference storage bit includes a second free layer and a second reference layer. The first terminal of the second transistor is electrically connected to the second reference layer. The first connection line includes a first sub-connection line and a second sub-connection line. The first sub-connection line is electrically connected to the first free layer. The second connection line includes a third sub-connection line and a fourth sub-connection line. The third sub-connection line is electrically connected to the second terminal of the first transistor. The first terminal of the first interconnect line is electrically connected to the second sub-connection line. The second terminal of the first interconnect line is electrically connected to the second terminal of the second transistor. The first terminal of the second interconnect line is electrically connected to the fourth sub-connection line. The second terminal of the second interconnect line is electrically connected to the second free layer. Compared to existing technologies that design two sets of read logic circuits within a single chip to achieve reverse read current, resulting in excessive chip area and high read power consumption, this application addresses the issue in the memory array region (i.e., the region where the memory circuit is located). In this application, the first sub-connection line connects to the first free layer, and the third sub-connection line connects to the first reference layer via a first transistor. During read operations, a positive voltage is applied to the first connection line (i.e., the first sub-connection line is positive voltage), and a negative voltage is applied to the second connection line (i.e., the third sub-connection line is negative voltage). The read current flows from the first free layer to the first reference layer. In the reference region (i.e., the region where the reference circuit is located), the second sub-connection line is electrically connected to the second transistor via a first interconnect line. The second transistor is electrically connected to the second reference layer. Therefore, the second sub-connection line is equivalent to… Electrically connected to the second reference layer, the fourth sub-connector is electrically connected to the second free layer via the second interconnect. During reading, the first connection is positively charged (i.e., the second sub-connector is positively charged), and the second connection is negatively charged (i.e., the fourth sub-connector is negatively charged). At this time, the read current flows from the second reference layer to the second free layer, ensuring that the read current of the reference circuit and the memory circuit are opposite. Only one set of read logic circuit needs to be designed, such that the read logic circuit applies positive voltage to the first connection and negative voltage to the second connection. This ensures that, with the same read logic circuit, the read current is reversed only by a small-scale modification of the metal traces (i.e., the first interconnect and the second interconnect), ensuring low read power consumption and a small chip area.

[0035] In this embodiment of the application, the first connection line is BL (Bit Line) and the second connection line is SL (Source Line).

[0036] In one alternative, such as Figure 1As shown in (b), the first interconnect line 17 includes: a first sub-interconnect line 171 and a second sub-interconnect line 172 that are perpendicular to each other. The first sub-interconnect line 171 is perpendicular to the first plane. The first end of the first sub-interconnect line 171 is the first end of the first interconnect line 17. The second end of the first sub-interconnect line 171 is electrically connected to the first end of the second sub-interconnect line 172. The second end of the second sub-interconnect line 172 is the second end of the first interconnect line 17. The second interconnect line 18 includes: a third sub-interconnect line 181 and a fourth sub-interconnect line 182 that are perpendicular to each other. The third sub-interconnect line 181 is perpendicular to the first plane. The first end of the third sub-interconnect line 181 is the first end of the second interconnect line 18. The second end of the third sub-interconnect line 181 is electrically connected to the first end of the fourth sub-interconnect line 182. The second end of the fourth sub-interconnect line 182 is the second end of the second interconnect line 18. In this embodiment, the vertical design of the first and second sub-interconnects, and the vertical design of the third and fourth sub-interconnects, achieves an effective layout in three-dimensional space, making the circuit design more compact and further saving chip space.

[0037] Specifically, the second sub-connecting line and the fourth sub-interconnecting line can be located at the same height or at different heights; this application does not impose specific limitations on this. In the embodiments of this application, as shown... Figure 1 As shown in (b), the second sub-connector 152 and the fourth sub-interconnector 182 are at the same height.

[0038] Specifically, the fourth sub-connecting line and the second sub-interconnecting line may be located at the same height or at different heights, and this application does not impose any specific restrictions on this.

[0039] Specifically, such as Figure 1 As shown, the first connecting line 15 and the second connecting line 16 are metal lines arranged in a plane; the first sub-interconnect line 171 and the third sub-interconnect line 181 are metal lines arranged in a vertical direction (that is, the first sub-interconnect line 171 and the third sub-interconnect line 181 are both vertical interconnect lines).

[0040] In other embodiments, such as Figure 1As shown, the above-mentioned read circuit further includes a third connection line 19, comprising a fifth sub-connection line 191 and a sixth sub-connection line 192. The fifth sub-connection line 191 is electrically connected to the control terminal of the first transistor 12, and the sixth sub-connection line 192 is electrically connected to the control terminal of the second transistor 14. The third connection line 19 is parallel to the first plane and is a word line. In this embodiment, the fifth and sixth sub-connection lines are electrically connected to the control terminals of the first and second transistors, respectively, so that the control signal can be effectively transmitted to the transistors, thereby realizing the control of the transistors.

[0041] Specifically, such as Figure 1 As shown, the first end of the first transistor 12 is electrically connected to the first reference layer through the first metal via 20, the second end of the first transistor 12 is electrically connected to the third sub-interconnect line 161 through the second metal via 21, and the control terminal of the first transistor 12 is electrically connected to the fifth sub-interconnect line 191 through the third metal via 22; the first end of the second transistor 14 is electrically connected to the second reference layer through the fourth metal via 23, the second end of the second transistor 14 is electrically connected to the second sub-interconnect line 172 through the fifth metal via 24, and the control terminal of the second transistor 14 is electrically connected to the sixth sub-interconnect line 192.

[0042] In some alternative solutions, the read circuit further includes a read logic circuit, wherein a first terminal of the read logic circuit is electrically connected to the first connection line, and a second terminal of the read logic circuit is electrically connected to the second connection line. The read logic circuit provides a positive voltage to the first connection line and a negative voltage to the second connection line. In this embodiment, the read logic circuit provides a positive voltage to the first connection line and a negative voltage to the second connection line, so that the read current of the memory bit under test flows from the first free layer to the first reference layer, while the read current of the reference memory bit flows from the second reference layer to the second free layer. This can reduce read interference effects, especially in the scheme using a "1"-state MTJ as the reference resistor, this design can significantly improve the stability of the reference.

[0043] In some exemplary embodiments, the reference memory bit is in an antiparallel state. In this embodiment, in the antiparallel state, the resistance value of the reference memory bit is more stable compared to other states (such as the parallel state), which helps to more accurately compare the resistance difference between the memory bit under test and the reference memory bit, thereby further improving the accuracy of data reading.

[0044] In other exemplary embodiments, both the first connecting line and the second connecting line are made of metal. In this embodiment, metal materials generally have excellent electrical conductivity, and using metal as the material for the connecting lines can reduce resistance loss of electrons during transmission and improve circuit efficiency.

[0045] In other embodiments, both the first connecting line and the second connecting line are made of copper. In this embodiment, copper is an excellent conductive material. Using copper as the material for the first and second connecting lines can further improve the conductivity of the circuit, further reduce resistance, and thus further improve the efficiency of the circuit.

[0046] According to some exemplary embodiments of this application, the material of the third connecting wire is metal. In this embodiment, metal materials generally have excellent electrical conductivity, and using metal as the material of the connecting wire can reduce the resistance loss of electrons during transmission and improve the efficiency of the circuit.

[0047] According to some other exemplary embodiments of this application, the material of the third connecting wire includes copper. In this embodiment, copper is an excellent conductive material, and using copper as the material of the third connecting wire can further improve the conductivity of the circuit, further reduce the resistance, and thus further improve the efficiency of the circuit.

[0048] This application also provides an MRAM, including a read circuit for any of the above-described magnetic storage chips.

[0049] In the above embodiments, the MRAM includes a read circuit for a magnetic storage chip. The read circuit includes a storage circuit, a reference circuit, a first connection line, a second connection line, a first interconnect line, and a second interconnect line. The storage circuit includes a memory bit under test (MDT) and a first transistor. The MMT includes a first free layer and a first reference layer. A first terminal of the first transistor is electrically connected to the first reference layer. The reference circuit includes a reference memory bit and a second transistor. The reference memory bit includes a second free layer and a second reference layer. A first terminal of the second transistor is electrically connected to the second reference layer. The first connection line includes a first sub-connection line and a second sub-connection line. The first sub-connection line is electrically connected to the first free layer. The second connection line includes a third sub-connection line and a fourth sub-connection line. The third sub-connection line is electrically connected to the second terminal of the first transistor. The first terminal of the first interconnect line is electrically connected to the second sub-connection line. The second terminal of the first interconnect line is electrically connected to the second terminal of the second transistor. The first terminal of the second interconnect line is electrically connected to the fourth sub-connection line. The second terminal of the second interconnect line is electrically connected to the second free layer. Compared to existing technologies that design two sets of read logic circuits within a single chip to achieve reverse read current, resulting in excessive chip area and high read power consumption, this application addresses the issue in the memory array region (i.e., the region where the memory circuit is located). In this application, the first sub-connection line connects to the first free layer, and the third sub-connection line connects to the first reference layer via a first transistor. During read operations, a positive voltage is applied to the first connection line (i.e., the first sub-connection line is positive voltage), and a negative voltage is applied to the second connection line (i.e., the third sub-connection line is negative voltage). The read current flows from the first free layer to the first reference layer. In the reference region (i.e., the region where the reference circuit is located), the second sub-connection line is electrically connected to the second transistor via a first interconnect line. The second transistor is electrically connected to the second reference layer. Therefore, the second sub-connection line is equivalent to… Electrically connected to the second reference layer, the fourth sub-connector is electrically connected to the second free layer via the second interconnect. During reading, the first connection is positively charged (i.e., the second sub-connector is positively charged), and the second connection is negatively charged (i.e., the fourth sub-connector is negatively charged). At this time, the read current flows from the second reference layer to the second free layer, ensuring that the read current of the reference circuit and the memory circuit are opposite. Only one set of read logic circuit needs to be designed, such that the read logic circuit applies positive voltage to the first connection and negative voltage to the second connection. This ensures that, with the same read logic circuit, the read current is reversed only by a small-scale modification of the metal traces (i.e., the first interconnect and the second interconnect), ensuring low read power consumption and a small chip area.

[0050] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0051] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0052] 1) In the read circuit of the magnetic storage chip of this application, the read circuit of the magnetic storage chip includes a storage circuit, a reference circuit, a first connection line, a second connection line, a first interconnect line, and a second interconnect line. The storage circuit includes a storage bit under test and a first transistor. The storage bit under test includes a first free layer and a first reference layer. The first terminal of the first transistor is electrically connected to the first reference layer. The reference circuit includes a reference storage bit and a second transistor. The reference storage bit includes a second free layer and a second reference layer. The first terminal of the second transistor is electrically connected to the second reference layer. The first connection line includes a first sub-connection line and a second sub-connection line. The first sub-connection line is electrically connected to the first free layer. The second connection line includes a third sub-connection line and a fourth sub-connection line. The third sub-connection line is electrically connected to the second terminal of the first transistor. The first terminal of the first interconnect line is electrically connected to the second sub-connection line. The second terminal of the first interconnect line is electrically connected to the second terminal of the second transistor. The first terminal of the second interconnect line is electrically connected to the fourth sub-connection line. The second terminal of the second interconnect line is electrically connected to the second free layer. Compared to existing technologies that design two sets of read logic circuits within a single chip to achieve reverse read current, resulting in excessive chip area and high read power consumption, this application addresses the issue in the memory array region (i.e., the region where the memory circuit is located). In this application, the first sub-connection line connects to the first free layer, and the third sub-connection line connects to the first reference layer via a first transistor. During read operations, a positive voltage is applied to the first connection line (i.e., the first sub-connection line is positive voltage), and a negative voltage is applied to the second connection line (i.e., the third sub-connection line is negative voltage). The read current flows from the first free layer to the first reference layer. In the reference region (i.e., the region where the reference circuit is located), the second sub-connection line is electrically connected to the second transistor via a first interconnect line. The second transistor is electrically connected to the second reference layer. Therefore, the second sub-connection line is equivalent to… Electrically connected to the second reference layer, the fourth sub-connector is electrically connected to the second free layer via the second interconnect. During reading, the first connection is positively charged (i.e., the second sub-connector is positively charged), and the second connection is negatively charged (i.e., the fourth sub-connector is negatively charged). At this time, the read current flows from the second reference layer to the second free layer, ensuring that the read current of the reference circuit and the memory circuit are opposite. Only one set of read logic circuit needs to be designed, such that the read logic circuit applies positive voltage to the first connection and negative voltage to the second connection. This ensures that, with the same read logic circuit, the read current is reversed only by a small-scale modification of the metal traces (i.e., the first interconnect and the second interconnect), ensuring low read power consumption and a small chip area.

[0053] 2) In the MRAM of this application, the MRAM includes a read circuit for a magnetic storage chip. The read circuit for the magnetic storage chip includes a storage circuit, a reference circuit, a first connection line, a second connection line, a first interconnect line, and a second interconnect line. The storage circuit includes a memory bit under test and a first transistor. The memory bit under test includes a first free layer and a first reference layer. The first terminal of the first transistor is electrically connected to the first reference layer. The reference circuit includes a reference memory bit and a second transistor. The reference memory bit includes a second free layer and a second reference layer. The first terminal of the second transistor is electrically connected to the second reference layer. The first connection line includes a first sub-connection line and a second sub-connection line. The first sub-connection line is electrically connected to the first free layer. The second connection line includes a third sub-connection line and a fourth sub-connection line. The third sub-connection line is electrically connected to the second terminal of the first transistor. The first terminal of the first interconnect line is electrically connected to the second sub-connection line. The second terminal of the first interconnect line is electrically connected to the second terminal of the second transistor. The first terminal of the second interconnect line is electrically connected to the fourth sub-connection line. The second terminal of the second interconnect line is electrically connected to the second free layer. Compared to existing technologies that design two sets of read logic circuits within a single chip to achieve reverse read current, resulting in excessive chip area and high read power consumption, this application addresses the issue in the memory array region (i.e., the region where the memory circuit is located). In this application, the first sub-connection line connects to the first free layer, and the third sub-connection line connects to the first reference layer via a first transistor. During read operations, a positive voltage is applied to the first connection line (i.e., the first sub-connection line is positive voltage), and a negative voltage is applied to the second connection line (i.e., the third sub-connection line is negative voltage). The read current flows from the first free layer to the first reference layer. In the reference region (i.e., the region where the reference circuit is located), the second sub-connection line is electrically connected to the second transistor via a first interconnect line. The second transistor is electrically connected to the second reference layer. Therefore, the second sub-connection line is equivalent to… Electrically connected to the second reference layer, the fourth sub-connector is electrically connected to the second free layer via the second interconnect. During reading, the first connection is positively charged (i.e., the second sub-connector is positively charged), and the second connection is negatively charged (i.e., the fourth sub-connector is negatively charged). At this time, the read current flows from the second reference layer to the second free layer, ensuring that the read current of the reference circuit and the memory circuit are opposite. Only one set of read logic circuit needs to be designed, such that the read logic circuit applies positive voltage to the first connection and negative voltage to the second connection. This ensures that, with the same read logic circuit, the read current is reversed only by a small-scale modification of the metal traces (i.e., the first interconnect and the second interconnect), ensuring low read power consumption and a small chip area.

[0054] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A read circuit for a magnetic storage chip, characterized in that, include: A storage circuit includes a storage bit under test and a first transistor. The storage bit under test includes a first free layer and a first reference layer. A first terminal of the first transistor is electrically connected to the first reference layer. A reference circuit includes a reference memory bit and a second transistor. The reference memory bit includes a second free layer and a second reference layer. A first terminal of the second transistor is electrically connected to the second reference layer. A first connection line is located in a first plane. The first connection line includes a first sub-connection line and a second sub-connection line. The first sub-connection line is electrically connected to the first free layer. The first connection line is a bit line or a source line. The second connection line is located in the second plane. The second connection line includes a third sub-connection line and a fourth sub-connection line. The third sub-connection line is electrically connected to the second terminal of the first transistor. The second plane is parallel to the first plane. When the first connection line is the bit line, the second connection line is the source line. When the first connection line is the source line, the second connection line is the bit line. A first interconnect line is located in a third plane. A first end of the first interconnect line is electrically connected to a second sub-connect line, and a second end of the first interconnect line is electrically connected to a second end of the second transistor. The third plane is perpendicular to the first plane. The second interconnect is located in the fourth plane. The first end of the second interconnect is electrically connected to the fourth sub-connector, and the second end of the second interconnect is electrically connected to the second free layer. The fourth plane is perpendicular to the first plane.

2. The read circuit of the magnetic storage chip according to claim 1, characterized in that, The first interconnect includes: a first sub-interconnect and a second sub-interconnect that are perpendicular to each other. The first sub-interconnect is perpendicular to the first plane. A first end of the first sub-interconnect is the first end of the first interconnect. A second end of the first sub-interconnect is electrically connected to the first end of the second sub-interconnect. A second end of the second interconnect is the second end of the first interconnect. The second interconnect includes a third sub-interconnect and a fourth sub-interconnect that are perpendicular to each other. The third sub-interconnect is perpendicular to the first plane. The first end of the third sub-interconnect is the first end of the second interconnect. The second end of the third sub-interconnect is electrically connected to the first end of the fourth sub-interconnect. The second end of the fourth sub-interconnect is the second end of the second interconnect.

3. The read circuit of the magnetic storage chip according to claim 1, characterized in that, The reading circuit also includes: The third connection line includes a fifth sub-connection line and a sixth sub-connection line. The fifth sub-connection line is electrically connected to the control terminal of the first transistor, and the sixth sub-connection line is electrically connected to the control terminal of the second transistor. The third connection line is parallel to the first plane and is a word line.

4. The read circuit of the magnetic storage chip according to claim 1, characterized in that, The reading circuit also includes: A read logic circuit is provided, wherein a first terminal of the read logic circuit is electrically connected to the first connection line, a second terminal of the read logic circuit is electrically connected to the second connection line, the read logic circuit is used to provide positive voltage to the first connection line, and the read logic circuit is used to provide negative voltage to the second connection line.

5. The read circuit of the magnetic storage chip according to claim 1, characterized in that, The reference storage bit is in an antiparallel state.

6. The read circuit of the magnetic storage chip according to claim 1, characterized in that, Both the first connecting wire and the second connecting wire are made of metal.

7. The read circuit of the magnetic storage chip according to claim 6, characterized in that, Both the first connecting wire and the second connecting wire are made of copper.

8. The read circuit of the magnetic storage chip according to claim 3, characterized in that, The material of the third connecting line is metal.

9. The read circuit of the magnetic storage chip according to claim 8, characterized in that, The material of the third connecting wire includes copper.

10. An MRAM, characterized in that, The read circuit includes the magnetic storage chip according to any one of claims 1 to 9.

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