Bootstrapped charge pump structure

Abstract

This invention discloses a bootstrap charge pump structure, comprising: a clock control logic circuit, a bootstrap switch array, a boost capacitor, and an input voltage buffer. The clock control logic circuit is connected to the bootstrap switch array and is used to generate a four-phase non-overlapping clock to control the orderly activation of the switches in the bootstrap switch array. The bootstrap switch array is connected to the boost capacitor, and the clock control logic circuit boosts the voltage of the boost capacitor. The input voltage buffer is connected to the bootstrap switch array and is used to provide an adjustable voltage input to the bootstrap switch array. This invention improves the charge transfer efficiency of the charge pump and reduces resistance, representing an efficient bootstrap charge pump structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a bootstrap charge pump structure. Background Technology

[0002] With the rapid development of integrated circuit design, on-chip integrated voltage conversion circuits have been widely used. Among them, charge pump circuits, which can generate voltages higher than the chip's power supply, play an important role in various electronic devices. The on-chip integrated charge pump circuit was proposed by Dickson in 1976, initially using a diode and capacitor structure to achieve voltage multiplication. Since MOS switches can be equivalent to diodes in Dickson's bootstrap charge pump structure, with innovations in semiconductor manufacturing and design technologies, various types of bootstrap charge pump structures based on MOS switches have gradually emerged, such as four-phase clock charge pumps and cross-coupled charge pumps, as well as various improved circuits for these structures.

[0003] In a four-phase clock charge pump based on MOS switches, the effective turn-on of the MOS switches, especially at low supply voltages, directly determines the efficiency of the charge pump. However, during chip manufacturing, the threshold voltage of the MOS switches is difficult to keep constant, resulting in process variations. High-threshold MOS switches exhibit extremely poor conduction characteristics under low voltage conditions. Furthermore, traditional techniques address the problem of excessive on-resistance in MOS switches by increasing their size. However, this approach not only fails to overcome the increased resistance caused by manufacturing deviations, but its on-resistance is also modulated by the input voltage. When the input voltage approaches half the supply voltage, unacceptably high resistance values ​​appear in the bootstrap charge pump structure, leading to a significant deterioration in charge pump efficiency and reliability.

[0004] Furthermore, bootstrap switches are commonly used in existing technologies for sampling switches in ADCs to improve sampling accuracy, or to increase the control voltage of the switch by utilizing charge pumps to improve switching efficiency. However, bootstrap switch structures are rarely applied to charge pumps to increase the gate voltage of the MOS switch within the charge pump, thereby addressing the issues of low efficiency and poor reliability of charge pumps at low voltages. Therefore, a new bootstrap charge pump structure is urgently needed to circumvent the negative impacts of MOS switch threshold voltage dispersion and power supply voltage reduction, ensuring efficient and stable operation of the charge pump. Summary of the Invention

[0005] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by the present invention is to provide a bootstrap charge pump structure that can improve the charge transfer efficiency of a charge pump, reduce resistance, and improve efficiency.

[0007] To solve the above-mentioned technical problems, the present invention provides a bootstrap charge pump structure, comprising: a clock control logic circuit 1, a bootstrap switch array 2, a boost capacitor 3, and an input voltage buffer 4; The clock control logic circuit 1 is connected to the bootstrap switch array 2 and is used to generate four-phase non-overlapping clocks CK1, CK2, CK3, and CK4 to control the orderly opening of the switches in the bootstrap switch array 2. The bootstrap switch array 2 is connected to the boost capacitor 3, and the boost capacitor 3 is boosted by the clock control logic circuit 1. The input voltage buffer 4 is connected to the bootstrap switch array 2 and is used to provide an adjustable voltage input to the bootstrap switch array 2.

[0008] Preferably, the bootstrap charge pump structure is further improved, wherein the bootstrap switch array 2 includes eight bootstrap switches, namely the first bootstrap switch to the eighth bootstrap switch S0, S1, S2, S3, S4, S5, S6, and S7. One end of the first boot switch, the third boot switch, the fifth boot switch, and the seventh boot switch S0, S2, S4, and S6 is connected to the first end CAPL of the boot switch array 2; The second boot switch, the fourth boot switch, the sixth boot switch, and the eighth boot switch S1, S3, S5, and S7 are connected at one end to the second terminal CAPH of the boot switch array 2. The first bootstrap switch S0 is connected to the third voltage input terminal VL3 of the bootstrap switch array 2 at the other end. The second bootstrap switch S1 is connected at one end to the fourth voltage input terminal VL4 of the bootstrap switch array 2. The third bootstrap switch S2 is connected at one end to the second voltage input terminal VL2 of the bootstrap switch array 2. The fourth bootstrap switch S3 is connected at one end to the third voltage input terminal VL3 of the bootstrap switch array 2. The fifth bootstrap switch S4 is connected at one end to the first voltage input terminal VL1 of the bootstrap switch array 2. The sixth bootstrap switch S5 is connected at one end to the second voltage input terminal VL2 of the bootstrap switch array 2. The seventh boot switch S6 has its other end connected to ground; The eighth bootstrap switch S7 is connected at one end to the first voltage input terminal VL1 of the bootstrap switch array 2.

[0009] Preferably, the bootstrap charge pump structure is further improved, wherein the boost capacitor 3 includes capacitors CFLY (first capacitor) to CFLY (fifth capacitor), C1, C2, C3, and C4. The two ends of the first capacitor CFLY are respectively connected to the first terminal CAPL and the second terminal CAPH of the bootstrap switch array 2. The second capacitor C1 has one end connected to the first voltage input terminal VL1 of the bootstrap switch array 2, and the other end grounded. The third capacitor C2 has one end connected to the second voltage input terminal VL2 of the bootstrap switch array 2, and the other end grounded. The fourth capacitor C3 has one end connected to the third voltage input terminal VL3 of the bootstrap switch array 2, and the other end grounded. The fifth capacitor C4 has one end connected to the fourth voltage input terminal VL4 of the bootstrap switch array 2, and the other end grounded.

[0010] Preferably, the bootstrap charge pump structure is further improved in that the first clock CK1 of the clock control logic circuit 1 is connected to the seventh bootstrap switch S6 and the eighth bootstrap switch S7 of the bootstrap switch array 2 to control the opening of the seventh bootstrap switch S6 and the eighth bootstrap switch S7. The second clock CK2 is connected to the fifth boot switch S4 and the sixth boot switch S5 of the boot switch array 2, and controls the opening of the fifth boot switch S4 and the sixth boot switch S5. The third clock CK3 is connected to the third boot switch S2 and the fourth boot switch S3 of the boot switch array 2, and controls the opening of the third boot switch S2 and the fourth boot switch S3. The fourth clock CK4 is connected to the first boot switch S0 and the second boot switch S1 of the boot switch array 2, and controls the opening of the first boot switch S0 and the second boot switch S1.

[0011] Preferably, in a further improved version of the bootstrap charge pump structure, the timing relationship of the four-phase non-overlapping clocks CK1, CK2, CK3, and CK4 generated by the clock control logic circuit (1) is as follows: The first high-level pulse of the first clock CK1 is generated after the first high-level pulse of the second clock CK2. After three high-level pulses of the first clock CK1, the next high-level pulse of the second clock CK2 is generated. The first high-level pulse of the third clock CK3 is generated after the second high-level pulse of the first clock CK1, and the next high-level pulse of the third clock CK3 is generated after three high-level pulses of the first clock CK1. The first high-level pulse of the fourth clock CK4 is generated after the third high-level pulse of the first clock CK1, and then the next high-level pulse of the fourth clock CK4 is generated after three more high-level pulses of the first clock CK1, and so on.

[0012] Preferably, the bootstrap charge pump structure is further improved in that the input voltage Buffer4 is powered by the power supply voltage VDD, the input terminal is connected to the voltage reference source input VREF, and the output terminal is connected to the first voltage input terminal VL1 of the bootstrap switch array 2 and one end of the second capacitor C1 of the boost capacitor 3.

[0013] Preferably, the bootstrap charge pump structure is further improved, wherein the input voltage buffer 4 includes a first amplifier AMP1, a second amplifier AMP2, a first variable resistor R1, a second variable resistor R2, and a sixth PMOS transistor MP5; The non-inverting input of the first amplifier AMP1 is connected to VREF, the inverting input is connected to the lower end of the first variable resistor R1 and the upper end of the second variable resistor R2, and the output is connected to the gate of the sixth PMOS transistor MP5. The non-inverting input of the second amplifier AMP2 is connected to the upper end of the first variable resistor R1 and the drain of the sixth PMOS transistor MP5, while the inverting input is connected to its own output and the first voltage input VL1. The source of the sixth PMOS transistor MP5 is connected to the power supply voltage VDD; The lower end of the second variable resistor R2 is connected to ground.

[0014] Preferably, the bootstrap charge pump structure is further improved such that each bootstrap switch in the bootstrap switch array 2 has the same structure, including: first NMOS transistors to eighth NMOS transistors MN0, MN1, MN2, MN3, MN4, MN5, MN6, MN7, first PMOS transistors to fifth PMOS transistors MP0, MP1, MP2, MP3, MP4, and a sixth capacitor C0. The first NMOS transistor MN0 has its gate directly connected to the bootstrap control terminal VGATE to receive the high-voltage control signal after bootstrapping. Its drain is connected to the source of the sixth NMOS transistor MN5 and is connected to the input voltage VIN. Its source is directly connected to the output voltage VOUT to provide the output voltage to the load. The gate of the second NMOS transistor MN1 is connected to the gate of the second PMOS transistor MP1 and is simultaneously connected to the control clock CK. The drain of the second PMOS transistor MP1, the drain of the third NMOS transistor MN2, and the gate of the third PMOS transistor MP2 are all connected to the same node. The source of the second NMOS transistor MN1 is connected to the negative terminal of the sixth capacitor C0, the source of the third NMOS transistor MN2, the drain of the sixth NMOS transistor MN5, and the drain of the eighth NMOS transistor MN7 are all connected to the same node. The gate G of the third NMOS transistor MN2 is connected to the gate of the sixth NMOS transistor MN5 and is also connected to the bootstrap control terminal VGATE. The drain D is connected to the drain of the second NMOS transistor MN1, the drain of the second PMOS transistor MP1, and the gate of the third PMOS transistor MP2 at the same node. The source S is connected to the source of the second NMOS transistor MN1, the negative terminal of the sixth capacitor C0, the drain of the sixth NMOS transistor MN5, and the drain of the eighth NMOS transistor MN7 at the same node.

[0015] The gate of the fourth NMOS transistor MN3 is connected to the gate of the fourth PMOS transistor MP3 and is connected to the control clock CK. The drain of the fourth PMOS transistor MP3 and the gate of the eighth NMOS transistor MN7 are connected to the same node and are connected to the clock inversion input CKB. The source is grounded to GND. The gate of the sixth NMOS transistor MN5 is connected to the gate of the third NMOS transistor MN2 and is also connected to the bootstrap control terminal VGATE. The drain of the sixth NMOS transistor MN5 is connected to the source of the second NMOS transistor MN1, the source of the third NMOS transistor MN2, the negative terminal of the sixth capacitor C0, and the drain of the eighth NMOS transistor MN7 at the same node. The source of the sixth NMOS transistor MN5 is connected to the drain of the first NMOS transistor MN0 and is also connected to the input voltage VIN. The gate of the seventh NMOS transistor MN6 is connected to the source of the fifth PMOS transistor MP4 and is also connected to the power supply voltage VDD. The drain D is connected to the drain of the third PMOS transistor MP2 and the gate of the first PMOS transistor MP0 at the same node and is also connected to the bootstrap control terminal VGATE. The source S is connected to the drain of the fifth NMOS transistor MN4 and the drain of the fifth PMOS transistor MP4 at the same node.

[0016] The gate of the eighth NMOS transistor MN7 is connected to the same node as the drain of the fourth NMOS transistor MN3 and the drain of the fourth PMOS transistor MP3. The clock inverting input CKB is also connected to the same node. The drain is connected to the same node as the source of the second NMOS transistor MN1, the source of the third NMOS transistor MN2, the negative terminal of the sixth capacitor C0, and the drain of the sixth NMOS transistor MN5. The source is connected to ground GND. The gate of the fifth NMOS transistor MN4 is directly connected to the clock inverting input CKB. Its drain is connected to the same node as the source of the seventh NMOS transistor MN6 and the drain of the fifth PMOS transistor MP4. Its source S is grounded to GND. The gate of the first PMOS transistor MP0 is connected to the same node as the drain of the seventh NMOS transistor MN6 and the drain of the third PMOS transistor MP2, and is also connected to the bootstrap control terminal VGATE. The source S is connected to the same node as the gate of the seventh NMOS transistor MN6 and the source of the fifth PMOS transistor MP4, and is also connected to the power supply voltage VDD. The drain of the first PMOS transistor MP0 is connected to the same node as the source of the third PMOS transistor MP2 and the positive terminal of the sixth capacitor C0.

[0017] The gate of the second PMOS transistor MP1 is connected to the gate of the second NMOS transistor MN1, and is simultaneously connected to the control clock CK. The source is connected to the power supply voltage VDD, and the drain is connected to the drain of the second NMOS transistor MN1, the drain of the third NMOS transistor MN2, and the gate of the third PMOS transistor MP2 at the same node. The gate of the third PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN1, the drain of the third NMOS transistor MN2, and the drain of the second PMOS transistor MP1 at the same node. The source is connected to the drain of the first PMOS transistor MP0 and the positive terminal of the sixth capacitor C0 at the same node. The drain is connected to the drain of the seventh NMOS transistor MN6 and the gate of the first PMOS transistor MP0 at the same node. It is also connected to the bootstrap control terminal VGATE. The gate of the fourth PMOS transistor MP3 is connected to the gate of the fourth NMOS transistor MN3 and is connected to the control clock CK. The source is connected to the power supply voltage VDD. The drain is connected to the drain of the fourth NMOS transistor MN3 and the gate of the eighth NMOS transistor MN7 at the same node and is connected to the clock inversion input CKB. The gate of the fifth PMOS transistor MP4 is connected to the gate of the fifth NMOS transistor MN4, and the clock inversion input CKB is also connected to it. The source of the first PMOS transistor MP0 and the gate of the seventh NMOS transistor MN6 are connected to the same node, and the power supply voltage VDD is also connected to them. The drain of the fifth NMOS transistor MN4 and the source of the seventh NMOS transistor MN6 are connected to the same node. The positive terminal of the sixth capacitor C0 is connected to the same node as the drain of the first PMOS transistor MP0 and the source S of the third PMOS transistor MP2, and the negative terminal is connected to the same node as the source of the second NMOS transistor MN1, the source of the third NMOS transistor MN2, the drain of the sixth NMOS transistor MN5, and the drain of the eighth NMOS transistor MN7.

[0018] Compared with the prior art, the present invention can achieve at least the following technical effects; 1. Existing technologies that increase the size of MOS switches essentially reduce on-resistance by optimizing the structural parameters of the MOS transistor itself. However, the on-resistance of the MOS transistor is still determined by its inherent characteristics such as threshold voltage and input voltage. It cannot get rid of the modulation effect of the input voltage, and process deviations will directly cause changes in the threshold voltage, thereby affecting the on-resistance. Therefore, it cannot solve the problems caused by input voltage and process deviations. This invention employs a bootstrap switch array to replace traditional MOS switches. The bootstrap switch achieves gate voltage bootstrapping through a sixth capacitor C0. When the control clock CK is high, the bootstrap control terminal VGATE voltage is raised to the level of VIN+VDD, which is much higher than the gate control voltage of traditional MOS switches. This significantly reduces the on-resistance of the NMOS transistor MN0. Furthermore, this bootstrap mechanism is not significantly affected by input voltage fluctuations, effectively avoiding the modulation effect of input voltage on on-resistance. This results in a significant reduction in the on-resistance of the MOS switch, with minimal influence from input voltage and process variations, thus improving the charge transfer efficiency of the charge pump.

[0019] 2. Traditional charge pumps do not employ a bootstrap switching structure. The gate control voltage of the MOS switch is only the power supply voltage VDD. Under low power supply voltage, the gate-source voltage difference is insufficient, resulting in insufficient conduction of the MOS transistor and increased on-resistance. Furthermore, process deviations will further exacerbate the uncertainty of the threshold voltage, making it impossible for traditional structures to guarantee a stable low on-resistance under low voltage and process deviation conditions. This invention employs a bootstrap switch, whose on-resistance is primarily determined by the bootstrap effect of the bootstrap capacitor, rather than relying on the inherent characteristics of the MOS switch. Even if process variations cause changes in the MOS switch threshold voltage, the high gate voltage after bootstrapping still ensures full conduction of the switch, thereby reducing the impact of process variation on charge pump performance. This invention enhances the robustness of the charge pump to process variation, ensuring low on-resistance even with deviations in the MOS switch threshold voltage, thus guaranteeing stable operation of the charge pump.

[0020] 3. In the prior art, the application scenarios of bootstrap switches are limited to ADC sampling switches, etc., and they are not combined with the voltage multiplication mechanism of charge pumps. The gate voltage boosting advantage of bootstrap switches is not used to solve the conduction problem of MOS switches in charge pumps.

[0021] This invention employs a bootstrap switch. Under low power supply voltage conditions, the high gate-source voltage difference obtained by the bootstrap switch through gate voltage bootstrapping can compensate for the insufficient conduction capability of the MOSFET under low power supply voltage, ensuring that the switch still has a low on-resistance. This allows the charge pump to efficiently complete charge transfer and voltage multiplication even under low voltage conditions, improving the working performance of the charge pump under low power supply voltage, achieving efficient voltage multiplication under low voltage conditions, and expanding the application scenarios of the charge pump.

[0022] Because the bootstrap switch itself has low on-resistance, there is no need to increase the size of the switching transistor to reduce the resistance, thus avoiding the problem of increased leakage current caused by increasing the size of the switching transistor in traditional solutions. This improves efficiency while ensuring the low power consumption of the charge pump. Attached Figure Description

[0023] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the overall structure of the present invention.

[0024] Figure 2 This is a timing diagram of the present invention.

[0025] Figure 3 This is a schematic diagram of the bootstrap switch structure of the present invention.

[0026] Figure 4 This is a schematic diagram of the input voltage buffer structure of the present invention. Detailed Implementation

[0027] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the present invention is thorough and complete, and that the technical solutions of these exemplary embodiments are fully conveyed to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Other terms used to describe the relationship between elements or layers should be interpreted in the same way (e.g., “between” and “directly between”, “adjacent to” and “directly adjacent to”, “on” and “directly on”, etc.).

[0028] First embodiment; refer to Figure 1 As shown, the present invention provides a bootstrap charge pump structure, including: a clock control logic circuit 1, a bootstrap switch array 2, a boost capacitor 3, and an input voltage buffer 4; The clock control logic circuit 1 is connected to the bootstrap switch array 2 and is used to generate four-phase non-overlapping clocks CK1, CK2, CK3, and CK4 to control the orderly opening of the switches in the bootstrap switch array 2. The bootstrap switch array 2 is connected to the boost capacitor 3, and the boost capacitor 3 is boosted by the clock control logic circuit 1. The input voltage buffer 4 is connected to the bootstrap switch array 2 and is used to provide an adjustable voltage input to the bootstrap switch array 2.

[0029] Based on the main design concept of the first embodiment, the second to fifth embodiments are provided to illustrate preferred implementation methods of each component of the first embodiment.

[0030] Second embodiment; Continue to refer to Figure 1 As shown, the present invention provides a bootstrap switch array 2 for the first embodiment described above. The bootstrap switch array 2 includes eight bootstrap switches, namely the first bootstrap switch to the eighth bootstrap switch S0, S1, S2, S3, S4, S5, S6, and S7. One end of the first boot switch, the third boot switch, the fifth boot switch, and the seventh boot switch S0, S2, S4, and S6 is connected to the first end CAPL of the boot switch array 2; The second boot switch, the fourth boot switch, the sixth boot switch, and the eighth boot switch S1, S3, S5, and S7 are connected at one end to the second terminal CAPH of the boot switch array 2. The first bootstrap switch S0 is connected to the third voltage input terminal VL3 of the bootstrap switch array 2 at the other end. The second bootstrap switch S1 is connected at one end to the fourth voltage input terminal VL4 of the bootstrap switch array 2. The third bootstrap switch S2 is connected at one end to the second voltage input terminal VL2 of the bootstrap switch array 2. The fourth bootstrap switch S3 is connected at one end to the third voltage input terminal VL3 of the bootstrap switch array 2. The fifth bootstrap switch S4 is connected at one end to the first voltage input terminal VL1 of the bootstrap switch array 2. The sixth bootstrap switch S5 is connected at one end to the second voltage input terminal VL2 of the bootstrap switch array 2. The seventh boot switch S6 has its other end connected to ground; The eighth bootstrap switch S7 is connected at one end to the first voltage input terminal VL1 of the bootstrap switch array 2.

[0031] Third embodiment; Continue to refer to Figure 1 As shown, the present invention provides a boost capacitor 3 for the first embodiment described above, the boost capacitor 3 including capacitors CFLY, C1, C2, C3, and C4. The first capacitor CFLY is connected to the first terminal CAPL and the second terminal CAPH of the bootstrap switch array 2, respectively; the first capacitor CFLY is used to realize the transfer of charge between different nodes. The second capacitor C1 has one end connected to the first voltage input terminal VL1 of the bootstrap switch array 2, and the other end grounded. The third capacitor C2 has one end connected to the second voltage input terminal VL2 of the bootstrap switch array 2, and the other end grounded. The fourth capacitor C3 has one end connected to the third voltage input terminal VL3 of the bootstrap switch array 2, and the other end grounded. The fifth capacitor C4 has one end connected to the fourth voltage input terminal VL4 of the bootstrap switch array 2, and the other end grounded.

[0032] The second capacitor C1 through the fifth capacitor C4 are used to store the charge at nodes VL1 through VL4, thereby achieving voltage multiplication.

[0033] Fourth embodiment; refer to Figure 1 Combination Figure 2 As shown, the present invention provides a clock control logic circuit 1 for the first embodiment described above. The first clock CK1 of the clock control logic circuit 1 is connected to the seventh boot switch S6 and the eighth boot switch S7 of the boot switch array 2 to control the opening of the seventh boot switch S6 and the eighth boot switch S7. The second clock CK2 is connected to the fifth boot switch S4 and the sixth boot switch S5 of the boot switch array 2, and controls the opening of the fifth boot switch S4 and the sixth boot switch S5. The third clock CK3 is connected to the third boot switch S2 and the fourth boot switch S3 of the boot switch array 2, and controls the opening of the third boot switch S2 and the fourth boot switch S3. The fourth clock CK4 is connected to the first boot switch S0 and the second boot switch S1 of the boot switch array 2, and controls the opening of the first boot switch S0 and the second boot switch S1.

[0034] The timing relationship of the four-phase non-overlapping clocks CK1, CK2, CK3, and CK4 generated by the clock control logic circuit (1) is as follows: The first high-level pulse of the first clock CK1 is generated after the first high-level pulse of the second clock CK2. After three high-level pulses of the first clock CK1, the next high-level pulse of the second clock CK2 is generated. The first high-level pulse of the third clock CK3 is generated after the second high-level pulse of the first clock CK1, and the next high-level pulse of the third clock CK3 is generated after three high-level pulses of the first clock CK1. The first high-level pulse of the fourth clock CK4 is generated after the third high-level pulse of the first clock CK1, and then the next high-level pulse of the fourth clock CK4 is generated after three more high-level pulses of the first clock CK1, and so on.

[0035] Fifth embodiment; refer to Figure 4 As shown, the present invention provides an input voltage buffer 4 for the first embodiment described above. The input voltage buffer 4 is powered by the power supply voltage VDD, its input terminal is connected to the voltage reference source input VREF, and its output terminal is connected to the first voltage input terminal VL1 of the bootstrap switch array 2 and one end of the second capacitor C1 of the boost capacitor 3. The input voltage buffer 4 includes a first amplifier AMP1, a second amplifier AMP2, a first variable resistor R1, a second variable resistor R2, and a sixth PMOS transistor MP5. The non-inverting input of the first amplifier AMP1 is connected to VREF, the inverting input is connected to the lower end of the first variable resistor R1 and the upper end of the second variable resistor R2, and the output is connected to the gate of the sixth PMOS transistor MP5. The non-inverting input of the second amplifier AMP2 is connected to the upper end of the first variable resistor R1 and the drain of the sixth PMOS transistor MP5, while the inverting input is connected to its own output and the first voltage input VL1. The source of the sixth PMOS transistor MP5 is connected to the power supply voltage VDD; The lower end of the second variable resistor R2 is connected to ground.

[0036] Sixth embodiment; refer to Figure 3 As shown, the present invention provides a bootstrap switch structure for the first embodiment described above. Each bootstrap switch structure is identical, including: first NMOS transistors to eighth NMOS transistors MN0, MN1, MN2, MN3, MN4, MN5, MN6, MN7, first PMOS transistors to fifth PMOS transistors MP0, MP1, MP2, MP3, MP4, and a sixth capacitor C0. The first NMOS transistor MN0 has its gate directly connected to the bootstrap control terminal VGATE to receive the high-voltage control signal after bootstrapping. Its drain is connected to the source of the sixth NMOS transistor MN5 and is connected to the input voltage VIN. Its source is directly connected to the output voltage VOUT to provide the output voltage to the load. The gate of the second NMOS transistor MN1 is connected to the gate of the second PMOS transistor MP1 and is simultaneously connected to the control clock CK. The drain of the second PMOS transistor MP1, the drain of the third NMOS transistor MN2, and the gate of the third PMOS transistor MP2 are all connected to the same node. The source of the second NMOS transistor MN1 is connected to the negative terminal of the sixth capacitor C0, the source of the third NMOS transistor MN2, the drain of the sixth NMOS transistor MN5, and the drain of the eighth NMOS transistor MN7 are all connected to the same node. The gate G of the third NMOS transistor MN2 is connected to the gate of the sixth NMOS transistor MN5 and is also connected to the bootstrap control terminal VGATE. The drain D is connected to the drain of the second NMOS transistor MN1, the drain of the second PMOS transistor MP1, and the gate of the third PMOS transistor MP2 at the same node. The source S is connected to the source of the second NMOS transistor MN1, the negative terminal of the sixth capacitor C0, the drain of the sixth NMOS transistor MN5, and the drain of the eighth NMOS transistor MN7 at the same node.

[0037] The gate of the fourth NMOS transistor MN3 is connected to the gate of the fourth PMOS transistor MP3 and is connected to the control clock CK. The drain of the fourth PMOS transistor MP3 and the gate of the eighth NMOS transistor MN7 are connected to the same node and are connected to the clock inversion input CKB. The source is grounded to GND. The gate of the sixth NMOS transistor MN5 is connected to the gate of the third NMOS transistor MN2 and is also connected to the bootstrap control terminal VGATE. The drain of the sixth NMOS transistor MN5 is connected to the source of the second NMOS transistor MN1, the source of the third NMOS transistor MN2, the negative terminal of the sixth capacitor C0, and the drain of the eighth NMOS transistor MN7 at the same node. The source of the sixth NMOS transistor MN5 is connected to the drain of the first NMOS transistor MN0 and is also connected to the input voltage VIN. The gate of the seventh NMOS transistor MN6 is connected to the source of the fifth PMOS transistor MP4 and is also connected to the power supply voltage VDD. The drain D is connected to the drain of the third PMOS transistor MP2 and the gate of the first PMOS transistor MP0 at the same node and is also connected to the bootstrap control terminal VGATE. The source S is connected to the drain of the fifth NMOS transistor MN4 and the drain of the fifth PMOS transistor MP4 at the same node.

[0038] The gate of the eighth NMOS transistor MN7 is connected to the same node as the drain of the fourth NMOS transistor MN3 and the drain of the fourth PMOS transistor MP3. The clock inverting input CKB is also connected to the same node. The drain is connected to the same node as the source of the second NMOS transistor MN1, the source of the third NMOS transistor MN2, the negative terminal of the sixth capacitor C0, and the drain of the sixth NMOS transistor MN5. The source is connected to ground GND. The gate of the fifth NMOS transistor MN4 is directly connected to the clock inverting input CKB. Its drain is connected to the same node as the source of the seventh NMOS transistor MN6 and the drain of the fifth PMOS transistor MP4. Its source S is grounded to GND. The gate of the first PMOS transistor MP0 is connected to the same node as the drain of the seventh NMOS transistor MN6 and the drain of the third PMOS transistor MP2, and is also connected to the bootstrap control terminal VGATE. The source S is connected to the same node as the gate of the seventh NMOS transistor MN6 and the source of the fifth PMOS transistor MP4, and is also connected to the power supply voltage VDD. The drain of the first PMOS transistor MP0 is connected to the same node as the source of the third PMOS transistor MP2 and the positive terminal of the sixth capacitor C0.

[0039] The gate of the second PMOS transistor MP1 is connected to the gate of the second NMOS transistor MN1, and is simultaneously connected to the control clock CK. The source is connected to the power supply voltage VDD, and the drain is connected to the drain of the second NMOS transistor MN1, the drain of the third NMOS transistor MN2, and the gate of the third PMOS transistor MP2 at the same node. The gate of the third PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN1, the drain of the third NMOS transistor MN2, and the drain of the second PMOS transistor MP1 at the same node. The source is connected to the drain of the first PMOS transistor MP0 and the positive terminal of the sixth capacitor C0 at the same node. The drain is connected to the drain of the seventh NMOS transistor MN6 and the gate of the first PMOS transistor MP0 at the same node. It is also connected to the bootstrap control terminal VGATE. The gate of the fourth PMOS transistor MP3 is connected to the gate of the fourth NMOS transistor MN3 and is connected to the control clock CK. The source is connected to the power supply voltage VDD. The drain is connected to the drain of the fourth NMOS transistor MN3 and the gate of the eighth NMOS transistor MN7 at the same node and is connected to the clock inversion input CKB. The gate of the fifth PMOS transistor MP4 is connected to the gate of the fifth NMOS transistor MN4, and the clock inversion input CKB is also connected to it. The source of the first PMOS transistor MP0 and the gate of the seventh NMOS transistor MN6 are connected to the same node, and the power supply voltage VDD is also connected to them. The drain of the fifth NMOS transistor MN4 and the source of the seventh NMOS transistor MN6 are connected to the same node. The positive terminal of the sixth capacitor C0 is connected to the same node as the drain of the first PMOS transistor MP0 and the source S of the third PMOS transistor MP2, and the negative terminal is connected to the same node as the source of the second NMOS transistor MN1, the source of the third NMOS transistor MN2, the drain of the sixth NMOS transistor MN5, and the drain of the eighth NMOS transistor MN7.

[0040] Based on the above embodiments, the working process of the present invention is further described as follows; 1. The working process of the clock-controlled logic circuit: The clock control logic circuit outputs four non-overlapping clocks, from the first clock CK1 to the fifth clock CK4, as referenced. Figure 2As shown, there is a dead time between the rising and falling edges of each clock to avoid charge leakage caused by adjacent clocks conducting simultaneously. The timing relationship is as follows: the first high-level pulse of the first clock CK1 triggers the first high-level pulse of the second clock CK2, and after an interval of three high-level pulses of the first clock CK1, the second clock CK2 is triggered again; the second high-level pulse of the first clock CK1 triggers the first high-level pulse of the third clock CK3, and after an interval of three high-level pulses of the first clock CK1, the third clock CK3 is triggered again; the third high-level pulse of the first clock CK1 triggers the first high-level pulse of the fourth clock CK4, and after an interval of three high-level pulses of the first clock CK1, the fourth clock CK4 is triggered again, forming a six-phase operating timing sequence (Phase 0-Phase 5) in a cycle, providing timing control for the 4x voltage multiplier operation of the charge pump.

[0041] 2. The working process of the input voltage buffer: The input voltage buffer is powered by the power supply voltage VDD. The first amplifier AMP1 compares VREF with the feedback voltage and outputs a control signal to adjust the conduction level of the sixth PMOS transistor MP5. The second amplifier AMP2 forms a voltage follower to ensure the stability of the voltage at the VL1 terminal. By adjusting the resistance ratio of the first variable resistor R1 and the second variable resistor R2, the output voltage at the VL1 terminal can be precisely adjusted to provide the bootstrap switch array (2) with a modulated input voltage that meets the requirements.

[0042] 3. The collaborative operation process of the bootstrap switch array and the boost capacitor, based on the 4x voltage multiplier mode, reference... Figure 3 As shown: Phase 0: The fourth clock CK4 is valid, the bootstrap switches S0 and S1 are turned on, the charge at the VL3 terminal is transferred to the CAPL terminal through S0, the CAPH terminal is connected to the VL4 terminal through S1, and the flying capacitor CFLY begins pre-charging. Phase 1: The first clock CK1 is valid, the bootstrap switches S6 and S7 are turned on, the voltage at the VL1 terminal is transferred to the CAPH terminal through S7, the CAPH terminal is grounded through S6, and CFLY completes the charge transfer preparation. Phase 2: When the second clock CK2 is active, the bootstrap switches S4 and S5 are turned on. The voltage at the VL1 terminal is transferred to the CAPL terminal through S4, and the CAPH terminal is self-connected through S5. The voltage difference across the CFLY terminals is further stabilized. Phase 3: When the third clock CK3 is active, bootstrap switches S2 and S3 are turned on. Charge at the CAPH terminal is transferred to the VL3 terminal through S3, and charge at the VL2 terminal is transferred to the CAPH terminal through S2, thus realizing the cascade transfer of charge. Phase 4-Phase 5: The clock signal cycles through the switches, and each switch is turned on alternately according to the timing. Charge is transferred between CAPL, CAPH and VL1-VL4 terminals through CFLY. Energy storage capacitors C1-C4 store the charge of the corresponding nodes. Finally, a voltage VLCD of 4 times VIN is output at VL4 terminal, and a voltage of 2 times VLCD2 and a voltage of 3 times VLCD3 are output at VL2 and VL3 terminals respectively.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0044] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A bootstrap charge pump structure, characterized in that, include: Clock control logic circuit (1), bootstrap switch array (2), boost capacitor (3), and input voltage buffer (4); The clock control logic circuit (1) is connected to the bootstrap switch array (2) to generate four-phase non-overlapping clocks (CK1, CK2, CK3, CK4) to control the orderly opening of the switches in the bootstrap switch array (2); The bootstrap switch array (2) is connected to the boost capacitor (3), and the boost capacitor (3) is boosted by the clock control logic circuit (1); The input voltage buffer (4) is connected to the bootstrap switch array (2) and is used to provide an adjustable voltage input to the bootstrap switch array (2).

2. The bootstrap charge pump structure as described in claim 1, characterized in that: The bootstrap switch array (2) includes eight bootstrap switches, namely the first bootstrap switch to the eighth bootstrap switch (S0, S1, S2, S3, S4, S5, S6, S7). The first boot switch, the third boot switch, the fifth boot switch and the seventh boot switch (S0, S2, S4, S6) are connected at one end to the first end (CAPL) of the boot switch array (2). The second boot switch, the fourth boot switch, the sixth boot switch and the eighth boot switch (S1, S3, S5, S7) are connected at one end to the second end (CAPH) of the boot switch array (2); The first boot switch (S0) is connected to the third voltage input terminal (VL3) of the boot switch array (2). The second bootstrap switch (S1) is connected at one end to the fourth voltage input terminal (VL4) of the bootstrap switch array (2). The third bootstrap switch (S2) is connected at one end to the second voltage input terminal (VL2) of the bootstrap switch array (2); The fourth bootstrap switch (S3) is connected at one end to the third voltage input terminal (VL3) of the bootstrap switch array (2). The fifth bootstrap switch (S4) is connected at one end to the first voltage input terminal (VL1) of the bootstrap switch array (2). The sixth bootstrap switch (S5) is connected at one end to the second voltage input terminal (VL2) of the bootstrap switch array (2); The seventh boot switch (S6) has its other end connected to ground; The eighth bootstrap switch (S7) is connected at one end to the first voltage input terminal (VL1) of the bootstrap switch array (2).

3. The bootstrap charge pump structure as described in claim 2, characterized in that: The boost capacitor (3) includes capacitors one through five (CFLY, C1, C2, C3, C4). The first capacitor (CFLY) is connected to the first terminal (CAPL) and the second terminal (CAPH) of the bootstrap switch array (2) respectively. The second capacitor (C1) has one end connected to the first voltage input terminal (VL1) of the bootstrap switch array (2) and the other end grounded. The third capacitor (C2) has one end connected to the second voltage input terminal (VL2) of the bootstrap switch array (2), and the other end grounded. The fourth capacitor (C3) has one end connected to the third voltage input terminal (VL3) of the bootstrap switch array (2), and the other end grounded. The fifth capacitor (C4) has one end connected to the fourth voltage input terminal (VL4) of the bootstrap switch array (2), and the other end grounded.

4. The bootstrap charge pump structure as described in claim 2, characterized in that: The first clock (CK1) of the clock control logic circuit (1) is connected to the seventh boot switch (S6) and the eighth boot switch (S7) of the boot switch array (2) to control the opening of the seventh boot switch (S6) and the eighth boot switch (S7). The second clock (CK2) is connected to the fifth boot switch (S4) and the sixth boot switch (S5) of the boot switch array (2) to control the opening of the fifth boot switch (S4) and the sixth boot switch (S5); The third clock (CK3) is connected to the third boot switch (S2) and the fourth boot switch (S3) of the boot switch array (2) to control the opening of the third boot switch (S2) and the fourth boot switch (S3); The fourth clock (CK4) is connected to the first boot switch (S0) and the second boot switch (S1) of the boot switch array (2) to control the opening of the first boot switch (S0) and the second boot switch (S1).

5. The bootstrap charge pump structure as described in claim 1, characterized in that: The timing relationship of the four non-overlapping clocks (CK1, CK2, CK3, CK4) generated by the clock control logic circuit (1) is as follows: The first high-level pulse of the first clock (CK1) is generated after the first high-level pulse of the second clock (CK2), and the next high-level pulse of the second clock (CK2) is generated after three high-level pulses of the first clock (CK1). The first high-level pulse of the third clock (CK3) is generated after the second high-level pulse of the first clock (CK1), and the next high-level pulse of the third clock (CK3) is generated after three high-level pulses of the first clock (CK1). The third high-level pulse of the first clock (CK1) is followed by the first high-level pulse of the fourth clock (CK4). After three high-level pulses of the first clock (CK1), the next high-level pulse of the fourth clock (CK4) is generated, and the cycle repeats.

6. The bootstrap charge pump structure as described in claim 3, characterized in that: The input voltage buffer (4) is powered by the power supply voltage (VDD), the input terminal is connected to the voltage reference source input (VREF), and the output terminal is connected to the first voltage input terminal (VL1) of the bootstrap switch array (2) and one end of the second capacitor (C1) of the boost capacitor (3).

7. The bootstrap charge pump structure as described in claim 1, characterized in that: The input voltage buffer (4) includes a first amplifier (AMP1), a second amplifier (AMP2), a first variable resistor (R1), a second variable resistor (R2), and a sixth PMOS transistor (MP5). The non-inverting input of the first amplifier (AMP1) is connected to VREF, the inverting input is connected to the lower end of the first variable resistor (R1) and the upper end of the second variable resistor (R2), and the output is connected to the gate of the sixth PMOS transistor (MP5). The non-inverting input of the second amplifier (AMP2) is connected to the upper end of the first variable resistor (R1) and the drain of the sixth PMOS transistor (MP5), while the inverting input is connected to its own output and the first voltage input (VL1). The source of the sixth PMOS transistor (MP5) is connected to the power supply voltage (VDD); The lower end of the second variable resistor (R2) is connected to ground.

8. The bootstrap charge pump structure as described in any one of claims 1-7, characterized in that: Each bootstrap switch in the bootstrap switch array (2) has the same structure, including: the first NMOS transistor to the eighth NMOS transistor (MN0, MN1, MN2, MN3, MN4, MN5, MN6, MN7), the first PMOS transistor to the fifth PMOS transistor (MP0, MP1, MP2, MP3, MP4), and the sixth capacitor (C0). The first NMOS transistor (MN0) has its gate directly connected to the bootstrap control terminal (VGATE) to receive the high-voltage control signal after bootstrapping. Its drain is connected to the source of the sixth NMOS transistor (MN5) and is connected to the input voltage (VIN). Its source is directly connected to the output voltage (VOUT) to provide the output voltage to the load. The gate of the second NMOS transistor (MN1) is connected to the gate of the second PMOS transistor (MP1) and is simultaneously connected to the control clock CK. The drain of the second PMOS transistor (MP1), the drain of the third NMOS transistor (MN2), and the gate of the third PMOS transistor (MP2) are all connected to the same node. The source of the sixth capacitor (C0), the source of the third NMOS transistor (MN2), the drain of the sixth NMOS transistor (MN5), and the drain of the eighth NMOS transistor (MN7) are all connected to the same node. The gate (G) of the third NMOS transistor (MN2) is connected to the gate of the sixth NMOS transistor (MN5) and is also connected to the bootstrap control terminal (VGATE). The drain (D) is connected to the drain of the second NMOS transistor (MN1), the drain of the second PMOS transistor (MP1), and the gate of the third PMOS transistor (MP2) at the same node. The source (S) is connected to the source of the second NMOS transistor (MN1), the negative terminal of the sixth capacitor (C0), the drain of the sixth NMOS transistor (MN5), and the drain of the eighth NMOS transistor (MN7) at the same node. The gate of the fourth NMOS transistor (MN3) is connected to the gate of the fourth PMOS transistor (MP3) and is also connected to the control clock CK. The drain of the fourth PMOS transistor (MP3) and the gate of the eighth NMOS transistor (MN7) are connected to the same node and are also connected to the clock inversion input CKB. The source is grounded (GND). The gate of the sixth NMOS transistor (MN5) is connected to the gate of the third NMOS transistor (MN2) and is also connected to the bootstrap control terminal (VGATE). The drain of the sixth NMOS transistor (MN5) is connected to the source of the second NMOS transistor (MN1), the source of the third NMOS transistor (MN2), the negative terminal of the sixth capacitor (C0), and the drain of the eighth NMOS transistor (MN7) at the same node. The source of the sixth NMOS transistor (MN5) is connected to the drain of the first NMOS transistor (MN0) and is also connected to the input voltage VIN. The gate of the seventh NMOS transistor (MN6) is connected to the source of the fifth PMOS transistor (MP4) and is also connected to the power supply voltage VDD. Its drain (D) is connected to the drain of the third PMOS transistor (MP2) and the gate of the first PMOS transistor (MP0) at the same node and is also connected to the bootstrap control terminal (VGATE). Its source (S) is connected to the drain of the fifth NMOS transistor (MN4) and the drain of the fifth PMOS transistor (MP4) at the same node. The gate of the eighth NMOS transistor (MN7) is connected to the same node as the drain of the fourth NMOS transistor (MN3) and the drain of the fourth PMOS transistor (MP3), and is connected to the clock inversion input CKB. The drain of the eighth NMOS transistor (MN7) is connected to the same node as the source of the second NMOS transistor (MN1), the source of the third NMOS transistor (MN2), the negative terminal of the sixth capacitor (C0), and the drain of the sixth NMOS transistor (MN5). The source of the sixth NMOS transistor (MN7) is connected to ground (GND). The fifth NMOS transistor (MN4) has its gate directly connected to the clock inversion input CKB. Its drain is connected to the same node as the source of the seventh NMOS transistor (MN6) and the drain of the fifth PMOS transistor (MP4). Its source (S) is grounded (GND). The gate of the first PMOS transistor (MP0) is connected to the drain of the seventh NMOS transistor (MN6) and the drain of the third PMOS transistor (MP2) at the same node, and is also connected to the bootstrap control terminal (VGATE). The source (S) is connected to the gate of the seventh NMOS transistor (MN6) and the source of the fifth PMOS transistor (MP4) at the same node, and is also connected to the power supply voltage (VDD). The drain is connected to the source of the third PMOS transistor (MP2) and the positive terminal of the sixth capacitor (C0) at the same node. The gate of the second PMOS transistor (MP1) is connected to the gate of the second NMOS transistor (MN1) and is simultaneously connected to the control clock CK. The source is connected to the power supply voltage VDD, and the drain is connected to the drain of the second NMOS transistor (MN1), the drain of the third NMOS transistor (MN2), and the gate of the third PMOS transistor (MP2) at the same node. The gate of the third PMOS transistor (MP2) is connected to the drain of the second NMOS transistor (MN1), the drain of the third NMOS transistor (MN2), and the drain of the second PMOS transistor (MP1) at the same node. The source is connected to the drain of the first PMOS transistor (MP0) and the positive terminal of the sixth capacitor (C0) at the same node. The drain is connected to the drain of the seventh NMOS transistor (MN6) and the gate of the first PMOS transistor (MP0) at the same node. It is also connected to the bootstrap control terminal (VGATE). The gate of the fourth PMOS transistor (MP3) is connected to the gate of the fourth NMOS transistor (MN3) and is connected to the control clock CK. The source is connected to the power supply voltage VDD. The drain is connected to the drain of the fourth NMOS transistor (MN3) and the gate of the eighth NMOS transistor (MN7) at the same node and is connected to the clock inversion input CKB. The gate of the fifth PMOS transistor (MP4) is connected to the gate of the fifth NMOS transistor (MN4) and is also connected to the clock inversion input CKB; the source is connected to the same node as the source of the first PMOS transistor (MP0) and the gate of the seventh NMOS transistor (MN6) and is also connected to the power supply voltage VDD; the drain is connected to the same node as the drain of the fifth NMOS transistor (MN4) and the source of the seventh NMOS transistor (MN6). The positive terminal of the sixth capacitor (C0) is connected to the same node as the drain of the first PMOS transistor (MP0) and the source (S) of the third PMOS transistor (MP2), and the negative terminal is connected to the same node as the source of the second NMOS transistor (MN1), the source of the third NMOS transistor (MN2), the drain of the sixth NMOS transistor (MN5), and the drain of the eighth NMOS transistor (MN7).

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