A charge pump circuit, a PCB board and a controller

Abstract

This invention discloses a charge pump circuit, a PCB board, and a controller. The sources of a first, second, third, and fourth field-effect transistor (FET) are connected to a power supply terminal. One end of a first capacitor is connected to a first clock signal terminal, and the other end is connected to the drain of the first FET, the gate of the second FET, and the gate of the third FET. One end of a second capacitor is connected to a second clock signal terminal, and the other end is connected to the gate of the first FET, the drain of the second FET, and the gate of the fourth FET. One end of a third capacitor is connected to a third clock signal terminal, and the other end is connected to the drain of the third FET and the input terminal of a signal suppression unit. One end of a fourth capacitor is connected to a fourth clock signal terminal, and the other end is connected to the drain of the fourth FET and the input terminal of a switching unit. The output terminal of the signal suppression unit is connected to the enable terminal of the switching unit, and the output terminal of the switching unit is connected to one end of a fifth capacitor, the other end of which is grounded. This circuit manages the charge transfer process in an orderly manner through the signal suppression unit, reducing output voltage ripple.

Description

Technical Field

[0001] This invention relates to the field of charge pump technology, and in particular to a charge pump circuit, PCB board and controller. Background Technology

[0002] While current charge pump circuits can meet basic voltage boosting requirements, their overall output ripple is relatively large in practical applications due to limitations in circuit structure and control methods. The charging and discharging process relies entirely on simple clock signal switching, causing significant fluctuations in the load voltage with each charge-discharge cycle. This results in poor output voltage stability, severely impacting the performance of subsequent analog circuits and making them unsuitable for applications requiring high voltage stability and interference immunity, such as high-precision ADC / DAC reference voltage generation, on-chip EEPROM programming voltage generation, and low-noise LDO pre-boost modules.

[0003] It is evident that existing technologies still need improvement and enhancement. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a charge pump circuit that, by introducing an ordered charge transfer control mechanism, can reduce the ripple of the output voltage, improve voltage stability, and thus improve the working efficiency of the subsequent analog circuit.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A charge pump circuit includes a first field-effect transistor (FET) M1, a second field-effect transistor (FET) M2, a third field-effect transistor (FET) M3, a fourth field-effect transistor (FET) M4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a signal suppression unit, a switching unit, and a fifth capacitor C5. The sources of the first FET M1, the second FET M2, the third FET M3, and the fourth FET M4 are connected to an external power supply. One end of the first capacitor C1 is connected to an external first clock signal terminal, and the other end of the first capacitor C1 is connected to the drain of the first FET M1, the gate of the second FET M2, and the gate of the third FET M3. One end of the second capacitor C2 is connected to an external second clock signal terminal. The other end of the second capacitor C2 is connected to the gate of the first field-effect transistor M1, the drain of the second field-effect transistor M2, and the gate of the fourth field-effect transistor M4. One end of the third capacitor C3 is connected to an external third clock signal terminal, and the other end of the third capacitor C3 is connected to the drain of the third field-effect transistor M3 and the input terminal of the signal suppression unit. One end of the fourth capacitor C4 is connected to an external fourth clock signal terminal, and the other end of the fourth capacitor C4 is connected to the drain of the fourth field-effect transistor M4 and the input terminal of the switching unit. The output terminal of the signal suppression unit is connected to the enable terminal of the switching unit. The output terminal of the switching unit is connected to one end of the fifth capacitor C5, and the other end of the fifth capacitor C5 is connected to an external power supply terminal.

[0006] In the charge pump circuit, the signal suppression unit includes a Schmitt trigger SIMIT1 and an inverter INV1. The input terminal of the Schmitt trigger SIMIT1 is connected to the drain of the third field-effect transistor M3, the output terminal of the Schmitt trigger SIMIT1 is connected to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 is connected to the enable terminal of the switching unit.

[0007] The charge pump circuit further includes a dynamic voltage regulator unit, which is located between the output terminal of the signal suppression unit and the enable terminal of the switching unit, and is also connected to the output terminal of the switching unit. The dynamic voltage regulator unit is used to compare the output voltage of the fifth capacitor C5 with a reference voltage. When the output voltage is greater than the reference voltage, the switching signal output by the signal suppression unit is suppressed.

[0008] In the charge pump circuit, the dynamic voltage regulation unit includes a resistance adjustment section, an operational amplifier OP1, and a reference voltage supply section. The input terminal of the resistance adjustment section is connected to the output terminal of the signal suppression unit, the output terminal of the resistance adjustment section is connected to the enable terminal of the switching unit, the output terminal of the operational amplifier OP1 is connected to the enable terminal of the resistance adjustment section, the inverting input terminal of the operational amplifier OP1 is connected to the reference voltage supply section, and the non-inverting input terminal of the operational amplifier OP1 is connected to the output terminal of the switching unit. The resistance adjustment section is used to adjust the total resistance value according to the output signal of the operational amplifier OP1.

[0009] In the charge pump circuit, the resistance adjustment section includes a fifth field-effect transistor M5, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The gate of the fifth field-effect transistor M5 is connected to the output terminal of the operational amplifier OP1. One end of the third resistor R3 is connected to the output terminal of the signal suppression unit, and the other end of the third resistor R3 is connected to the source of the fifth field-effect transistor M5 and one end of the fourth resistor R4. One end of the fifth resistor R5 is connected to the drain of the fifth field-effect transistor M5 and the other end of the fourth resistor R4, and the other end of the fifth resistor R5 is connected to the enable terminal of the switching unit.

[0010] In the charge pump circuit, a filter unit is provided between the output terminal of the dynamic voltage regulator unit and the enable terminal of the switching unit; the filter unit is used to filter the output signal of the dynamic voltage regulator unit.

[0011] In the charge pump circuit, the filtering unit includes a first filtering section and a second filtering section; the switching unit includes a sixth field-effect transistor M6 and a seventh field-effect transistor M7; the input terminals of the first filtering section and the second filtering section are respectively connected to the output terminal of the dynamic voltage regulator unit; the output terminal of the first filtering section is connected to the gate of the sixth field-effect transistor M6; the output terminal of the second filtering section is connected to the gate of the seventh field-effect transistor M7; the source of the sixth field-effect transistor M6 is connected to the source of the seventh field-effect transistor M7; the drain of the sixth field-effect transistor M6 is connected to one end of the fifth capacitor C5; and the drain of the seventh field-effect transistor M7 is connected to the drain of the fourth field-effect transistor M4.

[0012] In the charge pump circuit, the first filter section includes a first resistor R1 and a sixth capacitor C6; the second filter section includes a second resistor R2 and a seventh capacitor C7; one end of the first resistor R1 and the second resistor R2 are respectively connected to the output terminal of the dynamic voltage regulator unit, the other end of the first resistor R1 is connected to one end of the sixth capacitor C6 and the gate of the sixth field-effect transistor M6, the other end of the sixth capacitor C6 is grounded, the other end of the second resistor R2 is connected to one end of the seventh capacitor C7 and the gate of the seventh field-effect transistor M7, and the other end of the seventh capacitor C7 is grounded.

[0013] This application also provides a PCB board printed with the charge pump circuit described above.

[0014] This application also provides a controller that uses the charge pump circuit described above for operation control.

[0015] Beneficial effects: This invention provides a charge pump circuit. By setting a signal suppression unit to process the pump voltage signal, noise, kickback, or voltage spikes in the original signal can be suppressed to a certain extent, providing a cleaner and more reliable control logic for the switching unit. This reduces the probability of the switching unit malfunctioning due to interference signals, thus improving the reliability of the circuit operation. Secondly, by assigning control of the charge transfer path to a processed signal, the transfer of charge from the fourth capacitor C4 to the fifth capacitor C5 becomes more orderly and controllable. Compared with a simple direct clock drive mode, this reduces the randomness and uncertainty of charge transfer timing. This orderly charge transfer mechanism, combined with the voltage regulation and filtering function of the fifth capacitor C5 at the output end, can effectively suppress the fluctuation amplitude of the output voltage at the load end and improve the output ripple characteristics. Attached Figure Description

[0016] Figure 1 The circuit structure diagram of the charge pump circuit provided by the present invention.

[0017] Explanation of key component symbols: 1-Signal suppression unit, 2-Switching unit, 3-Dynamic voltage regulation unit, 4-Filtering unit. Detailed Implementation

[0018] This invention provides a charge pump circuit, a PCB board, and a controller. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0019] In the description of this invention, it should be understood that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0020] Please see Figure 1 This invention provides a charge pump circuit, including a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a signal suppression unit 1, a switching unit 2, and a fifth capacitor C5. The sources of the first field-effect transistors M1, M2, M3, and M4 are all connected to an external power supply terminal VDD. One end of the first capacitor C1 is connected to an externally provided first clock signal terminal CLK1, and the other end is connected to the drain of the first field-effect transistor M1, the gate of the second field-effect transistor M2, and the gate of the third field-effect transistor M3. One end of the second capacitor C2 is connected to an externally provided second clock signal terminal CLK2, and the other end is connected to the gate of the first field-effect transistor M1, the drain of the second field-effect transistor M2, and the gate of the fourth field-effect transistor M4. One end of the third capacitor C3 is connected to the externally provided third clock signal terminal CLK3, and the other end is connected to the drain of the third field-effect transistor M3 and the input terminal of the signal suppression unit 1. One end of the fourth capacitor C4 is connected to the externally provided fourth clock signal terminal CLK4, and the other end is connected to the drain of the fourth field-effect transistor M4 and the input terminal of the switching unit 2. The output terminal of the signal suppression unit 1 is connected to the enable terminal of the switching unit 2 to control the switching of the switching unit 2. The output terminal of the switching unit 2 is connected to one end of the fifth capacitor C5, and the other end of the fifth capacitor C5 is grounded, forming the circuit's output voltage VOUT at that end. In this circuit, the first field-effect transistor M1 to the fourth field-effect transistor M4, and the first capacitor C1 to the fourth capacitor C4 constitute a cross-coupled charge pump boost circuit. When the first clock signal terminal CLK1 and the second clock signal terminal CLK2, the third clock signal terminal CLK3 and the fourth clock signal terminal CLK4 work alternately in an inverse relationship, the third capacitor C3 and the fourth capacitor C4 can be charged alternately, thereby generating a pump voltage higher than the power supply voltage VDD at the drain of the third field-effect transistor M3 and the fourth field-effect transistor M4.

[0021] In this embodiment, by setting up a signal suppression unit 1 to process the pump voltage signal, noise, backlash, or voltage spikes present in the original signal can be suppressed to a certain extent, providing a cleaner and more reliable control logic for the switching unit 2. This reduces the possibility of the switching unit 2 malfunctioning due to interference signals, which helps improve the reliability of the circuit operation. Secondly, by entrusting the control of the charge transfer path to a processed signal, the transfer of charge from the fourth capacitor C4 to the fifth capacitor C5 becomes more orderly and controllable. Compared with the simple clock direct drive mode, this reduces the randomness and uncertainty of charge transfer timing. This orderly charge transfer mechanism, combined with the voltage stabilization and filtering effect of the fifth capacitor C5 at the output end, can effectively suppress the fluctuation amplitude of the output voltage at the load end and improve the output ripple characteristics. This charge pump circuit can provide a more stable output voltage than the traditional structure, and its power supply quality is improved, making it more suitable for powering load circuits that are sensitive to voltage stability and noise, such as the reference voltage source of high-precision analog-to-digital converters or digital-to-analog converters, and the programming voltage of non-volatile memory.

[0022] The working principle of this application is as follows: The cross-coupled charge pump boost circuit, consisting of the first field-effect transistor M1, the second field-effect transistor M2, the third field-effect transistor M3, the fourth field-effect transistor M4, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, is the pumping part of the circuit. During operation, the first clock signal CLK1 and the second clock signal CLK2 are an inverted pair of clock signals, and the third clock signal CLK3 and the fourth clock signal CLK4 are another inverted pair of clock signals. These two pairs of clock signals control the charge pumping process. Specifically, when the clock signals change, the coupling effect of the first capacitor C1 and the second capacitor C2 drives the gate voltages of the first field-effect transistor M1 to the fourth field-effect transistor M4, causing the third field-effect transistor M3 and the fourth field-effect transistor M4 to alternately turn on and off, thereby alternately charging the third capacitor C3 and the fourth capacitor C4. This process can gradually pump charge from the power supply terminal VDD to a higher voltage point, that is, generate phase-interleaved pump voltages at the drains of the third field-effect transistor M3 and the fourth field-effect transistor M4 respectively.

[0023] The input of signal suppression unit 1 directly monitors the pump voltage signal from the drain of the third field-effect transistor M3 in the charge pump boost circuit. This unit processes the received pump voltage signal, which may contain noise or waveform distortion, to generate a relatively stable and deterministic control signal. This control signal is then sent to the enable terminal of switching unit 2 as the logical basis for commanding switching unit 2 to turn on or off. The input of switching unit 2 is connected to another pump voltage output point of the charge pump boost circuit, namely the drain of the fourth field-effect transistor M4. When switching unit 2 is turned on by the control signal output from signal suppression unit 1, the charge stored in the fourth capacitor C4 is transferred through switching unit 2 to the fifth capacitor C5, which serves as the output energy storage element, thereby establishing and maintaining the required output voltage VOUT.

[0024] To ensure a stable and reliable control signal for switching unit 2 and prevent false start-up due to noise or signal backlash, signal suppression unit 1 includes a Schmitt trigger (SIMIT1) and an inverter (INV1). The input of Schmitt trigger (SIMIT1) is connected to the drain of the third field-effect transistor (FET) M3 to receive the pump voltage signal from the charge pump core. Schmitt trigger (SIMIT1) exhibits hysteresis, shaping the input signal and suppressing uncertainties caused by glitches or slow changes, thus outputting a signal with a steep edge and a defined level. This signal is then inverted by inverter (INV1) and finally output to the enable terminal of switching unit 2. In this way, signal suppression unit 1 provides a relatively clean and stable control signal for switching unit 2.

[0025] To further improve the stability of the output voltage VOUT and achieve dynamic adjustment of its amplitude, this embodiment of the invention also provides a dynamic voltage regulator unit 3 between the output terminal of the signal suppression unit 1 and the enable terminal of the switching unit 2. This dynamic voltage regulator unit 3 is also connected to the output terminal of the switching unit 2. The dynamic voltage regulator unit 3 is used to compare the output voltage VOUT across the fifth capacitor C5 with an internal reference voltage VREF in real time. When the output voltage VOUT is detected to be higher than the set reference voltage VREF, the dynamic voltage regulator unit 3 can suppress or attenuate the switching control signal from the signal suppression unit 1 to a certain extent, thereby weakening the opening strength of the switching unit 2 or delaying its opening timing, slowing down the charging speed of the fifth capacitor C5, and causing the output voltage VOUT to drop; conversely, if the output voltage VOUT is too low, the suppression effect is weakened, and the charging efficiency is restored. This closed-loop regulation mechanism helps to stabilize the output voltage VOUT at a desired level, reducing output voltage fluctuations caused by load changes or power supply fluctuations.

[0026] Further, in one embodiment of the present invention, the dynamic voltage regulation unit 3 includes a resistance adjustment section, an operational amplifier OP1, and a reference voltage providing section. The input terminal of the resistance adjustment section is connected to the output terminal of the signal suppression unit 1, and its output terminal is connected to the enable terminal of the switching unit 2. The operational amplifier OP1 constitutes an error amplifier; its non-inverting input terminal is connected to the output terminal of the switching unit 2 to sample the output voltage VOUT, and its inverting input terminal is connected to the reference voltage providing section to receive the reference voltage VREF. The output terminal of the operational amplifier OP1 is connected to the enable terminal of the resistance adjustment section. The resistance adjustment section is used to dynamically adjust its equivalent resistance value in the signal path according to the error signal output by the operational amplifier OP1. When the output voltage VOUT is higher than the reference voltage VREF, the output level of the operational amplifier OP1 increases, causing the equivalent resistance value of the resistance adjustment section to increase, thereby producing a stronger voltage division attenuation effect on the control signal transmitted to the enable terminal of the switching unit 2, weakening the driving capability of the control signal; when the output voltage VOUT is lower than the reference voltage VREF, the adjustment process is reversed. By changing the impedance on the control signal path, linearization or gradient modulation of the switching behavior of the switching unit 2 is achieved, rather than simple on / off control, which is beneficial for achieving smoother voltage regulation.

[0027] It should be noted that the reference voltage supply unit is a bandgap reference voltage source. Its input terminal is connected to the external power supply terminal VDD, its ground terminal is grounded, and its output terminal is the output terminal of the reference voltage VREF.

[0028] To achieve the aforementioned resistance adjustment function, the resistance adjustment unit includes a fifth field-effect transistor (FET) M5, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The gate of the fifth FET M5 serves as the control terminal and is connected to the output of operational amplifier OP1. One end of the third resistor R3 serves as the input terminal of the resistance adjustment unit and is connected to the output of signal suppression unit 1. The other end of the third resistor R3 is connected to the source of the fifth FET M5 and one end of the fourth resistor R4. One end of the fifth resistor R5 is connected to the drain of the fifth FET M5 and the other end of the fourth resistor R4. The other end of the fifth resistor R5 serves as the output terminal of the resistance adjustment unit and is connected to the enable terminal of switching unit 2. The fifth FET M5 operates in the linear region, and its channel resistance is controlled by the gate voltage. The third resistor R3, the fourth resistor R4, the channel resistance of the fifth FET M5, and the fifth resistor R5 together form an adjustable voltage divider network. The change in the output voltage of operational amplifier OP1 will change the on-resistance of the fifth field-effect transistor M5, thereby changing the attenuation coefficient of the control signal of the entire voltage divider network and realizing the dynamic adjustment of the resistance value.

[0029] To filter out high-frequency noise or switching glitches that may exist in the output signal of the dynamic voltage regulator unit 3 and prevent them from interfering with the switching unit 2, a filter unit 4 may be provided between the output terminal of the dynamic voltage regulator unit 3 and the enable terminal of the switching unit 2 in this embodiment of the invention. The filter unit 4 can perform low-pass filtering on the control signal processed by the dynamic voltage regulator unit 3, making its edges smoother. This helps to reduce the current surge generated by the switching unit 2 at the moment of turning on and off, and further reduces output ripple and noise.

[0030] A specific structure of the switching unit 2 and the cooperating filtering unit 4 is as follows: The switching unit 2 includes a sixth field-effect transistor (FET) M6 and a seventh field-effect transistor (FET) M7. The filtering unit 4 includes a first filtering section and a second filtering section. The input terminals of the first filtering section and the second filtering section are connected to the output terminal of the dynamic voltage regulator unit 3, respectively, to generate filtered control signals to drive the sixth FET M6 and the seventh FET M7. The source of the sixth FET M6 is connected to the source of the seventh FET M7, and this connection point serves as the input terminal of the switching unit 2, connected to the drain of the fourth FET M4 and one end of the fourth capacitor C4. The drain of the sixth FET M6 serves as the output terminal of the switching unit 2, connected to one end of the fifth capacitor C5. The drain of the seventh FET M7 is connected to an intermediate node. The output terminal of the first filtering section is connected to the gate of the sixth FET M6, and the output terminal of the second filtering section is connected to the gate of the seventh FET M7. When the control signal from the dynamic voltage regulator unit 3 is at an effective level, after filtering, the sixth field-effect transistor M6 and the seventh field-effect transistor M7 are turned on, so that the charge stored on the fourth capacitor C4 can be transferred to the fifth capacitor C5 through the switching unit 2.

[0031] Specifically, the first filter section includes a first resistor R1 and a sixth capacitor C6; the second filter section includes a second resistor R2 and a seventh capacitor C7. One end of the first resistor R1 and the second resistor R2 together serve as the input terminal of the filter unit 4, connected to the output terminal of the dynamic voltage regulation unit 3. The other end of the first resistor R1 is connected to one end of the sixth capacitor C6 and the gate of the sixth field-effect transistor M6, and the other end of the sixth capacitor C6 is grounded. The other end of the second resistor R2 is connected to one end of the seventh capacitor C7 and the gate of the seventh field-effect transistor M7, and the other end of the seventh capacitor C7 is grounded. The first resistor R1 and the sixth capacitor C6 form an RC low-pass filter to smooth the gate voltage of the sixth field-effect transistor M6; similarly, the second resistor R2 and the seventh capacitor C7 form another RC low-pass filter to smooth the gate voltage of the seventh field-effect transistor M7. This design can effectively slow down the rise and fall edges of the gate voltage of the switching transistor, making its switching action smoother, thereby significantly reducing the high-frequency noise and ripple components introduced into the output voltage VOUT by the switching transient process.

[0032] In summary, by introducing signal suppression unit 1 to shape the pump control signal, the reliability of the control signal is increased; by introducing dynamic voltage regulation unit 3 to form a voltage negative feedback loop, automatic adjustment of the output voltage is achieved, improving the steady-state accuracy and load regulation of the output voltage; furthermore, by introducing filtering unit 4 to smooth the control signal that ultimately drives the switching transistor, the charge transfer process is made smoother. The synergistic effect of these measures effectively suppresses the output voltage ripple of the charge pump circuit, improving stability and anti-interference capabilities, thus better adapting to applications with high power quality requirements, such as high-precision analog circuits and non-volatile memory programming voltage generation.

[0033] This application also provides a PCB board printed with the charge pump circuit described above.

[0034] This application also provides a controller that uses the charge pump circuit described above for operation control.

[0035] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. A charge pump circuit, characterized in that, The system includes a first field-effect transistor (FET) M1, a second field-effect transistor (FET) M2, a third field-effect transistor (FET) M3, a fourth field-effect transistor (FET) M4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a signal suppression unit, a switching unit, and a fifth capacitor C5. The sources of the first FET M1, second FET M2, third FET M3, and fourth FET M4 are connected to an external power supply. One end of the first capacitor C1 is connected to an external first clock signal terminal, and the other end of the first capacitor C1 is connected to the drain of the first FET M1, the gate of the second FET M2, and the gate of the third FET M3. One end of the second capacitor C2 is connected to an external second clock signal terminal. The other end of capacitor C2 is connected to the gate of the first field-effect transistor M1, the drain of the second field-effect transistor M2, and the gate of the fourth field-effect transistor M4. One end of the third capacitor C3 is connected to an external third clock signal terminal, and the other end of the third capacitor C3 is connected to the drain of the third field-effect transistor M3 and the input terminal of the signal suppression unit. One end of the fourth capacitor C4 is connected to an external fourth clock signal terminal, and the other end of the fourth capacitor C4 is connected to the drain of the fourth field-effect transistor M4 and the input terminal of the switching unit. The output terminal of the signal suppression unit is connected to the enable terminal of the switching unit. The output terminal of the switching unit is connected to one end of the fifth capacitor C5, and the other end of the fifth capacitor C5 is connected to an external power supply terminal.

2. The charge pump circuit according to claim 1, characterized in that, The signal suppression unit includes a Schmitt trigger SIMIT1 and an inverter INV1. The input terminal of the Schmitt trigger SIMIT1 is connected to the drain of the third field-effect transistor M3. The output terminal of the Schmitt trigger SIMIT1 is connected to the input terminal of the inverter INV1. The output terminal of the inverter INV1 is connected to the enable terminal of the switching unit.

3. The charge pump circuit according to claim 1, characterized in that, It also includes a dynamic voltage regulator unit, which is located between the output terminal of the signal suppression unit and the enable terminal of the switching unit, and is also connected to the output terminal of the switching unit; the dynamic voltage regulator unit is used to compare the output voltage of the fifth capacitor C5 with the reference voltage, and when the output voltage is greater than the reference voltage, the switching signal output by the signal suppression unit is suppressed.

4. The charge pump circuit according to claim 3, characterized in that, The dynamic voltage regulation unit includes a resistance adjustment section, an operational amplifier OP1, and a reference voltage supply section. The input terminal of the resistance adjustment section is connected to the output terminal of the signal suppression unit, the output terminal of the resistance adjustment section is connected to the enable terminal of the switching unit, the output terminal of the operational amplifier OP1 is connected to the enable terminal of the resistance adjustment section, the inverting input terminal of the operational amplifier OP1 is connected to the reference voltage supply section, and the non-inverting input terminal of the operational amplifier OP1 is connected to the output terminal of the switching unit. The resistance adjustment section is used to adjust the total resistance value according to the output signal of the operational amplifier OP1.

5. The charge pump circuit according to claim 4, characterized in that, The resistance adjustment section includes a fifth field-effect transistor M5, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The gate of the fifth field-effect transistor M5 is connected to the output terminal of the operational amplifier OP1. One end of the third resistor R3 is connected to the output terminal of the signal suppression unit, and the other end of the third resistor R3 is connected to the source of the fifth field-effect transistor M5 and one end of the fourth resistor R4. One end of the fifth resistor R5 is connected to the drain of the fifth field-effect transistor M5 and the other end of the fourth resistor R4, and the other end of the fifth resistor R5 is connected to the enable terminal of the switching unit.

6. The charge pump circuit according to claim 3, characterized in that, A filtering unit is provided between the output terminal of the dynamic voltage regulator and the enable terminal of the switching unit; the filtering unit is used to filter the output signal of the dynamic voltage regulator.

7. The charge pump circuit according to claim 6, characterized in that, The filtering unit includes a first filtering section and a second filtering section; the switching unit includes a sixth field-effect transistor M6 and a seventh field-effect transistor M7; the input terminals of the first filtering section and the second filtering section are respectively connected to the output terminal of the dynamic voltage regulation unit; the output terminal of the first filtering section is connected to the gate of the sixth field-effect transistor M6; the output terminal of the second filtering section is connected to the gate of the seventh field-effect transistor M7; the source of the sixth field-effect transistor M6 is connected to the source of the seventh field-effect transistor M7; the drain of the sixth field-effect transistor M6 is connected to one end of the fifth capacitor C5; and the drain of the seventh field-effect transistor M7 is connected to the drain of the fourth field-effect transistor M4.

8. The charge pump circuit according to claim 7, characterized in that, The first filter section includes a first resistor R1 and a sixth capacitor C6; the second filter section includes a second resistor R2 and a seventh capacitor C7; one end of the first resistor R1 and the second resistor R2 are respectively connected to the output terminal of the dynamic voltage regulator unit, the other end of the first resistor R1 is connected to one end of the sixth capacitor C6 and the gate of the sixth field-effect transistor M6, and the other end of the sixth capacitor C6 is grounded; the other end of the second resistor R2 is connected to one end of the seventh capacitor C7 and the gate of the seventh field-effect transistor M7, and the other end of the seventh capacitor C7 is grounded.

9. A PCB board, characterized in that, The PCB board is printed with a charge pump circuit as described in any one of claims 1-8.

10. A controller, characterized in that, The controller employs a charge pump circuit as described in any one of claims 1-8.

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