A current steering cell circuit for constant on current source switch glitch compensation

Abstract

The present application belongs to the field of analog integrated circuit design, and particularly relates to a current steering cell circuit with normally-on current source switch glitch compensation. The present application is based on a normally-on current source and combines the concept of switch glitch compensation, improves the switch control logic of the normally-on current source, and multiplexes it as a redundant compensation current source: when switching from the last period to the current period, if the main current source switch is switched, the compensation current source remains in the original state; otherwise, if the main current source is not switched, the compensation current source will be state converted; a glitch current V CS is artificially introduced at the output end of the compensation current source to reduce the nonlinearity introduced by the glitch current. Without increasing the number of current sources, the present application can not only significantly suppress the switch glitch, but also effectively attenuate the coupling glitch energy from the output end, and finally greatly improve the dynamic performance with limited chip area.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design, specifically a current steering unit circuit for compensating glitches in a normally open current source switch. Background Technology

[0002] With the rapid development of technologies such as 5G mobile communication, radar detection, and high-speed test instruments, various radio frequency and microwave systems place extremely high demands on the conversion rate and output accuracy of data converters (DACs). Unlike R-2R ladder network DACs, which are mainly suitable for medium-speed and high-precision scenarios, current-steering DACs have irreplaceable advantages in achieving high-speed conversion at the hundreds of MHz and even GHz levels due to their inherent parallel processing capabilities and current output characteristics that can directly drive loads. Therefore, current-steering DACs are a core component in high-bandwidth scenarios such as wireless communication base stations and direct digital frequency synthesis (DDS).

[0003] Generally speaking, the dynamic performance of a current-controlled DAC, especially its spurious-free dynamic range (SFDR), directly determines the signal quality of the entire system. Improving SFDR and linearity hinges on optimizing the matching of the current source array and reducing transient distortion of the output signal. However, in deep submicron processes, gradient and random mismatches between current sources intensify with increasing precision. Simultaneously, switching glitches generated during high-speed switching of the digital control signal become a major bottleneck limiting performance. Due to physical effects such as clock feedthrough, charge injection, and switching timing mismatch, glitch energy is particularly significant under high-speed operation.

[0004] Traditional thermometer decoding structures, while ensuring a fixed output impedance and improving differential nonlinearity (DNL), experience significant state transitions due to numerous switching units at major input points. This leads to substantial instantaneous current spikes, severely degrading integral nonlinearity (INL) and SFDR. Therefore, effectively suppressing the nonlinear distortion introduced by switching glitches has become a core challenge in overcoming the performance bottleneck of high-speed, high-linearity current-controlled DACs. Virtual cells and dynamic element matching are common techniques for suppressing switching glitches, but the former requires the introduction of additional switches and current sources, increasing area overhead; the latter cannot effectively suppress glitches coupled from the output to the current source. Summary of the Invention

[0005] To address the aforementioned problems and solve the nonlinear distortion caused by inter-symbol interference during high-speed switching in existing current-driven DACs, this invention provides a current-driven unit circuit with normally open current source switching glitch compensation. This circuit is a high-linearity current-driven digital-to-analog converter circuit based on a normally open current source and incorporating the concept of switching glitch compensation, effectively suppressing the nonlinearity caused by switching glitch. Without increasing the number of current sources, this invention not only significantly suppresses switching glitch but also effectively attenuates the coupling glitch energy from the output, ultimately achieving a substantial improvement in dynamic performance with a limited chip area.

[0006] A current rudder unit circuit for compensating glitches in a normally open current source switch, as shown in the attached diagram. Figure 1 As shown, it includes: a switch and current source unit circuit and a complementary switch control signal generation circuit.

[0007] The switch and current source unit circuit (as shown in the attached) Figure 2 As shown in the figure, it includes: main current source module, compensation current source module, main switch module, compensation switch module and normally open switch module.

[0008] The main current source module includes NMOS transistors M1 and M2. The source of M1 is grounded, and its drain is connected to the source of M2. The gate of M1 is connected to the common-source bias voltage provided separately to the main current source module. The source of M2 is connected to the drain of M1, forming a cascaded current source. The gate of M2 is connected to the common-gate bias voltage provided separately to the main current source module. The drain of M2 is connected to node X1 as the output of the main current source module. The output current of the main current source module is defined as I0.

[0009] The main switching module includes NMOS transistors M3 and M4. The source terminal of M3 is connected to node X1, and the gate terminal is connected to the control signal. The drain of M4 is connected to node A; the source of M4 is connected to node X1, and the gate is connected to the control signal. The drain end connects to node B.

[0010] The compensation current source module includes NMOS transistors M5, M6, M9, and M10. The source of M5 is grounded, its drain is connected to the source of M6, and its gate is connected to the common-source bias voltage provided to the compensation current source module. The source of M6 is connected to the drain of M5, forming a cascaded current source. Its gate is connected to the common-gate bias voltage provided to the compensation current source module, and its drain serves as the compensation current I0' output terminal connected to node X2. M9 and M10 are connected in the same way as M5 and M6, and the drain of M10 serves as the compensation current I0' output terminal connected to node X3.

[0011] The compensation switching module includes NMOS transistors M7, M8, M11, and M12. The source terminal of M7 is connected to node X2, and the gate terminal is connected to the control signal. The drain of M8 is connected to node B; the source of M8 is connected to node X2, and the gate is connected to the control signal. The drain terminal is connected to node A. The source terminal of M11 is connected to node X3, and the gate terminal is connected to the control signal. The drain of M12 is connected to node B; the source of M12 is connected to node X3, and the gate is connected to the control signal. The drain is connected to node A. The control signal... and As complementary signals, and These are complementary signals, and switching control is achieved through the timing coordination of these signals.

[0012] The normally open switch module includes NMOS transistors M13 and M14. The source of M13 is connected to node A, the gate is connected to the bias voltage VB, and the drain is connected to the output terminal OUTP; the source of M14 is connected to node B, the gate is connected to the bias voltage VB, and the drain is connected to the output terminal OUTN.

[0013] The complementary switch control signal generation circuit generates the switching signals required to control the complementary switch through logic circuits.

[0014] Furthermore, the compensation current source module provides a bias path to the normally open switch module through the compensation switch module: when When the voltage is high, M7 and M12 are turned on, and the compensation current provides source current to M14 and M13 through M7 and M12, ensuring that M13 and M14 always remain on. Conversely, when the voltage is low... When it is low level, When the signal is high, M8 and M11 are turned on. The compensation current provides the source current for M13 and M14 through M8 and M11, ensuring that M13 and M14 are always turned on. The compensation current on both sides is consistent, and the value of the compensation current source I0' is less than that of the main current source I0.

[0015] Furthermore, the complementary switch control signal generation circuit includes two XNOR gates and two NOT gates, and the signals included are the current cycle data signals. Previous cycle data signal Switch detection signal Complementary switching detection signal and compensation switch control signal (as attached) Figure 1 (As shown).

[0016] Current period data signal Connected to one input of the XNOR gate XNOR1; the data signal from the previous cycle. Connected to the other input of the XNOR gate, the output of the XNOR gate generates a complementary switching detection signal. , Then, the switching detection signal is generated by the inverter INV1. ; This indicates whether the current period's data differs from the previous period's data. and When the logical values ​​are different, A high active level indicates that the compensation switch needs to undergo a state switch. Compensation switch control signal from the previous cycle Connect the XOR gate formed by XNOR2 and INV2. When When it is high level, = The compensation switch control signal switches, and vice versa. = The compensation switch control signal does not switch.

[0017] Furthermore, the ratio of the compensation current I0' output by the compensation current source module to the main current I0 output by the main current source module is configured to be 1 / 10 to 1 / 5; and the complementary switch control signal generation circuit is configured to control the compensation current source switch state to switch in the opposite direction based on whether the main current source switch state is switched, so that the total number of switching times of the main current source switch module and the compensation current source switch module remains constant in each clock cycle. Under this configuration, the data converter in which the current steering unit circuit is located can improve its spurious-free dynamic range by more than 5dB compared with the conventional circuit without this compensation structure, while introducing less additional power consumption.

[0018] In summary, this invention improves the switching control logic of a normally open current source by incorporating the concept of switching glitch compensation, reusing it as a redundant compensation current source: when switching from the previous cycle to the current cycle, if the main current source switch changes, the compensation current source maintains its original state; conversely, if the main current source does not change, the compensation current source will undergo a state transition; and a glitch current V is artificially introduced at the output of the compensation current source. CS This invention reduces the nonlinearity introduced by spurious current. Although the value I0' of the normally open current source is smaller than that of the main current source, subsequent modeling and simulation verification show that its spurious-free dynamic range (SFDR) can still be improved by more than 5dB when I0' = 0.2I0. Without increasing the number of current sources, this invention not only significantly suppresses switching glitches but also effectively attenuates the energy of coupling glitches from the output, ultimately achieving a significant improvement in dynamic performance with a limited chip area. Attached Figure Description

[0019] Figure 1 This is a schematic block diagram of the structure of the present invention.

[0020] Figure 2 This is a schematic block diagram of the switch and current source unit circuit of the present invention.

[0021] Figure 3 This is a schematic diagram of a traditional switch and current source unit circuit.

[0022] Figure 4 This is a schematic diagram illustrating the source of glitches in a traditional switch and current source unit circuit.

[0023] Figure 5 This is a timing diagram of the 3-bit current steering DAC in Example 3.

[0024] Figure 6 This is a schematic diagram illustrating the principle of burr energy optimization in this invention. Detailed Implementation

[0025] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0026] When the sampling rate reaches the GHz level, timing mismatch between switches can cause glitches during output switching. (See attached image) Figure 3 As shown, in a traditional current source compensation topology, the compensation current sources on both sides only ensure the operation of the normally open switch pair. When the main switch switches, although the voltage difference fluctuation across OUTP and OUTN is attenuated by the normally open switch pair, it still causes glitches at the current source output. Similarly, non-ideal characteristics of the switch, such as feedthrough and charge injection, also cause glitches at the current source drain, resulting in spike currents at the current source output.

[0027] Appendix Figure 4 The image shows the glitches generated during switching of a 1-bit current-controlled DAC using a traditional normally open current source compensation topology (V is used for ease of understanding). out V ideal and V glitch (The waveforms have all been simplified). It can be seen that the glitch voltage V... glitch Current state of the digital-to-analog converter and its previous state Closely related, this characteristic can be expressed by functions Description. Extending this to an N-bit current-controlled DAC, when the output jumps from the (n-1)th cycle to the nth cycle, there are a total of The switch changes state, and The switches remain in their original states. The total element switching rate (ETR) characterizes the number of switch switching events within a single cycle, and this error can be further expressed as:

[0028]

[0029] Existing glitch compensation techniques typically employ redundant current sources to ensure the total ETR value remains constant across all cycles, thereby maintaining a constant DAC output glitch amplitude and converting it into a value independent of the encoding to improve nonlinear distortion. However, this approach often results in additional area and power consumption overhead. Meanwhile, normally open current source structures are widely used in various designs due to their simple architecture, low parasitic capacitance at switching nodes, and high output impedance.

[0030] This invention provides a current steering unit circuit for compensating for switching glitches in a normally open current source. It is based on a normally open current source and incorporates the concept of switching glitches compensation. Figure 1 The structure shown includes: a switch and current source unit circuit and a complementary switch control signal generation circuit. Figure 2 This is a schematic block diagram of the switch and current source unit circuit of the present invention.

[0031] This invention improves the switching control logic of a normally open current source, reusing it as a redundant compensation current source. The control strategy is attached. Figure 6 As shown: When switching from the previous cycle to the current cycle, if the main current source switch changes (D)... IN [n-1]≠D IN [n]), the compensation current source remains in its original state (D CS [n-1] = D CS [n]); Conversely, if the main current source is not switched (D IN [n-1] = D IN [n]), the compensation current source will then undergo a state transition (D). CS [n-1]≠D CS [n]). A glitch current V is artificially introduced at the output of the compensation current source. CS This reduces the nonlinearity introduced by glitch current.

[0032] With attachment Figure 5 Taking the 3-digit thermometer code single-ended output DAC as an example: U0-U7 represent seven main current sources, and C0-C7 represent seven compensation current sources. In the first cycle, D... IN [1] When = 4, U0-U4 is turned on, U5-U7 is turned off, and C0-C7 is initially turned on; in the second cycle, D IN[2] When U5-U7 is 7, ETR_U = 3. To compensate for the unconducted main current source, C0-C4 is switched, i.e., ETR_C = 4. The total number of switches is ETR = ETR_U + ETR_C = 7. Similarly, ETR remains 7 in the third cycle, and the total number of switches remains constant across all cycles, thereby reducing nonlinear distortion caused by code-dependent switching activity. It is worth noting that although the value of the normally open current source I0' is usually smaller than that of the main current source (I0' = 0.2I0), its spurious-free dynamic range (SFDR) can still be improved by more than 5dB after modeling and simulation verification.

[0033] As can be seen from the above embodiments, this invention improves the switching control logic of a normally open current source by incorporating the concept of switching glitch compensation, reusing it as a redundant compensation current source: when switching from the previous cycle to the current cycle, if the main current source switch switches, the compensation current source maintains its original state; conversely, if the main current source does not switch, the compensation current source will undergo a state transition; a glitch current V is artificially introduced at the output of the compensation current source. CS This invention reduces the nonlinearity introduced by glitch current. Without increasing the number of current sources, it can not only significantly suppress switching glitches, but also effectively attenuate the coupling glitch energy from the output terminal. Ultimately, it achieves a significant improvement in dynamic performance with a limited chip area, achieving a good balance between area, power consumption and performance, without introducing additional switches and redundant current sources.

Claims

1. A current steering unit circuit for compensating glitches in a normally open current source switch, characterized in that, include: Switch and current source unit circuit and complementary switch control signal generation circuit; The switch and current source unit circuit includes: a main current source module, a compensation current source module, a main switch module, a compensation switch module, and a normally open switch module; The main current source module includes NMOS transistors M1 and M2; the source of M1 is grounded, the drain is connected to the source of M2, and the gate is connected to the common-source bias voltage provided separately to the main current source module; the source of M2 is connected to the drain of M1 to form a cascaded current source, and the gate is connected to the common-gate bias voltage provided separately to the main current source module. The drain of M2 is connected to node X1 as the output of the main current source module, and the output current of the main current source module is defined as I0. The main switching module includes NMOS transistors M3 and M4; the source of M3 is connected to node X1, and the gate is connected to the control signal. The drain of M4 is connected to node A; the source of M4 is connected to node X1, and the gate is connected to the control signal. The drain end connects to node B; The compensation current source module includes NMOS transistors M5, M6, M9, and M10. The source terminal of M5 is grounded, and its drain terminal is connected to the source terminal of M6. The gate terminal is connected to the common-source bias voltage provided to the compensation current source module. The source terminal of M6 is connected to the drain terminal of M5 to form a cascaded current source. The gate terminal is connected to the common-gate bias voltage provided to the compensation current source module. The drain terminal of M6 is connected to node X2 as the compensation current I0' output terminal. The connection method of M9 and M10 is the same as that of M5 and M6. The drain terminal of M10 is connected to node X3 as the compensation current I0' output terminal. The compensation switching module includes NMOS transistors M7, M8, M11, and M12; the source terminal of M7 is connected to node X2, and the gate terminal is connected to the control signal. The drain of M8 is connected to node B; the source of M8 is connected to node X2, and the gate is connected to the control signal. The drain of M11 is connected to node A; the source of M11 is connected to node X3, and the gate is connected to the control signal. The drain of M12 is connected to node B; the source of M12 is connected to node X3, and the gate is connected to the control signal. The drain is connected to node A; where the control signal... and As complementary signals, and These are complementary signals, and switching control is achieved through the timing coordination of these signals; The normally open switch module includes NMOS transistors M13 and M14; the source of M13 is connected to node A, the gate is connected to the bias voltage VB, and the drain is connected to the output terminal OUTP; the source of M14 is connected to node B, the gate is connected to the bias voltage VB, and the drain is connected to the output terminal OUTN. The complementary switch control signal generation circuit generates the switching signals required to control the complementary switch through logic circuits.

2. The current steering unit circuit for glitch compensation of normally open current source switch as described in claim 1, characterized in that: The compensation current source module provides a bias path to the normally open switch module through the compensation switch module: when When the level is high, M7 and M12 are turned on, and the compensation current provides the source current for M14 and M13 through M7 and M12, ensuring that M13 and M14 always remain in the on state. Conversely, when When it is low level, When the signal is high, M8 and M11 are turned on. The compensation current provides the source current for M13 and M14 through M8 and M11, ensuring that M13 and M14 are always turned on. The compensation current on both sides is consistent, and the value of the compensation current source I0' is less than that of the main current source I0.

3. The current steering unit circuit for glitch compensation of normally open current source switch as described in claim 1, characterized in that: The complementary switch control signal generation circuit includes two XOR gates and two NOT gates, and includes the current period data signal. Previous cycle data signal Switch detection signal Complementary switching detection signal and compensation switch control signal ; Current period data signal Connected to one input of the XNOR gate XNOR1; the data signal from the previous cycle. Connected to the other input of the XNOR gate, the output of the XNOR gate generates a complementary switching detection signal. , Then, the switching detection signal is generated by the inverter INV1. ; This indicates whether the current period's data differs from the previous period's data. and When the logical values ​​are different, A high active level indicates that the compensation switch needs to undergo a state switch. Compensation switch control signal from the previous cycle Connect the XOR gate formed by XNOR2 and INV2; when When it is high level, = The compensation switch control signal switches, and vice versa. = The compensation switch control signal does not switch.

4. The current steering unit circuit for glitch compensation of normally open current source switch as described in claim 1, characterized in that: The ratio of the compensation current I0' output by the compensation current source module to the main current I0 output by the main current source module is configured to be 1 / 10 to 1 / 5; and the complementary switch control signal generation circuit is configured to control the compensation current source switch state to switch in the opposite direction based on whether the main current source switch state is switched, so that the total number of switching times of the main current source switch module and the compensation current source switch module in each clock cycle remains constant.

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