A high-resolution two-step ADC for temperature sensing and electronic device

Abstract

The application provides a high-resolution two-step ADC for temperature sensing and an electronic device, and relates to the technical field of integrated circuits. A front-end buffer input end is coupled to a temperature-sensing front end; a switched capacitor integrator input end is coupled to an output end of the front-end buffer; a comparator input end is coupled to an output end of the switched capacitor integrator; a counter input end is coupled to an output end of the comparator; and a logic control unit input end is coupled to an output end of the comparator. The application proposes a structure of coarse quantization SDM+fine quantization SAR, without the need of additional high-speed counters, and the system power consumption and hardware complexity are reduced. By multiplexing the integration branch of the switched capacitor integrator, the comparator can not need to eliminate the offset voltage, further simplifying the comparator and the front-end buffer, and achieving the balance between high precision and low power consumption. The SDM can be high-speed running and has good noise performance for specific oversampling ratios, while realizing small chip integration size and low power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to a high-resolution two-step ADC and electronic device for temperature sensing. Background Technology

[0002] With the development of the Internet of Things (IoT), wearable devices, and intelligent sensing systems, there is a need to achieve extremely high equivalent resolution (ENOB) with the lowest possible power consumption under extremely low bandwidth conditions. Sound Distributed Modeling (SDM) is widely used in low-bandwidth, high-precision applications due to its noise shaping capabilities. However, for low-order SDM, high resolution can only be achieved by increasing its oversampling rate or the number of quantizer bits, which leads to slow overall circuit setup and high power consumption. Using high-order SDM results in complex loop structures, high design difficulty, and high-order integrators are susceptible to variations in process technology, temperature, and voltage. Therefore, while traditional SDM is suitable for high precision, it has limitations in terms of power consumption, complexity, and scalability. Summary of the Invention

[0003] In view of the above problems, this application proposes a high-resolution two-step ADC and electronic device for temperature sensing to overcome the shortcomings of the prior art.

[0004] In a first aspect, embodiments of this application provide a high-resolution two-step ADC for temperature sensing, comprising: A front-end buffer, whose input is coupled to the temperature sensing front end, is used to receive the analog input voltage from the temperature sensing front end, and to isolate the high impedance of the front end and drive the subsequent circuitry. A switched-capacitor integrator, whose input is coupled to the output of the front-end buffer, is used to sample the analog input voltage and transfer charge. A comparator, whose input is coupled to the output of the switched capacitor integrator, is used to compare the output voltage of the switched capacitor integrator and generate a comparison result. A counter, whose input is coupled to the output of the comparator, is used to count the comparison results to obtain a coarse quantization result; A logic control unit, whose input is coupled to the output of the comparator, is used to successively approximate the comparison result to obtain a fine quantization result; In a complete cycle, the switched capacitor integrator operates as a first-order Sigma-Delta modulator during the coarse quantization process. During the fine quantization process, the switched capacitor integrator and the comparator are reused to quantize the residual voltage remaining after coarse quantization.

[0005] Optionally, the front-end buffer includes: a first operational amplifier; The non-inverting input of the first operational amplifier is connected to the output of the temperature sensing front end, and the inverting input is shorted to its own output. The output of the first operational amplifier is connected to the input of the switched capacitor integrator; The front-end buffer is a unity-gain buffer.

[0006] Optionally, the switched capacitor integrator includes: a first integration branch, a second integration branch, and an integration negative feedback structure; The first integral branch and the second integral branch form a ping-pong structure. The input of the ping-pong structure is connected to the output of the front-end buffer, and the output is connected to the input of the integral negative feedback structure. It works alternately through two non-overlapping clocks. During coarse quantization, while the first integration branch performs charge transfer and integration through the integral negative feedback structure, the second integration branch samples the analog input voltage; while the first integration branch samples the analog input voltage, the second integration branch performs charge transfer and integration through the integral negative feedback structure.

[0007] Optionally, the integral negative feedback structure includes: a second operational amplifier, a feedback capacitor, and a reset switch; The inverting input of the second operational amplifier is connected to the output of the ping-pong structure, and the non-inverting input is grounded. The output of the second operational amplifier is connected to the input of the comparator; The feedback capacitor and the reset switch are both connected across the inverting input and the output of the second operational amplifier.

[0008] Optionally, the ping-pong structure is connected to the front-end buffer via a first control switch and grounded via a second control switch; During a complete cycle, the first control switch is closed and the second control switch is open during the coarse quantization process. The feedback voltage received by the ping-pong structure is controlled by the comparison result of the comparator. If the comparison result is high, the feedback voltage is connected to an external high voltage; otherwise, the feedback voltage is connected to 0 voltage. During a complete cycle, the first control switch is opened and the second control switch is closed during the fine-tuning process. The feedback voltage received by the ping-pong structure is generated by the logic control unit controlling the N-bit resistor array.

[0009] Optionally, during the coarse quantization process, the ping-pong structure continuously integrates the difference between the analog input voltage and the feedback voltage, and the comparator module quantizes the integration result and outputs a digital bit stream. The counter counts the number of high levels in the digital bitstream and converts them into M-bit binary code values, which are used as the coarse quantization result. The oversampling rate of the ping-pong structure is 2. k After completing 2 k After the secondary product branch switching and quantization cycle, the first control switch is opened and the second control switch is closed, the coarse quantization process ends, and the process switches to fine quantization.

[0010] Optionally, during the fine quantization process, only the first integration branch of the ping-pong structure is operational, the output node of the switched capacitor integrator remains unchanged after the coarse quantization, the comparator, the logic control unit, and the N-bit resistor array constitute successive approximation logic, the comparison result of the comparator is input to the logic control unit, and the logic control unit controls the output of the N-bit resistor array bit by bit, and after N comparisons, an N-bit binary number is obtained as the fine quantization result.

[0011] Optionally, both the first operational amplifier and the second operational amplifier adopt a system chopper structure; The system chopper structure corresponding to the first operational amplifier is controlled by a set of switching signals with opposite timings to control its input and output phases, while the system chopper structure corresponding to the second operational amplifier is controlled by another set of switching signals with opposite timings to control its input and output phases. Within a complete cycle, the two sets of switch switching signals are separated by one sub-cycle. The timing of each switch switching signal is divided into four sub-cycles. Each sub-cycle includes a reset time, a coarse quantization time, and a fine quantization time. The coarse quantization time corresponds to the coarse quantization process, and the fine quantization time corresponds to the fine quantization process. The two sets of four switching signals each switch the input and output phases of the corresponding operational amplifiers within four sub-cycles. After the analog input voltage is quantized four times, the four quantization results are averaged off-chip to cancel the input offset voltages of the first and second operational amplifiers.

[0012] Optionally, during any sub-cycle, the output voltage V of the front-end buffer... X Expressed as:

[0013] When A1 is very large, Vx can be directly approximated as .

[0014] After the output point of the switched capacitor integrator is reset, its initial voltage V BINI Expressed as:

[0015] When A2 is very large, V BINI It can be directly approximated as In the above two equations, A1 represents the gain of the first operational amplifier, A2 represents the gain of the second operational amplifier, and V OS1 It is the input offset voltage of the first operational amplifier, V. OS2 It is the input offset voltage of the second operational amplifier, V IN Indicates the analog input voltage; For the inverting input of the second operational amplifier, the law of charge conservation is satisfied. Therefore, charge conservation analysis of any integral branch in the ping-pong structure yields the following: After the first charge transfer:

[0016] After the second charge transfer:

[0017] And so on, after the Nth charge transfer:

[0018] Therefore, we can conclude that:

[0019]

[0020] In the above formula, N is the total number of charge transfers, k is the number of 1s in the comparison result, and V out（i） C is the voltage output by the integrator after each charge transfer. S It is the capacitance value of the sampling capacitor, C f It is the capacitance value of the feedback capacitor, k. （1） This indicates the number of 1s in the comparison result within the first sub-period; Similarly, the number of 1s in the comparison results of the other three sub-cycles can be obtained:

[0021]

[0022]

[0023] The four quantization results are averaged off-chip to obtain N. 1total have:

[0024] In the above formula, k （2） k represents the number of 1s in the comparison result within the second sub-period. （3） k represents the number of 1s in the comparison result within the third sub-period. （4）V represents the number of 1s in the comparison results within the fourth sub-period. H This indicates a high external voltage.

[0025] Secondly, embodiments of this application provide an electronic device comprising a high-resolution two-step ADC for temperature sensing as described in any of the first aspects.

[0026] The high-resolution two-step ADC for temperature sensing proposed in this application departs from traditional technical solutions. It creatively proposes a coarse-quantization SDM + fine-quantization SAR structure, that is, introducing a second-stage SAR ADC into the first-order SDM modulator to quantize the residual in a two-step ADC. Coarse quantization is performed using the first-order SDM modulator, and fine quantization is performed using the SAR ADC. The coarse and fine quantization are multiplexed using a switched-capacitor integrator and a comparator, naturally eliminating inter-branch mismatch and ensuring system linearity. It also eliminates the need for an additional ramp signal generator and high-speed counter, reducing hardware complexity. By multiplexing the integration branch of the switched-capacitor integrator, the comparator does not need to eliminate offset voltage, further simplifying the comparator and front-end buffer.

[0027] First-order SDM modulators inherently possess excellent linearity and natural suppression capabilities against circuit noise and mismatch. Placing them as the first stage alleviates the stringent matching requirements of subsequent SAR stages, ensuring better overall system linearity. They employ a ping-pong integrator structure with switched capacitors, using two sets of alternating integration and sampling channels. This allows for parallel sampling and integration, where one channel performs charge transfer and integration while the other performs input sampling. The first-order SDM modulator performs high-resolution coarse conversion first, leaving the subsequent SAR stage to handle only the minimal residual voltage. This allows for a very simple design, avoiding large capacitors and achieving a balance between high accuracy and low power consumption.

[0028] In addition, the voltage signal generated by the thermistor from the controllable current source is output to the switched capacitor integrator after passing through the front-end buffer (first-level buffer), thus avoiding the problem of having to increase system power consumption in order to shorten the settling time.

[0029] This application provides an SDM that can operate at high speed and has good noise performance for a specific oversampling ratio, while achieving a small chip integration size and low power consumption, which has broad application prospects and high practicality. Attached Figure Description

[0030] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a circuit diagram showing the introduction of a second-stage ADC into a first-order SDM modulator in traditional technology. Figure 2 This is a schematic diagram of a high-resolution two-step ADC modular structure for temperature sensing according to an embodiment of this application. Figure 3 This is a circuit diagram illustrating a preferred high-resolution two-step ADC in the embodiments of this application. Figure 4 The corresponding examples exemplified in this application are Figure 2 The control signal timing diagram of the circuit shown is as follows; Figure 5 This is a schematic diagram illustrating a preferred circuit structure of a first operational unit and a second operational amplifier as exemplified in the embodiments of this application; Figure 6 The corresponding examples exemplified in this application are Figure 5 The control timing diagram of the switching signals corresponding to the switches in the chopper structure of the medium system. Detailed Implementation

[0031] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0032] The inventors discovered that SDM is widely used in low-bandwidth, high-precision applications due to its noise shaping capabilities. However, low-order SDMs, such as first-order SDM modulators, are widely used in temperature sensors with low resolution requirements and extremely low bandwidth. But as the sensitivity to minute temperature changes increases, more stringent requirements are placed on SDMs. For traditional SDMs, performance improvements (such as signal-to-noise ratio, SNR) can only be achieved by increasing the order of the loop filter, increasing the number of bits in the quantizer, or increasing the oversampling rate, which leads to slower overall circuit setup and higher power consumption.

[0033] For high-order SDMs, the loop structure is complex, the design is difficult, and the high-order integrators are easily affected by process, temperature, and voltage variations. Therefore, although traditional SDMs are suitable for high precision, they have limitations in terms of power consumption, complexity, and scalability.

[0034] Therefore, simplifying the overall circuit structure of SDM without affecting performance remains an unsolved problem. For the switching integrator circuit in SDM, the traditional structure usually adopts a single integrator channel and time-division multiplexing: within one clock cycle, the integrator circuit first samples the input signal, then stops sampling and performs charge transfer and integration operations. Since the sampling phase and the charge transfer phase do not overlap in time, the quantization operation can only be performed after the charge transfer is completed, and the quantization time is strictly compressed within a finite non-overlapping phase.

[0035] Further research by the inventors revealed that, to address the aforementioned problem, existing methods propose introducing a second-stage ADC into a first-order SDM modulator to quantize the residual. (See reference...) Figure 1 As shown, the structure includes an SDM ( Figure 1 (21 indicates), a decimation filter ( Figure 1 (23 indicates) and a signal converter ( Figure 1 (See section 27). An integral signal is generated by integrating the difference between the oversampled analog input signal and the feedback signal. Based on a reference signal, the integral signal is converted into an L-bit digital bitstream BS corresponding to the feedback signal. Then, the error signal Err is converted into P-bit digital bits based on a ramp signal. A decimation filter converts the L-bit digital bitstream BS into decimated multi-bit digital data. A signal converter converts the P-bit digital bits into multi-bit digital data based on a clock signal.

[0036] However, the inventors discovered that this structure still has some problems. The ramp signal generator needs to ensure linearity, which not only consumes additional power but also occupies a large chip area. In order to ensure quantization accuracy, the counter needs to match the slope of the ramp signal, and the high-speed clock will bring significant dynamic power consumption.

[0037] In response to the problems identified in the aforementioned inventive discovery, the inventors, through extensive research, have creatively proposed this application: a high-resolution two-step ADC and electronic device for temperature sensing. The technical solution of this application is explained and described in detail below.

[0038] This application discloses a high-resolution two-step ADC for temperature sensing, referring to... Figure 2 The modular structure shown includes: a front-end buffer, a temperature sensing front-end, a switched capacitor integrator, a comparator, a counter, and a logic control unit.

[0039] A front-end buffer, whose input is coupled to the temperature sensing front end, is used to receive the analog input voltage from the temperature sensing front end and to isolate the high impedance of the front end and drive the subsequent circuitry; a switched-capacitor integrator, whose input is coupled to the output of the front-end buffer, is used to sample the analog input voltage and transfer charge.

[0040] The comparator, whose input is coupled to the output of the switched-capacitor integrator, is used to compare the output voltage of the switched-capacitor integrator and generate a comparison result; the counter, whose input is coupled to the output of the comparator, is used to count the comparison result and obtain a coarse quantization result; the logic control unit, whose input is coupled to the output of the comparator, is used to successively approximate the comparison result and obtain a fine quantization result.

[0041] During operation, within a complete cycle (a complete cycle refers to the time required to fully quantize any analog input voltage, for example, 10 ns; that is, regardless of the analog input voltage, as long as an analog input voltage is generated, the quantization of this analog input voltage is completed within 10 ns to obtain the corresponding quantization structure), the switched capacitor integrator works as a first-order Sigma-Delta modulator during coarse quantization. During fine quantization, the switched capacitor integrator and comparator are reused to quantize the residual voltage remaining after coarse quantization.

[0042] The reason for designing a front-end buffer is that, typically, a temperature sensing front-end consists of a negative temperature coefficient thermistor and an adjustable current source. The output of the adjustable current source is connected in series with the negative temperature coefficient thermistor, and their series connection point is connected to the input of the front-end buffer. This series connection point outputs an analog input voltage, which is linearly related to the ambient temperature. This analog input voltage is transmitted to the front-end buffer. Without this buffer, the high resistance of the thermistor and the high capacitance of the input pad (the solder pad or the pin corresponding to a large-capacity transistor) could lead to a long settling time. For high-sampling-rate SDMs, a long settling time can result in failure to establish a sensor. Therefore, isolating the temperature sensing front-end from the switched-capacitor circuit using a front-end buffer effectively solves this long settling time problem.

[0043] The technical solution proposed in this application deviates from traditional solutions, creatively proposing a coarse-quantization SDM + fine-quantization SAR structure. Coarse quantization is performed using a first-order Sigma-Delta modulator, and the residual voltage (i.e., the voltage difference) is quantized using SAR. This allows for the reuse of existing hardware resources: the core of SAR is a "comparator + DAC + register," where the comparator can reuse the original quantizer comparator of the Σ-Δ modulator, eliminating the need for additional ramp signal generators and high-speed counters, thus reducing hardware complexity. Furthermore, by reusing the product branch, the comparator does not need to eliminate offset voltage, further simplifying the comparator. Simultaneously, adding a buffer at the front end effectively shortens the setup time and avoids increased power consumption.

[0044] In one embodiment of this application, the front-end buffer preferably includes: a first operational amplifier; the non-inverting input of the first operational amplifier is connected to the output of the temperature sensing front-end, and the inverting input is shorted to its own output; the output of the first operational amplifier is connected to the input of the switched-capacitor integrator; the front-end buffer is a unity-gain buffer. Therefore, this front-end buffer can reduce the settling time constant between the high output impedance of the temperature sensing front-end and the sampling capacitance of the switched-capacitor integrator, avoiding the increase in system power consumption to shorten the settling time.

[0045] In one embodiment of this application, the switched capacitor integrator preferably includes: a first integration branch, a second integration branch, and an integral negative feedback structure. Specifically, the first integration branch and the second integration branch form a ping-pong structure. The input of this ping-pong structure is connected to the output of the front-end buffer, and the output is connected to the input of the integral negative feedback structure. It operates alternately using two non-overlapping clock phases.

[0046] During coarse quantization, while the first integration branch performs charge transfer and integration through the integral negative feedback structure, the second integration branch samples the analog input voltage; while the first integration branch samples the analog input voltage, the second integration branch performs charge transfer and integration through the integral negative feedback structure.

[0047] In one embodiment of this application, the integral negative feedback structure preferably includes: a second operational amplifier, a feedback capacitor, and a reset switch. The inverting input of the second operational amplifier is connected to the output of the ping-pong structure, and the non-inverting input is grounded; the output of the second operational amplifier is connected to the input of the comparator; the feedback capacitor and the reset switch are both connected across the inverting input and the output of the second operational amplifier.

[0048] In other words, during coarse quantization, charge injection and extraction are performed by controlling the switching of two non-overlapping clock signals, thereby controlling the voltage at the output of the second operational amplifier. The charge transfer uses a ping-pong structure, consisting of two integration branches. One integration branch closes first, sampling occurs on that branch, while the other branch, which is open, performs charge transfer. After one quantization cycle, the closed branch opens again for charge transfer, and then the previously open branch closes for sampling.

[0049] In one embodiment of this application, preferably, during coarse quantization, the ping-pong structure continuously integrates the difference between the analog input voltage and the feedback voltage, the comparator module quantizes the integration result, and outputs a digital bit stream; a counter counts the number of high-level (i.e., 1) signals in the digital bit stream and converts them into M-bit binary code values ​​as the coarse quantization result. That is, during coarse quantization, the two integration branches of the ping-pong structure work alternately, which can halve the coarse quantization time. The logic control unit is not operational.

[0050] In one embodiment of this application, preferably, the ping-pong structure is connected to the front-end buffer via a first control switch and grounded via a second control switch. During a complete cycle, in the coarse quantization process, the first control switch is closed and the second control switch is open. The feedback voltage received by the ping-pong structure is controlled by the comparison result of the comparator. If the comparison result is high, the feedback voltage is connected to an external high voltage; otherwise, the feedback voltage is connected to 0 voltage. During the fine quantization process, in a complete cycle, the first control switch is open and the second control switch is closed. The feedback voltage received by the ping-pong structure is generated by the logic control unit controlling the N-bit resistor array.

[0051] A better approach is to set the oversampling rate of the ping-pong structure to 2. k After completing 2 k After the secondary product branch switching and quantization cycle, the first control switch is opened and the second control switch is closed, ending the coarse quantization process and switching to the fine quantization process. That is, the last sampled voltage is the reference voltage VCM.

[0052] In one embodiment of this application, preferably, during the fine quantization process, the two integration branches in the ping-pong structure no longer work alternately, but only the first integration branch works. The output node of the switched capacitor integrator remains unchanged after the coarse quantization is completed. Therefore, the comparator, the logic control unit, and the N-bit resistor array constitute successive approximation logic (i.e., constitute SARADC). The comparison result of the comparator is input to the logic control unit, and the logic control controls the output of the N-bit resistor array bit by bit. After N comparisons are completed, an N-bit binary number is obtained as the fine quantization result.

[0053] To better understand the high-resolution two-step ADC for temperature sensing proposed in this application, refer to... Figure 3 The diagram shows a preferred circuit structure for a high-resolution two-step ADC. Figure 3 The preferred structure described above is shown in the figure, but it does not mean that it can only be this structure. Any other structure or integrated circuit that can achieve the same function can be replaced accordingly.

[0054] Figure 3 The temperature sensing front end includes: a negative temperature coefficient thermistor R and an adjustable current source I, with an analog input voltage of V. INOP1 represents the front-end buffer. All switches are named according to their corresponding control signals; for example, ENC_VIN represents the first control switch, SEL represents the second control switch, φ1 and φ2 represent the switches corresponding to the first and second integration branches, Cs represents the integrating capacitor, and these together form two integration branches; VDAC represents the feedback voltage. OP2 represents the second operational amplifier, Cf represents the feedback capacitor, and RST represents the reset switch. COMP represents the comparator, COUNTER represents the counter, and SAR_LOGIC represents the logic control unit. Q C <M:1> represents the coarse quantization result, Q F <N:1> indicates the fine quantization result. ENC represents the coarse quantization control signal, active high, indicating that the circuit performs coarse quantization; ENF represents the fine quantization control signal, active high, indicating that the circuit performs fine quantization.

[0055] The feedback voltage VDAC is generated as follows: When the control signal ENC is high, the circuit performs coarse quantization. At this time, if the comparator COMP outputs the digital signal D... OUT When the signal is high, VDAC is connected to an external high-level input VH; otherwise, it is connected to a low-level input 0. When the control signal ENF is high, VDAC is connected to an N-bit resistor array ( Figure 3 (Not shown in the diagram for simplicity).

[0056] Combination Figure 4 The control signal timing diagram shown illustrates the working principle of the high-resolution two-step ADC for temperature sensing proposed in this application: When ENC is high, the entire circuit performs coarse quantization, i.e., SDM. During this process, the first control signal ENC_VIN is closed, and the second control signal SEL is open. By controlling the switching of φ1 and φ2 (two non-overlapping phases), charge injection and extraction are performed to control the voltage at the output of the second operational amplifier. The charge transfer adopts a ping-pong structure, with the entire circuit divided into upper and lower branches. φ2 is closed first, the lower branch samples, and the upper branch transfers charge. After completing one quantization cycle, φ2 is opened, and then φ1 is closed, the lower branch transfers charge, and the upper branch samples.

[0057] The oversampling rate is 2 k Switch to 2 k After this, the first control signal ENC_VIN is disconnected, the second control signal SEL is closed, and φ2 is closed, meaning the last sampled voltage is the reference voltage VCM. The coarsely quantized result is then processed by the counter COUNTER, which counts the number of 1s in the comparison result of the comparator COMP, converting it into an M-bit binary code value, which is the coarse quantization result Q. C <M:1>. Adding a charge transfer branch to the single-branch system can halve the coarse quantization time.

[0058] When ENF is high, the entire circuit undergoes fine quantization. At the start of fine quantization, the output node V of OP2... B Maintaining the level after the last charge transfer, φ2 is closed, and fine quantization is performed through the same integration loop of SDM, i.e., φ1 is open and φ2 is closed, with no switching. The comparator COMP output controls the logic control unit SAR_LOGIC, which then controls the output voltage of the N-bit resistor array bit by bit, feeding it back to the voltage input node, thus obtaining the feedback voltage VDAC, achieving the effect of successive approximation. The N-bit binary number output by comparator COMP is used as the fine quantization result Q. F <N:1>.

[0059] In one embodiment of this application, although introducing a front-end buffer can effectively improve the front-end setup speed, it also introduces an offset voltage because it is an operational amplifier. Therefore, a four-phase cascaded system chopper is creatively added to eliminate the offset voltage of the two operational amplifiers. Preferably, both the first and second operational amplifiers employ a system chopper structure to eliminate offset bias.

[0060] The system chopper structure corresponding to the first operational amplifier is controlled by a set of timing-opposite switching signals to control its input and output phases, while the system chopper structure corresponding to the second operational amplifier is controlled by another set of timing-opposite switching signals to control its input and output phases.

[0061] Within a complete cycle, the two sets of switching signals are separated by one sub-cycle. The timing of each switching signal is divided into four sub-cycles, each of which includes a reset time, a coarse quantization time, and a fine quantization time. The coarse quantization time corresponds to the coarse quantization process, and the fine quantization time corresponds to the fine quantization process. The two sets of four switching signals switch the input and output phases of the corresponding operational amplifiers within the four sub-cycles. After the analog input voltage is quantized four times, the four quantization results are averaged off-chip to cancel the input offset voltages of the first and second operational amplifiers.

[0062] To better understand the chopper structure of this system, refer to... Figure 5 The diagram shows a preferred circuit structure of a first operational unit and a second operational amplifier. Figure 5 The diagram on the right shows the circuit structure of the first operational amplifier; the diagram on the left shows the circuit structure of the second operational amplifier. P1 and P2 are the control signals for the switches of the second operational amplifier; P3 and P4 are the control signals for the switches of the first operational amplifier.

[0063] Combination Figure 6 The control timing diagram of the switch signal shown represents a complete cycle T. totalIt is divided into four cycles: T1, T2, T3, and T4, where each sub-cycle includes a reset time T. RST Coarse quantization time T C And fine quantization time T F The switching control signals P1, P2, P3, and P4 switch phases respectively within these four cycles to eliminate offset voltage. The specific principle is as follows: During any sub-cycle, the output voltage V of the front-end buffer X Expressed as:

[0064] When A1 is very large, Vx can be directly approximated as .

[0065] After the output point of the switched capacitor integrator is reset, its initial voltage V BINI Expressed as:

[0066] When A2 is very large, V BINI It can be directly approximated as In the above two equations, A1 represents the gain of the first operational amplifier, A2 represents the gain of the second operational amplifier, and V... OS1 It is the input offset voltage of the first operational amplifier, V. OS2 It is the input offset voltage of the second operational amplifier, V IN Indicates the analog input voltage; For the inverting input of the second operational amplifier, the law of charge conservation is satisfied. Therefore, charge conservation analysis of any integral branch in the ping-pong structure yields the following: After the first charge transfer:

[0067] After the second charge transfer:

[0068] And so on, after the Nth charge transfer:

[0069] Therefore, we can conclude that:

[0070]

[0071] In the above formula, N is the total number of charge transfers, k is the number of 1s in the comparison result, and V out（i） C is the voltage output by the integrator after each charge transfer. S It is the capacitance value of the sampling capacitor, Cf It is the capacitance value of the feedback capacitor, k. （1） This indicates the number of 1s in the comparison result within the first sub-period; Similarly, the number of 1s in the comparison results of the other three sub-cycles can be obtained:

[0072]

[0073]

[0074] The four quantization results are averaged off-chip to obtain N. 1total have:

[0075] In the above formula, k （2） k represents the number of 1s in the comparison result within the second sub-period. （3） k represents the number of 1s in the comparison result within the third sub-period. （4） V represents the number of 1s in the comparison results within the fourth sub-period. H This indicates a high external voltage. Therefore, V... IN The four quantization results are averaged off-chip, which can eliminate the input offset voltage V of the front-end buffer (i.e., the first operational amplifier). OS1 In the integral negative feedback structure, the offset voltage V of the second operational amplifier OS2 Its function.

[0076] Compared to traditional two-phase chopping, this four-state discrete ergodic process, namely:

[0077] In the two-phase (traditional scheme): Phase 1: Buffer forward ( The integrator (equivalent to the second operational amplifier of this application) is forward-biased ( Total error = ; Phase 2: Buffer Reverse ( ), integrator reverse ( Total error = .

[0078] Although the average is 0, the premise is... These two phases must be completely equal. However, in actual circuits, the buffer stage (first stage) is affected by input signal swing, power supply fluctuations, or its own non-ideal gain. When switching between "forward" and "reverse", a tiny offset (called a second-order change) actually occurs. The integrator cannot distinguish which one caused the residual error, resulting in error coupling.

[0079] However, for the phase in this application, in both the first sub-cycle T1 and the second sub-cycle T2, the second operational amplifier remains in "+" polarity. If we add the first sub-cycle T1 and the second sub-cycle T2, we have:

[0080] Therefore, it can be concluded that: regardless of At this point, as long as it remains relatively stable within the first sub-period T1 and the second sub-period T2, it will be eliminated.

[0081] Similarly, we can obtain the third sub-period T3 and the fourth sub-period T4 as follows:

[0082] In the third sub-period T3 and the fourth sub-period T4 It is eliminated again. Therefore, when we average the sums (T1+T2) and (T3+T4) again: ,final, It was also eliminated.

[0083] Based on the aforementioned high-resolution two-step ADC for temperature sensing, this application also proposes an electronic device comprising the high-resolution two-step ADC for temperature sensing as described in any of the preceding claims.

[0084] In summary, the high-resolution two-step ADC for temperature sensing proposed in this application departs from traditional technical solutions. It creatively proposes a coarse-quantization SDM + fine-quantization SAR structure, that is, introducing a second-stage SAR ADC into the first-order SDM modulator to quantize the residual in a two-step ADC. Coarse quantization is performed using the first-order SDM modulator, and fine quantization is performed using the SAR ADC. The coarse and fine quantization are multiplexed using a switched-capacitor integrator and a comparator, naturally eliminating inter-branch mismatch and ensuring system linearity. It also eliminates the need for an additional ramp signal generator and high-speed counter, reducing hardware complexity. By multiplexing the integration branch of the switched-capacitor integrator, the comparator does not need to eliminate offset voltage, further simplifying the comparator and front-end buffer.

[0085] Compared with the mainstream coarse-quantized SAR + fine-quantized SDM (e.g., zoom ADC), the structure proposed in this application, which adopts coarse-quantized SDM + fine-quantized SAR, has the following advantages: SDM alleviates the accuracy pressure on SAR: Traditional SAR ADCs require large capacitor arrays and high matching to achieve high accuracy, which consumes a lot of area and power. This application allows the front-end coarse SDM to perform high-resolution coarse conversion first, so the subsequent SAR only needs to handle a very small residual range. This allows for a very simple design, avoiding large capacitors and achieving a balance between high accuracy and low power consumption. It also leverages the inherent linearity and noise immunity of SDM: SDM itself has excellent linearity and natural suppression of circuit noise and mismatch. Placing it in the first stage reduces the stringent matching requirements of the subsequent SAR, ensuring better overall system linearity.

[0086] Despite the aforementioned theoretical advantages, several insurmountable obstacles arise in practical circuit design, creating technical barriers and information transmission challenges: SDM outputs a high-speed bitstream, while SAR needs to process specific residual voltages. How to convert the SDM bitstream into analog residuals for SAR in real time and with high accuracy is a problem that traditional technologies have yet to solve.

[0087] This application uses a shared loop (including an integrator, comparator, and DAC) for both SDM and SAR. The output voltage of the switched-capacitor integrator (i.e., the output voltage of OP2) is passed to the negative terminal of the comparator, while the positive terminal of the comparator is connected to the common-mode level. The comparison result controls the output of the 1-bit DAC to be high or low, thereby controlling the switching-capacitor integrator to extract or inject charge (the output voltage of OP2 also changes accordingly). After N charge transfers, the output voltage of OP2 serves as the residual voltage for coarse quantization, which does not need to be subtracted from the common-mode level to obtain the residual voltage. Because a shared loop is used, the common-mode level can be successively approximated directly based on this residual voltage to obtain a fine quantization result.

[0088] First-order SDM modulators inherently possess excellent linearity and natural suppression capabilities against circuit noise and mismatch. Placing them as the first stage alleviates the stringent matching requirements of subsequent SAR stages, ensuring better overall system linearity. They employ a ping-pong integrator structure with switched capacitors, using two sets of alternating integration and sampling channels. This allows for parallel sampling and integration, where one channel performs charge transfer and integration while the other performs input sampling. The first-order SDM modulator performs high-resolution coarse conversion first, leaving the subsequent SAR stage to handle only the minimal residual voltage. This allows for a very simple design, avoiding large capacitors and achieving a balance between high accuracy and low power consumption.

[0089] Furthermore, the voltage signal generated by the thermistor from the controllable current source is passed through a front-end buffer (first-stage buffer) before being output to the switched-capacitor integrator, avoiding the problem of having to increase system power consumption to shorten the settling time. A four-phase cascaded system chopper is also creatively added to eliminate the offset voltage of the two operational amplifiers.

[0090] This application provides an SDM that can operate at high speed and has good noise performance for a specific oversampling ratio, while achieving a small chip integration size and low power consumption, which has broad application prospects and high practicality.

[0091] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0092] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0093] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. A high-resolution two-step ADC for temperature sensing, characterized in that, include: A front-end buffer, whose input is coupled to the temperature sensing front end, is used to receive the analog input voltage from the temperature sensing front end, and to isolate the high impedance of the front end and drive the subsequent circuitry. A switched-capacitor integrator, whose input is coupled to the output of the front-end buffer, is used to sample the analog input voltage and transfer charge. A comparator, whose input is coupled to the output of the switched capacitor integrator, is used to compare the output voltage of the switched capacitor integrator and generate a comparison result. A counter, whose input is coupled to the output of the comparator, is used to count the comparison results to obtain a coarse quantization result; A logic control unit, whose input is coupled to the output of the comparator, is used to successively approximate the comparison result to obtain a fine quantization result; In a complete cycle, the switched capacitor integrator operates as a first-order Sigma-Delta modulator during the coarse quantization process. During the fine quantization process, the switched capacitor integrator and the comparator are reused to quantize the residual voltage remaining after coarse quantization.

2. The high-resolution two-step ADC for temperature sensing according to claim 1, characterized in that, The front-end buffer includes: a first operational amplifier; The non-inverting input of the first operational amplifier is connected to the output of the temperature sensing front end, and the inverting input is shorted to its own output. The output of the first operational amplifier is connected to the input of the switched capacitor integrator; The front-end buffer is a unity-gain buffer.

3. The high-resolution two-step ADC for temperature sensing according to claim 1, characterized in that, The switched capacitor integrator includes: a first integration branch, a second integration branch, and an integration negative feedback structure; The first integral branch and the second integral branch form a ping-pong structure. The input of the ping-pong structure is connected to the output of the front-end buffer, and the output is connected to the input of the integral negative feedback structure. It works alternately through two non-overlapping clocks. During coarse quantization, while the first integration branch performs charge transfer and integration through the integral negative feedback structure, the second integration branch samples the analog input voltage; while the first integration branch samples the analog input voltage, the second integration branch performs charge transfer and integration through the integral negative feedback structure.

4. The high-resolution two-step ADC for temperature sensing according to claim 3, characterized in that, The integral negative feedback structure includes: a second operational amplifier, a feedback capacitor, and a reset switch; The inverting input of the second operational amplifier is connected to the output of the ping-pong structure, and the non-inverting input is grounded. The output of the second operational amplifier is connected to the input of the comparator; The feedback capacitor and the reset switch are both connected across the inverting input and the output of the second operational amplifier.

5. The high-resolution two-step ADC for temperature sensing according to claim 3, characterized in that, The ping-pong structure is connected to the front-end buffer via a first control switch and is also grounded via a second control switch; During a complete cycle, the first control switch is closed and the second control switch is open during the coarse quantization process. The feedback voltage received by the ping-pong structure is controlled by the comparison result of the comparator. If the comparison result is high, the feedback voltage is connected to an external high voltage; otherwise, the feedback voltage is connected to 0 voltage. During a complete cycle, the first control switch is opened and the second control switch is closed during the fine-tuning process. The feedback voltage received by the ping-pong structure is generated by the logic control unit controlling the N-bit resistor array.

6. The high-resolution two-step ADC for temperature sensing according to claim 5, characterized in that, During the coarse quantization process, the ping-pong structure continuously integrates the difference between the analog input voltage and the feedback voltage, and the comparator module quantizes the integration result and outputs a digital bit stream. The counter counts the number of high levels in the digital bitstream and converts them into M-bit binary code values, which are used as the coarse quantization result. The oversampling rate of the ping-pong structure is 2. k After completing 2 k After the secondary product branch switching and quantization cycle, the first control switch is opened and the second control switch is closed, the coarse quantization process ends, and the process switches to fine quantization.

7. The high-resolution two-step ADC for temperature sensing according to claim 5, characterized in that, During the fine quantization process, only the first integration branch of the ping-pong structure is working. The output node of the switched capacitor integrator remains unchanged after the coarse quantization. The comparator, the logic control unit, and the N-bit resistor array constitute successive approximation logic. The comparison result of the comparator is input to the logic control unit. The logic control unit controls the output of the N-bit resistor array bit by bit. After N comparisons, an N-bit binary number is obtained as the fine quantization result.

8. The high-resolution two-step ADC for temperature sensing according to claim 2 or 4, characterized in that, Both the first operational amplifier and the second operational amplifier adopt a system chopper structure; The system chopper structure corresponding to the first operational amplifier is controlled by a set of switching signals with opposite timings to control its input and output phases, while the system chopper structure corresponding to the second operational amplifier is controlled by another set of switching signals with opposite timings to control its input and output phases. Within a complete cycle, the two sets of switch switching signals are separated by one sub-cycle. The timing of each switch switching signal is divided into four sub-cycles. Each sub-cycle includes a reset time, a coarse quantization time, and a fine quantization time. The coarse quantization time corresponds to the coarse quantization process, and the fine quantization time corresponds to the fine quantization process. The two sets of four switching signals each switch the input and output phases of the corresponding operational amplifiers within four sub-cycles. After the analog input voltage is quantized four times, the four quantization results are averaged off-chip to cancel the input offset voltages of the first and second operational amplifiers.

9. The high-resolution two-step ADC for temperature sensing according to claim 8, characterized in that, During any sub-cycle, the output voltage V of the front-end buffer X Expressed as: When A1 is very large, Vx can be directly approximated as ; After the output point of the switched capacitor integrator is reset, its initial voltage V BINI Expressed as: When A2 is very large, V BINI It can be directly approximated as In the above two equations, A1 represents the gain of the first operational amplifier, A2 represents the gain of the second operational amplifier, and V OS1 It is the input offset voltage of the first operational amplifier, V. OS2 It is the input offset voltage of the second operational amplifier, V IN Indicates the analog input voltage; For the inverting input of the second operational amplifier, the law of charge conservation is satisfied. Therefore, charge conservation analysis of any integral branch in the ping-pong structure yields the following: After the first charge transfer: After the second charge transfer: And so on, after the Nth charge transfer: Therefore, we can conclude that: In the above formula, N is the total number of charge transfers, k is the number of 1s in the comparison result, and V out（i） C is the voltage output by the integrator after each charge transfer. S It is the capacitance value of the sampling capacitor, C f It is the capacitance value of the feedback capacitor, k. （1） This indicates the number of 1s in the comparison result within the first sub-period; Similarly, the number of 1s in the comparison results of the other three sub-cycles can be obtained: The four quantization results are averaged off-chip to obtain N. 1total have: In the above formula, k （2） k represents the number of 1s in the comparison result within the second sub-period. （3） k represents the number of 1s in the comparison result within the third sub-period. （4） V represents the number of 1s in the comparison results within the fourth sub-period. H This indicates a high external voltage.

10. An electronic device, characterized in that, The electronic device includes a high-resolution two-step ADC for temperature sensing as described in any one of claims 1-9.

Images