Low complexity snr estimation method and system based on table lookup

Abstract

The application relates to a low-complexity signal-to-noise ratio estimation method and system based on a lookup table method, which comprises the following steps: acquiring a square second-moment term and a fourth-moment of a to-be-tested signal; extracting a magnitude index and a normalized mantissa of the square second-moment term and the fourth-moment respectively; calculating a base address according to the magnitude index, calculating an offset address according to the normalized mantissa, and splicing the base address and the offset address into a complete memory retrieval address bus; and retrieving a preset block read-write memory according to the complete memory retrieval address bus to output a target signal-to-noise ratio estimation value. The application has the advantages that a lightweight hardware addressing operation is used to replace a traditional high-overhead division operation, underlying logic resources are greatly saved, precision overflow in fixed-pointing is effectively avoided, and system throughput speed is significantly improved.

Description

Technical Field

[0001] This application relates to the field of digital signal processing, and in particular to a low-complexity signal-to-noise ratio estimation method and system based on a lookup table. Background Technology

[0002] In the field of digital signal processing, signal-to-noise ratio (SNR) is a crucial indicator for measuring the link quality and signal reliability of communication systems. In blind signal detection or demodulation, the system typically does not need to know the specific modulation scheme of the signal; instead, it uses the statistical characteristics of the received signal to estimate the SNR. Standard moment estimation methods usually extract the second and fourth moments of the signal and reflect the signal-to-noise ratio by calculating the ratio of the squared second moment to the fourth moment. While this mathematical operation is relatively mature at the software algorithm level, implementing it in underlying hardware such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) presents significant engineering challenges.

[0003] Traditional hardware architectures typically rely on instantiating the underlying divider logic core to handle the aforementioned ratio calculations. The internal logic structure of a hardware divider is relatively complex, and the operation requires significant digital signal processing unit (DSP) and logic register resources. Since division operations are usually based on iterative algorithms or long pipeline structures, their computation cycle is relatively long. In high-speed communication or multi-channel concurrent processing scenarios, this long combinational logic path lowers the system's maximum operating clock frequency, increases data processing latency, and makes it difficult to meet the real-time throughput requirements at high symbol rates.

[0004] The squared terms of the second and fourth moments of a signal have a wide dynamic range. When the signal power at the receiving end fluctuates, the magnitude of these characteristic values ​​changes significantly. If a conventional fixed-point divider is used for direct calculation, designers must allocate a wide data bus width to prevent data overflow or underflow that could cause precision loss. Wide-width dividers not only increase logic resource consumption but also lead to wiring difficulties and increased power consumption. Introducing a standard floating-point core to replace fixed-point division, while accommodating a wider dynamic range, results in higher resource consumption and a significantly increased overall system architecture complexity. Summary of the Invention

[0005] To bypass complex hardware division links and quickly process feature data with a wide dynamic range under limited underlying logic resources, this application provides a low-complexity signal-to-noise ratio estimation method and system based on table lookup.

[0006] Firstly, this application provides a low-complexity signal-to-noise ratio estimation method based on a lookup table, employing the following technical solution: A low-complexity signal-to-noise ratio estimation method based on table lookup includes the following steps: S1. Obtain the squared term of the second moment of the signal under test and the fourth moment of the signal under test; S2. Extract the first order exponent of the squared term of the second moment of the signal under test and the second order exponent of the fourth moment of the signal under test, and extract the first normalized mantissa of the squared term of the second moment of the signal under test and the second normalized mantissa of the fourth moment of the signal under test. S3. Calculate the base address based on the first order of magnitude exponent and the second order of magnitude exponent, calculate the offset address based on the first normalized mantissa and the second normalized mantissa, and concatenate the base address and the offset address to form a complete memory retrieval address; S4. Retrieve the preset block read / write memory based on the complete memory retrieval address to output the target signal-to-noise ratio estimate.

[0007] By employing the above technical solution, the second-order moment squared term and the fourth-order moment of the signal under test are decomposed into a first-order exponent, a second-order exponent, and a first-normalized mantissa and a second-normalized mantissa, respectively. This decomposes the physical parameter with a wide dynamic range into an exponential component representing the macroscopic magnitude and a mantissa component representing the microscopic precision. The exponential and mantissa components operate independently on the physical data path, freeing the data bus width of the logic gate operation node from the constraint of the absolute amplitude of the signal under test. This mechanism for separating feature data converges the requirement for solving division ratios spanning a wide numerical range to a constant bit-width processing range, avoiding numerical overflow and low-bit precision truncation when the underlying digital signal processing module performs long-bit-width fixed-point operations.

[0008] The base address generated by subtracting the first and second order of magnitude exponents represents the macroscopic data page offset of the mapped data in physical memory. The offset address generated by subtracting the first and second normalized mantissas represents the microscopic row offset of the mapped data within a specific data page. The mechanism of physically concatenating the base and offset addresses to generate the complete memory retrieval address replaces the conventional arithmetic divider entity in the underlying logic netlist. Differential addressing reduces the multi-level iterative combinational logic network included in traditional divider circuits, compressing the clock cycle time of data flow through the computing nodes.

[0009] After receiving the complete memory retrieval address, the pre-configured block read / write memory directly outputs the corresponding target signal-to-noise ratio (SNR) estimate using an internally fixed nonlinear compensation data array. The single-clock-cycle memory physical address lookup operation offsets the latency caused by long pipelined division arithmetic operations at the timing level. The offline-configured mapping array within the pre-configured block read / write memory compensates for the accuracy loss caused by the front-end feature truncation step. The static memory lookup structure reduces the wiring occupancy of the arithmetic logic units within the field-programmable gate array (FPGA), controlling the silicon logic resource footprint of the SNR estimation hardware system.

[0010] Optionally, S2 includes the following sub-steps: S21. Scan the bit width of the squared term of the second moment of the signal under test to extract the first order of magnitude exponent, and scan the bit width of the fourth moment of the signal under test to extract the second order of magnitude exponent. S22. Perform a shift and truncation operation on the squared term of the second moment of the signal under test according to the first order exponent to output the first normalized mantissa, and perform a shift and truncation operation on the fourth moment of the signal under test according to the second order exponent to output the second normalized mantissa.

[0011] By employing the above technical solution, a mechanism is used to extract the first-order and second-order exponents respectively by scanning the bit width of the second-order moment squared term and the bit width of the fourth-order moment of the signal under test. The carry-chain logic at the bottom layer of the digital circuit converts the spatial effective bit positions of the data into numerical exponential signals representing power level differences. Shift operations are performed on the second-order moment squared term based on the first-order exponent and on the fourth-order moment based on the second-order exponent, driving the underlying hardware shift network to uniformly slide the effective bit sequences scattered across different intervals of the wide data bus to the higher bit interval of the physical bus. The truncation operation directly discards invalid background noise and sign extension bits that deviate from the preset effective bit width window. The collaborative working mechanism of exponent extraction and shift truncation decomposes the original dynamic wide-range data into a scale frame with mutually independent dimensions and a high-precision mantissa, severing the binding relationship between the number of physical pins of subsequent calculation modules and the peak power fluctuation of the baseband input signal. This allows the underlying calculation path to process moment characteristic parameters with a wide dynamic range using a constant narrow bit width while avoiding arithmetic overflow.

[0012] Optionally, S22 includes the following sub-steps: S221. Receive the first magnitude index and convert the first magnitude index into a first hardware control word; S222. Perform a parallel left shift operation on the second-order moment squared term of the signal under test according to the first hardware control word, so that the preset valid data bits of the second-order moment squared term of the signal under test are aligned to the preset highest physical data bit of the preset target data bus; S223. Apply a first hardware mask to extract a preset target bit-width data segment of the preset target data bus as the first normalized mantissa.

[0013] By employing the above technical solution, the operation of converting the first-order exponent into the first hardware control word is performed, and the scalar value is decoded into a physical strobe signal for configuring the underlying multiplexer array. Based on the first hardware control word, a parallel left shift operation is performed on the second-order squared term of the signal under test, causing the signal data to be shifted to its position in a single data flow within the pure combinational logic network. This physically maps the preset valid data bits of the second-order squared term of the signal under test to the preset highest physical data bit of the preset target data bus. The operation of using a first hardware mask to truncate a preset target bit-width data segment as the first normalized mantissa filters out invalid transition signals from the low-order register output port through hard-wired shielding. The hardware mask truncation mechanism replaces the bit-width reduction process achieved through a digital signal processing multiplication core with pure physical connection extraction, and the parallel left shift structure avoids the multiple clock cycle waiting states associated with serial shifters. The cascaded link of instruction decoding, combined shifting, and hard-line masking compresses the physical time of the data alignment and normalization process to the gate-level delay range of a single clock cycle, controlling the consumption of the data feature warping stage on the estimated system pipeline throughput.

[0014] Optionally, step S3 includes the following sub-steps: S31. Receive the first magnitude index and the second magnitude index, and generate the base address based on the first magnitude index and the second magnitude index; S32. Receive the first normalized mantissa and the second normalized mantissa, subtract the second normalized mantissa from the first normalized mantissa to generate the original mantissa difference, and truncate the original mantissa difference to extract a preset truncated bit-width data segment as the offset address. S33. The base address and the offset address are physically concatenated to form the complete memory retrieval address.

[0015] By adopting the above technical solution, the operation of receiving the first and second order of magnitude exponents to generate the base address establishes the macroscopic addressing segmentation of the mapped data in the preset storage array. The operation of subtracting the second normalized mantissa from the first normalized mantissa and truncating it to extract a data segment with a preset truncation width to generate the offset address establishes the microscopic addressing granularity within a specific macroscopic segment. The truncation processing of the mantissa difference intercepts redundant low-order signals that exceed the memory's designed addressing width, controlling the number of physical pins required for subsequent address mapping. The mechanism of physically concatenating the base address and the offset address to form a complete memory retrieval address utilizes the parallel wiring of the underlying digital circuit to replace the numerical synthesis of the arithmetic logic unit. Hard-wired concatenation completes the physical fusion of independent data dimensions without consuming clock cycles and register flip-flop resources, reducing the multi-level interactive combinational logic contained in the traditional division circuit and lowering the end-to-end latency of signal characteristic data flow.

[0016] Optionally, S31 includes the following sub-steps: S311. Receive the first magnitude index and the second magnitude index, and fill the first magnitude index and the second magnitude index with sign bits respectively to expand them into a first signed magnitude index and a second signed magnitude index; S312. Perform a two's complement subtraction operation on the first signed exponent and the second signed exponent to generate the original exponent difference; S313. When the original exponential difference is detected to exceed the preset upper limit threshold of the physical lookup table address or fall below the preset lower limit threshold of the physical lookup table address, the original exponential difference is forcibly overwritten as the preset lookup table address boundary extreme value as the base address output.

[0017] By employing the above technical solution, the first and second order-of-magnitude exponents are expanded into first and second signed order-of-magnitude exponents respectively by filling the sign bits, thus endowing unsigned order-of-magnitude data with the fundamental electrical properties for directional physical offset calculation. Binary two's complement subtraction is performed on the expanded signed exponents, and the logarithmic domain difference solution characterizing the signal power multiple difference is completed using a basic adder logic network. When the difference of the original exponents exceeds the preset physical lookup table address boundary threshold, a clamping operation is performed to forcibly overwrite it to the preset lookup table address boundary extreme value, constructing a hardware-level anti-address overflow barrier for abnormal burst input signals. The clamping overwrite mechanism blocks the failure path caused by base address out-of-bounds addressing leading to system memory bus timing errors or reading unexpected mapped addresses. The hardware-level boundary clamping replaces the software-level abnormal interrupt protection program with the physical selection action of the underlying multiplexer, maintaining the addressing output stability of the signal-to-noise ratio estimation hardware path when processing wide peak-to-average power ratio baseband signals.

[0018] Optionally, step S32 includes the following sub-steps: S321. Divide the original mantissa difference into a preset primary index data segment and a preset secondary interpolation data segment according to the preset physical bit width dividing boundary; S322. Set the preset main index data segment as the preset truncated bit-width data segment, and output the preset truncated bit-width data segment as the offset address; S323. Output the preset secondary interpolation data segment as the interpolation compensation mantissa.

[0019] By employing the above technical solution, the original mantissa difference is divided into a preset primary index data segment and a preset secondary interpolation data segment according to a preset physical bit-width segmentation boundary. This decouples the single-dimensional wide bit-width lookup table index into two signals: a static memory addressing reference and dynamic linear compensation parameters. Setting the preset primary index data segment as a preset truncated bit-width data segment and using it as the offset address output limits the wiring size of the direct physical memory address input port, suppressing the exponential expansion of the physical capacity consumed by the lookup table as the estimation accuracy requirement increases. Using the preset secondary interpolation data segment as the step of interpolation compensation mantissa output intercepts and preserves the micro-quantization deviation that escapes the high-order bus during hard truncation. The bit-width segmentation and splitting output logic constructs parallel high-order coarse addressing and low-order fine compensation data channels. The establishment of the preset physical bit-width segmentation boundary severs the strong binding relationship between memory space depth and final estimation resolution, enabling the underlying hardware system to provide the data foundation for full floating-point precision error compensation parameters to the subsequent computing network while maintaining a small silicon area footprint.

[0020] Optionally, the target reference signal-to-noise ratio and the target fitting slope factor are all programmed into the physical storage units of the preset block read / write memory. The step of outputting the target signal-to-noise ratio estimate in S4 includes: performing piecewise linear interpolation using the target baseline signal-to-noise ratio, the target fitting slope factor, and the interpolation compensation tail to output the target signal-to-noise ratio estimate.

[0021] By adopting the above technical solution, the physical storage units of the pre-installed block read / write memory are all programmed with a mechanism for the target reference signal-to-noise ratio (SNR) and the target fitting slope factor. This mechanism effectively resolves the continuous nonlinear mapping curve into a first-order linear distribution matrix with a specific bias and fixed tilt angle within the micro-addressing interval. The operation utilizes the target reference SNR, the target fitting slope factor, and the interpolation compensation mantissa to perform piecewise linear interpolation to output the estimated target SNR value. The underlying quantization residuals retained by the front-end address truncation action are used to participate in the numerical reconstruction of the terminal SNR result. The dual-track storage architecture of the reference SNR and slope factor compresses the massive high-resolution nonlinear mapping table into a sparse discrete anchor array. The piecewise linear interpolation mechanism decouples the binding relationship between the system estimation resolution and the physical memory capacity, enabling the SNR estimation hardware to restore the local precision discarded by the truncation action through dynamic calculation links without expanding the number of static random access memory address bus pins. This avoids the systematic quantization step error caused by the finite word length effect in the direct lookup table method.

[0022] Optionally, the step of performing piecewise linear interpolation includes the following sub-steps: S41. Input the complete memory retrieval address into the preset block read / write memory, and use the complete memory retrieval address to retrieve the physical storage unit, so as to output the target reference signal-to-noise ratio and the target fitting slope factor in parallel; S42. Receive the target fitting slope factor and the interpolation compensation tail number, and multiply the target fitting slope factor by the interpolation compensation tail number to generate a dynamic error compensation amount; S43. Receive the target reference signal-to-noise ratio and the dynamic error compensation amount, add the target reference signal-to-noise ratio to the dynamic error compensation amount to generate the target signal-to-noise ratio estimate, and output the target signal-to-noise ratio estimate.

[0023] By employing the above technical solution, the operation of inputting the complete memory retrieval address to a preset block read / write memory and retrieving physical memory units to output the target reference signal-to-noise ratio and the target fitting slope factor in parallel activates the wide data bus characteristics of the underlying dual-port read-only memory to synchronously extract the intercept and slope parameters of the nonlinear curve within a single clock cycle. The step of receiving the target fitting slope factor and the interpolation compensation mantissa and multiplying them to generate the dynamic error compensation amount drives the underlying hardware digital multiplier core to linearly map the truncated mantissa deviation in the input data dimension to a quantization correction value in the output signal-to-noise ratio dimension. The operation of receiving the target reference signal-to-noise ratio and the dynamic error compensation amount and adding them to generate the target signal-to-noise ratio estimate involves the physical synthesis of the static addressing anchor point and the dynamic fine-tuning component at the bit alignment level within the arithmetic logic unit. The pipelined cascade structure of parallel memory reading, multiplier dimension transformation, and adder reference synthesis eliminates the high-density stacking requirement of silicon wafer storage space for high-precision signal lookup table schemes. The combined approach of pre-feature segmentation and post-operation fitting shifts the addressing pressure of the lookup table depth to the underlying multiply-accumulator slicing module with higher logic throughput, thus maintaining the low resource consumption of the hardware entity when processing nonlinear signal-to-noise ratio conversion mapping.

[0024] Secondly, this application provides a low-complexity signal-to-noise ratio estimation system, which adopts the following technical solution: A low-complexity signal-to-noise ratio estimation system includes: A signal preprocessing unit is used to obtain the squared term of the second moment of the signal under test and the fourth moment of the signal under test. The feature extraction unit includes a first leading zero detector, a second leading zero detector, a first wide decoder, a first barrel shifter, a second barrel shifter, and a first mask logic. The feature extraction unit is used to extract the first order exponent of the squared term of the second moment of the signal under test and the second order exponent of the fourth moment of the signal under test, and to extract the first normalized mantissa of the squared term of the second moment of the signal under test and the second normalized mantissa of the fourth moment of the signal under test. The differential indexing unit includes a first sign bit extension logic, a first subtractor, a first clamping logic, a second subtractor, truncation logic, and a system address mapping unit. The differential indexing unit is used to calculate a base address based on the first order of magnitude exponent and the second order of magnitude exponent, calculate an offset address based on the first normalized mantissa and the second normalized mantissa, and concatenate the base address and the offset address to form a complete memory retrieval address. The nonlinear mapping core includes a block read / write memory for a preset target baseline signal-to-noise ratio and a target fitting slope factor, a hardware multiplier, and a hardware adder. The nonlinear mapping core is used to retrieve the preset block read / write memory according to the complete memory retrieval address and perform piecewise linear interpolation to output the target signal-to-noise ratio estimate.

[0025] In summary, this application includes at least one of the following beneficial technical effects: 1. The moment characteristics of the signal under test are decomposed into a first-order exponent, a second-order exponent, a first-normalized mantissa, and a second-normalized mantissa. Base address and offset address are generated by subtraction between exponents and between mantissas, and then concatenated into a complete memory retrieval address bus, replacing the conventional arithmetic divider entity in the underlying logic circuit. Feature separation and differential addressing mechanisms free the data bus width of the logic operation node from the constraint of the absolute amplitude of the signal under test, avoiding numerical overflow when the underlying digital signal processing module performs long-width fixed-point operations. Furthermore, the iterative combinational logic network included in traditional division circuits is reduced, compressing the system clock cycle time of data flow through the computing node.

[0026] 2. The truncation logic divides the original mantissa difference into a preset primary index data segment and a preset secondary interpolation data segment. The nonlinear mapping core uses the target baseline SNR retrieved from the physical address, the target fitting slope factor, and the interpolation compensation mantissa to perform piecewise linear interpolation. The bit-width segmentation and split-output logic constructs parallel high-bit coarse addressing and low-bit fine compensation data channels, decoupling the binding relationship between the system estimation resolution and the physical memory capacity. The piecewise linear interpolation mechanism calls the underlying hardware digital multiplier and adder cores to restore the local precision discarded by the truncation operation, compensating for the quantization step error without expanding the number of static random access memory address bus pins, and controlling the silicon logic resource area occupied by the SNR estimation module.

[0027] 3. When the first clamping logic detects that the original exponent difference exceeds the preset upper limit threshold of the physical lookup table address or falls below the preset lower limit threshold of the physical lookup table address, it forcibly overwrites the original exponent difference with the preset lookup table address boundary extreme value and outputs it as the base address. The hardware-level boundary clamping mechanism uses the physical selection action of the underlying multiplexer to block the failure path caused by the timing disorder of the system memory bus due to the base address going out of bounds, and maintains the addressing output stability of the signal-to-noise ratio estimation hardware path when dealing with sudden fluctuations in the wide peak-to-average ratio baseband signal. Attached Figure Description

[0028] Figure 1 A flowchart illustrating a low-complexity signal-to-noise ratio estimation method based on a lookup table method in one embodiment of this application is shown. Detailed Implementation

[0029] The present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the scope of the application.

[0030] This application discloses a low-complexity signal-to-noise ratio estimation method based on table lookup, including the following steps S1-S4.

[0031] S1. Obtain the squared term of the second moment of the signal under test and the fourth moment of the signal under test.

[0032] The signal under test originates from the discrete-time complex baseband data stream sampled and output by the analog-to-digital converter (ADC) of the communication system's RF front-end. The data structure is a discrete digital sequence containing in-phase and quadrature components. The squared term of the second moment represents the expected square of the instantaneous power of the signal under test, reflecting the total energy distribution after the signal and noise are superimposed. The fourth moment represents the statistical mean of the square of the instantaneous power of the signal under test, reflecting the probability distribution characteristics of the signal envelope fluctuations. By extracting the squared term of the second moment and the fourth moment of the signal under test, the high-frequency fluctuating baseband signal waveform is transformed into a stable scalar value representing statistical characteristics, allowing the system to avoid the complex link of solving for point-by-point ratios of the instantaneous signal amplitude.

[0033] The signal preprocessing unit utilizes a low-level digital signal processing multiplier-accumulator array to acquire the squared term of the second-order moment and the fourth-order moment of the signal under test. The multiplier-accumulator array receives the discrete digital sequence of the signal under test, uses a low-level hardware multiplier to perform squaring calculations and higher-order multiplication operations on the in-phase and quadrature components, and utilizes internal accumulator logic to perform cross-cycle integration and accumulation on the discrete product data within a preset observation time window. The parallel multiply-accumulate data path converts discrete sampling points into unified moment characteristic values ​​through hardware computation.

[0034] In a specific implementation scenario where the baseband signal is processed at the receiver of a quadrature amplitude modulation (QAM) communication system, the physical bit width of the signal under test (SUT) output by the analog-to-digital converter (ADC) is set to 16 bits. When the SUT undergoes second-order moment squaring and higher-order fourth-order moment accumulation operations in the signal preprocessing unit, the data stream undergoes multi-stage cascaded multiplication in the underlying multiplier-accumulator network. This causes the squared term of the second-order moment of the output SUT and the fourth-order moment of the SUT to be expanded into a 64-bit wide-amplitude characteristic data on the numerical bus. The continuous integration of the wide dynamic range input signal within the preset observation time window further exacerbates the bit width occupancy of the high-order registers, ultimately generating a 64-bit moment characteristic value at the end of the multiply-accumulate data path.

[0035] S2. Extract the first order exponent of the squared term of the second moment of the signal under test and the second order exponent of the fourth moment of the signal under test, and extract the first normalized mantissa of the squared term of the second moment of the signal under test and the second normalized mantissa of the fourth moment of the signal under test.

[0036] The first and second order of magnitude exponents characterize the physical spatial location of the most significant bit (HN) of the second-order moment squared term and the fourth-order moment of the signal under test in the underlying register of the digital circuit. The longer-width second-order moment squared term and fourth-order moment have consecutive leading zero-level bits in the register. The values ​​of the order of magnitude exponents correspond to the starting physical pin numbers of the non-zero data sequence on the hardware register bus, reflecting the multiple relationship of the baseband signal power level difference. The first and second normalized mantissas are binary data segments composed of consecutive effective data bits. The normalized mantissa truncates the high-order zero bits and low-order thermal noise bits from the original register data sequence, aggregating the effective signal characteristics distributed in different intervals of the wide data bus into a fixed-width structure, directly defining the effective precision of the physical signal energy.

[0037] The feature extraction process divides the wide-width operand into two independent channels: the order of magnitude exponent and the normalized mantissa. The first and second order of magnitude exponents represent scaling parameters of the signal energy, while the first and second normalized mantissas represent high-precision numerical parameters at that scaling. This mechanism of separating wide-amplitude values ​​into order of magnitude exponents and precision mantissas frees the physical bit width of the feature bus from the constraint of the absolute amplitude of the signal under test, converging the wide numerical range into a narrow and fixed bit-width processing range.

[0038] Following the aforementioned implementation scenario of a 64-bit wide feature value, when the input second-order moment squared term is represented in the 64-bit register as a data sequence of 40 consecutive high-order leading zeros followed by 24 significant bits, the feature extraction unit extracts a first-order exponent of 23, indicating that the highest bit of the non-zero data is located at the 23rd physical pin. The feature extraction unit then extracts the higher 12 bits from these 24 significant bits at a fixed length to generate a 12-bit wide first normalized mantissa. The 64-bit data sequence with invalid zeros is then converted into a 6-bit wide first-order exponent and a 12-bit wide first normalized mantissa after the extraction operation.

[0039] Specifically, S2 includes the following sub-steps S21-S22.

[0040] S21. Scan the bit width of the squared term of the second moment of the signal under test to extract the first order of magnitude exponent, and scan the bit width of the fourth moment of the signal under test to extract the second order of magnitude exponent.

[0041] The leading zero detector hardware link detects the level state bit by bit from the high-order physical pin down through a combinational logic network. When the first high-level transition is captured, detection stops and the physical location number of the high-level pin is output, completing the bit width scan operation. The first and second order of magnitude exponents directly correspond to the rounded result of the logarithmic operation of the input data in the binary architecture, reflecting the multiple difference of the instantaneous power envelope of the baseband signal in different time windows. The leading zero detector converts the horizontally continuous spatially arranged wide bit-width data sequence into a scalar value representing the most significant bit vertically, realizing the circuit mapping conversion from linear data bit width to logarithmic scalar value.

[0042] When the instantaneous peak of the input signal generates a 64-bit wide second-order moment squared term, the leading zero detector logic network scans downwards from bit 63, continuously locking 40 zero-level pins. A level transition is detected at bit 23, and the first-order exponent, with a value of 23, is directly output. The fourth-order moment data link performs an equivalent hardware scan within the same clock cycle to generate the second-order exponent.

[0043] S22. Perform a shift and truncation operation on the squared term of the second moment of the signal under test according to the first order exponent to output the first normalized mantissa, and perform a shift and truncation operation on the fourth moment of the signal under test according to the second order exponent to output the second normalized mantissa.

[0044] Shift and truncation operations drive the underlying register array to uniformly slide the effective bit sequence scattered across different intervals of the wide data bus to the higher bits of the data bus, thus standardizing the effective load distribution of the underlying data bus. Normalization of the mantissa eliminates the bit difference caused by fluctuations in the absolute amplitude of the signal, characterizing the transient fluctuations of the signal waveform within a unified scaling framework. The shift and truncation actions directly strip away the sign extension bits in the higher bits of the bus and the redundant background noise bits in the lower bits through hardware connections, retaining the core effective bits that reflect the true energy distribution of the signal.

[0045] Specifically, S22 includes the following sub-steps S221-S223.

[0046] S221. Receive the first magnitude index and convert the first magnitude index into a first hardware control word.

[0047] S222. Perform a parallel left shift operation on the second-order moment squared term of the signal under test according to the first hardware control word, so that the preset valid data bits of the second-order moment squared term of the signal under test are aligned to the preset highest physical data bit of the preset target data bus.

[0048] S223. Apply a first hardware mask to extract a preset target bit-width data segment of the preset target data bus as the first normalized mantissa.

[0049] The first-order exponent is converted into a first hardware control word. An instruction decoder then parses the scalar value into physical gating signals for the underlying multiplexer array, directly driving the corresponding physical data gating path. A barrel shifter receives the first hardware control word and performs a parallel left shift operation on the input bus data based on a pure combinational logic network. This parallel structure allows data to slide without occupying additional clock cycles of waiting time, eliminating the clock delay of traditional serial shifters. A first hardware mask, through hard-wired shielding, physically disconnects or grounds register pins exceeding the preset target bit width, intercepting invalid transition signals from lower-order register ports and preventing irrelevant background noise from entering subsequent computational networks.

[0050] In the gate-level timing flow, the decoding network converts the first order of magnitude exponent of 23 into the first hardware control word of the barrel shifter. Based on the first hardware control word, the barrel shifter shifts the 24 significant bits of data starting from bit 23 of the 64-bit bus 40 bits to the left, aligning its most significant bit to bit 63 of the output bus. Subsequently, the first hardware mask directly truncates the physical connection from bit 51 to bit 0, precisely fixing the 12-bit data segment from bit 63 to bit 52, converting the left-shifted signal sequence into a first normalized mantissa with a fixed 12-bit width.

[0051] S3. Calculate the base address based on the first order of magnitude exponent and the second order of magnitude exponent, calculate the offset address based on the first normalized mantissa and the second normalized mantissa, and concatenate the base address and the offset address to form a complete memory retrieval address.

[0052] The process of independently calculating the exponent and mantissa and physically concatenating them to generate a complete memory retrieval address utilizes a basic adder / subtractor array and a direct-connection network of underlying pins to replace the numerical synthesis process within the arithmetic logic unit. This dual-channel architecture, which calculates separately and then physically merges the results, directly eliminates the multi-level interactive combinational logic required in traditional solutions to perform high-precision floating-point division on wide-range input data, reducing end-to-end clock latency in signal feature data flow. When processing baseband features with wide dynamic range fluctuations, the 6-bit wide first-order exponent and the 12-bit wide first normalized mantissa are differentially calculated in their respective independent hardware data paths, and then merged into a unified memory retrieval bus with a specific width in the underlying logic netlist, completing the hardware mapping from two parallel channels to a unique address coordinate.

[0053] Specifically, S3 includes the following sub-steps S31-S33.

[0054] S31. Receive the first magnitude index and the second magnitude index, and generate the base address based on the first magnitude index and the second magnitude index.

[0055] The base address represents the starting address of the page segment of the mapped data in the physical addressing space of the pre-defined block read / write memory. The base address is generated based on the magnitude exponent, and the logarithmic scalar difference obtained during the signal feature extraction stage is directly mapped to the vertical segment retrieval pin input of the lookup table. This bypasses the long-cycle division pipeline while constructing a nonlinear mapping reference with a specific bias. For the first magnitude exponent of 23 extracted from the 64-bit wide-range features and the second magnitude exponent generated during the same clock cycle, the underlying logic network performs logarithmic subtraction and merging on these two independent signal energy scaling parameters, converting them into a single base address channel value that guides page-by-page addressing of the physical memory.

[0056] Optionally, S31 includes the following sub-steps S311-S313.

[0057] S311. Receive the first magnitude index and the second magnitude index, and fill the first magnitude index and the second magnitude index with sign bits respectively to expand them into a first signed magnitude index and a second signed magnitude index.

[0058] S312. Perform a two's complement subtraction operation on the first signed exponent and the second signed exponent to generate the original exponent difference.

[0059] S313. When the original exponential difference is detected to exceed the preset upper limit threshold of the physical lookup table address or fall below the preset lower limit threshold of the physical lookup table address, the original exponential difference is forcibly overwritten as the preset lookup table address boundary extreme value as the base address output.

[0060] The first and second order of magnitude exponents are filled with their highest sign bits, giving the unsigned data the electrical properties of directional physical offset calculations, thus providing register width margin for subsequent negative difference representation. The underlying basic adder network inverts the second signed order of magnitude exponent, adds one, and adds it to the first signed order of magnitude exponent. Using two's complement subtraction, it performs the differential solution representing the signal power multiple difference, outputting the original exponent difference. Hardware clamping logic, forcibly overwritten to the preset lookup table address boundary extremes, constructs an address overflow protection barrier against abnormal burst input signals. The boundary clamping operation, through the physical selection action of the underlying multiplexer, blocks the failure path of reading unexpected mapped addresses caused by the original exponent difference exceeding the boundary.

[0061] In specific engineering scenarios where the baseband signal encounters sudden high-power background noise interference, the extracted second-order exponent rises rapidly due to the sharp increase in noise power. This causes the underlying binary two's complement subtraction network to output a negative original exponent difference value that is lower than the preset physical lookup table address lower limit threshold. At this time, the underflow flag pin of the underlying hardware is pulled high, triggering the multiplexer to switch the data selection path, directly cutting off the transmission connection of the negative difference to the next level register, and overwriting the pre-fixed minimum physical all-zero address extreme value pulled low to the output port as the base address, maintaining the address bus stability of the hardware system under the condition of drastic fluctuations in the peak-to-average power ratio of the signal.

[0062] S32. Receive the first normalized mantissa and the second normalized mantissa, subtract the second normalized mantissa from the first normalized mantissa to generate the original mantissa difference, and truncate the original mantissa difference to extract a preset truncated bit-width data segment as the offset address.

[0063] The offset address represents the physical location of the memory cell row offset within a specific data page. The operation of subtracting the second normalized mantissa from the first normalized mantissa to generate the original mantissa difference uses a local linear approximation to replace high-precision floating-point ratio calculations. This engineering mechanism, which transforms division into logarithmic addition and subtraction and performs direct subtraction in the mantissa field, avoids the iterative shift-and-subtraction network that consumes a large number of clock cycles in arithmetic dividers. Truncating the original mantissa difference to extract a preset truncated bit-width data segment limits the size of the parallel wiring directly connected to the lookup table address input pin, controlling the capacity expansion of the on-chip static random access memory.

[0064] Receive the 12-bit first normalized mantissa output by the aforementioned feature extraction unit, and assume that the second normalized mantissa output within the same clock cycle is also 12 bits wide. The underlying subtraction logic netlist receives these two 12-bit features and outputs the original mantissa difference with a width of 12 bits. To limit the address space, the hardware interconnect directly extracts the high-order bits of the original mantissa difference with a specific narrow bit width (e.g., the higher 6 bits) to generate an offset address with a specific narrow bit width.

[0065] Optionally, S32 includes the following sub-steps S321-S323.

[0066] S321. Divide the original mantissa difference into a preset primary index data segment and a preset secondary interpolation data segment according to the preset physical bit width dividing boundary.

[0067] S322. Set the preset main index data segment as the preset truncated bit-width data segment, and output the preset truncated bit-width data segment as the offset address.

[0068] S323. Output the preset secondary interpolation data segment as the interpolation compensation mantissa.

[0069] The preset physical bit-width segmentation boundary is represented on the underlying register data bus by a fixed arrangement and disconnection rule of physical connections. The hardware netlist forcibly separates the original continuous wire bundles at specific bit nodes. Preset secondary interpolation data segments are converted into interpolation compensation mantissas, retaining the underlying computational quantization residuals that detach from the high-order bus during the hard truncation process, forming a residual data storage mechanism. The primary index data segment is separated from the secondary interpolation data segment, constructing a parallel hardware channel for high-order coarse addressing and low-order fine compensation. This architectural separation logic severs the physical pin binding relationship between memory space depth and the final estimated resolution.

[0070] Following the register route that flows along the aforementioned 12-bit original mantissa difference, the preset physical bit-width split boundary is set between the 5th and 6th bits. The 12-bit continuous bundle splits at the split boundary, with the physical connections of the higher 6 bits (bits 11 to 6) converging into the main index address line, which is set as a preset truncated bit-width data segment and output as an offset address; the physical connections of the lower 6 bits (bits 5 to 0) converging into the secondary compensation data line, which retains the complete mantissa as interpolation compensation and outputs it.

[0071] S33. The base address and the offset address are physically concatenated to form the complete memory retrieval address.

[0072] Physical wiring directly aggregates two independent binary buses in terms of spatial pin arrangement through parallel harness bundling of the underlying logic netlist. This pure hardware wiring replaces the process of calling the arithmetic adder unit for data synthesis. The spatial combination of the base address harness and the offset address harness ensures that the two independently calculated address coordinate parameters arrive at the memory address input port within the same clock cycle. Harness bundling avoids the time consumption of the departmental carry chain within the arithmetic adder, compressing the end-to-end combinational logic delay in the feature indexing stage.

[0073] Received from the aforementioned computational path, the 6-bit wide base address bundle and the 6-bit wide offset address bundle are transmitted in parallel to the hardware splicing node. The underlying physical wiring splicing mechanism routes the 6-bit wide base address bundle to the high-order range of the target retrieval bus, i.e., pins 11 to 6, and routes the 6-bit wide offset address bundle to the low-order range of the target retrieval bus, i.e., pins 5 to 0. The two independently routed exponent logic channels and mantissa logic channels are connected through spatial pin arrangement and directly merged into a unified 12-bit wide physical address bus, forming a complete memory retrieval address for subsequent read operations.

[0074] S4. Retrieve the preset block read / write memory based on the complete memory retrieval address to output the target signal-to-noise ratio estimate.

[0075] The pre-configured block read / write memory is a static random access memory hardware module embedded within the field-programmable gate array (FPGA). The block read / write memory has independently distributed address bus pins, data output pins, and synchronous clock control pins. Once the complete memory retrieval address reaches the address input port of the block read / write memory, it directly triggers the physical gating network of the internal read circuit. The high and low level distributions on the address lines drive the row and column decoder arrays inside the memory, performing physical addressing and precisely activating the specific target memory cell matrix.

[0076] The physical address location and reading operation directly transforms the high-precision floating-point division and nonlinear logarithmic operations that require multiple iterations in a conventional structure into a static memory data extraction process within a single clock cycle. By replacing arithmetic computation time with fixed storage space, the mechanism offsets the long clock cycle delay caused by the traditional arithmetic logic unit performing complex nonlinear operations, effectively reducing the system clock consumption of the signal-to-noise ratio estimation module during the numerical conversion stage.

[0077] Received from the aforementioned 12-bit wide complete memory retrieval address generated by physically concatenating the base address and offset address, this 12-bit parallel harness is directly connected to the external addressing pin of the preset block read / write memory. When the rising edge of the system global clock arrives, the external logic pulls high the memory read enable port. The sensor amplifier inside the block read / write memory then locks onto the specific memory row selected by the 12-bit bus, and within the same system clock cycle, sends the pre-configured nonlinear mapping data in that memory row into the output register, directly latches it onto the next-level data link, and outputs the extracted signal-to-noise ratio related numerical parameters.

[0078] Specifically, the target reference signal-to-noise ratio and the target fitting slope factor are all programmed into the physical storage units of the preset block read / write memory. The step of outputting the target signal-to-noise ratio estimate in S4 includes: performing piecewise linear interpolation using the target reference signal-to-noise ratio, the target fitting slope factor, and the interpolation compensation mantissa to output the target signal-to-noise ratio estimate.

[0079] The target baseline signal-to-noise ratio and the target fitting slope factor characterize the intercept and tilt angle of a first-order linear distribution within a specific addressing interval. Fitting parameters are pre-programmed into the physical storage unit, compressing the massive nonlinear mapping table into a sparse discrete anchor array storage architecture. Piecewise linear interpolation operations utilize the interpolation compensation mantissa retained by the front-end truncation action to participate in the numerical reconstruction of the terminal signal-to-noise ratio result, compensating for the systematic quantization step error caused by the finite word length effect in the direct lookup table method. The separation mechanism that utilizes residuals in the calculation severs the absolute binding relationship between estimation accuracy and memory depth.

[0080] Following the 6-bit interpolation compensation mantissa generated by truncating and splitting the 12-bit original mantissa difference, the system reads the offline configured sparse anchor array and extracts the target baseline signal-to-noise ratio and target fitting slope factor corresponding to the complete memory retrieval address. The computational network combines this 6-bit interpolation compensation mantissa to perform linear extrapolation, completing the numerical reconstruction with full floating-point precision.

[0081] Specifically, the step of performing piecewise linear interpolation includes the following sub-steps S41-S43.

[0082] S41. Input the complete memory retrieval address into the preset block read / write memory, use the complete memory retrieval address to retrieve the physical storage unit, and output the target reference signal-to-noise ratio and the target fitting slope factor in parallel.

[0083] S42. Receive the target fitting slope factor and the interpolation compensation mantissa, and multiply the target fitting slope factor by the interpolation compensation mantissa to generate a dynamic error compensation amount.

[0084] S43. Receive the target reference signal-to-noise ratio and the dynamic error compensation amount, add the target reference signal-to-noise ratio to the dynamic error compensation amount to generate the target signal-to-noise ratio estimate, and output the target signal-to-noise ratio estimate.

[0085] The block read / write memory utilizes the wide data bus to output reference and slope data in parallel under a single addressing operation. The multiplication logic linearly maps the interpolation compensation mantissa, which is in the dimension of the input data, to the dynamic error compensation quantity, which is in the dimension of the output signal-to-noise ratio, completing the numerical conversion across physical dimensions. The addition logic performs bit-aligned synthesis of the static addressing anchor point and the dynamic fine-tuning component. The synthesis operation eliminates the dependence of high-precision requirements on high-density stacking of silicon chip storage space, achieving high-resolution feature reconstruction with limited memory capacity.

[0086] During the gate-level clock cycle, the 12-bit wide full memory retrieval address triggers the memory array in the first clock cycle, reading the target baseline SNR and the target fitting slope factor in parallel. In the second clock cycle, the underlying multiplier core directly multiplies the read slope factor with the 6-bit wide interpolation compensation mantissa to generate the dynamic error compensation. In the third clock cycle, the underlying adder core superimposes the dynamic error compensation onto the target baseline SNR data pin, driving the multiply-adder pipeline slice to generate a high-resolution SNR estimate.

[0087] A complete and specific embodiment is provided here for reference.

[0088] In step S1, the 16-bit discrete-time complex baseband data stream output from the analog-to-digital converter enters the multiply-accumulator array. After the underlying hardware performs multi-stage multiplication and cross-cycle integration and accumulation, a 64-bit wide second-order moment square term and a 64-bit wide fourth-order moment are generated on the data bus.

[0089] In step S2, the leading zero detector performs a parallel scan of the two 64-bit buses. When 40 consecutive zero levels appear in the high-order bits of the second-order moment square term and a high-level transition occurs at pin 23, the scan logic directly outputs a 6-bit wide first-order exponent, with a binary value of 010111. Similarly, when a high-level transition occurs at pin 25 of the fourth-order moment, a second-order exponent with a binary value of 011001 is generated. The barrel shifter receives the exponent signal and converts it into a control word, shifting the second-order moment square term bus 40 bits to the left, so that the most significant bit, originally located at pin 23, is slid and aligned to pin 63. Subsequently, the first hardware mask truncates the low-order connections, directly extracting a 12-bit binary sequence 101100101010 from pins 63 to 52 as the first normalized mantissa. The fourth-order matrix bus is synchronously shifted 38 bits to the left, and the resulting binary sequence 100111000101 is truncated by a mask and used as the 12-bit second normalized mantissa.

[0090] In step S3, the adder network performs a two's complement subtraction operation between the first-order exponent and the second-order exponent after extending the sign bit. Due to high-power noise interference on the input signal, subtracting 011001 from 010111 triggers the underflow flag pin of the underlying logic. The multiplexer detects the negative underflow signal and forces the output port to be overwritten to an all-zero state, outputting 000000 as a 6-bit base address. Simultaneously, the subtraction logic netlist subtracts the second-normalized mantissa 100111000101 from the first normalized mantissa 101100101010, generating a 12-bit original mantissa difference of 000101100101. The physical bit-width splitting logic truncates this difference on the register connection, splitting the sequence 000101 from the 11th to the 6th bit into a 6-bit offset address, and retaining the sequence 100101 from the 5th to the 0th bit as a 6-bit interpolation compensation mantissa. The physical wiring mechanism directly routes the base address bundle of 000000 and the offset address bundle of 000101 side by side on the pins to synthesize a complete memory retrieval address of 000000000101 with a width of 12 bits.

[0091] Upon execution to step S4, the full memory retrieval address 000000000101 drives the address input pin of the preset block read / write memory. The internal sensing amplifier of the memory positions itself to the corresponding memory row at the clock edge and outputs in parallel the pre-programmed binary data 01001100 as the target reference signal-to-noise ratio (SNR) and the binary data 00000011 as the target fitting slope factor. After receiving the data, the multiplier core performs hardware multiplication of the target fitting slope factor 00000011 with the previously reserved interpolation compensation mantissa 100101, generating the dynamic error compensation amount 01101111. The adder core performs bit-aligned superposition of the target reference SNR data pin 01001100 and the dynamic error compensation amount data pin 01101111, synthesizing the binary value 10111011 on the output bus, completing the hardware reconstruction and output of the full floating-point precision target SNR estimation value.

[0092] This application also discloses a low-complexity signal-to-noise ratio estimation system, including: A signal preprocessing unit is used to obtain the squared term of the second moment of the signal under test and the fourth moment of the signal under test. The feature extraction unit includes a first leading zero detector, a second leading zero detector, a first wide decoder, a first barrel shifter, a second barrel shifter, and a first mask logic. The feature extraction unit is used to extract the first order exponent of the squared term of the second moment of the signal under test and the second order exponent of the fourth moment of the signal under test, and to extract the first normalized mantissa of the squared term of the second moment of the signal under test and the second normalized mantissa of the fourth moment of the signal under test. The differential indexing unit includes a first sign bit extension logic, a first subtractor, a first clamping logic, a second subtractor, truncation logic, and a system address mapping unit. The differential indexing unit is used to calculate a base address based on the first order of magnitude exponent and the second order of magnitude exponent, calculate an offset address based on the first normalized mantissa and the second normalized mantissa, and concatenate the base address and the offset address to form a complete memory retrieval address. The nonlinear mapping core includes a block read / write memory for a preset target baseline signal-to-noise ratio and a target fitting slope factor, a hardware multiplier, and a hardware adder. The nonlinear mapping core is used to retrieve the preset block read / write memory according to the complete memory retrieval address and perform piecewise linear interpolation to output the target signal-to-noise ratio estimate.

[0093] The signal preprocessing unit, feature extraction unit, differential indexing unit, and nonlinear mapping core form a global hardware cascade and data flow topology within the underlying field-programmable gate array (FPGA). Abstract algorithmic logic operations flow directly to the underlying physical silicon chip logic netlist, arithmetic operation core, and memory block physical pins. Leading zero detectors and shifters are mapped to parallel combinational logic netlists, subtractors and clamping logic are mapped to adder arithmetic operation slices, and the nonlinear mapping table is mapped to a two-port block read / write memory. The hardware resource mapping mechanism transforms the signal-to-noise ratio estimation process into a regular transmission action of underlying electrical signals between different physical gate circuit pins.

[0094] The cascaded multi-hardware-unit pipeline architecture cuts off long combinational logic delay paths within a single cycle by inserting register flip-flops between different computing nodes. This cascaded architecture improves global data throughput and isolates the impact of wide dynamic range fluctuations on the system's highest operating clock frequency, maintaining the timing stability of the underlying hardware under high-speed sampling clocks.

[0095] In the end-to-end hardware pipeline's cycle time, baseband feature data continuously traverses the physical pins of various functional units, ultimately generating a full floating-point SNR estimate at the nonlinear mapping core. Specifically, after the initial observation window, the signal preprocessing unit outputs a 64-bit wide second-order moment square term and a fourth-order moment to the feature extraction unit. The feature extraction unit, through a combinational logic network, removes invalid bits within one clock cycle, outputting a 6-bit wide first-order exponent, a second-order exponent, and a 12-bit wide first-normalized mantissa, a second-normalized mantissa. The differential indexing unit receives these scaling and precision features, and through internal arithmetic logic and physical wiring concatenation, outputs a 12-bit wide complete memory retrieval address and a truncated 6-bit wide interpolation compensation mantissa to the next stage. The 12-bit complete memory retrieval address drives the nonlinear mapping core to read and write discrete anchor points in the memory block, and then performs linear interpolation within the subsequent multiply-accumulate pipeline slice, combining the 6-bit interpolation compensation mantissa to output the final high-resolution target SNR estimate.

[0096] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0097] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0098] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A low-complexity signal-to-noise ratio estimation method based on table lookup, characterized in that, Includes the following steps: S1. Obtain the squared term of the second moment of the signal under test and the fourth moment of the signal under test; S2. Extract the first order exponent of the squared term of the second moment of the signal under test and the second order exponent of the fourth moment of the signal under test, and extract the first normalized mantissa of the squared term of the second moment of the signal under test and the second normalized mantissa of the fourth moment of the signal under test. S3. Calculate the base address based on the first order of magnitude exponent and the second order of magnitude exponent, calculate the offset address based on the first normalized mantissa and the second normalized mantissa, and concatenate the base address and the offset address to form a complete memory retrieval address; S4. Retrieve the preset block read / write memory based on the complete memory retrieval address to output the target signal-to-noise ratio estimate.

2. The low-complexity signal-to-noise ratio estimation method based on table lookup as described in claim 1, characterized in that, S2 includes the following sub-steps: S21. Scan the bit width of the squared term of the second moment of the signal under test to extract the first order of magnitude exponent, and scan the bit width of the fourth moment of the signal under test to extract the second order of magnitude exponent. S22. Perform a shift and truncation operation on the squared term of the second moment of the signal under test according to the first order exponent to output the first normalized mantissa, and perform a shift and truncation operation on the fourth moment of the signal under test according to the second order exponent to output the second normalized mantissa.

3. The low-complexity signal-to-noise ratio estimation method based on table lookup as described in claim 2, characterized in that, S22 includes the following sub-steps: S221. Receive the first magnitude index and convert the first magnitude index into a first hardware control word; S222. Perform a parallel left shift operation on the second-order moment squared term of the signal under test according to the first hardware control word, so that the preset valid data bits of the second-order moment squared term of the signal under test are aligned to the preset highest physical data bit of the preset target data bus; S223. Apply a first hardware mask to extract a preset target bit-width data segment of the preset target data bus as the first normalized mantissa.

4. The low-complexity signal-to-noise ratio estimation method based on table lookup as described in claim 1, characterized in that, S3 includes the following sub-steps: S31. Receive the first magnitude index and the second magnitude index, and generate the base address based on the first magnitude index and the second magnitude index; S32. Receive the first normalized mantissa and the second normalized mantissa, subtract the second normalized mantissa from the first normalized mantissa to generate the original mantissa difference, and truncate the original mantissa difference to extract a preset truncated bit-width data segment as the offset address. S33. The base address and the offset address are physically concatenated to form the complete memory retrieval address.

5. The low-complexity signal-to-noise ratio estimation method based on table lookup as described in claim 4, characterized in that, S31 includes the following sub-steps: S311. Receive the first magnitude index and the second magnitude index, and fill the first magnitude index and the second magnitude index with sign bits respectively to expand them into a first signed magnitude index and a second signed magnitude index; S312. Perform a two's complement subtraction operation on the first signed exponent and the second signed exponent to generate the original exponent difference; S313. When the original exponential difference is detected to exceed the preset upper limit threshold of the physical lookup table address or fall below the preset lower limit threshold of the physical lookup table address, the original exponential difference is forcibly overwritten as the preset lookup table address boundary extreme value as the base address output.

6. The low-complexity signal-to-noise ratio estimation method based on table lookup as described in claim 4, characterized in that, S32 includes the following sub-steps: S321. Divide the original mantissa difference into a preset primary index data segment and a preset secondary interpolation data segment according to the preset physical bit width dividing boundary; S322. Set the preset main index data segment as the preset truncated bit-width data segment, and output the preset truncated bit-width data segment as the offset address; S323. Output the preset secondary interpolation data segment as the interpolation compensation mantissa.

7. The low-complexity signal-to-noise ratio estimation method based on table lookup as described in claim 6, characterized in that, The target reference signal-to-noise ratio and the target fitting slope factor are all burned into the physical storage units of the preset block read-write memory. The step of outputting the target signal-to-noise ratio estimate in S4 includes: performing piecewise linear interpolation using the target baseline signal-to-noise ratio, the target fitting slope factor, and the interpolation compensation tail to output the target signal-to-noise ratio estimate.

8. The low-complexity signal-to-noise ratio estimation method based on table lookup as described in claim 7, characterized in that, The step of performing piecewise linear interpolation includes the following sub-steps: S41. Input the complete memory retrieval address into the preset block read / write memory, and use the complete memory retrieval address to retrieve the physical storage unit, so as to output the target reference signal-to-noise ratio and the target fitting slope factor in parallel; S42. Receive the target fitting slope factor and the interpolation compensation tail number, and multiply the target fitting slope factor by the interpolation compensation tail number to generate a dynamic error compensation amount; S43. Receive the target reference signal-to-noise ratio and the dynamic error compensation amount, add the target reference signal-to-noise ratio to the dynamic error compensation amount to generate the target signal-to-noise ratio estimate, and output the target signal-to-noise ratio estimate.

9. A low-complexity signal-to-noise ratio estimation system, characterized in that, A method for implementing the low-complexity signal-to-noise ratio estimation method based on the lookup table method as described in any one of claims 1 to 8 includes: A signal preprocessing unit is used to obtain the squared term of the second moment of the signal under test and the fourth moment of the signal under test. The feature extraction unit includes a first leading zero detector, a second leading zero detector, a first wide decoder, a first barrel shifter, a second barrel shifter, and a first mask logic. The feature extraction unit is used to extract the first order exponent of the squared term of the second moment of the signal under test and the second order exponent of the fourth moment of the signal under test, and to extract the first normalized mantissa of the squared term of the second moment of the signal under test and the second normalized mantissa of the fourth moment of the signal under test. The differential indexing unit includes a first sign bit extension logic, a first subtractor, a first clamping logic, a second subtractor, truncation logic, and a system address mapping unit. The differential indexing unit is used to calculate a base address based on the first order of magnitude exponent and the second order of magnitude exponent, calculate an offset address based on the first normalized mantissa and the second normalized mantissa, and concatenate the base address and the offset address to form a complete memory retrieval address. The nonlinear mapping core includes a block read / write memory for a preset target baseline signal-to-noise ratio and a target fitting slope factor, a hardware multiplier, and a hardware adder. The nonlinear mapping core is used to retrieve the preset block read / write memory according to the complete memory retrieval address and perform piecewise linear interpolation to output the target signal-to-noise ratio estimate.

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