Networking method based on a honeycomb soft bus module and electronic device

Abstract

This application discloses a networking method and electronic device based on the HarmonyOS soft bus module. The method involves a processor storing discovery messages from access devices into random access memory (RAM); reading and broadcasting the discovery messages using a field-programmable gate array (FPGA); and if a response message from each access device is received, storing the response message in RAM using the FPGA. The processor then reads the response message to network each access device. This offloads the processor's functionality to the FPGA, accelerating large-scale networking, reducing the processor's workload and resource consumption, and improving networking efficiency.

Description

Technical Field

[0001] This application relates to the field of Internet of Things (IoT) technology, and in particular to a networking method and electronic device based on the HarmonyOS soft bus module. Background Technology

[0002] With the accelerating arrival of the era of the Internet of Everything, IoT technology has become a core driving force for the intelligent upgrading of industries. Efficient collaboration between devices, seamless cross-scenario connectivity, and large-scale networking capabilities have become key challenges for the development of the IoT ecosystem. HarmonyOS, an open-source, fully independent and controllable distributed operating system, achieves automatic device identification and dynamic networking through distributed soft bus technology, building high-bandwidth, low-latency communication links and becoming an important foundation for cross-device collaboration.

[0003] However, with the surge in the number of IoT devices and the continuous expansion of network scale requirements, HarmonyOS soft bus only supports networking of a limited number of devices. Although the software optimization solution can be extended to networking of medium-sized devices, its networking time is long and consumes a lot of central processing unit computing power, which cannot meet the self-discovery and self-organization requirements of large-scale scenarios, resulting in HarmonyOS soft bus being unable to be applied on a large scale in the IoT field. Summary of the Invention

[0004] Based on this, this application provides a networking method and electronic device based on the HarmonyOS soft bus module, which can reduce the consumption of processor resources and improve networking efficiency while carrying out large-scale networking.

[0005] Firstly, this application provides a networking method based on a HarmonyOS soft bus module, which is applied to a networking system based on a HarmonyOS soft bus module running a HarmonyOS soft bus. The networking system based on the HarmonyOS soft bus module includes at least one master device and multiple access devices. Both the master device and the access devices have a HarmonyOS soft bus module inside. The master device includes a processor, random access memory, and field-programmable gate array circuitry. The method includes:

[0006] The processor places the discovery message of the access device into the random access memory. The discovery message is read from the field-programmable gate array circuit and then broadcast. If a response message is received from each access device in response to the discovery message, the response message is placed into the random access memory according to the field programmable gate array circuit. The processor reads the response message to configure the network for each access device.

[0007] Secondly, this application also provides a networking system based on the HarmonyOS soft bus module, including: At least one master device, the master device including a processor, random access memory and field-programmable gate array circuit, the processor and the field-programmable gate array circuit are both connected to the random access memory, the processor is configured to put the discovery message of the discovery access device into the random access memory, and the field-programmable gate array circuit is configured to read the discovery message from the random access memory and broadcast the discovery message. Multiple access devices, each configured to send a response message to the field programmable gate array (FPGA) based on the discovery message broadcast by the FPGA circuit; Both the main device and the access device have a HarmonyOS soft bus module. The field-programmable gate array circuit is also configured to put each response message into the random access memory. The processor is also configured to read each response message from the random access memory to network each access device.

[0008] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the networking method based on the HarmonyOS soft bus module provided in the first aspect above.

[0009] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to execute the networking method based on the HarmonyOS soft bus module provided in the first aspect.

[0010] Fifthly, embodiments of this application also provide a computer program product, including a computer program or instructions, wherein the computer program or instructions are executed by a processor to perform the networking method based on the HarmonyOS soft bus module provided in the first aspect.

[0011] The networking method based on the HarmonyOS soft bus module provided in this application involves the processor placing discovery messages for access devices into random access memory; reading and broadcasting the discovery messages according to the field-programmable gate array (FPGA); and if a response message is received from each access device responding to the discovery message, the response message is placed into random access memory according to the FPGA, and then the processor reads the response message to network each access device. This offloads the processor's functions to the FPGA, thereby accelerating large-scale networking, reducing the processor's burden and resource consumption, and improving networking efficiency. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A schematic block diagram of a networking system based on the HarmonyOS soft bus module provided in an embodiment of this application; Figure 2 A schematic block diagram of the main device provided in the embodiments of this application; Figure 3 This is a flowchart illustrating the networking method based on the HarmonyOS soft bus module provided in the embodiments of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0016] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0017] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0018] Furthermore, in this application, unless otherwise explicitly specified or limited in the embodiments, the terms "installation," "connection," "joining," and "fixing" appearing in the embodiments should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral part; it can also be a mechanical connection, an electrical connection, etc. Of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication between two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific implementation.

[0019] Among related technologies, the open-source Harmony OS, as a fully independent and controllable distributed operating system, has become a breakthrough solution for solving the problem of cross-device collaboration due to its architecture concept of "develop once, deploy on multiple devices" and distributed soft bus technology.

[0020] The open-source HarmonyOS operating system virtualizes heterogeneous terminals such as sensors and industrial equipment into a unified super terminal through a distributed architecture. Its innovative soft bus technology, centered on self-discovery and self-organizing networking, builds high-bandwidth, low-latency communication links, enabling automatic device identification and dynamic networking. It can quickly complete device topology construction and achieve end-to-end ultra-fast transmission of ≤10ms, enabling 4K video stream bandwidth utilization to exceed 85%. As the "neural network" of the distributed system, the HarmonyOS soft bus, through its intelligent connection scheduling mechanism, becomes the cornerstone of cross-device collaboration. As a core component of the HarmonyOS operating system, the HarmonyOS soft bus plays a crucial role in achieving efficient communication and resource sharing between devices.

[0021] However, driven by industrial development, HarmonyOS soft bus also faces many challenges in its large-scale deployment.

[0022] First, with the surge in the number of IoT devices, the demand for network scale is also constantly expanding. The existing open-source HarmonyOS soft bus can only support networking of 10+ devices; software optimization supports networking of 200 devices, but the networking time is long and CPU computing power is high, resulting in the inability to scale linearly. Consequently, it cannot meet the self-discovery and self-organizing networking requirements of large-scale scenarios with 200 to 1000 devices, let alone the requirements for multi-service parallel networking.

[0023] Secondly, the overhead during discovery and networking also becomes a limiting factor. Under current conditions, discovering and networking 10+ devices is extremely CPU-intensive. The software protocol stack handles the networking process inefficiently, with long processing times and high CPU consumption. This not only fails to linearly improve performance but also severely impacts the stable operation of business applications, leading to a decline in overall system performance.

[0024] Furthermore, different IoT devices exhibit significant differences in underlying computing power due to variations in chip architecture. The underlying protocol stack used by HarmonyOS's soft bus relies on software to handle network communication protocols at various levels, consuming substantial CPU resources. This results in inconsistent performance of the soft bus across different chip architectures, making it unable to accommodate heterogeneous chips with varying computing power across different architectures. Simultaneously, the extended time required to update session keys during the networking process affects the frequency of session key updates, increasing communication security risks. These risks include weakened forward security, increased feasibility of brute-force attacks, a wider window for man-in-the-middle attacks, a prolonged impact period on key leaks, increased pressure to defend against replay attacks, and the risk of key entropy decay.

[0025] It is evident that the limited scale of HarmonyOS soft bus in the industry's development is mainly reflected in the constraints of network scale, slow network speed, high CPU utilization, security risks, and insufficient transmission performance, which in turn prevents HarmonyOS soft bus from being widely applied in the Internet of Things field.

[0026] To address this, this application provides a networking system based on the HarmonyOS soft bus module, including at least one master device and multiple access devices. The master device includes a processor, random access memory (RAM), and a field-programmable gate array (FPGA). Both the processor and the FPGA are connected to the RAM. The processor is configured to store discovery messages from the access devices into the RAM, and the FPGA is configured to read and broadcast discovery messages from the RAM. Each access device is configured to send a response message to the FPGA based on the discovery message broadcast by the FPGA. The FPGA is also configured to store each response message into the RAM, and the processor is further configured to read each response message from the RAM to network each access device. This offloads the processor's functionality to the FPGA, accelerating large-scale networking, reducing the processor's burden and resource consumption, and improving networking efficiency.

[0027] For ease of understanding, the following explains some key terms in this embodiment: A networking system based on the HarmonyOS soft bus module can be understood as an overall architecture capable of enabling interconnection, communication, and resource sharing among multiple devices. In this application, the system aims to support large-scale, efficient device interconnection via the HarmonyOS soft bus.

[0028] As the core communication mechanism of the HarmonyOS operating system, the HarmonyOS Soft Bus provides capabilities such as device self-discovery, self-networking, and data transmission, aiming to achieve seamless collaboration and resource sharing among devices. Functionally, the HarmonyOS Soft Bus is logically divided into a device discovery module, a connection management module, a networking and topology module, and a data transmission module. The HarmonyOS Soft Bus module mentioned in this application runs in every device participating in the networking system and can be pre-installed at the factory.

[0029] The master device can be understood as the device that plays a core control role in the networking system based on the HarmonyOS soft bus module, responsible for initiating device discovery, managing the networking process, and coordinating data transmission.

[0030] A processor (Central Processing Unit, CPU) can be understood as the central processing unit in a main device, responsible for executing software instructions, performing logical operations, and controlling system operations. In this application, it mainly undertakes high-level protocol processing and networking decisions.

[0031] Random Access Memory (RAM) can be understood as a storage unit in the master device used for temporary storage of data and instructions. In this application, it serves as a shared buffer for exchanging discovery and response messages between the processor and the field-programmable gate array circuit.

[0032] A Field Programmable Gate Array (FPGA) can be understood as a configurable integrated circuit capable of implementing specific hardware logic functions through programming. In this application, it is configured to offload some tasks from the processor during the device discovery and response processing phases, thereby achieving hardware acceleration.

[0033] like Figure 2As shown, in this application, the field-programmable gate array circuit includes PCIe DMA_IP (hardware logic module), REG (register), HOSTIF_RX (host interface receive module), HOSTIF_TX (host interface transmit module), RX_EDIT (receive editing module), MSG_TX (message send module), PKT_DECRP (packet decryption module), PKT_ENCRP (packet encryption module), RX_QUE (receive queue), TX_QUE (transmit queue), PARSER (protocol parsing module), RX_MEM (receive memory), TCP_LINK (core connection state management module), TCP_TABLE (TCP connection management module), TX_EDIT (transmit editing module), MAC_RX (MAC receive module), MAC_TX (MAC transmit module), RGMII_RX (RGMII receive module), and RGMII_TX (RGMII transmit module).

[0034] Access devices can be understood as terminal devices that need to join a networking system based on the HarmonyOS soft bus module and communicate with the master device. They can respond to the master device's discovery request and participate in the networking process.

[0035] Discovery messages can be understood as specific data packets sent by the master device to probe and identify available access devices in the network.

[0036] A response message can be understood as a data packet containing confirmation and its own information sent by the access device to the master device after receiving a discovery message.

[0037] Networking can be understood as the process of connecting multiple independent access devices to a networking system based on the HarmonyOS soft bus module through a series of protocols and operations, enabling them to communicate with each other and work collaboratively.

[0038] Please see Figure 1 , Figure 1 This is a schematic block diagram of a networking system based on the HarmonyOS soft bus module provided in an embodiment of this application. Figure 1 As shown, this application provides a networking system based on the HarmonyOS soft bus module, including: At least one master device, the master device including a processor, random access memory and field-programmable gate array circuit, the processor and the field-programmable gate array circuit are both connected to the random access memory, the processor is configured to put the discovery message of the discovery access device into the random access memory, and the field-programmable gate array circuit is configured to read the discovery message from the random access memory and broadcast the discovery message. Multiple access devices, each configured to send a response message to the field programmable gate array (FPGA) based on the discovery message broadcast by the FPGA circuit; Both the main device and the access device have a built-in HarmonyOS soft bus module. The field-programmable gate array circuit is also configured to put each response message into the random access memory. The processor is also configured to read each response message from the random access memory to network each access device.

[0039] A networking system based on the HarmonyOS soft bus module can be understood as an overall architecture capable of enabling interconnection, communication, and resource sharing among multiple devices. In this application, the networking system based on the HarmonyOS soft bus module aims to support large-scale, efficient device interconnection via the HarmonyOS soft bus.

[0040] In this embodiment, the networking system based on the HarmonyOS soft bus module can be an Internet of Things (IoT) environment consisting of multiple smart devices, where the HarmonyOS soft bus serves as the underlying communication framework, responsible for the connection and data exchange between devices.

[0041] Specifically, a networking system based on the HarmonyOS soft bus module includes at least one master device, which has the HarmonyOS soft bus module built-in. The master device can be a high-performance computing unit, such as an industrial controller, edge gateway, or server. Internally, the master device includes a processor, random access memory (RAM), and a field-programmable gate array (FPGA). The processor can be a general-purpose CPU, such as an ARM-based processor. The RAM can be a DDR memory module, providing high-speed data access capabilities. The FPGA can be a standalone chip, implementing specific hardware functions through its programmable logic.

[0042] Both the processor and the field-programmable gate array (FPGA) are connected to random access memory (RAM). For example, the processor can directly access RAM through its memory controller. The FPGA can access RAM through its internal memory interface logic or through a memory bus interface shared with the processor.

[0043] The processor is configured to place discovery messages for access devices into random access memory (RAM). Specifically, the processor can generate discovery messages conforming to the HarmonyOS soft bus protocol specification and write these message data into a preset buffer in the RAM. The processor can maintain a pointer or index indicating the starting position and length of the discovery message in the RAM.

[0044] Field-programmable gate arrays (FPGAs) are configured to read discovery messages from random access memory (RAM) and broadcast them. For example, an FPGA can periodically check a specific address in RAM to determine if a new discovery message is available to read. Once a discovery message is detected, the FPGA reads it from RAM and broadcasts it via its integrated network interface (e.g., a simple Ethernet MAC controller).

[0045] Multiple access devices, each with a built-in HarmonyOS soft bus module, are configured to send a response message to the field-programmable gate array (FPGA) based on the discovery message broadcast by the FPGA. Each access device can be a smart sensor, smart home appliance, or industrial terminal. Upon receiving the discovery message broadcast by the FPGA, the access device's internal communication module parses the message and generates a response message containing its own information. The access device then sends this response message back to the FPGA.

[0046] When a field-programmable gate array (FPGA) circuit receives a response message from an access device, its internal message processing logic parses the response message and writes the message payload or complete message data into a preset receive buffer in the random access memory.

[0047] The processor is also configured to read each response message from random access memory to network each access device. For example, the processor can be configured to read these messages from random access memory when a new response message is detected in the receive buffer. Subsequently, based on the device information in the read response message, the processor executes the higher-level networking logic of the HarmonyOS soft bus, such as establishing a secure connection, allocating network resources, or registering device services, thereby completing the networking of the access devices.

[0048] In this application, by offloading the device discovery and response processing tasks in the HarmonyOS soft bus to the field-programmable gate array circuit, the computing power occupation of the main device processor is effectively reduced, thereby significantly improving the speed and efficiency of large-scale device networking and supporting more device access. This overcomes the limitations of the traditional HarmonyOS soft bus in terms of networking scale, speed and CPU load, and enhances the performance and stability of the system in IoT scenarios.

[0049] In one embodiment, the master device further includes an AXI interface; wherein the AXI interface is connected to the processor, the random access memory and the field programmable gate array circuit respectively to transmit discovery messages and response messages.

[0050] In this embodiment, the AXI interface is a high-performance, high-bandwidth on-chip bus protocol that serves as a data transmission channel between the processor, random access memory (RAM), and field-programmable gate array (FPGA) circuits, enabling efficient data exchange. The AXI interface can employ an AXI memory-mapped mode for processor access to the FPGA's internal registers or memory space, or an AXI stream mode for high-speed, continuous data stream transmission, such as the rapid transfer of discovery and response messages. By incorporating an AXI interface into the host device, this application effectively reduces processor intervention during data transmission, thereby improving data transmission efficiency.

[0051] In this application, the introduction of the AXI interface provides a high-speed, low-latency data transmission path between the processor, random access memory, and field-programmable gate array circuits, significantly improving the transmission efficiency of discovery and response messages, reducing the burden on the processor in data handling, and thus alleviating the efficiency bottleneck.

[0052] Furthermore, in one embodiment, the field-programmable gate array circuit is provided with a PCIe DMA IP core, which is connected to an AXI interface.

[0053] In this embodiment, the PCIe DMA IP core is a hardware logic module for implementing direct memory access (DMA) via the PCIe (PCI Express) bus. It allows peripherals to directly read and write system memory without occupying processor resources, thereby achieving efficient data transfer.

[0054] For example, the PCIe DMA IP core can use the XDMA IP core provided by Xilinx. The PCIe DMA IP core supports independent read and write DMA channels, can handle the transfer of multiple hashed memory blocks, and is connected to the internal logic of the field programmable gate array circuit through the AXI interface.

[0055] As an example, this application can also design and implement a custom DMA controller IP core inside the field-programmable gate array circuit. The PCIe DMA IP core is responsible for managing DMA transfer requests on the PCIe bus, including address mapping, data transfer, interrupt generation and other functions.

[0056] The AXI interface can be either an AXI Memory Mapped (AXI-MM) interface for memory-mapped access, supporting burst transfers and wide data bit widths, suitable for batch data processing, such as data exchange between internal logic of a field-programmable gate array (FPGA) and random access memory; or an AXI Stream (AXI-ST) interface for streaming data transmission, requiring no address bus, supporting unlimited data burst sizes, suitable for data stream processing, such as data pipelines between internal modules of an FPGA.

[0057] In this application, by introducing a PCIe DMA IP core, the field-programmable gate array (FPGA) circuit can directly exchange data with the random access memory at high speed. This significantly reduces the processor's intervention in the transmission of discovery and response messages, thereby effectively reducing the processor's load and improving data transmission efficiency. The GE interface provides a stable gigabit-level wired communication channel between the FPGA circuit and the first switch, ensuring that high-concurrency discovery and response messages can be transmitted at line speed in large-scale networking scenarios. This avoids data congestion and processing delays caused by insufficient network bandwidth, solving the problems of insufficient data transmission efficiency, high CPU utilization, slow networking speed, and limited interface expansion capabilities in large-scale networking. This enables the HarmonyOS soft bus to support larger-scale, higher-concurrency device networking and ensures the stability and reliability of system performance.

[0058] In one embodiment, the networking system based on the HarmonyOS soft bus module further includes at least one first switch; wherein the first switch is connected to a field-programmable gate array circuit and multiple access devices respectively, and is configured to transmit discovery messages and response messages.

[0059] In this embodiment, the first switch is a network device, which can be a core switch used to connect multiple network devices and forward data frames. The function of the first switch is to expand the physical connectivity of the field-programmable gate array (FPGA), enabling the FPGA to connect to more access devices, thereby achieving large-scale wired networking. The first switch can be an Ethernet switch supporting multiple port speeds, such as Gigabit Ethernet ports, to meet the connection needs of different access devices.

[0060] In one embodiment, the networking system based on the HarmonyOS soft bus module further includes at least one GE interface; wherein one end of the GE interface is connected to a field-programmable gate array circuit, and the other end of the GE interface is connected to a first switch.

[0061] In this embodiment, the GE interface can be understood as a gigabit Ethernet interface, which is a physical interface that supports a data transmission rate of 1Gbps and is used to realize wired network connections between devices.

[0062] For example, a GE interface can be composed of an RGMII (Reduced Gigabit Media Independent Interface) interface and a Gigabit Ethernet physical layer chip. The RGMII interface achieves Gigabit Ethernet connectivity by reducing the number of pins and is usually used in conjunction with an external Gigabit Ethernet physical layer (PHY) chip to convert digital signals into physical layer signals for transmission.

[0063] Alternatively, the GE interface can be composed of an SGMII (Serial Gigabit Media Independent Interface) interface and a Gigabit Ethernet physical layer chip. The SGMII interface transmits data through serial differential signals, has fewer pins and a longer transmission distance, and also requires an external PHY chip.

[0064] In one embodiment, the GE interface includes an RGMII interface and a Gigabit Ethernet physical layer chip; wherein, one end of the RGMII interface is connected to a field-programmable gate array circuit, and the Gigabit Ethernet physical layer chip is connected to the other end of the RGMII interface and a first switch.

[0065] In this embodiment, the GE interface adopts a combination of the RGMII interface and the Gigabit Ethernet physical layer chip. The RGMII interface, through its simplified pin design and double data rate technology, realizes efficient data exchange between the MAC layer and the PHY layer, overcoming the shortcomings of traditional interfaces with a large number of pins and complex wiring at gigabit speeds, and ensuring low latency and high throughput of data transmission.

[0066] The Gigabit Ethernet physical layer chip is responsible for converting the digital signals output from the RGMII interface into analog signals that can be transmitted over the physical medium, and for reliable transmission and reception, ensuring the stability and compatibility of data on the physical link.

[0067] One end of the RGMII interface is directly connected to a field-programmable gate array (FPGA), enabling efficient data output from the FPGA, reducing latency in intermediate stages, and improving the processing speed of discovery and response messages.

[0068] Meanwhile, the Gigabit Ethernet physical layer chip connects to the other end of the RGMII interface and the first switch, ensuring a stable and high-speed physical connection between the field-programmable gate array circuit and the first switch, providing a solid foundation for the transmission of discovery and response messages in large-scale networking.

[0069] In one embodiment, the networking system based on the HarmonyOS soft bus module further includes multiple second switches; wherein the second switches are respectively connected to the second switches and the access devices, and are configured to transmit discovery messages and response messages.

[0070] In this embodiment, the second switch is a network device, which can be understood as an access switch, used to forward data frames in a local area network. It achieves accurate forwarding by learning the MAC address table, thereby expanding network connectivity and managing network traffic.

[0071] For example, the second switch can be an Ethernet switch with multiple ports, capable of connecting multiple access devices and an upstream switch (such as the first switch) to achieve data frame forwarding and isolation.

[0072] Alternatively, the second switch can also be an industrial-grade switch, designed for industrial environments, with higher reliability, a wider operating temperature range, and stronger anti-interference capabilities, making it suitable for harsh industrial IoT scenarios.

[0073] In this application, by introducing multiple second switches, the networking system can further expand its connectivity, incorporate more access devices into the network, and form a multi-level network topology. This not only increases the network scale but also enhances the network's flexibility and scalability.

[0074] In one embodiment, the second switch is connected to the first switch via a wired or wireless connection.

[0075] In this embodiment, the second switch and the first switch are connected by wired or wireless connection, which provides a flexible connection method for the networking system, enabling the system to adapt to different deployment environments and network topology requirements, and enhancing the system's scalability and adaptability.

[0076] For example, wired connections can be selected in scenarios requiring high bandwidth and low latency, while wireless connections can be selected in scenarios requiring deployment flexibility and mobility. This ensures data transmission efficiency and stability while improving the deployment flexibility and environmental adaptability of the entire networking system, and further optimizes the performance of HarmonyOS soft bus in large-scale networking scenarios.

[0077] In one embodiment, the field-programmable gate array circuit uses a wireless local area network physical layer chip to wirelessly connect with multiple access devices.

[0078] In this embodiment, the field-programmable gate array (FPGA) circuit can acquire wireless communication capabilities by integrating or connecting a wireless LAN physical layer chip. The wireless LAN physical layer chip is responsible for handling physical layer functions such as modulation and demodulation of radio signals and RF transceiver, enabling the FPGA circuit to communicate with access devices wirelessly (e.g., via Wi-Fi). This provides flexible wireless networking options, allowing the system to adapt to more diverse deployment environments and solving the problem of limited connectivity options.

[0079] In one embodiment, the networking system based on the HarmonyOS soft bus module further includes a cloud server; wherein the cloud server communicates with at least one master device.

[0080] In this embodiment, the cloud server possesses powerful computing, storage, and networking capabilities. The cloud server communicates with at least one host device and can serve as a remote management, data aggregation, and analysis platform for a networking system based on the HarmonyOS soft bus module.

[0081] Specifically, this application establishes a communication connection between a cloud server and the main device. The cloud server can receive network status information and device data from the main device, and send configuration commands or software updates to the main device, thereby enabling remote monitoring, management and maintenance of the entire networking system based on the HarmonyOS soft bus module.

[0082] It is understood that the networking system based on the HarmonyOS soft bus module provided in the above embodiments is merely an example. The networking system based on the HarmonyOS soft bus module described in the embodiments of this application is to more clearly illustrate the technical solutions of the embodiments of this application, and does not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of the system and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems. Detailed descriptions will follow.

[0083] It should be noted that the order of description in the following embodiments is not intended to limit the preferred order of embodiments. The networking method based on the HarmonyOS soft bus module will be described in detail below. Furthermore, the networking method based on the HarmonyOS soft bus module provided in this application can be executed by the master device within a networking system based on the HarmonyOS soft bus module.

[0084] The networking method based on the HarmonyOS soft bus module provided in this application will be described in detail below.

[0085] like Figure 2 As shown, the method includes the following steps S210~S240.

[0086] S210. The processor places the discovery message of the access device into the random access memory. S220: Read the discovery message according to the field programmable gate array circuit and broadcast the discovery message; S230. If a response message is received from each access device in response to the discovery message, the response message is placed into the random access memory according to the field programmable gate array circuit. S240: Read the response message from the processor to form a network for each access device.

[0087] In this embodiment, the processor can put the discovery message of the access device into the random access memory, and after completing the initialization task, it exits the real-time processing stage of network communication. The field-programmable gate array circuit reads the discovery message from the random access memory and efficiently broadcasts the discovery message through its hardware parallel capability, avoiding direct intervention of the processor in the transmission process.

[0088] When an access device receives a discovery message, it immediately generates a response message and sends it to the field-programmable gate array (FPGA). The FPGA receives and parses the response message at line speed, places each response message into a preset receive buffer in the random access memory (RAM), and finally the processor only needs to read the response message from the RAM, execute higher-level networking decisions based on the device information, and complete the establishment of secure connections and resource allocation for each access device.

[0089] Specifically, this application offloads the broadcasting of discovery messages and the receiving of response messages to the field-programmable gate array (FPGA) by dividing the tasks between the processor and the FPGA, thereby avoiding the processor directly processing the high-speed response data stream. The FPGA utilizes its hardware logic to implement pipelined parsing and buffer management of messages, enabling it to handle network line-speed bandwidth with a processing capacity of 1.5 MPPS, while the processor only undertakes the initialization and decision-making stages, significantly reducing the real-time computing burden.

[0090] Meanwhile, because the field-programmable gate array circuit independently processes message transmission and reception, the processor utilization rate is significantly reduced, the networking time is shortened, the system can stably support large-scale devices to network simultaneously, ensuring consistent performance in a heterogeneous chip environment, and improving the session key update frequency through hardware acceleration, effectively reducing communication security risks.

[0091] In this application, a field-programmable gate array (FPGA) circuit is used as a hardware acceleration unit, which not only solves the CPU bottleneck problem in response message processing, but also provides a scalable foundation for large-scale networking. This enables the networking scale to break through traditional limitations, supports the stable access of more than 200 devices, significantly shortens networking time, and reduces CPU utilization by more than 50%. As a result, it provides a high-performance and high-security networking solution for IoT scenarios such as gas monitoring, fundamentally improving the practicality and reliability of HarmonyOS soft bus in industrial applications.

[0092] In some embodiments, the discovery message includes first load data and a first descriptor. The random access memory is provided with a first circular buffer, and the field-programmable gate array (FPGA) is provided with a first descriptor circular buffer. The process of placing the discovery message of the access device into the random access memory according to the processor includes: placing the first load data and the first descriptor into the first circular buffer and the first descriptor circular buffer respectively according to the processor; and notifying the FPGA to read the first load data and the first descriptor according to the processor.

[0093] In this embodiment, the first payload data can be understood as the actual payload of the message, such as application layer data or discovery service information in the CoAP protocol. The first payload data can exist in the form of raw binary data, or it can be a data block that has been specifically encoded (such as TLV format).

[0094] The first descriptor can be understood as metadata associated with the first payload data, used to describe information such as the attributes, location, length, and type of the first payload data, such as its starting address in memory, data length, message priority, and target device identifier. The first descriptor can be a structure or a fixed-length data block, generated by the processor and used to guide the field-programmable gate array circuitry in data processing.

[0095] The random access memory (RAM) includes a first circular buffer, which is a circular queue structure used to efficiently store and manage the initial payload data to be sent. When data is written to the end of the buffer, writing continues from the beginning of the buffer, forming a logical loop. This effectively avoids memory fragmentation and supports data stream transmission under the producer-consumer model.

[0096] For example, the first circular buffer can be composed of a contiguous physical memory region in random access memory, managed by read and write pointers; or it can be composed of multiple non-contiguous memory blocks logically connected by a linked list structure, and scheduled in a circular manner by software or hardware logic.

[0097] Field-programmable gate arrays (FPGAs) include a first descriptor circular buffer, which is a circular queue specifically used to store the first descriptors. The first descriptor circular buffer is typically located in the on-chip memory (such as BRAM) inside the FPGA or in an external high-speed memory controlled by the FPGA.

[0098] For example, the first descriptor ring buffer can be a FIFO (First-In-First-Out) queue that is directly accessed by the internal logic of the field-programmable gate array (FPGA), or an external SRAM region that is accessed by the FPGA through the AXI interface.

[0099] Specifically, the processor can write the payload of the discovery message to be sent into the first circular buffer of the random access memory through a DMA (direct memory access) controller or a direct memory write operation, and at the same time write the description information of the payload data into the first descriptor circular buffer of the field programmable gate array circuit.

[0100] For example, the processor can initiate a DMA write request to the field-programmable gate array (FPGA) via the PCIe interface, write the first load data to the random access memory, and write the first descriptor to the descriptor ring buffer inside the FPGA; or, the processor can directly write the data and descriptor to the corresponding buffer address through memory mapping.

[0101] Simultaneously, after completing the writing of the first load data and the first descriptor, the processor sends a signal to the field-programmable gate array (FPGA) through a specific mechanism, indicating that a new message has been discovered and is awaiting processing. For example, the processor can trigger the message processing logic of the FPGA by writing a "doorbell" value to a specific register of the FPGA; or, the processor can generate an interrupt signal, which is received and responded to by the FPGA.

[0102] In some embodiments, reading a discovery message according to a field-programmable gate array circuit and broadcasting the discovery message includes: in response to a notification sent by a processor, reading first load data and a first descriptor from a first circular buffer and a first descriptor circular buffer; combining the first load data and the first descriptor into a discovery message; and broadcasting the discovery message using a restricted application protocol.

[0103] In this embodiment, after receiving a notification signal from the processor, the field-programmable gate array circuit can autonomously read the required data from a designated area in the random access memory.

[0104] For example, a field-programmable gate array (FPGA) circuit can integrate a DMA (Direct Memory Access) controller. After receiving a notification from the processor, the controller directly retrieves the first load data and the first descriptor from the first circular buffer and the first descriptor circular buffer in the random access memory according to the preset address and length information, thereby avoiding the processor's direct involvement in data transfer.

[0105] Alternatively, the field-programmable gate array (FPGA) can act as a bus master device, initiating read requests through a bus interface (such as an AXI interface) to directly access the random access memory to obtain the corresponding data.

[0106] Furthermore, after acquiring the first load data and the first descriptor, the field-programmable gate array (FPGA) circuit uses its internal hardware logic or hardware protocol stack to encapsulate the first load data and the first descriptor into a complete discovery message according to a predetermined format, and broadcasts it through a specific protocol.

[0107] For example, a field-programmable gate array (FPGA) circuit can implement a simplified hardware protocol stack that can automatically generate discovery messages conforming to the format of a constrained application protocol (such as CoAP) based on the first load data and the first descriptor (which may contain protocol header information, target address, etc.), and broadcast them through physical layer interfaces (such as Ethernet MAC or wireless PHY).

[0108] Alternatively, this application can also implement message assembly logic through a programmable gate array, splicing the first payload data and the first descriptor according to a predefined message structure, adding necessary protocol fields, and then broadcasting it through a built-in sending module or an external physical layer chip.

[0109] In this application, the processor only needs to send a notification, and the field-programmable gate array (FPGA) can autonomously read the first payload data and first descriptor required for the discovery message from the random access memory, and automatically assemble them into a discovery message for broadcast. This significantly reduces the processor's involvement in data handling and message encapsulation, offloading these computationally intensive tasks to the hardware logic of the FPGA. At the same time, the hardware parallel processing capability of the FPGA enables the reading, assembly, and broadcasting of messages to be completed with higher efficiency and faster speed, thereby improving the overall processing efficiency and networking speed of the discovery phase.

[0110] In some embodiments, the random access memory further includes a second circular buffer and a second descriptor circular buffer; placing a response message into the random access memory according to the field-programmable gate array circuit includes: parsing the response message according to the field-programmable gate array circuit to obtain second load data and a second descriptor; placing the second load data into the second circular buffer according to the field-programmable gate array circuit, and placing the second descriptor into the second descriptor circular buffer.

[0111] In this embodiment, the second circular buffer and the second descriptor circular buffer function similarly to the first circular buffer and the first descriptor circular buffer, respectively, for storing and managing the second payload data and the second descriptor of the received response message. For example, the second circular buffer may share the same physical memory as the first circular buffer, but they are isolated and managed through different read / write pointers and logic.

[0112] In the process of parsing the response message to obtain the second payload data and the second descriptor according to the field programmable gate array circuit, after receiving the response message, the field programmable gate array circuit uses its internal hardware logic (such as the protocol parsing module PARSER) to analyze the message header and content, and extract the message's payload (second payload data) and metadata (second descriptor) related to the message.

[0113] For example, a field-programmable gate array (FPGA) circuit can contain a state machine that parses the message byte by byte or field by field according to the protocol specification (such as CoAP), identifies the start and length of the payload data, and generates a second descriptor containing information such as source IP, port, and message type.

[0114] Furthermore, during the process of placing the second load data into the second ring buffer and the second descriptor into the second descriptor ring buffer according to the field-programmable gate array circuit, after parsing the second load data and the second descriptor, the field-programmable gate array circuit, through its internal DMA controller or direct memory write logic, writes the second load data into the second ring buffer of the random access memory and writes the second descriptor into the second descriptor ring buffer inside the field-programmable gate array circuit.

[0115] For example, a field-programmable gate array (FPGA) circuit can directly write the parsed second load data into a random access memory via an AXI interface, and write the second descriptor into its internal BRAM area.

[0116] In this application, by separating the data and descriptors of discovery and response messages and using a circular buffer for efficient storage, the processor only needs to write the data and descriptors to the designated buffer and send the notification. Subsequent message reading, parsing, and storage are all independently completed by the field-programmable gate array (FPGA). This significantly reduces the processor's direct involvement in the message processing, thereby greatly reducing CPU utilization.

[0117] In some embodiments, the field-programmable gate array (FPGA) circuit includes a core connection state management module; according to the response message read by the processor, to network each access device, the method includes: according to the response message read by the processor, to apply for index resources from the core connection state management module using a driver; if the core connection state management module allocates index resources to the driver, to write the third descriptor of the access device to the FPGA circuit according to the driver, and to connect and network each access device according to the FPGA circuit.

[0118] In this embodiment, the core connection state management module is a hardware logic unit responsible for maintaining and managing the connection state information of all access devices, including connection ID, session key, connection parameters, etc. For example, the core connection state management module can be a hardware implementation based on a lookup table (such as TCP_TABLE) and a state machine, used for quickly querying, updating, and allocating connection resources.

[0119] Specifically, in the process of the processor reading the response message to request index resources from the core connection state management module using the driver, the processor sends a request to the core connection state management module of the field-programmable gate array circuit through the driver interface provided by the operating system to obtain a unique identifier or resource handle for establishing a new connection.

[0120] For example, the driver can write a request instruction to a specific control register of the field-programmable gate array circuit, and the core connection state management module will process the instruction after receiving it.

[0121] Meanwhile, once the core connection state management module successfully allocates index resources, the driver writes a third descriptor containing detailed connection information (such as target IP address, port number, protocol type, allocated index, etc.) into a designated area of ​​the field-programmable gate array circuit.

[0122] After receiving the third descriptor, the field-programmable gate array (FPGA) circuit uses its internal connection management logic (such as the TCP_LINK module) to initiate the connection establishment process with the target access device based on the third descriptor. For example, it performs the TCP three-way handshake or HTLS protocol negotiation process to complete the connection and networking of the access device.

[0123] For example, the driver can write a third descriptor into the descriptor queue inside the field-programmable gate array (FPGA) via DMA. The TCP_LINK module of the FPGA then reads the descriptor from the queue and initiates the connection.

[0124] In this application, by setting a core connection state management module in the field-programmable gate array circuit, the actual operation of connection resource application, allocation and connection networking is offloaded from the processor to the hardware. This allows the processor to only need to perform high-level instruction interaction through the driver, without having to handle the low-level connection state maintenance and protocol details. This enables the networking system to process a large number of discovery and response messages at line speed, effectively solving the problems of excessive CPU computing power consumption and slow networking speed in large-scale networking scenarios, and improving the overall performance and scalability of HarmonyOS soft bus.

[0125] In some embodiments, the field-programmable gate array (FPGA) circuit includes a TCP connection management module; connecting and networking each access device according to the FPGA circuit includes: based on the TCP connection management module, performing multiple handshakes with the access device according to a third descriptor to connect and network each access device.

[0126] In this embodiment, the TCP connection management module can be understood as a hardware module integrated within the field-programmable gate array (FPGA) circuit specifically for handling TCP connection establishment and maintenance. The TCP connection management module can be a hardware TCP Offload Engine (TOE). Within the FPGA circuit, the TCP connection management module implements key functions of the TCP protocol stack, such as three-way handshake, four-way handshake, sequence number management, and retransmission mechanisms, thereby offloading these computationally intensive tasks from the processor to the FPGA circuit.

[0127] Alternatively, the TCP connection management module can be implemented using programmable logic from a field-programmable gate array (FPGA), including logic units such as state machines, timers, and buffer management. It is specifically designed to track and manage the states of multiple TCP connections and perform corresponding operations according to the protocol specifications.

[0128] Specifically, this application, based on the TCP connection management module, establishes a connection and completes the network by performing multiple handshakes with each access device according to the third descriptor. The field-programmable gate array circuit utilizes its built-in TCP connection management module to autonomously complete the TCP handshake process with the access device according to the third descriptor provided by the driver (which includes information such as target IP, port, and connection parameters), thereby establishing a connection and completing the network.

[0129] For example, after receiving the third descriptor, the TCP connection management module autonomously initiates the TCP three-way handshake process, sending SYN, receiving SYN-ACK, and sending ACK, and manages the connection state. Once the handshake is successful, the connection is considered established, and the network is completed.

[0130] Alternatively, the TCP connection management module may contain one or more state machines that initialize the connection state based on the third descriptor and drive the state machines to transition from states such as CLOSED, LISTEN, SYN_SENT, SYN_RECEIVED, and ESTABLISHED based on received TCP packets (such as SYN and SYN-ACK) and internal timers until the connection is established.

[0131] In this application, by integrating a TCP connection management module into a field-programmable gate array (FPGA), the complex connection establishment (multiple handshakes) logic in the TCP protocol stack is hardware-based. This enables the FPGA to autonomously perform a TCP three-way handshake with the access device and manage the connection state based on the third descriptor provided by the processor, without frequent processor intervention. This significantly reduces the processor's burden, especially in large-scale networking scenarios, where it can handle more TCP connection requests simultaneously. This significantly improves the real-time performance and reliability of the network connection, avoids the efficiency bottlenecks and CPU power consumption caused by software protocol stack processing, and improves networking efficiency and speed. In particular, in large-scale device networking scenarios, it enables faster and more reliable device discovery and connection.

[0132] In some embodiments, after connecting each access device to the network according to the field-programmable gate array circuit, the method further includes: notifying the field-programmable gate array circuit to disconnect the access device according to the driver; the field-programmable gate array circuit disconnects the access device in response to the notification sent by the driver.

[0133] In this embodiment, the driver can be understood as a software module in the HarmonyOS operating system kernel or user space, responsible for managing and controlling hardware devices. The driver can translate high-level disconnect instructions into hardware operations that can be understood and executed by the field-programmable gate array (FPGA). Furthermore, the driver can notify the FPGA by writing to specific control registers, triggering the FPGA's internal state machine.

[0134] Alternatively, this application can also use the DMA (Direct Memory Access) mechanism to transfer a data structure containing disconnect instructions and related parameters to a memory area accessible to the field-programmable gate array (FPGA) circuit, and then notify the FPGA circuit to process it through an interrupt or polling mechanism.

[0135] As an example, a driver can write a flag or command word to a specific register of a field-programmable gate array (FPGA) via the PCIe bus, which is continuously monitored by the FPGA. When the FPGA detects a change in the register value, it triggers the corresponding processing logic.

[0136] As another example, the driver prepares the data required to disconnect (e.g., the identifier of the device to be disconnected), places it in a shared memory region, and then informs the field-programmable gate array (FPGA) circuitry that there is a new task to process by sending a message signaling interrupt (MSI / MSI-X) to the FPGA circuitry.

[0137] Specifically, during the process of sending a disconnection request to the access device, the field-programmable gate array circuit initiates a disconnection process with the specific access device based on the received notification. This process may include generating and sending a disconnection request message conforming to a specific protocol (such as a TCP FIN message or RST message) to the target access device.

[0138] Alternatively, this application can also mark the connection status of the corresponding access device as "to be disconnected" or "disconnected" in the connection status table maintained internally, and release the relevant hardware resources, such as buffers, timers, etc.

[0139] In this application, the disconnection operation is performed by responding to the driver notification via a field-programmable gate array (FPGA), significantly reducing the need for CPU intervention. This allows the FPGA to send a disconnection command to the access device after network setup is complete, based on the driver notification. The driver acts as a bridge between the software and hardware layers, avoiding direct CPU processing of network protocol details and reducing computational power consumption. Simultaneously, the FPGA's response to the driver notification to disconnect the access device, achieved through hardware-accelerated disconnection, ensures rapid release of connection resources, improves system response speed and resource utilization, and reduces security risks caused by delayed disconnection.

[0140] In some embodiments, before notifying the field-programmable gate array circuit to send a disconnection notification to the access device according to the driver, the method further includes: writing the IP address and port number of the access device into the field-programmable gate array circuit according to the driver.

[0141] In this embodiment, the driver is responsible for collecting and transmitting the unique network address (IP address) and communication port number of the access device to be disconnected.

[0142] As an example, the driver can write this information into a specific register set or memory-mapped region inside the field-programmable gate array (FPGA) circuit, allowing the FPGA circuit to directly access these preset parameters.

[0143] As another example, the driver can construct a data structure containing IP addresses and port numbers, and transfer it to a designated buffer within the field-programmable gate array (FPGA) via direct memory access (DMA) to achieve efficient data transfer. By pre-writing this critical information, the FPGA does not need to request or perform complex queries from the processor upon receiving a disconnect command, thus providing immediate and accurate location information for subsequent disconnect operations.

[0144] In this application, before the driver notifies the field-programmable gate array (FPGA) to send a disconnection notification to the access device, the IP address and port number of the access device are pre-written into the FPGA. This effectively solves the problem that the FPGA cannot accurately identify the target device due to the lack of clear identification information during the disconnection process, which increases query and matching overhead and causes processing delays or erroneous disconnections. When the FPGA receives the disconnection notification, it can immediately use this pre-stored accurate information to quickly locate and identify the target access device without performing additional queries or complex matching operations. This significantly reduces the processor's involvement in the disconnection process, alleviates its computational burden, and avoids processing delays and erroneous disconnections that may occur due to unclear information. As a result, the response efficiency and stability of the entire networking system are significantly improved. Especially in large-scale networking scenarios, it can ensure rapid connection establishment and efficient disconnection, thereby optimizing the overall performance of the HarmonyOS soft bus.

[0145] In some embodiments, the field-programmable gate array (FPGA) circuit includes a TCP connection management module; the FPGA circuit responds to a notification sent by the driver to disconnect from the access device, including: the FPGA circuit responds to the notification sent by the driver to read the IP address and port number; and queries the IP address and port number according to the core connection status management module to disconnect from the access device using the TCP connection management module.

[0146] In this embodiment, the field-programmable gate array (FPGA) responds to the notification sent by the driver to read the IP address and port number, thereby ensuring that the FPGA can obtain the unique identification information of the access device that needs to be disconnected in a timely and accurate manner, namely the IP address and port number.

[0147] As an example, the driver writes the IP address and port number of the access device to be disconnected into a specific set of pre-set registers inside the field-programmable gate array (FPGA) circuit via the PCIe interface. The control logic of the FPGA circuit continuously monitors these registers and immediately reads the IP address and port number upon receiving a notification signal.

[0148] Meanwhile, after the core connection state management module confirms the connection is valid, the TCP connection management module will initiate the standard TCP four-way handshake protocol process based on the connection's state information. This involves sending a FIN packet to the peer access device, processing the ACK and FIN packets returned by the peer, and finally releasing all hardware resources occupied by the connection upon receiving the peer's ACK. Additionally, in certain abnormal or rapid cleanup scenarios, the TCP connection management module can also choose to send an RST packet to forcibly disconnect the connection.

[0149] In this application, the complex TCP disconnection process is handled directly at the hardware level by the TCP connection management module within the field-programmable gate array (FPGA), avoiding the enormous computational burden on the main processor when handling a large number of connection disconnection requests. This reduces CPU utilization and shortens the time required for disconnection. Simultaneously, when the driver notifies the FPGA to disconnect, the FPGA can quickly read the IP address and port number of the device to be disconnected. The core connection status management module efficiently queries this information, ensuring that only legitimate and existing connections are processed. This not only improves operational accuracy but also effectively shortens the potential security risk window by rapidly releasing connection resources. Compared to pure software processing, this solution enables faster and more reliable connection disconnection in large-scale networking environments, ensuring the stability and security of the entire network system. Its advantages are particularly evident when HarmonyOS soft bus needs to support the self-discovery and self-organizing network requirements of large-scale scenarios with 200-1000 devices.

[0150] Furthermore, during the data transmission process in the networking phase of this application, there are four sets of interactive data. The first three sets are transmitted in plaintext, and the last set is transmitted in encrypted text. Simultaneously, the data to be transmitted is obtained through the descriptor Ring of HOSTIF_TX. The corresponding descriptor can be looked up in TCP_TABLE to determine its validity. If valid, it proceeds to the next step; otherwise, it is discarded and recorded in a register. HOSTIF_TX determines whether fragmentation is necessary and retrieves the data from memory to send to PKT_ENCRP. PKT_ENCRP transmits the data transparently or encrypts it according to the corresponding rules. Meanwhile, the processor sending end releases the transmitter after receiving the ACK returned by the peer. If no ACK is received within the sending end's memory after a timeout, the data in memory will be retransmitted. After the receiving end of the FPGA receives a message, it can first use IP+Port to send it to TCP_TABLE to check the message's validity. If valid, proceed to the next step. The PARSER module determines whether the message is encrypted or transmitted in plaintext. If it is plaintext, an ACK is sent to the peer. If it is encrypted, an ACK is sent to the peer after successful authentication by PKT_DECRP. PKT_RXEDIT determines whether to transmit the entire packet or the payload to the HOST based on the descriptor. HOSTIF_RX writes the message to memory and notifies the HOST to retrieve the message.

[0151] Meanwhile, during the transmission phase, data encryption and decryption can be determined based on the port number. If the port number is greater than or equal to 30000, encryption and decryption are required; if the port number is less than 30000, encryption and decryption are not required. Furthermore, non-TCP / UDP packets do not require encryption or decryption.

[0152] In the networking method based on the HarmonyOS soft bus module provided in this application embodiment, the processor places the discovery message of the access device into the random access memory; the field-programmable gate array (FPGA) reads the discovery message and broadcasts it; if a response message from each access device is received, the FPGA places the response message into the random access memory, and then the processor reads the response message to network each access device. This offloads the processor's functions to the FPGA, accelerating large-scale discovery, connection, networking, and transmission, reducing the processor's burden and resource consumption, and improving the efficiency of discovery, connection, networking, and transmission during the networking process.

[0153] In some embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the networking method based on the HarmonyOS soft bus module as described above.

[0154] In this embodiment, electronic equipment can be understood as the main equipment mentioned in this application.

[0155] In some embodiments, this application also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the following steps: placing a discovery message for discovering access devices into random access memory according to the processor; reading the discovery message according to a field-programmable gate array (FPGA) and broadcasting the discovery message; if a response message from each access device responding to the discovery message is received, placing the response message into random access memory according to the FPGA; and reading the response message according to the processor to establish a network for each access device.

[0156] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0157] In another embodiment of this application, a computer storage medium is provided. This storage medium can be a non-volatile computer-readable storage medium or a volatile storage medium. The storage medium stores a computer program, which, when executed by a processor, performs the following steps: placing a discovery message for discovering access devices into random access memory according to the processor; reading the discovery message according to a field-programmable gate array (FPGA) and broadcasting the discovery message; if a response message from each access device is received in response to the discovery message, placing the response message into random access memory according to the FPGA; and reading the response message according to the processor to establish a network for each access device.

[0158] The storage medium can be any computer-readable storage medium that can store program code, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0159] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0160] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0161] The steps in the methods of this application embodiment can be adjusted, merged, or deleted according to actual needs. The units in the apparatus of this application embodiment can be merged, divided, or deleted according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0162] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods provided in the various embodiments of this application.

[0163] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A networking method based on the HarmonyOS soft bus module, characterized in that, The method is applied to a networking system based on a HarmonyOS soft bus module that runs HarmonyOS soft bus. The HarmonyOS soft bus-based networking system includes at least one master device and multiple access devices. Both the master device and the access devices have a HarmonyOS soft bus module. The master device includes a processor, random access memory, and a field-programmable gate array (FPGA). The processor places the discovery message of the access device into the random access memory. The discovery message is read according to the field-programmable gate array circuit, and the discovery message is broadcast. If a response message is received from each of the access devices in response to the discovery message, the response message is placed into the random access memory according to the field programmable gate array circuit. The processor reads the response message to form a network for each of the access devices.

2. The networking method based on the HarmonyOS soft bus module according to claim 1, characterized in that, The discovery message includes first payload data and a first descriptor. The random access memory is provided with a first circular buffer, and the field programmable gate array is provided with a first descriptor circular buffer. The step of placing the discovery message of the access device into the random access memory according to the processor includes: The processor places the first load data and the first descriptor into the first circular buffer and the first descriptor circular buffer, respectively. The processor instructs the field-programmable gate array circuit to read the first load data and the first descriptor.

3. The networking method based on the HarmonyOS soft bus module according to claim 2, characterized in that, The step of reading the discovery message according to the field-programmable gate array circuit and broadcasting the discovery message includes: In response to a notification sent by the processor, the first payload data and the first descriptor are read from the first circular buffer and the first descriptor circular buffer; The first payload data and the first descriptor are combined into the discovery message, and the discovery message is broadcast using a restricted application protocol.

4. The networking method based on the HarmonyOS soft bus module according to claim 1, characterized in that, The random access memory also includes a second circular buffer and a second descriptor circular buffer; The step of placing the response message into the random access memory according to the field-programmable gate array circuit includes: The response message is parsed according to the field-programmable gate array circuit to obtain the second load data and the second descriptor; The second load data is placed into the second circular buffer according to the field-programmable gate array circuit, and the second descriptor is placed into the second descriptor circular buffer.

5. The networking method based on the HarmonyOS soft bus module according to any one of claims 1-4, characterized in that, The field-programmable gate array circuit is equipped with a core connection status management module; The step of reading the response message according to the processor to form a network for each of the access devices includes: The processor reads the response message to request index resources from the core connection state management module using the driver. If the core connection state management module allocates the index resource to the driver, the driver writes the third descriptor connecting the access device into the field-programmable gate array circuit, and the field-programmable gate array circuit connects and networks each access device.

6. The networking method based on the HarmonyOS soft bus module according to claim 5, characterized in that, The field-programmable gate array circuit includes a TCP connection management module; The step of connecting and networking each access device according to the field-programmable gate array circuit includes: Based on the TCP connection management module, multiple handshakes are performed with the access devices according to the third descriptor to connect and network each access device.

7. The networking method based on the HarmonyOS soft bus module according to claim 5, characterized in that, After connecting and networking each access device according to the field-programmable gate array circuit, the method further includes: The driver program notifies the field-programmable gate array circuit to send a disconnection message to the access device. The field-programmable gate array circuit responds to a notification sent by the driver to disconnect from the access device.

8. The networking method based on the HarmonyOS soft bus module according to claim 7, characterized in that, Before instructing the field-programmable gate array circuit to send a disconnection message to the access device according to the driver, the method further includes: According to the driver program, the IP address and port number of the access device are written into the field-programmable gate array circuit.

9. The networking method based on the HarmonyOS soft bus module according to claim 8, characterized in that, The field-programmable gate array circuit includes a TCP connection management module; The field-programmable gate array circuit responds to a notification sent by the driver to disconnect from the access device, including: The field-programmable gate array circuit responds to a notification sent by the driver to read the IP address and the port number; The core connection status management module queries the IP address and port number to disconnect the access device using the TCP connection management module.

10. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the networking method based on the HarmonyOS soft bus module as described in any one of claims 1 to 9.

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