An event-driven pixel cell based on fdsoi

Abstract

This application discloses an event-driven pixel unit based on FDSOI, relating to the fields of semiconductor devices and integrated circuit technology. The FDSOI-based event-driven pixel unit includes: two FDSOI photosensitive units with different exposure area sizes and several ordinary logic transistors; the FDSOI photosensitive units are used for light sensing; the ordinary logic transistors are used to implement the circuit function of voltage pulse generation. This application can achieve output of corresponding polarity pulses only when the light intensity changes, and no output when the light intensity is constant, while simultaneously reducing pixel area, improving fill factor and photosensitivity, and accurately responding to high-speed moving objects while avoiding redundant information.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to an event-driven pixel unit based on FDSOI. Background Technology

[0002] In the field of visual sensors, event-based vision sensors (EVS) have received widespread attention. Traditional frame-based vision sensors sample at a fixed frame rate, with a fixed time interval between two frames. This results in some fast-moving objects not being accurately sampled, and the repeated sampling of the unchanging background generates a large amount of redundant information. In contrast, event-based vision sensors only generate pulse outputs when the light intensity changes (an event occurs). Positive pulses are generated when the light intensity increases, negative pulses are generated when the light intensity decreases, and no output is generated when the light intensity remains constant (no event). Therefore, event-based vision sensors can not only accurately sample fast-moving objects, but also avoid generating redundant full-frame spatial information, giving them a significant advantage in many scenarios.

[0003] Traditional event-driven vision sensors typically have a complex pixel unit structure, including multiple capacitors and operational amplifiers, which results in large pixel unit area and low fill factor. Summary of the Invention

[0004] The purpose of this application is to provide an event-driven pixel unit based on FDSOI, which can output a corresponding polarity pulse only when the light intensity changes, and no output when the light intensity is constant. At the same time, it can reduce the pixel area, improve the fill factor and photosensitivity, and accurately respond to high-speed moving objects while avoiding redundant information.

[0005] To achieve the above objectives, this application provides the following solution: This application provides an FDSOI-based event-driven pixel unit, which includes: Two FDSOI photosensitive units with different exposure area sizes and several ordinary logic transistors.

[0006] The FDSOI photosensitive unit is used for light sensing.

[0007] The ordinary logic transistor is used to implement the circuit function of voltage pulse generation.

[0008] Optionally, the FDSOI photosensitive unit includes: a substrate, a selective well doped structure, a buried oxide layer, and a selective transistor structure; the selective well doped structure includes: a p-type well and an n-type well; the selective transistor includes: an NMOS transistor and a PMOS transistor.

[0009] An exposure region is provided at the source end of the selective transistor.

[0010] A well electrode is provided on the selective well doped structure.

[0011] A shallow trench isolation is provided around the well electrode; the shallow trench isolation is a silicon dioxide portion vertically inserted in the selective well doped structure, with a thickness between the buried oxide layer and the selective well doped structure.

[0012] Optionally, when the selective transistor is an NMOS transistor and the selective well doped structure is a p-type well, the FDSOI photosensitive unit is an NMOS-p photosensitive transistor.

[0013] When the FDSOI photosensitive unit is used for photosensitive purposes, a constant negative trap voltage is applied; the channel current decreases linearly with the increase of the logarithm of the light intensity.

[0014] Optionally, when the FDSOI-based event-driven pixel unit is a pixel unit composed of NMOS-p photosensitive transistors, the FDSOI-based event-driven pixel unit includes: NMOS-p photosensitive transistor M1, NMOS-p photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7.

[0015] The gates of the NMOS-p phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the NMOS-p phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-p phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to the power supply voltage. The source of the NMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistors M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to the power supply voltage. The source of the FDSOI transistor M7 is connected to ground. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the NMOS-p photosensitive transistors M1 and M2 are connected together, and a negative well voltage is applied.

[0016] The exposure area of ​​the NMOS-p phototransistor M2 is larger than that of the NMOS-p phototransistor M1.

[0017] Optionally, when the selective transistor is a PMOS transistor and the selective well doped structure is a p-type well, the FDSOI photosensitive unit is a PMOS-p photosensitive transistor.

[0018] When the FDSOI photosensitive unit is used for photosensitive purposes, a constant negative trap voltage is applied; the channel current increases linearly with the logarithm of the light intensity.

[0019] Optionally, when the FDSOI-based event-driven pixel unit is a pixel unit composed of PMOS-p photosensitive transistors, the FDSOI-based event-driven pixel unit includes: PMOS-p photosensitive transistor M1, PMOS-p photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7.

[0020] The gates of the PMOS-p phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the PMOS-p phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-p phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to ground. The source of the PMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistor M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to ground. The source of the FDSOI transistor M7 is connected to the power supply voltage. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the PMOS-p photosensitive transistors M1 and M2 are connected together, and a negative well voltage is applied.

[0021] The exposure area of ​​the PMOS-p phototransistor M2 is larger than that of the PMOS-p phototransistor M1.

[0022] Optionally, when the selective transistor is an NMOS transistor and the selective well doped structure is an n-type well, the FDSOI photosensitive unit is an NMOS-n photosensitive transistor.

[0023] When the FDSOI photosensitive unit is used for photosensitive purposes, a constant positive trap voltage is applied; the channel current increases linearly with the logarithm of the light intensity.

[0024] Optionally, when the FDSOI-based event-driven pixel unit is a pixel unit composed of NMOS-n photosensitive transistors, the FDSOI-based event-driven pixel unit includes: NMOS-n photosensitive transistor M1, NMOS-n photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7.

[0025] The gates of the NMOS-n phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the NMOS-n phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-n phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to the power supply voltage. The source of the NMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistors M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to the power supply voltage. The source of the FDSOI transistor M7 is connected to ground. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the NMOS-n photosensitive transistors M1 and M2 are connected together, and a positive well voltage is applied.

[0026] The exposure area of ​​the NMOS-n phototransistor M1 is larger than the exposure area of ​​the NMOS-n phototransistor M2.

[0027] Optionally, when the selective transistor is a PMOS transistor and the selective well doped structure is an n-type well, the FDSOI photosensitive unit is a PMOS-n photosensitive transistor.

[0028] When the FDSOI photosensitive unit is used for photosensitive purposes, a constant positive trap voltage is applied; the channel current decreases linearly with the increase of the logarithm of the light intensity.

[0029] Optionally, when the FDSOI-based event-driven pixel unit is a pixel unit composed of PMOS-n photosensitive transistors, the FDSOI-based event-driven pixel unit includes: PMOS-n photosensitive transistor M1, PMOS-n photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7.

[0030] The gates of the PMOS-n phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the PMOS-n phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-n phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to ground. The source of the PMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistor M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to ground. The source of the FDSOI transistor M7 is connected to the power supply voltage. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the PMOS-n photosensitive transistors M1 and M2 are connected together, and a positive well voltage is applied.

[0031] The exposure area of ​​the PMOS-n phototransistor M1 is larger than the exposure area of ​​the PMOS-n phototransistor M2.

[0032] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides an FDSOI-based event-driven pixel unit, comprising: two FDSOI photosensitive units with different exposure area sizes and several ordinary logic transistors; the FDSOI photosensitive units are used for light sensing; and the ordinary logic transistors are used to implement the circuit function of voltage pulse generation. This application uses two FDSOI photosensitive units with different exposure area areas combined with ordinary logic transistors to form a pixel unit, eliminating the need for traditional capacitors, reducing pixel area, and increasing fill factor. Simultaneously, it relies on the difference in light intensity response of the photosensitive units to achieve event-driven output, reducing redundant information, improving response speed and light sensing efficiency, and resulting in a simpler circuit structure. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of four FDSOI photosensitive units provided in one embodiment of this application; Figure 2 A schematic diagram showing the relationship between transistor channel current and light intensity in four types of FDSOI photosensitive units provided in an embodiment of this application; Figure 3 A schematic diagram of the transient response of photosensitive units with different exposure area areas under light intensity changes, provided in an embodiment of this application; Figure 4 This is a schematic diagram illustrating the principle of implementing a capacitorless event-driven pixel unit according to an embodiment of this application; Figure 5 This is a schematic diagram of the pulse output of a capacitorless event-driven pixel unit provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] The photosensitive element used in this application is a fully depleted silicon-on-insulator (FDSOI) device. When a constant well voltage is applied as a bias, the concentration of photogenerated carriers accumulated in the depletion region of the FDSOI device varies under different light intensities. Therefore, the channel current of the transistor exhibits a monotonically logarithmic relationship with the light intensity, changing with the light intensity. When the exposure area of ​​the FDSOI device is designed to be different, the rate of change of the channel current after a change in light intensity differs. The larger the exposure area, the faster the channel current responds to changes in light intensity. Therefore, the difference in channel current between two FDSOI devices with different exposure area areas can reflect the change in light intensity. By embedding the FDSOI device in an operational amplifier structure, the output terminal can generate positive or negative voltage pulse responses to changes in light intensity, thereby realizing an event-driven pixel unit.

[0037] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] In one exemplary embodiment, an FDSOI-based event-driven pixel unit is provided, the FDSOI-based event-driven pixel unit comprising: Two FDSOI photosensitive units with different exposure area sizes and several ordinary logic transistors.

[0039] The FDSOI photosensitive unit is used for light sensing.

[0040] The ordinary logic transistor is used to implement the circuit function of voltage pulse generation.

[0041] In this embodiment, the capacitor-free event-driven pixel unit structure consists of 7 FDSOI transistors, of which 2 FDSOI transistors are used for photosensitive and have a dedicated exposure area design, while the other 5 FDSOI transistors are ordinary logic transistors with no photosensitive effect, used to implement the circuit function of voltage pulse delivery.

[0042] like Figure 1 As shown, the FDSOI photosensitive unit includes: a substrate, a selective well doped structure, a buried oxide layer, and a selective transistor structure; the selective well doped structure includes: a p-type well and an n-type well; the selective transistor includes: an NMOS transistor and a PMOS transistor.

[0043] An exposure region is provided at the source end of the selective transistor.

[0044] A well electrode is provided on the selective well doped structure.

[0045] A shallow trench isolation is provided around the well electrode; the shallow trench isolation is a silicon dioxide portion vertically inserted in the selective well doped structure, with a thickness between the buried oxide layer and the selective well doped structure.

[0046] Specifically, based on the type of transistor above the buried oxide layer and the doping type of the well below the buried oxide layer, FDSOI transistors can be divided into four different types: NMOS-p-well (Np) cells (i.e., NMOS-p photosensitive transistors), NMOS-n-well (Nn) cells (i.e., NMOS-n photosensitive transistors), PMOS-p-well (Pp) cells (i.e., PMOS-p photosensitive transistors), and PMOS-n-well (Pn) cells (i.e., PMOS-n photosensitive transistors). An additional exposure region is designed at the source end of the FDSOI transistor used for photosensitive applications. The exposure region reduces the obstruction from the metal layer and silicide, achieving higher photosensitive efficiency. When used for photosensitive applications, the constant well voltage applied to Np and Pp cells is negative, while the constant well voltage applied to Nn and Pn cells is positive. The relationship between the channel current of the transistor in the FDSOI photosensitive cell and the light intensity is shown in the attached figure. Figure 2 As shown, the channel current in the Np and Pn cells decreases linearly with increasing logarithm of light intensity, while the channel current in the Pp and Nn cells increases linearly with increasing logarithm of light intensity. The transient response of the transistor channel current in the FDSOI photosensitive cell to changes in light intensity is shown in the attached figure. Figure 3 As shown, devices with different exposure area areas exhibit different transient response speeds when light intensity changes; the larger the exposure area, the faster the transient light response speed. Based on different types of FDSOI phototransistors, four types of capacitor-free event-driven pixel units with different structures but similar principles can be obtained, as shown in the attached figure. Figure 4 As shown. The basic structure of a capacitorless event-driven pixel unit is a 7-transistor operational amplifier structure. Two of the input transistors are FDSOI transistors with different exposure area areas for photosensitive purposes. The remaining five transistors are ordinary logic transistors, not used for photosensitive purposes, and their well voltages are all grounded. When this pixel unit is operating, a constant positive voltage (Nn unit or Pn unit) or a constant negative voltage (Np unit or Pp unit) is applied to the well voltages of the two FDSOI transistors used for photosensitive purposes. When the light intensity changes (i.e., an event occurs), the two FDSOI transistors used for photosensitive purposes have small and large exposure areas respectively, and their photoresponse speeds differ. This causes a change in the voltage at the pulse output terminal of the operational amplifier, as shown in the attached diagram. Figure 5 As shown, when the light intensity increases, the pulse output generates a positive voltage pulse, while when the light intensity decreases, the pulse output generates a negative voltage pulse; when the light intensity remains constant (no event), the voltage at the pulse output remains constant.

[0047] The principle of this application is as follows: like Figure 1As shown, FDSOI photosensitive units can be classified into Np units, Nn units, Pp units, and Pn units based on the transistor type and well doping type. The source end of the transistor is designed with a dedicated exposure region for photosensitive purposes. The silicide above this region is removed, while avoiding obstruction by the metal layer, thus achieving high photosensitive efficiency. An FDSOI photosensitive unit has four electrodes: gate (G), drain (D), source (S), and well (B).

[0048] like Figure 2 As shown, for Np and Pp cells, when a constant negative voltage is applied to the well electrode, a depletion region forms in the p-well. Photogenerated holes due to illumination flow away from the well electrode within the depletion region, while photogenerated electrons accumulate below the buried oxide layer, resulting in a decrease in the potential below the buried oxide layer. Conversely, for Nn and Pn cells, when a constant positive voltage is applied to the well electrode, a depletion region forms in the n-well. Photogenerated electrons due to illumination flow away from the well electrode within the depletion region, while photogenerated holes accumulate below the buried oxide layer, resulting in an increase in the potential below the buried oxide layer. This potential change below the buried oxide layer will induce back-gate modulation in the transistor above the buried oxide layer, thereby affecting the transistor's threshold voltage and channel current. As light intensity increases, the concentration of photogenerated electrons accumulated beneath the buried oxide layer in the p-well increases and the potential decreases. This leads to a decrease in the channel current of the NMOS transistor in the Np cell and an increase in the channel current of the PMOS transistor in the Pp cell. Similarly, the concentration of photogenerated holes accumulated beneath the buried oxide layer in the n-well increases and the potential increases. This leads to an increase in the channel current of the NMOS transistor in the Nn cell and a decrease in the channel current of the PMOS transistor in the Pn cell. Therefore, the channel current in the Np and Pn cells decreases with increasing light intensity, while the channel current in the Pp and Nn cells increases with increasing light intensity.

[0049] like Figure 3As shown, photogenerated carriers beneath the buried oxide layer are primarily generated in the well below the exposure area. They then diffuse laterally under the influence of the concentration gradient to the area below the transistor channel, resulting in a back-gate modulation effect on the transistor channel current. The larger the exposure area, the stronger the lateral diffusion effect, and the faster the photogenerated carriers can achieve a uniform distribution below the buried oxide layer, resulting in a faster stabilization of the transistor channel current. For Np and Pn cells, as light intensity increases, the channel current of the photosensitive cell decreases; the current decreases more slowly in devices with small exposure areas, while it decreases more rapidly in devices with large exposure areas. Conversely, as light intensity decreases, the channel current of the photosensitive cell increases; the current increases more slowly in devices with small exposure areas, while it increases more rapidly in devices with large exposure areas. For Pp and Nn units, when the light intensity increases, the channel current of the photosensitive unit increases. The current of the device in the small exposure area increases more slowly, while the current of the device in the large exposure area increases more quickly. When the light intensity decreases, the channel current of the photosensitive unit decreases. The current of the device in the small exposure area decreases more slowly, while the current of the device in the large exposure area decreases more quickly.

[0050] like Figure 4 As shown, the circuit design of the pixel unit differs slightly when using different types of FDSOI photosensitive units, but the transient response of the voltage at the pulse output terminal to changes in light intensity is consistent, as shown in the figure. Figure 5 As shown, a positive pulse is generated when the light intensity increases, and a negative pulse is generated when the light intensity decreases. The principles are explained below for different types of photosensitive units: (1) When using Np units for photosensitive, two Np units are used as input tubes of a 7-transistor operational amplifier, and a constant negative voltage is applied to their well electrodes. The well electrodes of the other transistors in the operational amplifier are all grounded (the transistor current is not affected by the light intensity).

[0051] Specifically, when the FDSOI-based event-driven pixel unit is a pixel unit composed of NMOS-p photosensitive transistors, the FDSOI-based event-driven pixel unit includes: NMOS-p photosensitive transistor M1, NMOS-p photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7.

[0052] The gates of the NMOS-p phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the NMOS-p phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-p phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to the power supply voltage. The source of the NMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistors M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to the power supply voltage. The source of the FDSOI transistor M7 is connected to ground. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the NMOS-p photosensitive transistors M1 and M2 are connected together, and a negative well voltage is applied.

[0053] The exposure area of ​​the NMOS-p phototransistor M2 is larger than that of the NMOS-p phototransistor M1.

[0054] In other words, NMOS-p phototransistor M1 is a device with a small exposure area, and NMOS-p phototransistor M2 is a device with a large exposure area. When the light intensity increases, the current of both NMOS-p phototransistors M1 and M2 decreases, but the current of NMOS-p phototransistor M1 decreases more slowly than that of NMOS-p phototransistor M2. Therefore, for a period of time, the current of NMOS-p phototransistor M1 is greater than that of NMOS-p phototransistor M2. Since the currents of NMOS-p phototransistors M1, M3, M5, and M6 are equal, and the currents of NMOS-p phototransistors M2 and M4 are equal, the current of FDSOI transistor M6 is greater than that of M2 at this time. The current of FDSOI transistor M4 charges the parasitic capacitance at the pulse output terminal, increasing the voltage and generating a positive pulse. When the light intensity decreases, the currents of both NMOS-p phototransistors M1 and M2 increase, but the current of NMOS-p phototransistor M1 increases more slowly than that of NMOS-p phototransistor M2. Therefore, for a period of time, the current of NMOS-p phototransistor M1 is less than that of NMOS-p phototransistor M2, meaning the current of FDSOI transistor M6 is less than that of FDSOI transistor M4. This causes the parasitic capacitance at the pulse output terminal to discharge, decreasing the voltage and generating a negative pulse.

[0055] (2) When using Pp units for photosensitive, two Pp units are used as input tubes of a 7-transistor operational amplifier, and a constant negative voltage is applied to their well electrodes. The well electrodes of the other transistors in the operational amplifier are all grounded (the transistor current is not affected by the light intensity).

[0056] Specifically, when the FDSOI-based event-driven pixel unit is a pixel unit composed of PMOS-p photosensitive transistors, the FDSOI-based event-driven pixel unit includes: PMOS-p photosensitive transistor M1, PMOS-p photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7.

[0057] The gates of the PMOS-p phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the PMOS-p phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-p phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to ground. The source of the PMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistor M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to ground. The source of the FDSOI transistor M7 is connected to the power supply voltage. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the PMOS-p photosensitive transistors M1 and M2 are connected together, and a negative well voltage is applied.

[0058] The exposure area of ​​the PMOS-p phototransistor M2 is larger than that of the PMOS-p phototransistor M1.

[0059] PMOS-p phototransistor M1 is a small exposure area device, while PMOS-p phototransistor M2 is a large exposure area device. When light intensity increases, the current of both PMOS-p phototransistors M1 and M2 increases, but the current increase rate of PMOS-p phototransistor M1 is slower than that of PMOS-p phototransistor M2. Therefore, for a period of time, the current of PMOS-p phototransistor M1 is less than the current of PMOS-p phototransistor M2, meaning the current of FDSOI transistor M6 is less than the current of FDSOI transistor M4. This causes the parasitic capacitance at the pulse output terminal to be charged, increasing the voltage and thus generating a positive voltage. When the light intensity decreases, the currents of both PMOS-p phototransistors M1 and M2 decrease. However, the current of PMOS-p phototransistor M1 decreases more slowly than that of PMOS-p phototransistor M2. Therefore, for a period of time, the current of PMOS-p phototransistor M1 is greater than that of PMOS-p phototransistor M2, that is, the current of FDSOI transistor M6 is greater than that of FDSOI transistor M4. This causes the parasitic capacitance at the pulse output terminal to be discharged, the voltage to decrease, and thus a negative pulse is generated.

[0060] (3) When using Nn units for photosensitive, two Nn units are used as input tubes of a 7-transistor operational amplifier, and a constant positive voltage is applied to their well electrodes. The well electrodes of the other transistors in the operational amplifier are all grounded (the transistor current is not affected by the light intensity).

[0061] Specifically, when the FDSOI-based event-driven pixel unit is a pixel unit composed of NMOS-n photosensitive transistors, the FDSOI-based event-driven pixel unit includes: NMOS-n photosensitive transistor M1, NMOS-n photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7.

[0062] The gates of the NMOS-n phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the NMOS-n phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-n phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to the power supply voltage. The source of the NMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistors M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to the power supply voltage. The source of the FDSOI transistor M7 is connected to ground. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the NMOS-n photosensitive transistors M1 and M2 are connected together, and a positive well voltage is applied.

[0063] The exposure area of ​​the NMOS-n phototransistor M1 is larger than the exposure area of ​​the NMOS-n phototransistor M2.

[0064] In other words, NMOS-n phototransistor M1 is a device with a large exposure area, and NMOS-n phototransistor M2 is a device with a small exposure area. When the light intensity increases, the current of both NMOS-n phototransistors M1 and M2 increases, but the current of NMOS-n phototransistor M1 increases faster than that of NMOS-n phototransistor M2. Therefore, for a period of time, the current of NMOS-n phototransistor M1 is greater than the current of NMOS-n phototransistor M2, meaning the current of FDSOI transistor M6 is greater than the current of FDSOI transistor M4. This causes the parasitic capacitance at the pulse output terminal to be charged, increasing the voltage and thus generating a positive voltage. When the light intensity decreases, the currents of both NMOS-n phototransistors M1 and M2 decrease. However, the current of NMOS-n phototransistor M1 decreases faster than that of NMOS-n phototransistor M2. Therefore, for a period of time, the current of NMOS-n phototransistor M1 is less than that of NMOS-n phototransistor M2, that is, the current of FDSOI transistor M6 is less than that of FDSOI transistor M4. This causes the parasitic capacitance at the pulse output terminal to be discharged, the voltage to decrease, and thus a negative pulse is generated.

[0065] (4) When using Pn units for photosensitive, two Pn units are used as input tubes of a 7-transistor operational amplifier, and a constant positive voltage is applied to their well electrodes. The well electrodes of the other transistors in the operational amplifier are all grounded (the transistor current is not affected by the light intensity).

[0066] Specifically, when the FDSOI-based event-driven pixel unit is a pixel unit composed of PMOS-n photosensitive transistors, the FDSOI-based event-driven pixel unit includes: PMOS-n photosensitive transistor M1, PMOS-n photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7.

[0067] The gates of the PMOS-n phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the PMOS-n phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-n phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to ground. The source of the PMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistor M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to ground. The source of the FDSOI transistor M7 is connected to the power supply voltage. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the PMOS-n photosensitive transistors M1 and M2 are connected together, and a positive well voltage is applied.

[0068] The exposure area of ​​the PMOS-n phototransistor M1 is larger than the exposure area of ​​the PMOS-n phototransistor M2.

[0069] PMOS-n phototransistor M1 is a device with a large exposure area, while PMOS-n phototransistor M2 is a device with a small exposure area. When light intensity increases, the current of both PMOS-n phototransistors M1 and M2 decreases. However, the current of PMOS-n phototransistor M1 decreases faster than that of PMOS-n phototransistor M2. Therefore, for a period of time, the current of PMOS-n phototransistor M1 is less than the current of PMOS-n phototransistor M2, meaning the current of FDSOI transistor M6 is less than the current of FDSOI transistor M4. This causes the parasitic capacitance at the pulse output terminal to charge, increasing the voltage and thus generating a positive voltage. When the light intensity decreases, the currents of both PMOS-n phototransistors M1 and M2 increase. However, the current of PMOS-n phototransistor M1 increases faster than that of PMOS-n phototransistor M2. Therefore, for a period of time, the current of PMOS-n phototransistor M1 is greater than that of PMOS-n phototransistor M2, that is, the current of FDSOI transistor M6 is greater than that of FDSOI transistor M4. This causes the parasitic capacitance at the pulse output terminal to be discharged, the voltage to decrease, and thus a negative pulse is generated.

[0070] In summary, this application has the following beneficial effects: (1) Two FDSOI photosensitive units with different exposure area areas are used together with ordinary logic tubes to realize the event-driven function, eliminating the capacitor required for traditional event-driven pixels, significantly reducing the pixel unit area, improving the fill factor, and adapting to high-density sensor array integration.

[0071] (2) The dedicated exposure area at the source end of the FDSOI photosensitive unit removes silicon compounds and avoids metal layer blockage, greatly improving photosensitive efficiency; different exposure areas bring different transient response speeds, which can accurately capture changes in light intensity, realize high-speed light signal response, and clearly collect information of high-speed moving objects.

[0072] (3) Relying on the back gate modulation characteristics of FDSOI devices, the channel current changes linearly with the light intensity. It outputs a voltage pulse of the corresponding polarity only when the light intensity changes. There is no output when the light intensity is constant, which effectively reduces data redundancy and reduces invalid sampling and power consumption.

[0073] (4) It supports four types of FDSOI phototransistor structures: Np, Pp, Nn, and Pn. It can match different well voltage and current-light intensity response characteristics, and has strong circuit design compatibility and wide application scenarios.

[0074] (5) The overall circuit structure is simple, the working stability is high, and it is easy to integrate and mass-produce.

[0075] (6) The response speed and sensitivity can be flexibly adjusted by adjusting the exposure area and the trap voltage bias to meet the performance requirements of different visual sensing scenarios.

[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An event-driven pixel unit based on FDSOI, characterized in that, The FDSOI-based event-driven pixel unit includes: Two FDSOI photosensitive units with different exposure area sizes and several ordinary logic transistors; The FDSOI photosensitive unit is used for light sensing; The ordinary logic transistor is used to implement the circuit function of voltage pulse generation.

2. The event-driven pixel unit based on FDSOI according to claim 1, characterized in that, The FDSOI photosensitive unit includes: a substrate, a selective well doped structure, a buried oxide layer, and a selective transistor structure; the selective well doped structure includes: a p-type well and an n-type well; the selective transistor includes: an NMOS transistor and a PMOS transistor; An exposure region is provided at the source terminal of the selective transistor; A well electrode is provided on the selective well-doped structure; A shallow trench isolation is provided around the well electrode; the shallow trench isolation is a silicon dioxide portion vertically inserted in the selective well doped structure, with a thickness between the buried oxide layer and the selective well doped structure.

3. The event-driven pixel unit based on FDSOI according to claim 2, characterized in that, When the selective transistor is an NMOS transistor and the selective well doped structure is a p-type well, the FDSOI photosensitive unit is an NMOS-p photosensitive transistor; When the FDSOI photosensitive unit is used for photosensitive purposes, a constant negative trap voltage is applied; the channel current decreases linearly with the increase of the logarithm of the light intensity.

4. The event-driven pixel unit based on FDSOI according to claim 3, characterized in that, When the FDSOI-based event-driven pixel unit is a pixel unit composed of NMOS-p photosensitive transistors, the FDSOI-based event-driven pixel unit includes: NMOS-p photosensitive transistor M1, NMOS-p photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7. The gates of the NMOS-p phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the NMOS-p phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-p phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to the power supply voltage. The source of the NMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistor M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to the power supply voltage. The source of the FDSOI transistor M7 is connected to ground. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then connected to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the NMOS-p photosensitive transistor M1 and M2 are connected together. A negative well voltage is applied. The exposure area of ​​the NMOS-p phototransistor M2 is larger than that of the NMOS-p phototransistor M1.

5. The event-driven pixel unit based on FDSOI according to claim 2, characterized in that, When the selective transistor is a PMOS transistor and the selective well doped structure is a p-type well, the FDSOI photosensitive unit is a PMOS-p photosensitive transistor. When the FDSOI photosensitive unit is used for photosensitive purposes, a constant negative trap voltage is applied; the channel current increases linearly with the logarithm of the light intensity.

6. The event-driven pixel unit based on FDSOI according to claim 5, characterized in that, When the FDSOI-based event-driven pixel unit is a pixel unit composed of PMOS-p photosensitive transistors, the FDSOI-based event-driven pixel unit includes: PMOS-p photosensitive transistor M1, PMOS-p photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7. The gates of the PMOS-p phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the PMOS-p phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-p phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to ground. The source of the PMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-p phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistor M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to ground. The source of the FDSOI transistor M7 is connected to the power supply voltage. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the PMOS-p photosensitive transistor M1 and M2 are connected together. A negative well voltage is applied. The exposure area of ​​the PMOS-p phototransistor M2 is larger than that of the PMOS-p phototransistor M1.

7. The event-driven pixel unit based on FDSOI according to claim 2, characterized in that, When the selective transistor is an NMOS transistor and the selective well doped structure is an n-type well, the FDSOI photosensitive unit is an NMOS-n photosensitive transistor; When the FDSOI photosensitive unit is used for photosensitive purposes, a constant positive trap voltage is applied; the channel current increases linearly with the logarithm of the light intensity.

8. The event-driven pixel unit based on FDSOI according to claim 7, characterized in that, When the FDSOI-based event-driven pixel unit is a pixel unit composed of NMOS-n photosensitive transistors, the FDSOI-based event-driven pixel unit includes: NMOS-n photosensitive transistor M1, NMOS-n photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7. The gates of the NMOS-n phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the NMOS-n phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-n phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to the power supply voltage. The source of the NMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the NMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistor M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to the power supply voltage. The source of the FDSOI transistor M7 is connected to ground. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then connected to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the NMOS-n photosensitive transistor M1 and M2 are connected together. A positive well voltage is applied. The exposure area of ​​the NMOS-n phototransistor M1 is larger than the exposure area of ​​the NMOS-n phototransistor M2.

9. The event-driven pixel unit based on FDSOI according to claim 2, characterized in that, When the selective transistor is a PMOS transistor and the selective well doped structure is an n-type well, the FDSOI photosensitive unit is a PMOS-n photosensitive transistor. When the FDSOI photosensitive unit is used for photosensitive purposes, a constant positive trap voltage is applied; the channel current decreases linearly with the increase of the logarithm of the light intensity.

10. The event-driven pixel unit based on FDSOI according to claim 9, characterized in that, When the FDSOI-based event-driven pixel unit is a pixel unit composed of PMOS-n photosensitive transistors, the FDSOI-based event-driven pixel unit includes: PMOS-n photosensitive transistor M1, PMOS-n photosensitive transistor M2, FDSOI transistor M3, FDSOI transistor M4, FDSOI transistor M5, FDSOI transistor M6 and FDSOI transistor M7. The gates of the PMOS-n phototransistor M1 and M2 are connected, and a gate voltage is applied. The source of the PMOS-n phototransistor M1 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-n phototransistor M1 is connected to the source of the FDSOI transistor M3. The drain of the FDSOI transistor M3 is connected to the drain of the FDSOI transistor M5. The source of the FDSOI transistor M5 is connected to ground. The source of the PMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M7. The drain of the PMOS-n phototransistor M2 is connected to the drain of the FDSOI transistor M4. The sources of the FDSOI transistor M4 and M6 are connected together. The source of the FDSOI transistor M6 is connected to ground. The source of the FDSOI transistor M7 is connected to the power supply voltage. The gate of the FDSOI transistor M5 is connected to the gate of the FDSOI transistor M6 and then to the drain of the FDSOI transistor M3. The gate of the FDSOI transistor M3 is connected to the gate of the FDSOI transistor M4. A bias voltage 1 is applied. A bias voltage 2 is applied to the gate of the FDSOI transistor M7. The wells of the PMOS-n photosensitive transistors M1 and M2 are connected together. A positive well voltage is applied. The exposure area of ​​the PMOS-n phototransistor M1 is larger than the exposure area of ​​the PMOS-n phototransistor M2.

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