MOS transistor and method for manufacturing the same

Abstract

This application discloses a MOSFET and its fabrication method, relating to the field of semiconductor technology. The MOSFET includes a substrate and an epitaxial layer and a current spreading layer sequentially disposed on the substrate. A P-type well region is formed on the current spreading layer, extending along a first direction. An N+ doped region and a P+ doped region are formed within the P-type well region, wherein the N+ doped region surrounds the outer periphery of the P+ doped region. A conductive channel is formed between the P-type well region and the epitaxial layer. A source contact is disposed on the P+ doped region. This MOSFET and its fabrication method can reduce cell size and increase channel density without changing the process boundaries.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a MOS transistor and its fabrication method. Background Technology

[0002] As power electronic systems rapidly evolve towards higher efficiency, higher power density, miniaturization, and reliable operation at high temperatures, traditional silicon-based power devices are gradually approaching their physical limits in high-voltage, high-frequency, and high-temperature applications. To overcome this bottleneck, wide-bandgap semiconductor materials, represented by silicon carbide (SiC), have become ideal choices for next-generation high-voltage power electronic devices due to their excellent physical and electrical properties. Among them, SiC materials possess high breakdown electric field strength, large carrier saturation drift velocity, high thermal conductivity, and excellent thermal stability and radiation resistance, making SiC particularly suitable for high-power, high-voltage, high-temperature, and high-frequency power electronic applications, such as main drive inverters for new energy vehicles, photovoltaic / wind power converters, fast charging piles, industrial motor drives, and smart grids. Among the many SiC power devices, SiC MOSFETs have attracted much attention due to their unipolar operating mechanism. SiC MOSFETs do not exhibit minority carrier storage effects, thus possessing extremely low switching losses and excellent high-frequency performance.

[0003] However, the high interface state density at the SiC / SiO2 interface leads to a significant reduction in channel mobility, resulting in excessively high channel resistance (Rch), which becomes one of the main factors limiting the overall conduction performance of the device. To alleviate this problem, the industry generally adopts process techniques to continuously shrink the cell size, thereby increasing the channel density per unit area and effectively realizing multiple channels in parallel, thus reducing the total channel resistance. However, the miniaturization of the cell size is gradually approaching the physical limits of current semiconductor manufacturing processes. Specifically, factors such as photolithography linewidth, minimum spacing between metal / polysilicon layers, insulation reliability of the gate oxide layer, and lateral diffusion control of the doped region collectively limit the possibility of further shrinking the cell size. Once these process boundaries are exceeded, it will lead to problems such as decreased device yield, increased risk of gate oxide breakdown, and deterioration of parasitic parameters, which will ultimately damage device performance and reliability. Summary of the Invention

[0004] The purpose of this application is to provide a MOSFET and its fabrication method, which can reduce the cell size and increase the channel density without changing the process boundaries.

[0005] The embodiments of this application are implemented as follows: A first aspect of this application provides a MOS transistor, including a substrate and an epitaxial layer and a current spreading layer disposed sequentially on the substrate. A P-type well region is formed on the current spreading layer and extends along a first direction. An N+ doped region and a P+ doped region are formed within the P-type well region. The N+ doped region surrounds the outer periphery of the P+ doped region. A conductive channel is formed between the P-type well region and the epitaxial layer. A source contact is disposed on the P+ doped region.

[0006] As one possible implementation, the source contact includes an ohmic contact layer and a source metal sequentially disposed on a P+ doped region, and a gate oxide layer and a conductive gate are sequentially formed on an N+ doped region as a gate connection, and the gate connection is isolated from the source contact by an interlayer dielectric.

[0007] As one possible implementation, the upper surface of the N+ doped region is flush with the upper surface of the P+ doped region.

[0008] As one possible implementation, the ohmic contact layer extends to the upper surface of the N+ doped region and covers a portion of the N+ doped region.

[0009] In one possible implementation, the interlayer dielectric extends to the upper surface of the gate connection and covers the gate connection.

[0010] As one possible implementation, the source metal extends to the upper surface of the interlayer medium.

[0011] As one possible implementation, a drain metal is also provided on the side of the substrate away from the epitaxial layer. The substrate is N-type silicon carbide, and both the epitaxial layer and the current spreading layer are made of silicon carbide.

[0012] As one possible implementation, the conductive gate is polycrystalline silicon.

[0013] As one possible implementation, the doping concentration of the P-type well region is in the range of 1E. 16 cm -3 To 1E 19 cm -3 Between; the doping concentration of the N+ doped region is between 1E. 18 cm -3 To 1E 22 cm -3 Between; the doping concentration of the P+ doped region is between 1E. 16 cm -3 To 1E 19 cm -3 between.

[0014] A second aspect of this application provides a method for fabricating a MOS transistor, comprising: providing a substrate, the substrate including a substrate and an epitaxial layer and a current spreading layer sequentially disposed on the substrate; ion implantation to form a P-type well region on the current spreading layer, the P-type well region extending along a first direction; ion implantation to form an N+ doped region and a P+ doped region within the P-type well region, the N+ doped region surrounding the periphery of the P+ doped region; forming a gate connection on the current spreading layer, the gate connection covering a portion of the N+ doped region; forming an interlayer dielectric on the gate connection, the interlayer dielectric covering the upper surface of the gate connection and the sidewalls of the gate connection; and forming a source contact on the P+ doped region.

[0015] The beneficial effects of the embodiments of this application include: The MOS transistor provided in this application includes a substrate and an epitaxial layer and an epitaxial layer disposed sequentially on the substrate. A P-type well region is formed on the epitaxial layer and extends along a first direction. An N+ doped region and a P+ doped region are formed in the P-type well region. The N+ doped region surrounds the outer periphery of the P+ doped region. A conductive channel is formed between the P-type well region and the epitaxial layer. A source contact is provided on the P+ doped region. The P+ doped region is located at the center of the P-type well region, and a source contact is formed on the P+ doped region. This divides the cell of the MOS transistor 100 into two segments. Specifically, the first segment is the sum of the source contact and the insulating isolation region between the source contact and the gate; this first segment is used for contact to achieve electrical connection. The second segment corresponds to the N+ doped region 131, which is the channel region. In this embodiment, the electrical connection region and the channel region are separated. This separation eliminates the need to consider short circuits between the source contact and the gate, thus eliminating the need to maintain a distance between them. This application eliminates the distance between the source contact and the gate, thereby reducing the cell size along the second direction. Therefore, the MOS transistor of this embodiment can reduce the cell size and increase the channel density. Specifically, the cell size along the first direction is reduced to 2.1 μm in this embodiment. Furthermore, by adjusting the structure of the MOS transistor, the cell size of the MOS transistor is reduced without altering the existing semiconductor manufacturing process boundaries, such as minimum linewidth and interlayer spacing. In summary, the MOS transistor of the present application can reduce the cell size and increase the channel density without changing the process boundaries. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the structural schematic diagrams of a MOS transistor provided in the embodiments of this application; Figure 2 for Figure 1 Cross-sectional view along the Y1 direction; Figure 3 for Figure 1 Cross-sectional view along the Y2 direction; Figure 4 for Figure 1 Cross-sectional view along the X direction; Figure 5 This is a second schematic diagram of a MOS transistor provided in an embodiment of this application; Figure 6 The curves showing the relationship between channel density and cell size in this application and the prior art are shown. Figure 7 This is a flowchart illustrating a method for fabricating a MOS transistor, as provided in an embodiment of this application.

[0018] Icons: 100-MOS transistor; 110-substrate; 120-epitaxy layer; 121-P-type well region; 131-N+ doped region; 133-P+ doped region; 132-source contact; 134-ohmic contact layer; 143-current spread layer; 150-gate connection; 151-gate oxide layer; 152-conductive gate; 153-interlayer dielectric; 161-drain metal; 162-source metal. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. Similar reference numerals and letters in the following drawings indicate similar items. Once an item is defined in one drawing, it does not need to be further defined in other drawings.

[0020] The terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and should not be construed as limiting this application. The terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] Unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to connections within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Please refer to the reference. Figures 1 to 4 This application provides a MOS transistor 100, including a substrate 110 and an epitaxial layer 120 and a current spreading layer 143 sequentially disposed on the substrate 110. A P-type well region 121 is formed on the current spreading layer 143 and extends along a first direction. An N+ doped region 131 and a P+ doped region 133 are formed in the P-type well region 121. The N+ doped region 131 surrounds the outer periphery of the P+ doped region 133. A conductive channel is formed between the P-type well region 121 and the epitaxial layer 120. A source contact portion 132 is disposed on the P+ doped region 133.

[0023] The MOS transistor 100 provided in this embodiment has a substrate 110 as the bottom layer, typically heavily doped with N-type material, serving as the drain. Alternatively, it can be... Figure 2 , Figure 3 and Figure 4 As shown, a drain metal 161 is formed on the lower surface of the substrate 110 as the drain. An epitaxial layer 120 is grown on the substrate 110. The epitaxial layer 120 is lightly doped with N-type metal to withstand high voltage. A current spreading layer 143 is formed on the epitaxial layer 120. A P-type well region 121 is formed in the current spreading layer 143. The P-type well region 121 is along the first direction ( Figure 1 (in the X direction) strip-shaped extension; within the P-type well region 121, N+ doped region 131 and P+ doped region 133 are simultaneously fabricated.

[0024] In this embodiment, a P+ doped region 133 is disposed at the center of a P-type well region 121, and a source contact portion 132 is disposed on the P+ doped region 133, that is, the source contact portion 132 is disposed at the center of the P-type well region 121. Figure 5As shown, the cell of the MOS transistor 100 is divided into two segments. Specifically, the region corresponding to dimension a is the sum of the source contact 132 and the insulating isolation region between the source contact 132 and the gate connection 150. That is, within the range of dimension a, it is used for contact to achieve electrical connection. The region corresponding to dimension b is the N+ doped region 131, that is, the region of dimension b is the channel region. In this embodiment, the electrical connection region and the channel region are separated. After separation, there is no need to consider the short circuit problem between the source contact 132 and the gate connection 150, and there is no need to maintain a distance between the source contact 132 and the gate connection 150. That is, this application eliminates the distance between the source contact 132 and the gate connection 150, thereby reducing the size of the cell along the second direction. Therefore, the MOS transistor 100 of this embodiment can reduce the cell size and increase the channel density. Specifically, the cell size along the first direction of this embodiment is reduced to 2.1 μm.

[0025] Additionally, within the 'a' dimension range, contact is used to achieve electrical connection, while the 'b' dimension region is the channel region. In this case, both 'a' and 'b' dimensions are adjustable. When 'b' is set larger, the channel width increases; that is, by adjusting the length of 'b', the channel density can be adjusted. Figure 6 As shown, when the b / (a+b) ratio reaches 0.7, the channel density of a 2.1μm cell can surpass that of a traditional 3.0μm cell.

[0026] In addition, by adjusting the structure of the MOS transistor 100, the cell size of this application embodiment is reduced without changing the existing semiconductor manufacturing process boundaries, such as minimum linewidth and interlayer spacing. In summary, the MOS transistor 100 of this application embodiment can reduce the cell size and increase the channel density without changing the process boundaries.

[0027] In practical applications, a gate connection 150 is also formed on the P-type well region 121. Specifically, the gate connection 150 includes a gate oxide layer 151 and a polysilicon layer. When the MOSFET 100 is operating, a voltage level higher than the threshold voltage is applied through the gate connection 150, inducing an inversion layer (N-type channel) on the surface of the P-type well region 121. The N+ doped region 131 and the underlying N-type epitaxial layer 120 form a conductive channel, and electrons flow from the N+ doped region 131 through the channel to the drain. Since the N+ doped region 131 surrounds the source contact 132 and has sidewall contact, electrons can flow in from the entire circumferential interface, significantly shortening the lateral transport path. The current spreading layer 143 acts as a lateral conductive highway, allowing the current from multiple cells to quickly converge and be conducted downwards to the epitaxial layer 120, avoiding local congestion. The source metal 162 forms an ohmic contact with the P-type well region 121 through the source contact portion 132, fixing the potential of the P-type well region 121 to the source potential, effectively suppressing parasitic BJT conduction, and preventing dV / dt misconduction or latch-up.

[0028] The current spreading layer refers to a highly doped semiconductor layer disposed on the surface of the epitaxial layer 120. It serves to laterally extend the current path when the device is turned on, reducing current congestion and the parasitic resistance between the source and the drift region. Specifically, electrons travel along the N+ doped region 131 to the channel and then enter the top of the epitaxial layer 120. Without the current spreading layer, the current concentrates in the narrow region directly below the channel, causing current congestion. With the current spreading layer, electrons first enter the highly conductive current spreading layer, diffuse laterally, and then enter the lightly doped epitaxial layer 120, achieving current homogenization. Specifically, the current spreading layer 143 can be a heavily doped N-type layer.

[0029] In this embodiment, the N+ doped region 131 is heavily doped, and the doping element can be nitrogen ion or phosphorus ion. Preferably, phosphorus ion can be selected because phosphorus ion has a lower bulk resistance, which can further reduce the on-resistance of the MOS transistor 100 in this application embodiment.

[0030] Optionally, the source contact 132 includes an ohmic contact layer 134 and a source metal 162 sequentially disposed on the P+ doped region 133, and a gate oxide layer 151 and a conductive gate 152 sequentially formed on the N+ doped region 131 as a gate connection 150, and the gate connection 150 and the source contact 132 are isolated by an interlayer dielectric 153.

[0031] The source contact 132 is disposed on the P+ doped region 133 and includes an ohmic contact layer 134 and a source metal 162. The ohmic contact layer 134 may be a metal silicide, and the source metal 162 may be a stacked structure of Ni / Ti / Al, etc.

[0032] A gate oxide layer 151 and a conductive gate 152 are sequentially formed on the N+ doped region, wherein the conductive gate 152 may be polysilicon. When a sufficiently positive voltage is applied to the conductive gate 152, an inversion electron layer is induced on the surface of the P-type well region 121 below the gate; since the N+ doped region 131 surrounds the P+ doped region 133, the conductive channel is a ring formed by the interface between the N+ doped region 131 and the P-type well region 121, and electrons flow from the N+ doped region 131 through the inversion channel into the N-type epitaxial layer 120 and then reach the drain.

[0033] By setting the conductive channel as a ring, the channel perimeter is maximized, and the channel density per unit area is significantly improved.

[0034] The interlayer dielectric 153 physically separates the source contact 132 from the gate connection 150, preventing gate-source short circuits caused by overlapping metal layers; it also reduces parasitic capacitance Cgs and improves switching speed. In practical applications, the source contact 132 and the gate are connected to the outside via traces, and the interlayer dielectric 153 is also used to isolate the traces between the two.

[0035] As one possible approach, the upper surface of the N+ doped region 131 is flush with the upper surface of the P+ doped region 133.

[0036] The N+ doped region 131 and the P+ doped region 133 are located on the same planar layer, typically on top of the current spread layer 143, and their upper surfaces are at the same height. The source contact 132 needs to cover both the P+ doped region 133 and the N+ doped region 131. The P+ doped region 133 is used for potential clamping of the P-type well region 121, and the N+ doped region 131 is used for electron injection. If the surfaces of the N+ doped region and the P+ doped region are not flush, such as the P+ doped region being recessed or the N+ doped region being convex, voids, breaks, or stress concentrations are likely to occur during the deposition of the source contact 132, leading to increased local contact resistance or even open circuits. However, if the surfaces of the two regions are flush, the thin film of the source contact 132 is continuous and of uniform thickness, resulting in reliable ohmic contact with low resistance.

[0037] In addition, in high-voltage SiC MOSFETs, the source edge is a region of concentrated electric field. If there are steps or trenches at the junction of N+ doped region 131 and P+ doped region 133, an electric field enhancement effect will be induced at the sharp corner, which may lead to local breakdown of gate oxide layer 151 or surface leakage. However, the coplanar structure of the two has a smooth surface potential gradient, which suppresses electric field concentration and improves the withstand voltage reliability.

[0038] Optional, such as Figure 4 As shown, the ohmic contact layer 134 extends to the upper surface of the N+ doped region 131 and covers a portion of the N+ doped region 131.

[0039] The ohmic contact layer 134 mainly covers the P+ doped region 133 to form an ohmic contact with the P-type well. It also extends laterally, covering part of the upper surface of the N+ doped region 131. That is, the same ohmic contact layer 134 simultaneously contacts both the P+ doped region 133 and the N+ doped region 131. This single ohmic contact layer 134 directly bridges the P+ doped region 133 and the N+ doped region 131, achieving a short circuit between them without the need for additional wiring. Extending the ohmic contact layer 134 to the N+ doped region 131 allows for direct electron injection from the N+ doped region 131, avoiding current bypass and reducing the total source contact resistance.

[0040] As one possible implementation, the interlayer dielectric 153 extends to the upper surface of the gate connection 150 and covers the gate connection 150.

[0041] The interlayer dielectric 153 extends to the upper surface of the gate connection 150 and covers the gate connection 150, so that the interlayer dielectric 153 fully covers the gate connection 150, completely eliminating the risk of short circuit between the source and the gate. In addition, the interlayer dielectric 153 can smoothly wrap the gate connection 150, resulting in a uniform electric field distribution and reducing the risk of local breakdown.

[0042] Optionally, the source metal 162 extends to the upper surface of the interlayer dielectric 153.

[0043] The source metal 162 serves as the conductive layer of the source terminal and can be a metal such as Al, Cu, or Al-Si-Cu alloy. The interlayer dielectric 153 is an insulating layer covering the active region, gate connection 150, and other structures. The source metal 162 extends to the upper surface of the interlayer dielectric 153. That is, the source metal 162 is not only disposed on the ohmic contact layer 134, but also extends laterally above the interlayer dielectric 153 to form metal traces or pads.

[0044] The source metal 162 extends to the upper surface of the interlayer dielectric 153, forming exposed metal pads or traces that can be directly used for wire bonding or ball bonding. If the source metal 162 is limited to the contact hole (i.e., the space on the ohmic contact layer 134), the current path is narrow, resulting in a bottleneck effect, and the contact hole sidewall resistance and interface scattering are significant; while the laterally extended source metal 162 provides a wide cross-section, low-resistance path, effectively reducing resistance.

[0045] As one possible approach, a drain metal 161 is also provided on the side of the substrate 110 away from the epitaxial layer 120. The substrate 110 is N-type silicon carbide, and the epitaxial layer 120 and the current spreading layer 143 are both made of silicon carbide.

[0046] Current flows in from the back drain metal 161 and is rapidly conducted through the low-resistivity N-type substrate 110 to the N-type epitaxial layer 120. Under gate control, electrons enter the source region of the N+ doped region 131 through the channel at the interface between the P-type well region 121 and the N+ doped region 131, and finally flow out from the front source metal 162, forming a vertical structure. The vertical structure makes the area of ​​the active region determined only by the chip surface area, without needing to occupy lateral space for the drain, which greatly improves the current capability per unit area.

[0047] Optionally, the conductive gate 152 is made of polysilicon.

[0048] Polycrystalline silicon is typically heavily doped to reduce electrical resistance. Polycrystalline silicon can form a stable interface with the silicon dioxide gate oxide layer 151 through high-temperature annealing. Furthermore, the thermal expansion coefficient of polycrystalline silicon is more compatible with that of SiO2, reducing interface state generation caused by thermal stress, thereby lowering the interface state density and improving electron mobility.

[0049] As one feasible approach, the doping concentration of the P-type well region 121 is at 1E. 16 cm -3 To 1E 19 cm -3 Between; the doping concentration of N+ doped region 131 is between 1E. 18 cm -3 To 1E 22 cm-3 Between; the doping concentration of the P+ doped region 133 is between 1E. 16 cm -3 To 1E 19 cm -3 between.

[0050] This application embodiment also provides a method for fabricating a MOS transistor 100, such as... Figure 7 As shown, it includes: S100: A substrate is provided, the substrate including a substrate 110 and an epitaxial layer 120 and a current spreading layer 143 disposed on the substrate 110; The substrate 110 can be a silicon substrate 110, which can be heavily N-type doped to serve as the drain of the vertical MOS transistor 100, or a drain metal 161 can be disposed on the other side of the substrate 110 as the drain. The epitaxial layer 120 is a lightly doped N-type layer grown epitaxially to provide high-voltage blocking and to provide a basic platform for subsequent P-type well regions 121, etc. The specific structure and beneficial effects of the current spreading layer 143 are described in detail in the above embodiments and will not be repeated here.

[0051] S200: Ion implantation is performed on the current spreading layer 143 to form a P-type well region 121, which extends along the first direction; Specifically, boron ion implantation can be used to form a P-type well region 121 extending along a first direction on the surface of the epitaxial layer 120.

[0052] S300: An N+ doped region 131 and a P+ doped region 133 are formed by ion implantation in the P-type well region 121. The N+ doped region 131 surrounds the outer periphery of the P+ doped region 133, and the sidewall of the P+ doped region 133 is in contact with the sidewall of the N+ doped region 131. Using the same photomask or two self-aligned implantations, arsenic / phosphorus (As / P) is first implanted to form an N-type N+ doped region 131; then a high dose of boron is implanted to form a P+ doped region 133; the N+ doped region 131 surrounds the outer periphery of the P+ doped region 133 and is in edge contact; thus achieving a coplanar bifunctional source contact structure for the N+ doped region 131 and the P+ doped region 133, saving area.

[0053] S400: A gate connection 150 is formed on the current spreading layer 143, and the gate connection 150 covers a portion of the N+ doped region 131. A gate oxide layer 151 and a polysilicon layer are deposited to form a gate connection 150, wherein the gate connection 150 covers a portion of the N+ doped region 131, which facilitates the subsequent formation of an ohmic contact layer 134 on the P-type doped region.

[0054] S500: An interlayer dielectric 153 is formed on the gate connection 150, the interlayer dielectric 153 covering the upper surface of the gate connection 150 and the sidewalls of the gate connection.

[0055] Specifically, dielectric materials such as SiO2, Si3N4, or low-k materials can be deposited to completely cover the entire surface, including the P+ doped region 133, preparing for subsequent selective etching and protecting other areas. Before forming the dielectric material on the gate connection 150, a dielectric material also needs to be formed on the upper surface of the gate connection 150.

[0056] The dielectric material is etched to expose the P+ doped region 133, and the etched dielectric material and the dielectric material together form the interlayer dielectric 153. Specifically, contact hole photolithography and dry etching are used to create holes only above the P+ doped region 133.

[0057] S600: A source contact is formed on the P+ doped region 133; An ohmic contact layer 134 and a source metal 162 are formed on the P+ doped region 133, with the ohmic contact layer 134 and the source metal 162 serving as the source contact portion 132.

[0058] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0059] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application will not describe the various possible combinations separately.

Claims

1. A MOSFET, characterized in that, The device includes a substrate and an epitaxial layer and a current spreading layer sequentially disposed on the substrate. A P-type well region is formed on the current spreading layer and extends along a first direction. An N+ doped region and a P+ doped region are formed within the P-type well region. The N+ doped region surrounds the outer periphery of the P+ doped region. A conductive channel is formed between the P-type well region and the epitaxial layer. A source contact is disposed on the P+ doped region.

2. The MOS transistor according to claim 1, characterized in that, The source contact includes an ohmic contact layer and a source metal sequentially disposed on the P+ doped region. A gate oxide layer and a conductive gate are sequentially formed on the N+ doped region as a gate connection, and the gate connection is isolated from the source contact by an interlayer dielectric.

3. The MOS transistor according to claim 2, characterized in that, The upper surface of the N+ doped region is flush with the upper surface of the P+ doped region.

4. The MOS transistor according to claim 2, characterized in that, The ohmic contact layer extends to the upper surface of the N+ doped region and covers a portion of the N+ doped region.

5. The MOS transistor according to claim 2, characterized in that, The interlayer dielectric extends to the upper surface of the gate connection and covers the gate connection.

6. The MOS transistor according to claim 5, characterized in that, The source metal extends to the upper surface of the interlayer medium.

7. The MOS transistor according to claim 1, characterized in that, A drain metal is also disposed on the side of the substrate away from the epitaxial layer. The substrate is N-type silicon carbide, and both the epitaxial layer and the current spreading layer are made of silicon carbide material.

8. The MOS transistor according to claim 2, characterized in that, The conductive gate is made of polycrystalline silicon.

9. The MOS transistor according to claim 7, characterized in that, The doping concentration of the P-type well region is 1E. 16 cm -3 To 1E 19 cm -3 Between; the doping concentration of the N+ doped region is between 1E. 18 cm -3 To 1E 22 cm -3 Between; the doping concentration of the P+ doped region is between 1E. 16 cm -3 To 1E 19 cm -3 between.

10. A method for fabricating a MOS transistor, characterized in that, For manufacturing the MOS transistor according to any one of claims 1 to 9, comprising: A substrate is provided, the substrate comprising a substrate and an epitaxial layer and a current spreading layer sequentially disposed on the substrate; Ion implantation is performed to form a P-type well region on the current spreading layer, and the P-type well region extends along a first direction; Ion implantation is performed in the P-type well region to form an N+ doped region and a P+ doped region, wherein the N+ doped region surrounds the outer periphery of the P+ doped region. A gate connection is formed on the current spreading layer, the gate connection covering a portion of the N+ doped region; An interlayer dielectric is formed on the gate connection, the interlayer dielectric covering the upper surface of the gate connection and the sidewalls of the gate connection; A source contact is formed on the P+ doped region.

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