Vertical gallium nitride transistor

Abstract

Vertical gallium nitride (GaN) field effect transistors (FETs) are presented herein. A vertical GaN FET includes cylindrical trench gates arranged in a hexagonal array to form a vertical FET channel. At a surface of the vertical GaN FET is a source layer formed in a GaN epitaxial layer and formed above a GaN substrate. A channel can be formed in the form of "GaN pillars" between the cylindrical gates; and FET characteristics, including threshold voltage, can be determined at least in part as a function of trench nearest neighbor distance. Thus, the trench nearest neighbor distance can be selected so that the vertical GaN FET operates either as an enhancement mode transistor or as a depletion mode transistor.

Description

[0001] Cross-reference to related applications This application claims priority to U.S. Provisional Application No. 63 / 728,947, filed December 6, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to vertical power semiconductor devices, and more particularly to gallium nitride (GaN) power semiconductor devices. Background Technology

[0003] Gallium nitride (GaN) and other wide-bandgap group III nitride-based direct-transition semiconductor materials exhibit high breakdown electric fields and provide high current densities. In this regard, GaN-based semiconductor devices are actively studied as an alternative to silicon-based semiconductor devices in power and high-frequency applications. For example, compared to silicon power MOSFETs of similar area, GaN power devices can provide lower specific on-resistance and higher breakdown voltage.

[0004] Field-effect transistors (FETs)—including power FETs—can be either enhancement-mode (enhancement-mode) or depletion-mode (depletion-mode). An enhancement-mode device can refer to a transistor (e.g., a field-effect transistor) that blocks current (i.e., is off) when no gate bias is applied (i.e., when the gate-to-source bias is zero). In contrast, a depletion-mode device can refer to a transistor that allows current (i.e., is on) when the gate-to-source bias is zero.

[0005] Field-effect transistors (FETs) can be configured such that current is conducted laterally between the drain and source, which are separated at the device surface. Examples of lateral GaN FETs include high electron mobility transistors (HEMTs), which provide high conductivity due to the two-dimensional electron gas (2DEG) formed between the GaN and aluminum gallium nitride (AlGaN) layers.

[0006] Alternatively, the FET can be configured such that current flows vertically between the drain at the bottom of the device and the source at the surface of the device. Examples of vertical GaN FETs include current aperture vertical electron transistors (CAVETs), trench metal-oxide field-effect transistors (MOSFETs), and fin field-effect transistors (FinFETs). Summary of the Invention

[0007] State-of-the-art GaN HEMTs achieve high breakdown voltages (e.g., 1 kV) with low specific on-resistance (defined by the product of resistance and device area, e.g., milliohms per square centimeter). However, a drawback of GaN HEMTs is the "current collapse" phenomenon, which causes an undesirable dynamic increase in on-resistance. Furthermore, for applications requiring even higher breakdown voltages (e.g., 2 kV), vertical GaN FETs become an attractive alternative to lateral GaN HEMTs; this is because vertical GaN transistors can offer lower specific on-resistance, higher breakdown voltage, and better device reliability.

[0008] As mentioned above, vertical GaN power FETs, including CAVET, trench MOSFET, and FinFET, have been developed. Unfortunately, CAVET, trench MOSFET, and FinFET involve complex fabrication steps. For example, CAVET and trench MOSFET require the formation of a p-type GaN layer, which can be difficult to fabricate reliably. Furthermore, although FinFET can be fabricated without p-type GaN, the resulting narrow fins, typically between 0.18 μm and 0.4 μm, can be difficult to produce reliably and require expensive fabrication techniques (e.g., electron beam lithography).

[0009] Therefore, there is a need to develop a vertical GaN transistor suitable as a power FET, without the limitations of the current state-of-the-art CAVET, trench MOSFET, and FinFET.

[0010] This disclosure introduces a novel vertical GaN transistor (i.e., a vertical GaN FET) that differs from CAVET, trench MOSFETs, and FinFETs. According to the teachings herein, a vertical GaN FET includes cylindrical trench gates arranged in a hexagonal array to form a vertical FET channel. At the surface of the vertical GaN FET is a source layer formed in a GaN epitaxial layer and over a GaN substrate. The channel can be formed between the cylindrical gates in the form of “GaN pillars”; and the FET characteristics, including the threshold voltage, can be determined at least in part based on the trench nearest neighbor distance. Therefore, the trench nearest neighbor distance can be selected such that the vertical GaN FET operates either as an enhancement-mode transistor or as a depletion-mode transistor. Attached Figure Description

[0011] Non-limiting and non-exhaustive embodiments of vertical gallium nitride transistors are described with reference to the following figures, wherein, unless otherwise stated, the same reference numerals refer to the same parts in all the various views.

[0012] Figure 1AA cross-sectional perspective view of a vertical GaN transistor according to one embodiment is illustrated.

[0013] Figure 1B Examples Figure 1A A two-dimensional (2D) top view of a vertical GaN transistor.

[0014] Figure 1C Examples Figure 1A Another two-dimensional (2D) top view of a vertical GaN transistor.

[0015] Figure 2 A three-dimensional (3D) side perspective view of a vertical GaN transistor is shown.

[0016] Figure 3A Examples Figure 2 A two-dimensional (2D) cross-sectional view of a portion of a vertical GaN transistor depicted in the image.

[0017] Figure 3B Examples are given based on Figure 3A A plot of the doping concentration of the implementation scheme.

[0018] Figure 4 Another three-dimensional (3D) side perspective view of a vertical GaN transistor is shown.

[0019] Figure 5A A two-dimensional (2D) cross-sectional view of a vertical GaN transistor is shown.

[0020] Figure 5B Another two-dimensional (2D) cross-sectional view of a vertical GaN transistor is shown.

[0021] Figure 6 The simulated drain current transfer curve is shown.

[0022] Figure 7A Examples of the same Figure 6 The cross section corresponding to the first transfer curve.

[0023] Figure 7B Examples of the same Figure 6 The cross section corresponding to the second transfer curve.

[0024] Figure 7C Examples of the same Figure 6 The cross section corresponding to the third transition curve.

[0025] Figure 7D Examples of the same Figure 6 The cross section corresponding to the fourth transition curve.

[0026] Figure 7E Examples of the same Figure 6 The cross section corresponding to the fifth transition curve.

[0027] Figure 8 Another three-dimensional (3D) side perspective view of a vertical GaN transistor is shown.

[0028] Figure 9 Examples are given based on Figure 8 The electric field of the implementation scheme is drawn.

[0029] Figure 10 The simulated drain current transfer curve is shown.

[0030] Figure 11 Examples of the same Figure 10 The cross section corresponding to the transfer curve.

[0031] Figure 12A Examples are given based on Figure 10 A two-dimensional (2D) cross-sectional view of the implementation scheme.

[0032] Figure 12B Examples are given based on Figure 10 The electron density transfer curve of the implementation scheme.

[0033] Figure 13A A cross-section of a vertical GaN transistor is shown.

[0034] Figure 13B Examples are given based on Figure 13A The transition curve of the implementation plan.

[0035] Figure 13C Examples are given based on Figure 13A Additional transfer curves for the implementation scheme.

[0036] Figure 14 A cross-sectional perspective view of a vertical GaN transistor according to another embodiment is illustrated.

[0037] Figure 15A Examples Figure 14 A two-dimensional (2D) cross-sectional view of a vertical GaN transistor.

[0038] Figure 15B Examples of the same Figure 15A The corresponding magnified view.

[0039] Figure 15C Examples of the same Figure 15A A plot of the electron density corresponding to the cross-section.

[0040] Figure 16 Examples are given based on Figure 14 The transition curve of the implementation plan.

[0041] Figure 17 Examples are given based on Figure 16 The electron density transfer curve of the implementation scheme.

[0042] Figure 18A Examples Figure 14 Another two-dimensional (2D) cross-sectional view of a vertical GaN transistor.

[0043] Figure 18B Examples are given based on Figure 18A The electric field of the implementation scheme is drawn.

[0044] In all the views of the accompanying drawings, corresponding reference characters indicate the corresponding parts. Those skilled in the art will understand that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements and layers in the drawings may be exaggerated relative to other elements to aid in understanding the various embodiments taught herein. Furthermore, common but easily understood elements, layers, and / or process steps that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate viewing these various embodiments of the vertical gallium nitride transistor with less obstruction. Detailed Implementation

[0045] In the following description, numerous specific details are set forth to provide a thorough understanding of vertical gallium nitride transistors. However, it will be apparent to those skilled in the art that the specific details are not required to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail to avoid obscuring the contents of this disclosure.

[0046] Figure 1A A cross-sectional perspective view of a vertical GaN transistor 100 according to one embodiment is illustrated. The vertical GaN transistor 100 includes cylindrical trench gates 105a-c and 106a-c formed at a surface. The cylindrical trench gates 105a-c, 106a-c may be lined with a gate dielectric 112 (e.g., oxide) and filled with a gate electrode 111 (e.g., polysilicon and / or metal).

[0047] According to the teachings of this paper, the cylindrical trench gates 105a-c, 106a-c can be patterned (i.e., arranged) into a hexagonal array, as seen from above the surface. According to solid-state physics, a two-dimensional hexagonal array can also be characterized by a triangular unit cell; therefore, the cylindrical trench gates 105b, 106b, 106c form a triangular unit cell 117.

[0048] Figure 1B Examples Figure 1AA two-dimensional (2D) top view of the vertical GaN transistor 100. This 2D top view shows the arrangement of cylindrical trench gates 105b, 106b, and 106c. Based on their proximity, the cylindrical trench gates 105b, 106b, and 106c can be referred to as "nearest neighbors." (See above regarding...) Figure 1A The cylindrical trench gates 105b, 106b, and 106c discussed form a triangular unit cell 117, and can also be characterized as a portion of a hexagonal array, such as... Figure 1C As shown in the image.

[0049] Figure 1C Also exemplified Figure 1A A two-dimensional (2D) top view of a vertical GaN transistor 100. Figure 1C The 2D top view shows the arrangement of cylindrical trench gates 105a-e, 106a-f, and 107a-e; and as mentioned above regarding Figure 1A-1B The cylindrical trench gates 105b, 106b, and 106c discussed herein form a triangular cell 117. Furthermore, in accordance with the teachings of this document, the cylindrical trench gates 105b, 106b, and 106c of the triangular cell 117 may also be referred to as “nearest neighbors” due to their proximity.

[0050] Alternatively, and additionally, the cylindrical trench gates 105d-e, 106d-f, and 107d-e also form a hexagonal cell 118, with the cylindrical trench gate 106e located at its center. Therefore, based on their proximity, the cylindrical trench gates 105d-e, 106d, 106f, and 107d-e can be the nearest neighbors of the cylindrical trench gate 106e.

[0051] Figure 2 A three-dimensional (3D) side perspective view of a vertical GaN transistor 100 is illustrated. This 3D side perspective view illustrates a portion of the vertical GaN transistor 100 including cylindrical trench gates 105b, 106b, and 106c. As discussed above, the cylindrical trench gates 105b, 106b, and 106c can be nearest neighbors forming a triangular unit cell 117. The doping concentration can be depicted according to doping concentration diagram 202; and the coordinates are defined relative to the Cartesian axis 201.

[0052] According to the teachings of this document, cylindrical trench gates 105b, 106b, and 106c can be formed extending from the surface into the channel epitaxial layer 114 and extending above the drift epitaxial layer 113. For example, the cylindrical trench gates 105b, 106b, and 106c can extend into the channel epitaxial layer 114 by two micrometers (2 μm). The channel epitaxial layer 114 and the drift epitaxial layer 113 can be GaN epitaxial layers with different n-type doping concentrations. The source layer 204 can be a heavily doped n-type layer formed at the surface. Furthermore, the channel epitaxial layer 114, including the source layer 204, can form "GaN pillars" between the cylindrical trench gates 105b, 106b, and 106c.

[0053] Figure 3A Examples Figure 2 The image depicts a portion of a vertical GaN transistor 100 in a two-dimensional (2D) cross-sectional view. This 2D cross-sectional view shows a cross-section of the vertical GaN transistor 100 in an XZ plane defined by the Cartesian axis 201. Coordinate values ​​in micrometers are marked on both the X and Z axes. The source layer depth 309 can be the depth to which the source layer 204 extends from the surface of the vertical GaN transistor 100 into the channel epitaxial layer 114. As illustrated, the source layer depth 309 can be defined from the surface of the vertical GaN transistor 100 to twelve micrometers (12 μm).

[0054] Distance D1 can be the distance from the bottom of the channel epitaxial layer 114 extending beyond the cylindrical trench gates 105b and 106b to junction 307 (i.e., the drift-to-trench-bottom distance). Distance D1 can be 0.5 micrometers (0.5 μm); and junction 307 can be the location of epitaxial doping transition. For example, junction 307 can be abrupt junctions where the doping concentration transitions from a lower concentration in the channel epitaxial layer 114 to a higher concentration in the drift epitaxial layer 113.

[0055] The trench nearest neighbor distance D4 is the GaN mesa width (shortest distance) between adjacent cylindrical trench gates (e.g., between cylindrical trench gate 105b and cylindrical trench gate 106b). The trench nearest neighbor distance D4 can be 0.2 μm.

[0056] The sidewall thickness 305 can be the sidewall distance by which the gate dielectric 112 extends beyond the gate electrode 111. The sidewall thickness 305 can be between 0.02 μm and 0.1 μm.

[0057] The dielectric thickness of 306 can be the thickness of the bottom oxide.

[0058] According to the physics of semiconductor devices, the threshold voltage of a vertical GaN transistor 100 can depend at least in part on the sidewall thickness 305, the doping concentration of the channel epitaxial layer 114, and / or the work function of the gate electrode 111. For a vertical GaN transistor 100 rated for 1200 volts, the channel epitaxial layer 114 can have a doping concentration of 2 x 10^15 cm^-3. The gate electrode 111 can be heavily doped p-type polysilicon (P+ polysilicon) with a work function of 5.1 eV. Furthermore, the dielectric thickness 306 can be 0.5 micrometers (0.5 μm).

[0059] Based on the teachings of this paper, a superior and less complex vertical GaN transistor 100 can be advantageously realized using a triangular cell layout of cylindrical trench gates 105b, 106b, and 106c. For example, cylindrical trench gates can be fabricated without the need for electron beam lithography.

[0060] Figure 3B Examples are given based on Figure 3A Plot 303 shows the doping concentration of the proposed implementation. (Reference) Figure 3A The plot 303 can be plotted at an X-axis coordinate value of one micrometer (1 μm). The Z-axis value can extend between negative and positive coordinate values ​​and pass through the source layer 204. The doping concentration can be n-type, and under equilibrium conditions, it can also correspond to the equilibrium carrier concentration.

[0061] As illustrated, a Z-axis coordinate of zero (0) can define the location on the GaN substrate surface. As those skilled in the art will understand, the epitaxial layer (e.g., drift epitaxial layer 113) can be grown on a GaN substrate with a higher doping concentration than the drift epitaxial layer 113. The channel length D2 can be the thickness of the channel epitaxial layer 114 between the source layer (at z=12µm) and the junction 307. The channel length D2 can be 2.5 micrometers (2.5µm). A Z-axis coordinate less than zero can correspond to and be located within the GaN substrate.

[0062] The GaN substrate can be used as the drain of the vertical GaN transistor 100. The doping concentration of the GaN substrate can be greater than 1 x 10^19 per cubic centimeter (1e19cm-3). For example, the GaN substrate can have a doping concentration of 3 x 10^19 per cubic centimeter (3e19cm-3). The doping concentration (carrier concentration) of the channel epitaxial layer 114 can be between 10^15 per cubic centimeter (1e15cm-3) and 5 x 10^15 per cubic centimeter (5e15cm-3). The doping concentration (carrier concentration) of the source layer 204 can be on the order of 10^18 per cubic centimeter (1e18cm-3), between 9 x 10^17 per cubic centimeter (9e17cm-3) and 2 x 10^18 per cubic centimeter (2e18cm-3).

[0063] The drift epitaxial layer thickness D3 can be the thickness of the drift epitaxial layer 113 extending between junction 307 and the Z-axis coordinate zero (z=0). The drift epitaxial layer thickness D3 can be 9.5 micrometers (9.5 μm). The doping concentration (carrier concentration) of the drift epitaxial layer 113 can be on the order of 10 to the power of 16 per cubic centimeter (1e16 cm⁻³), between 9 to the power of 10 to the power of 15 per cubic centimeter (9e15 cm⁻³) and 2 to the power of 10 to the power of 16 per cubic centimeter (2e16 cm⁻³). Although the plot 303 of the carrier concentration (doping concentration) shows an abrupt distribution transition at coordinates z=0, 12 and at junction 307, other distributions are also possible. For example, the doping concentration (carrier concentration) can be a gradual rather than an abrupt transition, and have a gentler, less abrupt slope at coordinates z=0, 12 and at junction 307.

[0064] Figure 4 Another three-dimensional (3D) side perspective view of the vertical GaN transistor 100 is shown. (Compared to...) Figure 2 Unlike the side perspective view, this 3D side perspective view also includes sections 401 and 402. Section 401 includes (through) the drift epitaxial layer 113. Section 402 may be parallel to section 401 and includes (through) the cylindrical trench gates 105b, 106b, and 106c.

[0065] Figure 5A A two-dimensional (2D) cross-sectional view of a vertical GaN transistor 100 along section 401 is illustrated. Section 401 may include an XY plane (i.e., X-axis and Y-axis coordinates) at a fixed Z-axis coordinate and shows the doping concentration corresponding to the fixed Z-axis coordinate of the drift epitaxial layer 113. For example, the doping concentration may be a uniform value of 10 to the power of 16 per cubic centimeter (1e16cm⁻³).

[0066] Figure 5BAnother two-dimensional (2D) cross-sectional view of the vertical GaN transistor 100 along section 402 is illustrated. Section 402 may correspond to the Z-axis coordinate of the channel epitaxial layer 114, which also includes the cylindrical trench gates 105b, 106b, and 106c. Along section 402, the doping within the cylindrical trench gates 105b, 106b, and 106c may differ from the doping within the channel epitaxial layer 114.

[0067] As discussed above, the nearest neighbor distance D4 of the trench can be the (shortest) distance between adjacent cylindrical trench gates (e.g., between adjacent cylindrical trench gates 105b, 106b), and can be 0.2 micrometers (0.2 μm). Furthermore, as illustrated, distance D5 can be the widest distance of the channel epitaxial layer 114 confined between the cylindrical trench gates 105b, 106b, 106c and on cross-section 402. For example, distance D5 can be 0.9 micrometers (0.9 μm), while the nearest neighbor distance D4 is 0.2 micrometers (0.2 μm).

[0068] Therefore, as can be seen from the 2D cross-sectional view at section 402, the channel epitaxial layer 114 forms a “wedge” with a width varying between 0.2 μm (nearest neighbor distance D4) and 0.9 μm (distance D5). According to the teachings of this paper, forming a “wedge” between the cylindrical trench gates 105b, 106b, and 106c can facilitate the realization of a superior, less complex vertical GaN transistor 100.

[0069] Figure 6 The transfer curves 601-605 simulating drain current (in amperes) are illustrated; and Figures 7A-7E Cross sections 701-705 are illustrated, corresponding to transfer curves 601-605 respectively. For the monotonically decreasing nearest-neighbor distance D4 conveyed by cross sections 701-705 respectively, the drain current is plotted as a function of the gate-to-source voltage VGS (in volts). For example, cross section 701 can correspond to a nearest-neighbor distance D4 equal to one micrometer (1µm). Cross section 702 can correspond to a nearest-neighbor distance D4 equal to 0.8 micrometers (0.8µm). Cross section 703 can correspond to a nearest-neighbor distance D4 equal to 0.6 micrometers (0.6µm). Cross section 704 can correspond to a nearest-neighbor distance D4 equal to 0.4 micrometers (0.4µm); and cross section 705 can correspond to a nearest-neighbor distance D4 equal to 0.2 micrometers (0.2µm). The drain-to-source voltage VDS can be one volt (1V). The specific on-resistance Rsp can be approximately one milliohm-cm². For example, the on-resistance Rsp can be 1.06 milliohms square centimeters (1.06 mohm-cm^2).

[0070] In semiconductor device practice, the threshold voltage of a field-effect transistor can be quantified by measuring the gate-to-source voltage VGS at a specified fixed drain current. For example, the threshold voltage Vth can be defined based on a current of 10 to the power of negative 11 (1e-11) amperes. Therefore, as the nearest neighbor distance D4 decreases, the threshold voltage Vth can increase. Thus, as illustrated by transition curves 601-605, the threshold voltage Vth, as defined above, increases from negative to positive values, ranging from -1 volt (-1V) to +1 volt (1V).

[0071] Furthermore, according to semiconductor device practice, a negative threshold voltage Vth corresponds to depletion mode operation, and a positive threshold voltage Vth corresponds to enhancement mode operation. Therefore, as the spacing between the cylindrical trench gates 105b, 106b, and 106c decreases (i.e., as the nearest neighbor distance D4 decreases), the threshold voltage increases from a negative value to a positive value.

[0072] Therefore, the threshold voltage and operating mode (depletion mode, enhancement mode) can be determined at least in part by the nearest neighbor distance D4. Based on the teachings of this paper, the vertical GaN transistor 100 can be determined at least in part by whether the nearest neighbor distance D4 is in enhancement mode (i.e., with a threshold voltage greater than zero) or depletion mode (i.e., with a threshold voltage less than zero). Furthermore, the subthreshold slope—a quantity related to the slope of the transfer curves 601-605—can be determined at least in part by the sidewall thickness 305.

[0073] Figure 8 Another three-dimensional (3D) side perspective view of the vertical GaN transistor 100 is illustrated. This 3D side perspective view is... Figure 2 Similar to the side perspective view, except that it illustrates the electric field distribution instead of the doping concentration. This electric field can be caused by the applied drain-to-source voltage VDS. For example, the applied drain-to-source voltage VDS could be 1500 volts (1500 V). The electric field can be defined relative to electric field illustration 802 and has units of volts per centimeter (V / cm).

[0074] Figure 9 Examples are given based on Figure 8 The electric field of the implementation scheme is plotted in 901. The applied drain-to-source voltage VDS can be 1500V. The electric field increases monotonically from the substrate surface where the Z-axis coordinate is zero (z=0) and is maximum within the gate dielectric 112 (near z=10µm).

[0075] Figure 10A transfer curve 1001 of the simulated drain current (in amperes) as a function of the gate-to-source voltage VGS (in volts) is illustrated. The applied drain-to-source voltage VDS can be one volt (1V). The dielectric 112 can be an oxide. The sidewall thickness 305 can be 0.1 micrometer (0.1µm). The doping concentration in the channel epitaxial layer 114 can be an n-type concentration of 2 x 15^2 / 3 cm^-3. The simulated threshold voltage Vth based on the subthreshold slope can be greater than one volt. For example, the simulated threshold voltage Vth based on the subthreshold slope can be equal to 1.3 volts (1.3V). Furthermore, the calculated specific on-resistance Rsp can be equal to 1.06 milliohms per square centimeter (1.06 mohm-cm^2).

[0076] Figure 11 A cross section 1101 corresponding to transfer curve 1001 is illustrated. Cross section 1101 can be in the XY plane perpendicular to GaN transistor 100. Similar to cross sections 701-705, cross section 1101 includes cylindrical trench gates 105b, 106b, 106c and a channel epitaxial layer 114. The drain-to-source voltage VDS can be one volt (1V). The gate-to-source voltage VGS can be equal to one and a half volts (1.5V). Under these conditions (i.e., drain-to-source voltage VDS = 1V, gate-to-source voltage VGS = 1.5V), the carrier concentration can be approximately ten to the power of 12 per cubic centimeter (1e12cm⁻³).

[0077] As the gate-to-source voltage VGS changes from zero volts (0V) to five volts (5V), the (electron) carrier concentration in the channel epitaxial layer 114 can change from approximately 10⁻⁹ per cubic centimeter (1e⁻⁹cm⁻³) to approximately 10⁹ per cubic centimeter (1e¹⁹cm⁻³). When the gate-to-source voltage VGS is zero volts, carriers (i.e., electrons) are depleted, and the simulated carrier concentration can be approximately 10⁻⁹ per cubic centimeter (1e⁻⁹cm⁻³). When the gate-to-source voltage VGS is 0.5 volts (0.5V), the carrier concentration increases to approximately 10³ per cubic centimeter (1e³cm⁻³). When the gate-to-source voltage VGS is five volts (5V), the carrier concentration increases to approximately 10⁹ per cubic centimeter (1e¹⁹cm⁻³).

[0078] Figure 12A Examples are given based on Figure 10 A two-dimensional (2D) cross-sectional view of the implementation scheme. This 2D cross-sectional view is consistent with... Figure 3ASimilar to a 2D cross-sectional view, except that it illustrates electron density instead of doping concentration. The unit can be electrons (charge carriers) per cubic centimeter (cm⁻³). The dicing line 1210 can correspond to an X-axis coordinate value of approximately 1.5 micrometers, such that the dicing line 1210 is held within the channel epitaxial layer 114, close to the cylindrical trench gate 105b. The drain-to-source voltage VDS can be one volt (1V). The gate-to-source voltage VGS can be equal to 1.5 volts (1.5V).

[0079] Figure 12B Examples are given based on Figure 10 The electron density transfer curves 1201-1206 along the Z-axis of the cutting line 1210 of the proposed implementation are shown. For reference, Figure 12B A 1D plot 1220 showing the doping concentration along cut line 1210 is also illustrated. The drain-to-source voltage VDS can be one volt (1V). Transfer curve 1201 corresponds to a gate-to-source voltage VGS of zero volt (0V). Transfer curve 1202 corresponds to a gate-to-source voltage VGS of 0.5 volts (0.5V). Transfer curve 1203 corresponds to a gate-to-source voltage VGS of one volt (1.0V). Transfer curve 1204 corresponds to a gate-to-source voltage VGS of 1.5 volts (1.5V). Transfer curve 1205 corresponds to a gate-to-source voltage VGS of two volts (2.0V); and transfer curve 1206 corresponds to a gate-to-source voltage VGS of five volts (5.0V).

[0080] Figure 13A A cross section 1300 in the XY plane is illustrated to simulate the transfer curve of a vertical GaN transistor 100 with a variable nearest neighbor distance D4.

[0081] Figure 13B The transfer curves 1301-1305 illustrate the total drain current (in amperes) versus the gate-to-source voltage VGS (in volts); and Figure 13C Additional transfer curves 1311-1315 are illustrated for the total drain current relative to the gate-to-source voltage VGS. Transfer curves 1301-1305 and 1311-1315 can be based on the use of Figure 13A Simulation of a 1300 cross-section. In Figure 13B In the figure, the total drain current (in amperes) is plotted on a linear scale; and in Figure 13C In the figure, the total drain current (in amperes) is plotted on a logarithmic scale. The drain-to-source voltage VDS can be one volt (1V).

[0082] Plotting amperes on a logarithmic scale can provide a graphical insight into the behavior of the subthreshold slope. The subthreshold slope relates to the behavior of the current (e.g., the total drain current) as a function of the gate-to-source voltage VGS; and during subthreshold operation (under subthreshold conditions), the drain current can be exponential, indicating barrier-dominated current flow.

[0083] Transfer curves 1301 and 1311 correspond to the nearest neighbor distance D4 of 1 micrometer (1µm). Transfer curves 1302 and 1312 correspond to the nearest neighbor distance D4 of 0.8 micrometers (0.8µm). Transfer curves 1303 and 1313 correspond to the nearest neighbor distance D4 of 0.6 micrometers (0.6µm). Transfer curves 1304 and 1314 correspond to the nearest neighbor distance D4 of 0.4 micrometers (0.4µm); and transfer curves 1305 and 1315 correspond to the nearest neighbor distance D4 of 0.2 micrometers (0.2µm).

[0084] Figure 14 A cross-sectional perspective view of a vertical GaN transistor 100 according to another embodiment is illustrated. Figure 14 The vertical GaN transistor 100 is similar to the vertical GaN transistor in Figure 1, except that the source layer includes a two-dimensional electron gas (2DEG). Figure 14 The surface of the GaN transistor 100 may include an aluminum gallium nitride (AlGaN) layer 1401; and similar to the case of a lateral GaN HEMT, the AlGaN layer 1401 may form an AlGaN-GaN interface, which generates a 2DEG. This 2DEG can advantageously provide a high-concentration source of n-type carriers (i.e., electrons).

[0085] also, Figure 14 The vertical GaN transistor 1400 has an N-GaN epitaxial layer 1414 instead of a channel epitaxial layer 114 and a drift epitaxial layer 113. The N-GaN epitaxial layer 1414 can be n-type and uniformly doped; and although Figure 14 The GaN transistor 100 is illustrated as having only an N-GaN epitaxial layer 1414 with uniform doping, but other doping distributions are possible. The N-GaN epitaxial layer 1414, comprising 2DEG and AlGaN, can form "GaN pillars" between cylindrical trench gates 105b, 106b, and 106c.

[0086] Figure 15A Examples of the same Figure 14 The corresponding two-dimensional (2D) cross-sectional view of the implementation scheme; and Figure 15B Examples of the same Figure 15AThe corresponding enlarged view of 2DEG 1530 is shown. This 2D cross-sectional view shows a cross-section of the vertical GaN transistor 100 in the XZ plane, as defined by the Cartesian axis 201. Coordinate values ​​in micrometers are marked on both the X and Z axes. Figure 15B As illustrated, 2DEG 1530 can be formed between AlGaN layer 1401 and N-GaN epitaxial layer 1414.

[0087] The sidewall thickness 305 can be the sidewall distance by which the gate dielectric 112 extends beyond the gate electrode 111. The gate dielectric 112 can be an oxide. The sidewall thickness 305 can be between 0.1 μm and 0.5 μm. The device pinch-off characteristics can be determined at least in part by the sidewall thickness 305 and the doping concentration of the N-GaN epitaxial layer 1414. The nearest neighbor distance D4 can be between 1 μm and 2 μm.

[0088] The breakdown voltage rating (e.g., the maximum drain-to-source voltage rating) can depend at least in part on the dielectric thickness 306. For example, a vertical GaN transistor 1400 with a dielectric thickness of 0.5 μm can have a breakdown voltage greater than 1,200 volts (1,200 V).

[0089] The N-GaN epitaxial layer 1414 can have a doping concentration of 10 to the power of 16 per cubic centimeter (1e16cm-3). The dicing line 1501 can correspond to an X-axis coordinate value of about 1.5 micrometers (1.5um).

[0090] Figure 15C Plot 1520 illustrates the electron density (in cubic centimeters (cm⁻³)) along the Z-axis at tangent line 1501. (See reference) Figure 15A The plot 1520 can be located at an X-axis coordinate value of 1.5 micrometers (1.5 μm). The Z-axis coordinate value can extend between negative and positive coordinate values ​​and pass through 2DEG 1530. The Z-axis coordinate zero (0) can define the position of the GaN substrate surface. For Z-axis coordinate values ​​less than zero (z<0), the electron density can be substantially equal to the n-type doping concentration of the GaN substrate. The doping concentration in the GaN substrate can be greater than one multiplied by 10 to the power of 19 per cubic centimeter (1e19cm-3). Except for 2DEG 1530 between the AlGaN layer 1401 and the N-GaN epitaxial layer 1414, the electron density can be substantially equal to the n-type doping concentration of the N-GaN epitaxial layer 1414; and the n-type doping concentration of the N-GaN epitaxial layer 1414 can be 10 to the power of 16 per cubic centimeter (1e16cm-3). The distance D15—the thickness of the N-GaN epitaxial layer—can be 12 micrometers (12 μm).

[0091] Figure 16 A transfer curve 1601 of the simulated drain current (in amperes) as a function of the gate-to-source voltage VGS (in volts) is illustrated. The applied drain-to-source voltage VDS can be one volt (1V). The dielectric 112 can be an oxide. The sidewall thickness 305 can be 0.1 micrometer (0.1µm). The doping concentration in the channel epitaxial layer 1414 can be 1e16cm⁻³ and can be n-type. The calculated specific on-resistance Rsp can be equal to 0.72 milliohms square centimeters (0.72 mohm-cm²); and the pinch-off voltage can be -6 volts (-6V). Therefore, the vertical GaN transistor 1400 can be a depletion-mode vertical GaN HEMT.

[0092] Figure 17 Examples are given based on Figure 16 The implementation scheme shows electron density transfer curves 1701-1705 along the Z-axis of the cut line 1501. The drain-to-source voltage VDS can be one volt (1V). Transfer curve 1701 corresponds to a gate-to-source voltage VGS of -30 volts (-30V). Transfer curve 1702 corresponds to a gate-to-source voltage VGS of -22 volts (-22V). Transfer curve 1703 corresponds to a gate-to-source voltage VGS of -13 volts (-13V). Transfer curve 1704 corresponds to a gate-to-source voltage VGS of -5 volts (-5V); and transfer curve 1705 corresponds to a gate-to-source voltage VGS of zero volts (0.0V).

[0093] Figure 18A Examples are given based on Figure 14 Another two-dimensional (2D) cross-sectional view of the implementation scheme. This 2D cross-sectional view is consistent with... Figure 15A Similar to the 2D cross-sectional view, except that it illustrates the electric field distribution for an applied 1,000-volt (1000V) drain-to-source voltage. The gate-to-source voltage VGS can be -30V (-30V). The unit can be volts per centimeter (V / cm) and according to electric field diagram 802. The dicing line 1801 can correspond to an X-axis coordinate value of approximately two micrometers, such that the dicing line 1801 passes through the dielectric 112; and the dielectric 112 can be an oxide.

[0094] Figure 18B A plot 1820 illustrates the electric field along the Z-axis (in volts per centimeter (V / cm)) based on cut line 1801. The applied drain-to-source voltage VDS can be one kilovolt (1000V). The electric field monotonically increases from the substrate surface where the Z-axis coordinate is zero (z=0) and is maximum within the gate dielectric 112.

[0095] The above description of the illustrative embodiments of this disclosure, including those described in the abstract, is not intended to be exhaustive or to limit the precise forms disclosed. For example, the application of vertical gallium nitride transistors can be extended to radio frequency (RF) and / or higher frequency applications; and while specific embodiments of vertical gallium nitride transistors have been described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of this disclosure. Indeed, it should be understood that specific example device cross-sections are provided for illustrative purposes, and other embodiments may be employed in accordance with the teachings herein. Furthermore, specific example voltage, current, frequency, power range values, time, etc., are provided for illustrative purposes, and other values ​​may be employed in other embodiments and embodiments in accordance with the teachings herein.

[0096] Throughout this specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean that a specific feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of this disclosure. Therefore, the phrases "in one embodiment," "an embodiment," "one example," or "an example" appearing throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Additionally, it should be understood that the accompanying drawings are for explanation purposes to those skilled in the art and are not necessarily drawn to scale.

[0097] The foregoing description may refer to elements or features as “connected,” “electrically connected,” and / or “coupled” together. As used herein, unless otherwise expressly stated, “connected” means that one element / feature is directly or indirectly connected to another element / feature, and is not necessarily mechanically connected. Similarly, unless otherwise expressly stated, “coupled” means that one element / feature is directly or indirectly coupled to another element / feature, and is not necessarily mechanically coupled.

[0098] Furthermore, the conditional language used herein, such as “can,” “could,” “might,” “may,” “e.g., for example,” “such as,” etc., unless otherwise specified or understood as such in the context in which they are used, is generally intended to convey that certain embodiments include certain features, elements, and / or states, while other embodiments do not. Therefore, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way, or that one or more embodiments necessarily include logic for determining whether such features, elements, and / or states are included or performed in any particular embodiment.

[0099] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel apparatus, methods, and systems described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure.

[0100] For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may use different components, materials, and / or semiconductor device layers to perform similar functions; and some elements may be removed, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of elements and actions of the various embodiments described above may be combined to provide other embodiments. Therefore, the scope of the invention is defined only by reference to the appended claims.

[0101] Although the claims presented herein are in a single dependent format for filing with the USPTO, it should be understood that any claim may be dependent on any prior claim of the same type, unless it is clearly not technically feasible.

Claims

1. A vertical gallium nitride (GaN) field-effect transistor (FET), comprising: GaN substrate; A GaN epitaxial (epi) layer grown on the GaN substrate; A source layer is formed on the surface of the GaN epitaxial layer; as well as Multiple cylindrical trench gates are arranged in a hexagonal array to form multiple vertical FET channels.

2. The vertical GaN FET of claim 1, wherein each of the plurality of cylindrical trench gates includes a gate electrode surrounded by a gate dielectric.

3. The vertical GaN FET of claim 2, wherein the gate electrode comprises polysilicon.

4. The vertical GaN FET of claim 2, wherein the gate dielectric comprises silicon dioxide.

5. The vertical GaN FET of claim 1, wherein the threshold voltage of the vertical GaN FET is determined at least in part based on the trench nearest neighbor distance.

6. The vertical GaN FET of claim 5, wherein the nearest neighbor distance of the trench is between two micrometers (2 μm) and 0.1 μm.

7. The vertical GaN FET of claim 6, wherein the vertical GaN FET is an enhancement-mode vertical GaN FET.

8. The vertical GaN FET of claim 6, wherein the vertical GaN FET is a depletion-mode vertical GaN FET.

9. The vertical GaN FET of claim 1, wherein the GaN epitaxial layer comprises: Drift zone; as well as The lightly doped epitaxial region extends from the source layer to the drift region.

10. The vertical GaN FET of claim 9, wherein the plurality of cylindrical trench gates extend into the lightly doped epitaxial region and extend above the drift region by a drift region to the bottom of the trench.

11. The vertical GaN FET of claim 9, wherein the GaN substrate is an n-type GaN substrate having a doping concentration between 10 to the power of 18 per cubic centimeter (1e18 cm⁻³) and 10 to the power of 20 per cubic centimeter (1e20 cm⁻³).

12. The vertical GaN FET of claim 9, wherein the drift region comprises a thickness between eight micrometers (8 μm) and ten micrometers (10 μm), and an n-type doping concentration between nine to the power of 15 per cubic centimeter (9e15 cm⁻³) and two to the power of 16 per cubic centimeter (2e16 cm⁻³).

13. The vertical GaN FET of claim 9, wherein the lightly doped epitaxial region comprises a thickness between one micrometer (1µm) and three micrometers (3µm), and an n-type doping concentration between one ten-fifteenth power per cubic centimeter (1e15 cm-3) and three ten-fifteenth power per cubic centimeter (3e15 cm-3).

14. The vertical GaN FET of claim 9, wherein the source layer comprises an n-type doping concentration between nine to the power of 17 per cubic centimeter (9e17 cm⁻³) and two to the power of 18 per cubic centimeter (2e18 cm⁻³).

15. The vertical GaN FET of claim 1, wherein the source layer comprises a two-dimensional electron gas (2DEG) formed between the surface aluminum gallium nitride (AlGaN) layer and the GaN epitaxial layer.

16. The vertical GaN FET of claim 15, wherein the vertical GaN FET is a depletion-mode vertical GaN FET.

17. The vertical GaN FET of claim 15, wherein the vertical GaN FET is an enhancement-mode vertical GaN FET.

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