Thin film transistor substrate and display device including the same

Abstract

The present disclosure provides a thin film transistor substrate and a display device including the same. The thin film transistor substrate includes a base substrate, and a first thin film transistor and a second thin film transistor disposed on the base substrate and connected in series with each other, wherein the first thin film transistor includes a first active layer having a first channel portion, a first gate electrode disposed to be spaced apart from and overlap the first active layer, and a first source electrode and a first drain electrode disposed to be in contact with the first active layer and spaced apart from each other, and the second thin film transistor includes a second active layer having a second channel portion, a second gate electrode disposed to be spaced apart from and overlap the second active layer, and a second source electrode and a second drain electrode disposed to be in contact with the second active layer and spaced apart from each other, wherein the first drain electrode and the second source electrode are integrally formed and disposed on the same layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0180322, filed on December 6, 2024, the entire contents of which are incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to a thin-film transistor substrate and a display device including the thin-film transistor substrate. Background Technology

[0004] Because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching or driving elements in display devices such as liquid crystal displays or organic light-emitting devices.

[0005] Based on the material constituting the active layer, thin-film transistors can be classified into amorphous silicon thin-film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin-film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin-film transistors in which oxide semiconductor is used as the active layer.

[0006] Thin-film transistors (TFTs) can degrade over time, and when TFTs degrade, the reliability of the TFT device may also deteriorate. When the reliability of the device deteriorates due to the degradation of the TFT, the image quality of the display device may also deteriorate.

[0007] Research is ongoing to improve the degradation of thin-film transistors.

[0008] Public content

[0009] One embodiment of this disclosure may provide a thin-film transistor substrate in which stress due to high drain bias is reduced by forming a wide channel region of the thin-film transistor to which a high potential voltage is applied.

[0010] One embodiment of this disclosure may provide a thin-film transistor substrate in which stress due to high drain bias is reduced by allowing the drain electrode of the thin-film transistor to have an area in the plane that is larger than that of the source electrode when a high potential voltage is applied.

[0011] One embodiment of this disclosure may provide a thin-film transistor substrate having a narrow bezel achieved by giving the drain and source electrodes of different thin-film transistors a circular structure that is shared by each other.

[0012] To address the aforementioned technical issues, one embodiment of this disclosure provides a thin-film transistor substrate, comprising: a substrate; and a first thin-film transistor and a second thin-film transistor disposed on the substrate and connected in series with each other. The first thin-film transistor includes: a first active layer having a first channel portion; a first gate electrode spaced apart from and overlapping the first active layer; and a first source electrode and a first drain electrode spaced apart from each other and contacting the first active layer. The second thin-film transistor includes: a second active layer having a second channel portion; a second gate electrode spaced apart from and overlapping the second active layer; and a second source electrode and a second drain electrode spaced apart from each other and contacting the second active layer. The second channel portion has a larger area in a plane than the first channel portion.

[0013] The first gate electrode can be formed in a U-shape, the second gate electrode can be formed in a U-shape rotated 180°, and the first gate electrode and the second gate electrode can be integrally formed into a ring.

[0014] The first drain electrode and the second source electrode are integrally formed, and the first drain electrode and the second source electrode can be disposed inside the first gate electrode and the second gate electrode integrally formed in the plane.

[0015] The first active layer includes a first source conductor portion disposed on one side of the first channel portion; and a first drain conductor portion disposed on the other side of the first channel portion; the second active layer includes a second source conductor portion disposed on one side of the second channel portion; and a second drain conductor portion disposed on the other side of the second channel portion; the first channel portion is formed in a U-shape, the second channel portion is formed in a U-shape rotated 180°, and an opening portion may be provided between the first channel portion and the second channel portion.

[0016] The first channel portion has a first length and a first width perpendicular to the first length and extending along the first channel portion, and the second channel portion has a second length and a second width perpendicular to the second length and extending along the second channel portion, and the second width may be longer than the first width.

[0017] The first length and the second length can be the same.

[0018] The first width may narrow in the plane from the first source conductor portion to the first drain conductor portion, and the second width may widen in the plane from the second source conductor portion to the second drain conductor portion.

[0019] The first source electrode is formed in a U-shape, the second drain electrode is formed in a U-shape rotated 180°, and the second drain electrode has a larger area in the plane than the second source electrode, and an opening may be provided between the first source electrode and the second drain electrode.

[0020] The second drain electrode can have a larger area in the plane than the first source electrode, and the first source electrode can have a larger area in the plane than the first drain electrode.

[0021] The first gate electrode and the second gate electrode can be integrally formed in a plane as one of a circular ring, an elliptical ring, and a rectangular ring with rounded corners, and each edge of the inner surface of the first source electrode and the inner surface of the second drain electrode can have a rounded shape in the plane.

[0022] The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode can be disposed on the same layer.

[0023] The first active layer can be disposed between the substrate and the first gate electrode, and the second active layer can be disposed between the substrate and the second gate electrode.

[0024] The first thin-film transistor may be disposed in a first light-blocking layer between the substrate and the first active layer, and the second thin-film transistor may include a second light-blocking layer disposed between the substrate and the second active layer.

[0025] The first photoresist layer and the second photoresist layer can each be a gate electrode.

[0026] The first gate electrode can be disposed between the substrate and the first active layer, and the second gate electrode can be disposed between the substrate and the second active layer.

[0027] Another embodiment of this disclosure may provide a display device including a thin-film transistor.

[0028] The display device includes a gate driver having multiple stages, each stage driving multiple gate lines and pixel driving circuits. Each of the multiple stages includes: an output unit including a pull-up transistor controlled by a first node (hereinafter referred to as a Q node) to pull up and output a first clock signal input through a first clock terminal of a plurality of clocks to an output terminal, and a pull-down transistor controlled by a second node (hereinafter referred to as a QB node) to pull down the output terminal; and a control unit that charges and discharges the Q node and the QB node opposite to the Q node, wherein the control unit includes a QB charging transistor that charges the QB node with a high potential voltage, and the QB charging transistor includes a first QB charging transistor and a second QB charging transistor, wherein the high potential voltage is applied to the drain electrode of the first QB charging transistor and the source electrode of the second QB charging transistor is connected to the QB node, and the first QB charging transistor may be a second thin-film transistor and the second QB charging transistor may be a first thin-film transistor.

[0029] The control unit includes: a Q discharge transistor that discharges the Q node to a gate cutoff voltage under the control of the QB node, and the Q discharge transistor includes a third thin-film transistor and a fourth thin-film transistor connected in series with each other, and the third thin-film transistor includes a third active layer having a third channel portion; a third gate electrode that is spaced apart from and overlaps with the third active layer; a third source electrode and a fourth drain electrode that are contacted with and spaced apart from each other in the third active layer, and the fourth thin-film transistor includes a fourth active layer having a fourth channel portion; a fourth gate electrode that is spaced apart from and overlaps with the fourth active layer; and a fourth source electrode and a fourth drain electrode that are contacted with and spaced apart from each other in the fourth active layer, the third gate electrode and the fourth gate electrode being integrally formed and disposed on the same layer, the third drain electrode and the fourth source electrode being integrally formed, and the third channel portion having the same area in the plane as the fourth channel portion. Attached Figure Description

[0030] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 This is a plan view of a thin-film transistor substrate according to an embodiment of the present disclosure.

[0032] Figure 2 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0033] Figure 3This is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure.

[0034] Figure 4 This is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure.

[0035] Figure 5 This is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure.

[0036] Figures 6A to 6D This is a plan view of a thin-film transistor substrate according to another embodiment of the present disclosure.

[0037] Figure 7 This is a schematic diagram of a display device according to another embodiment of the present disclosure.

[0038] Figure 8 This is a block diagram schematically showing some stages of a gate driver according to the present disclosure.

[0039] Figure 9 This is a circuit diagram showing the configuration of each level according to this disclosure.

[0040] Figure 10 yes Figure 7 A circuit diagram for one pixel. Detailed Implementation

[0041] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the embodiments described below with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0042] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it would unnecessarily obscure important points of this disclosure.

[0043] When using the terms “comprising,” “having,” and “including” as described in this disclosure, an additional part may be added unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0044] When interpreting an element, although not explicitly described, the element is interpreted as including a fault-tolerant region.

[0045] When describing positional relationships, such as when the positional relationship is described as "on top of," "above," "below," and "beside," one or more parts can be placed between two other parts unless "exactly" or "directly" is used.

[0046] This document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to readily describe the relationship between one or more elements as shown in the figures and one or more other elements. It should be understood that these terms are intended to cover different orientations of the device in addition to those depicted in the figures. For example, if the device shown in the figures is inverted, a device described as being arranged “below” or “under” another device may be arranged “above” another device. Thus, the exemplary term “below or under” can include both “below or under” and “upper” orientations. Similarly, the exemplary term “upper” or “upper” can include both “upper” and “below or under” orientations.

[0047] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “only” or “directly” is used.

[0048] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0049] It should be understood that the term "at least one" includes all combinations relating to any one of them. For example, "at least one of the first element, the second element, and the third element" can include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0050] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate differently and be technically driven by each other. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0051] When adding reference numerals to components in each of the figures describing embodiments of this disclosure, the same components may have the same symbols that may be shown in other figures.

[0052] In the embodiments of this disclosure, for ease of description, the source electrode and the drain electrode are distinguished, and the source electrode and the drain electrode are interchangeable. The source electrode can be the drain electrode, and vice versa. Furthermore, in another embodiment, the source electrode of any embodiment can be the drain electrode, and in yet another embodiment, the drain electrode of any embodiment can be the source electrode.

[0053] In some embodiments of this disclosure, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode; however, the embodiments of this disclosure are not limited thereto. The source region can be a source electrode, and the drain region can be a drain electrode. Furthermore, the source region can be a drain electrode, and the drain region can be a source electrode.

[0054] Figure 1 This is a plan view of a thin-film transistor substrate 100 according to an embodiment of the present disclosure. Figure 2 It is along Figure 1 The cross-sectional view taken from line I-I'. Figure 3 This is a cross-sectional view of a thin-film transistor substrate 200 according to another embodiment of the present disclosure. Figure 4 This is a cross-sectional view of a thin-film transistor substrate 300 according to another embodiment of the present disclosure. Figure 5 This is a cross-sectional view of a thin-film transistor substrate 400 according to another embodiment of the present disclosure.

[0055] A thin-film transistor substrate 100 according to an embodiment of the present disclosure is disposed on a substrate 110.

[0056] According to one embodiment of the present disclosure, a thin-film transistor substrate 100 may include a first thin-film transistor T11 and a second thin-film transistor T12 connected in series with each other.

[0057] According to one embodiment of the present disclosure, a first thin-film transistor T11 includes a first active layer 131, a first gate electrode 151, a first source electrode 171, and a first drain electrode 172. A second thin-film transistor T12 includes a second active layer 132, a second gate electrode 152, a second source electrode 173, and a second drain electrode 174.

[0058] The components of the first thin-film transistor T11 and the second thin-film transistor T12 are described in detail below.

[0059] Glass or plastic can be used as the substrate 110. Transparent plastics with flexible properties, such as polyimide, can be used as the plastic.

[0060] The first light-blocking layer 105 and the second light-blocking layer 106 can be disposed on the substrate 110 (see [reference]). Figure 4The first light-blocking layer 105 and the second light-blocking layer 106 block light incident from the substrate 110 to protect the first active layer 131 and the second active layer 132. If another structure is used as the light blocker, the first light-blocking layer 105 and the second light-blocking layer 106 can be omitted.

[0061] According to one embodiment of this disclosure, the first light-blocking layer 105 may have a closed-loop shape and overlap with the first gate electrode 151. Additionally, the second light-blocking layer 106 may have a closed-loop shape and overlap with the second gate electrode 152.

[0062] According to one embodiment of the present disclosure, the buffer layer 120 may be disposed on the substrate 110.

[0063] The buffer layer 120 has insulating properties and protects the first active layer 131 and the second active layer 132. The buffer layer 120 may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and a metal oxide with insulating properties.

[0064] exist Figures 2 to 5 In this embodiment, the buffer layer 120 is shown as a single layer, but the embodiments of this disclosure are not limited thereto and may have multiple layers. In addition, another layer may be disposed between the substrate 110 and the buffer layer 120, and another layer may be disposed between the buffer layer 120 and the first active layer 131 and the second active layer 132.

[0065] According to one embodiment of this disclosure, a first active layer 131 and a second active layer 132 are disposed on a buffer layer 120.

[0066] The first active layer 131 includes a first channel portion 131n, a first source conductor portion 131a disposed on one side of the first channel portion 131n, and a first drain conductor portion 131b disposed on the other side of the first channel portion 131n. The second active layer 132 includes a second channel portion 132n, a second source conductor portion 132a disposed on one side of the second channel portion 132n, and a second drain conductor portion 132b disposed on the other side of the second channel portion 132n.

[0067] For example, a first channel portion 131n is disposed between a first source conductor portion 131a and a first drain conductor portion 131b, and a second channel portion 132n is disposed between a second source conductor portion 132a and a second drain conductor portion 132b.

[0068] The first active layer 131 may further include a first source connection portion 131c disposed between the first channel portion 131n and the first source conductor portion 131a, and a first drain connection portion 131d disposed between the first channel portion 131n and the first drain conductor portion 131b.

[0069] The second active layer 132 may further include a second source connection portion 132c disposed between the second channel portion 132n and the second source conductor portion 132a, and a second drain connection portion 132d disposed between the second channel portion 132n and the second drain conductor portion 132b.

[0070] The first active layer 131 and the second active layer 132 may include oxide semiconductor materials.

[0071] The oxide semiconductor material may include at least one of, for example, IZO (InZnO)-based oxide semiconductor materials, IGO (InGaO)-based oxide semiconductor materials, ITO (InSnO)-based oxide semiconductor materials, IGZO (InGaZnO)-based oxide semiconductor materials, IGZTO (InGaZnSnO)-based oxide semiconductor materials, GZTO (GaZnSnO)-based oxide semiconductor materials, GZO (GaZnO)-based oxide semiconductor materials, ITZO (InSnZnO)-based oxide semiconductor materials, and FIZO (FeInZnO)-based oxide semiconductor materials. However, the embodiments of this disclosure are not limited thereto, and the first active layer 131 and the second active layer 132 may be formed of other oxide semiconductor materials known in the art.

[0072] The first source connection portion 131c and the first drain connection portion 131d of the first active layer 131 can be formed by selectively conductiveizing the first active layer 131 made of semiconductor material. According to one embodiment of this disclosure, selective conductiveizing means imparting conductivity to specific portions of the first active layer 131, enabling it to function as a conductor. The second source connection portion 132c and the second drain connection portion 132d of the second active layer 132 can also be formed by selectively conductiveizing the second active layer 132 made of semiconductor material.

[0073] For example, the first active layer 131 and the second active layer 132 can be selectively conductiveized by ion doping. As a result, a first source connection portion 131c, a first drain connection portion 131d, a second source connection portion 132c, and a second drain connection portion 132d can be formed. However, the embodiments of this disclosure are not limited thereto, and the first active layer 131 and the second active layer 132 can also be selectively conductiveized by other methods known in the art.

[0074] The first source connection portion 131c, the first drain connection portion 131d, the second source connection portion 132c, and the second drain connection portion 132d do not overlap with the first gate electrode 151 and the second gate electrode 152. Compared with the first channel portion 131n and the second channel portion 132n, the first source connection portion 131c, the first drain connection portion 131d, the second source connection portion 132c, and the second drain connection portion 132d have excellent conductivity and high mobility. Therefore, the first source connection portion 131c, the first drain connection portion 131d, the second source connection portion 132c, and the second drain connection portion 132d can all be used as wiring.

[0075] According to one embodiment of this disclosure, the first drain conductor portion 131b and the second source conductor portion 132a can be integrally formed.

[0076] The first active layer 131 and the second active layer 132 can have a multi-layer structure.

[0077] According to one embodiment of this disclosure, the first thin-film transistor T11 may further include a first source electrode 171 and a first drain electrode 172, which are configured to contact the first active layer 131 and spaced apart from each other. Furthermore, the second thin-film transistor T12 may include a second source electrode 173 and a second drain electrode 174, which are configured to contact the second active layer 132 and spaced apart from each other.

[0078] For example, the first source electrode 171 and the first drain electrode 172 are spaced apart from each other and are in contact with the first source conductor portion 131a and the first drain conductor portion 131b of the first active layer 131, respectively. The second source electrode 173 and the second drain electrode 174 are spaced apart from each other and are in contact with the second source conductor portion 132a and the second drain conductor portion 132b of the second active layer 132, respectively.

[0079] According to one embodiment of the present disclosure, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 may each include at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), and barium (Ba).

[0080] The first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 can be reducible. The first active layer 131 can be selectively conductive by the first source electrode 171 and the first drain electrode 172. The second active layer 132 can be selectively conductive by the second source electrode 173 and the second drain electrode 174. According to one embodiment of this disclosure, the first source conductive portion 131a and the first drain conductive portion 131b are in contact with the first source electrode 171 and the first drain electrode 172, respectively. The regions of the first active layer 131 in contact with the first source electrode 171 and the first drain electrode 172 can be conductively conductive to form the first source conductive portion 131a and the first drain conductive portion 131b, respectively.

[0081] Specifically, according to one embodiment of this disclosure, the portions of the first active layer 131 that contact the first source electrode 171 and the first drain electrode 172 can be reduced respectively to generate a first source conductor portion 131a and a first drain conductor portion 131b. Furthermore, the portions of the second active layer 132 that contact the second source electrode 173 and the second drain electrode 174 can be reduced respectively to generate a second source conductor portion 132a and a second drain conductor portion 132b.

[0082] For example, when the portion of the first active layer 131 and the second active layer 132 that contacts and overlaps with the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 decreases, oxygen vacancies are generated in the first active layer 131 and the second active layer 132, and therefore, the first active layer 131 and the second active layer 132 can be selectively conductive. Through this selective reduction of the first active layer 131 and the second active layer 132, a first source conductor portion 131a, a first drain conductor portion 131b, a second source conductor portion 132a, and a second drain conductor portion 132b can be created.

[0083] Generally, dual-gate structures have been used to overcome the stress of applying high drain bias voltages inside transistors. Specifically, dual-gate structures with two gates connected in series have been used to distribute voltage.

[0084] In a dual-gate structure with two gates connected in series, the voltage applied to each gate may not always be equal. For example, a high voltage may be applied to the gate of the transistor with the higher voltage applied. In other words, the electric field may concentrate in the active layer of the transistor with the higher voltage applied, leading to degradation. Specifically, the electric field may concentrate in the drain region of the active layer of the transistor with the higher voltage applied, leading to degradation.

[0085] According to one embodiment of this disclosure, in order to prevent degradation concentration on the drain region of the transistor to which a high potential voltage is applied, the second drain electrode 174 may have a larger area in the plane than the second source electrode 173. In this case, a high potential voltage is applied to the second thin-film transistor T12.

[0086] Specifically, the second drain electrode 174 of the second thin-film transistor T12, to which a high potential voltage is applied, can be formed to be relatively wider than the second source electrode 173, thereby reducing the voltage applied to the second gate electrode 152 of the second thin-film transistor T12. As a result, the electric field effect concentrated on the second drain conductor portion 132b and the second drain connection portion 132d of the second active layer 132 can be reduced, and the degradation of the second thin-film transistor T12 can be prevented or suppressed.

[0087] According to one embodiment of this disclosure, the first source electrode 171 of the first thin-film transistor T11 may have a larger area in a plane than the first drain electrode 172. Specifically, the first drain electrode 172 of the first thin-film transistor T11 may be formed to be relatively narrower than the first source electrode 171 to increase the voltage applied to the first gate electrode 151 of the first thin-film transistor T11. As a result, the voltage applied to the second gate electrode 152 of the second thin-film transistor T12 can be reduced by the amount of increase in voltage applied to the first gate electrode 151 of the first thin-film transistor T11.

[0088] This reduces the electric field effect concentrated on the second drain conductor portion 132b and the second drain connection portion 132d of the second active layer 132, and prevents or suppresses the degradation of the second thin film transistor T12.

[0089] According to one embodiment of this disclosure, the first drain electrode 172 and the second source electrode 173 are integrally formed. Specifically, the first drain electrode 172 and the second source electrode 173 may have a circular shape.

[0090] According to one embodiment of this disclosure, since the first drain electrode 172 and the second source electrode 173 are integrally formed, the area occupied by the thin-film transistor substrate 100 can be reduced. For example, when the thin-film transistor substrate 100 according to one embodiment of this disclosure is provided in the gate driver of a display device, the display device of this disclosure can achieve a narrow bezel.

[0091] According to one embodiment of this disclosure, the first source electrode 171 can be formed in a U-shape, and the second drain electrode 174 can be formed in a U-shape rotated 180°. For example, the second drain electrode 174 can have a U-shape rotated 180°. In this case, the second drain electrode 174 can have a larger area in the plane compared to the first source electrode 171.

[0092] According to one embodiment of this disclosure, the first thin-film transistor T11 may further include a first gate electrode 151, which is configured to be spaced apart from and overlap with the first active layer 131. The second thin-film transistor T12 may further include a second gate electrode 152, which is configured to be spaced apart from and overlap with the second active layer 132.

[0093] The first gate electrode 151 and the second gate electrode 152 may each comprise at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). Although not shown in the figure, the first gate electrode 151 and the second gate electrode 152 may also have a multilayer film structure comprising two conductive films with different physical properties.

[0094] According to one embodiment of this disclosure, the first gate electrode 151 may be formed in a U-shape. The second gate electrode 152 may be formed in a U-shape rotated 180°.

[0095] refer to Figure 1 The first gate electrode 151 and the second gate electrode 152 can be integrally formed into the gate electrode 150. For example, the gate electrode 150 may include the first gate electrode 151 and the second gate electrode 152. The gate electrode 150 may have a ring shape. For example, the gate electrode 150 may have a circular or elliptical ring shape. For example, the gate electrode 150 may have a closed-loop shape. For example, the first gate electrode 151 and the second gate electrode 152 can be integrally formed into a closed-loop shape.

[0096] refer to Figure 1 The first gate electrode 151 refers to the region in the plane that overlaps with the first active layer 131. Similarly, the second gate electrode 152 refers to the region in the plane that overlaps with the second active layer 132. In this case, the gate electrode 150 may include a connection portion that does not overlap with the first active layer 131 or the second active layer 132.

[0097] For example, the region of the gate electrode 150 that overlaps with the first active layer 131 can be called the first gate electrode 151, and the region that overlaps with the second active layer 132 can be called the second gate electrode 152.

[0098] According to one embodiment of this disclosure, the second gate electrode 152 may have a larger area than the first gate electrode 151. When the area of ​​the second gate electrode 152 of the second thin-film transistor T12 is larger than the area of ​​the first gate electrode 151 of the first thin-film transistor T11, electric field concentration on the second active layer 132 of the second thin-film transistor T12 can be prevented. Therefore, degradation of the thin-film transistor substrate 100 according to this disclosure can be prevented.

[0099] According to one embodiment of this disclosure, a first drain electrode 172 and a second source electrode 173 are disposed inside the first gate electrode 151 and the second gate electrode 152 integrally formed in a plane. For example, the first drain electrode 172 and the second source electrode 173 are disposed inside the first gate electrode 151 and the second gate electrode 152 integrally formed in a plane.

[0100] Since the first drain electrode 172 and the second source electrode 173 are disposed inside the first gate electrode 151 and the second gate electrode 152 which are formed integrally, the area occupied by the thin-film transistor substrate 100 can be reduced. For example, when the thin-film transistor substrate 100 according to an embodiment of the present disclosure is disposed in the gate driver of a display device, the display device of the present disclosure can achieve a narrow bezel.

[0101] According to one embodiment of this disclosure, the second channel portion 132n may have a larger area in the plane than the first channel portion 131n. For example, when the area of ​​the second channel portion 132n is larger than the area of ​​the first channel portion 131n, the resistance in the second channel portion 132n can be reduced compared to the resistance in the first channel portion 131n, thereby reducing the occurrence of degradation of the second thin-film transistor T12.

[0102] For example, refer to Figure 1 The first channel portion 131n may have a first length L1 and a first width W1 perpendicular to the first length L1 and extending along the first channel portion 131n. The second channel portion 132n may have a second length L2 and a second width W2 perpendicular to the second length L2 and extending along the second channel portion 132n. In this case, the second width W2 of the second channel portion 132n may be longer than the first width W1 of the first channel portion 131n.

[0103] According to this disclosure, the first length L1 can be the shortest length between the first source connection portion 131c and the first drain connection portion 131d. For example, when the first source connection portion 131c and the first drain connection portion 131d are not present, it can be the shortest length between the first source conductor portion 131a and the first drain conductor portion 131b. A description of the second length L2 according to this disclosure is omitted because it overlaps with the first length L1.

[0104] According to this disclosure, the first width W1 can be the length of a region perpendicular to the first length L1 and extending along the first channel portion 131n. A description of the second width W2 according to this disclosure is omitted because it overlaps with the first width W1.

[0105] According to one embodiment of this disclosure, the first length L1 and the second length L2 may be equal.

[0106] According to one embodiment of this disclosure, the first width W1 may narrow in the plane toward the first drain conductor portion 131b. The second width W2 may widen in the plane toward the second drain conductor portion 132b. For example, the first width W1 may become shorter as it moves away from or closer to the first source conductor portion 131a. For example, the second width W2 may become longer as it moves away from or closer to the second source conductor portion 132a.

[0107] The electric field is concentrated on the second drain conductor portion 132b where a relatively high voltage is applied. Physical or electrical degradation may occur in the region where this electric field concentration occurs. The electric field concentration in the second drain conductor portion 132b can be mitigated when the second width W2 widens in the plane toward the second drain conductor portion 132b.

[0108] According to one embodiment of this disclosure, the first channel portion 131n may be formed in a U-shape. The second channel portion 132n may be formed in a U-shape rotated 180°. The first channel portion 131n overlaps with the first gate electrode 151 in a plane, and the second channel portion 132n overlaps with the second gate electrode 152 in a plane.

[0109] According to one embodiment of this disclosure, an opening portion OP1, OP2 may be provided therebetween the first channel portion 131n and the second channel portion 132n. Specifically, the opening portions OP1, OP2 include a first opening portion OP1 and a second opening portion OP2. The first opening portion OP1 and the second opening portion OP2 are spaced apart from each other, and a first drain electrode 172 and a second source electrode 173 are provided therebetween. Figure 1 The illustration shows a configuration where the first opening portion OP1 and the second opening portion OP2 are not parallel to each other and are symmetrical to each other, with the first drain electrode 172 and the second source electrode 173 located between them. However, embodiments of this disclosure are not limited to this, and the first opening portion OP1 and the second opening portion OP2 may be parallel to each other and symmetrical to each other, with the first drain electrode 172 and the second source electrode 173 located between them (see [link to documentation]). Figure 6C For example, the first opening portion OP1 and the second opening portion OP2 can be respectively set on the same line.

[0110] According to one embodiment of the present disclosure, a first source electrode 171 and a second drain electrode 174 are disposed in a plane and have a common area (such as openings OP1, OP2) between them.

[0111] According to one embodiment of this disclosure, a gate insulating film 140 is disposed on a first active layer 131 and a second active layer 132. Specifically, the gate insulating film 140 is disposed between the first active layer 131 and the first gate electrode 151, and between the second active layer 132 and the second gate electrode 152. However, the embodiments of this disclosure are not limited thereto, and in the case of a bottom gate structure in which the first gate electrode 151a is disposed between the substrate 110 and the first active layer 133 and the second gate electrode 152a is disposed between the substrate 110 and the second active layer 134, the gate insulating film 140a may be disposed on the first gate electrode 151a and the second gate electrode 152a (see [link to relevant documentation]). Figure 5 ).

[0112] According to one embodiment of this disclosure, the gate insulating film 140 may cover the entire upper surface of the first active layer 131 and the second active layer 132. Figure 2 The diagram shows a gate insulating film 140 covering the entire upper surface of the first active layer 131 and the second active layer 132. However, embodiments of this disclosure are not limited thereto, and the gate insulating film 140 may expose a portion of the upper surface of the first active layer 131 and the second active layer 132. For example, the first gate insulating film 141 and the second gate insulating film 142 may expose the first source connection portion 131c, the first drain connection portion 131d, the second source connection portion 132c, and the second drain connection portion 132d (see [link to documentation]). Figure 3 ).

[0113] The gate insulating film 140 may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 may have a single film structure or a multilayer film structure. The gate insulating film 140 protects the first active layer 131 and the second active layer 132.

[0114] According to one embodiment of this disclosure, the first gate electrode 151 and the second gate electrode 152 may be disposed on the gate insulating film 140. However, embodiments of this disclosure are not limited thereto, and in the case of a bottom gate structure, the first active layer 133 and the second active layer 134 may be disposed on the gate insulating film 140a (see [link to relevant documentation]). Figure 5 ).

[0115] An interlayer insulating film 160 is disposed on the first gate electrode 151 and the second gate electrode 152. The interlayer insulating film 160 is an insulating layer made of insulating material. Specifically, the interlayer insulating film 160 may be made of organic material, inorganic material, or a laminate of organic material layers and inorganic material layers.

[0116] According to one embodiment of this disclosure, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 can be disposed on the same layer. For example, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 can be disposed on the first active layer 131 and the second active layer 132, respectively. For example, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 can be disposed on a different layer than the first gate electrode 151 and the second gate electrode 152.

[0117] According to one embodiment of this disclosure, the first thin-film transistor T11 may further include a first light-blocking layer 105 disposed between the substrate 110 and the first active layer 131. The second thin-film transistor T12 may further include a second light-blocking layer 106 disposed between the substrate 110 and the second active layer 132.

[0118] For example, refer to Figure 4 In the top gate structure, a first active layer 131 is disposed between the substrate 110 and the first gate electrode 151, and a second active layer 132 is disposed between the substrate 110 and the second gate electrode 152. A first light-blocking layer 105 and a second light-blocking layer 106 can be disposed on the substrate 110. The first light-blocking layer 105 and the second light-blocking layer 106 can respectively protect the first channel portion 131n and the second channel portion 132n from external influences.

[0119] According to one embodiment of this disclosure, the first light-blocking layer 105 and the second light-blocking layer 106 can each be a gate electrode. For example, the first light-blocking layer 105 and the second light-blocking layer 106 can be used as lower gate electrodes. In this case, the first light-blocking layer 105 can be electrically connected to the first gate electrode 151, and the second light-blocking layer 106 can be electrically connected to the second gate electrode 152. In other words, the first thin-film transistor T11 and the second thin-film transistor T12 can each have a dual-gate structure.

[0120] refer to Figure 5The first thin-film transistor T11 may include a first active layer 133 and a first gate electrode 151a, and the second thin-film transistor T12 may include a second active layer 134 and a second gate electrode 152a. The first active layer 133 includes a first channel portion 133n, a first source conductor portion 133a disposed on one side of the first channel portion 133n, and a first drain conductor portion 133b disposed on the other side of the first channel portion 133n. The second active layer 134 includes a second channel portion 134n, a second source conductor portion 134a disposed on one side of the second channel portion 134n, and a second drain conductor portion 134b disposed on the other side of the second channel portion 134n. Figure 5 The first channel portion 133n, the first source conductor portion 133a, the first drain conductor portion 133b, the second channel portion 134n, the second source conductor portion 134a, and the second drain conductor portion 134b shown can respectively correspond to Figure 2 The diagram shows a first channel portion 131n, a first source conductor portion 131a, a first drain conductor portion 131b, a second channel portion 132n, a second source conductor portion 132a, and a second drain conductor portion 132b. Furthermore, Figure 5 The first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 shown correspond to respectively Figure 2 The first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 are shown.

[0121] Figures 6A to 6D This is a plan view of thin-film transistor substrates 500, 600, 700, and 800 according to another embodiment of the present disclosure.

[0122] According to one embodiment of this disclosure, the first gate electrode 151 and the second gate electrode 152 can be integrally formed in a plane as any one of a circular ring, an elliptical ring, and a square ring with rounded corners. For example, the gate electrode 150 formed by the first gate electrode 151 and the second gate electrode 152 can be formed as any one of a circular ring, an elliptical ring, and a square ring with rounded corners.

[0123] exist Figure 1 In the diagram, the first gate electrode 151 and the second gate electrode 152 are shown as integrally formed rectangular rings with rounded vertices. Figures 6A to 6C In the diagram, the first gate electrode 151 and the second gate electrode 152 are shown as an integrally formed elliptical ring.

[0124] When the first gate electrode 151 and the second gate electrode 152 are integrally formed into a polygonal ring shape, the lengths of the first channel portion 131n and the second channel portion 132n can be increased at the vertices of the polygon. As a result, the electric field can be concentrated at the vertices of the first gate electrode 151 and the second gate electrode 152, which may lead to degradation problems at the vertices of the first gate electrode 151 and the second gate electrode 152.

[0125] According to one embodiment of this disclosure, the first source electrode 171 may have an inner surface 171a and an outer surface 171b. Additionally, the second drain electrode 174 may have an inner surface 174a and an outer surface 174b.

[0126] According to one embodiment of this disclosure, each edge of the inner surface 171a of the first source electrode 171 and the inner surface 174a of the second drain electrode 174 may have a rounded shape or a curved shape in a plane. In this disclosure, the inner surface may refer to the side surface facing the gate electrode 150 in a plane.

[0127] refer to Figures 6A to 6C Each edge of the inner surface 171a of the first source electrode 171 and the inner surface 174a of the second drain electrode 174 can have a rounded shape. For example, even if the first gate electrode 151 and the second gate electrode 152 are integrally formed into a ring shape, if each edge of the inner surface 171a of the first source electrode 171 and the inner surface 174a of the second drain electrode 174 has a specific angle, the length of the conductive region may become longer in the region with the specific angle, and an increase in resistance may occur.

[0128] However, the outer surface 171b of the first source electrode 171 and the outer surface 174b of the second drain electrode 174 may each have a rounded shape or a specific angle.

[0129] For example, Figure 6A and 6C The outer surface 171b of the first source electrode 171 and the outer surface 174b of the second drain electrode 174 are shown to each have a rounded shape.

[0130] For example, Figure 6B An example is shown where the outer surface 171b of the first source electrode 171 and the outer surface 174b of the second drain electrode 174 have a vertical angle.

[0131] refer to Figure 6D The thin-film transistor substrate 800 may include a third thin-film transistor T13 and a fourth thin-film transistor T14 connected in series with each other.

[0132] The third thin-film transistor T13 includes a third active layer 231 having a third channel portion 231n, a third gate electrode 251 spaced apart from and overlapping the third active layer 231, and a third source electrode 271 and a third drain electrode 272 spaced apart from each other and in contact with the third active layer 231.

[0133] The fourth thin-film transistor T14 includes: a fourth active layer 232 having a fourth channel portion 232n; a fourth gate electrode 252 spaced apart from and overlapping the fourth active layer 232; and a fourth source electrode 273 and a fourth drain electrode 274 in contact with the fourth active layer 232 and spaced apart from each other.

[0134] According to Figure 6D In the thin-film transistor substrate 800, and according to Figure 1 Compared to the thin-film transistor substrate 100, the third channel portion 231n can have the same area in the plane as the fourth channel portion 232n, the third source electrode 271 and the fourth drain electrode 274 can have the same area in the plane, and the third gate electrode 251 and the fourth gate electrode 252 can have the same area in the plane.

[0135] In a planar view, the third source electrode 271 may have the same area as the fourth drain electrode 274. For example, in a planar view, the third gate electrode 251 and the fourth gate electrode 252 may have the same area. Similarly, in a planar view, the third active layer 231 and the fourth active layer 232 may have the same area.

[0136] Figure 7 This is a schematic diagram of a display device 1000 according to another embodiment of the present disclosure. Figure 8 This is a block diagram schematically showing some stages of the gate driver 320 according to the present disclosure. Figure 9 This is a circuit diagram showing the configuration of each STn stage according to this disclosure. Figure 10 yes Figure 7 A circuit diagram for a pixel P.

[0137] refer to Figure 7 The display device 1000 may include a display panel 310, a gate driver 320 (e.g., a GIP-type gate driver), a data driver 330, a timing controller 340, a level shifter 360, a gamma voltage generator 370, a power management circuit 350, etc.

[0138] The power management circuit 350 can generate and output various drive voltages required for the operation of all components of the display device 1000, such as the display panel 310, gate driver 320, data driver 330, timing controller 340, level shifter 360, gamma voltage generator 370, etc., by using an input voltage supplied from an external source.

[0139] The timing controller 340 can receive image data and synchronization signals from an external host system. The timing controller 340 can perform various image processing operations on the image data, such as brightness correction for power reduction or image quality correction, and provide the processed image data to the data driver 330. The timing controller 340 can generate multiple data control signals using the synchronization signal and internally stored timing settings (start timing, pulse width, etc.), and provide the generated data to the data driver 330. It also generates multiple control signals and provides them to the level shifter 360.

[0140] The gamma voltage generator 370 can generate a set of reference gamma voltages including multiple reference gamma voltages with different voltage levels and supply the set to the data driver 330.

[0141] The data driver 330 is controlled according to the data control signal provided by the timing controller 340, converting the digital data provided by the timing controller 340 into analog data signals, and providing the corresponding data signals to each data line of the display panel 310.

[0142] The level shifter 360 can generate multiple gate control signals based on multiple control signals supplied from the timing controller 340 and supply them to the gate driver 320. The level shifter 360 can level shift start signals, reset signals, etc. supplied from the timing controller 340 and supply them to the gate driver 320.

[0143] The display panel 310 displays an image through the display area AA, where the pixels P are arranged in a matrix. Each pixel P can be composed of a combination of red (R) sub-pixels that emit red light, green (G) sub-pixels that emit green light, blue (B) sub-pixels that emit blue light, and white (W) sub-pixels that emit white light.

[0144] The gate driver 320 consists of thin-film transistors disposed in the display area AA of the display panel 310, and can be disposed in the GIP (Gate In-Panel) type in the bezel area on one or both sides of the display panel 310. Specifically, in the GIP type, the gate driver 320 can be disposed on the substrate 110.

[0145] Gate driver 320 can receive multiple gate control signals from level shifter 360 and perform shift operations to individually drive the gate lines GL of display panel 310. Gate driver 320 is configured as a shift register with multiple stages that are cascaded together to generate individual gate outputs so as to individually drive multiple gate lines GL.

[0146] For convenience, Figure 8 The diagram only schematically illustrates the three stages STn-1, STn, STn+1 (where n is a natural number) that generate three gate outputs OUTn-1, OUTn, and OUTn+1 in the multiple stages constituting the gate driver 320.

[0147] Each stage STn can be provided with at least one of a plurality of clock signals CLK with different phases. Each stage STn can output an input clock pulse as a scan pulse for the gate output OUTn in response to either a start signal or the output (set signal) of the preceding stage. Each stage STn can output the gate cutoff voltage for the gate output OUTn in response to either a reset signal or the output (reset signal) of the succeeding stage. The gate output OUTn or carry output of each stage STn can be used as a carry signal and supplied to another stage as a set signal or a reset signal. A preceding stage refers to any stage that outputs a scan pulse before (above) or before the corresponding stage, and a succeeding stage refers to any stage that outputs a scan pulse after (below) or after the corresponding stage.

[0148] A display device 1000 according to one embodiment of the present disclosure may include the aforementioned thin-film transistor substrates 100, 200, 300, 400, 500, 600, 700, and 800. According to one embodiment of the present disclosure, a gate driver 320 may include the aforementioned thin-film transistor substrates 100, 200, 300, 400, 500, 600, 700, and 800.

[0149] refer to Figure 9 Each stage STn may include a first charging unit 10, a first discharging unit 20, a second charging unit 30, a second discharging unit 40, an output unit 50, and a QB stabilization circuit 60. The first charging unit 10, the first discharging unit 20, the second charging unit 30, the second discharging unit 40, and the QB stabilization circuit 60 can all be defined as control units for controlling the Q nodes and QB nodes of the output unit 50. The Q node can be defined as a first control node, and the QB node can be defined as a second control node. For example, the control unit can charge and discharge the Q nodes and charge and discharge the QB nodes in the opposite manner to the Q nodes.

[0150] Each stage STn may include a set terminal 2, a first power supply terminal 4, a second power supply terminal 8, a first clock terminal 12, an output terminal 14, a reset terminal 16, a second clock terminal 5, a control terminal 7, and a stabilizing terminal 18. A start signal VST and one of the outputs CRn-4 from the previous stage are applied to the set terminal 2 as the set signal. A high potential voltage VDD is applied to the first power supply terminal 4. A gate cutoff voltage VSS is applied to the second power supply terminal 8. A clock signal CLKn is applied to the first clock terminal 12. The gate output OUTn is output from the output terminal 14. A reset signal and one of the outputs CRn+4 from the subsequent stage are applied to the reset terminal 16 as the reset signal. An inverted clock signal CLK_B is applied to the second clock terminal 5. The output CRn-2 from another previous stage (e.g., the previous (n-2)th stage) is applied to the control terminal 7. A stabilizing signal (STB) is applied to the stabilizing terminal 18. The gate cutoff voltage VSS can be defined as the gate low voltage. The gate output OUTn of each stage STn can be output as a carry signal CRn to another stage.

[0151] The first charging unit 10 can receive the start signal VST or the output CRn-4 of the previous stage as a set signal through the set terminal 2, and use the set signal to charge the Q node. The output CRn-4 of the previous stage can be the gate output OUTn-4 from the previous (n-4)th stage.

[0152] The first charging unit 10 may include a first-1 Q charging transistor T1_a, which has a gate electrode and a drain electrode connected to the set terminal 2, and a source electrode connected to the drain electrode of the first-2 Q charging transistor T1_b. It may also include a first-2 Q charging transistor T1_b, which has a gate electrode connected to the set terminal 2, a drain electrode connected to the source electrode of the first-1 Q charging transistor T1_a, and a source electrode connected to the Q node.

[0153] In response to the control of the QB node, the first discharge unit 20 can discharge the Q node to the gate cutoff voltage VSS of the second power supply terminal 8. The first discharge unit 20 can receive a reset signal via the reset terminal 16 or the output CRn+4 of the subsequent stage as a reset signal to discharge the Q node to the gate cutoff voltage VSS of the second power supply terminal 8. The output CRn+4 of the subsequent stage can be the gate output OUTn+4 from the (n+4)th subsequent stage. For example, the first discharge unit 20 may include Q discharge transistors T3_a and T3_b, which discharge the Q node to the gate cutoff voltage VSS under the control of the QB node. For example, Q discharge transistors T3_a and T3_b may include a first-1 Q discharge transistor T3_a and a first-2 Q discharge transistor T3_b.

[0154] The first discharge unit 20 may include a first-1 Q discharge transistor T3_a, which has a gate electrode connected to the QB node, a source electrode connected to the drain electrode of the first-2 Q discharge transistor T3_b, and a drain electrode connected to the Q node, and may include a first-2 Q discharge transistor T3_b, which has a gate electrode connected to the QB node, a drain electrode connected to the source electrode of the first-1 Q discharge transistor T3_a, and a source electrode connected to the second power supply terminal 8. The first discharge unit 20 may include a second-1st Q discharge transistor T3n_a, which has a gate electrode connected to a reset terminal 16 supplied with the output signal CRn+4 or a reset signal of the subsequent stage, a source electrode connected to the drain electrode of the second-2nd Q discharge transistor T3n_b, and a drain electrode connected to the Q node. It may also include a second-2nd Q discharge transistor T3n_b, which has a gate electrode connected to a reset terminal 16 supplied with the output signal CRn+4 or a reset signal of the subsequent stage, a drain electrode connected to the source electrode of the second-1st Q discharge transistor T3n_a, and a source electrode connected to the second power supply terminal 8.

[0155] When Q discharge transistors T3_a and T3_b are subjected to positive bias and high temperature stress conditions, such as PBTS (positive bias temperature stress) conditions, the active layers of the first-1 Q discharge transistor T3_a and the first-2 Q discharge transistor T3_b need to be formed identically so that PBTS degradation is uniformly applied to the first-1 Q discharge transistor T3_a and the first-2 Q discharge transistor T3_b.

[0156] According to an embodiment of this disclosure, the Q discharge transistors T3_a and T3_b may include... Figure 6D The thin-film transistor substrate 800 is shown. For example, the first-1 Q discharge transistor T3_a can be the fourth thin-film transistor T14 of the thin-film transistor substrate 800, and the first-2 Q discharge transistor T3_b can be the third thin-film transistor T13 of the thin-film transistor substrate 800. The third thin-film transistor T13 and the fourth thin-film transistor T14 are connected in series with each other.

[0157] When the first-1 Q discharge transistor T3_a is the fourth thin-film transistor T14 of the thin-film transistor substrate 800 and the first-2 Q discharge transistor T3_b is the third thin-film transistor T13 of the thin-film transistor substrate 800, the areas of the third channel portion 231n and the fourth channel portion 232n are equal in the plane, so that PBTS degradation can be uniformly applied to the first-1 Q discharge transistor T3_a and the first-2 Q discharge transistor T3_b.

[0158] In response to a high-potential voltage VDD applied to the first power supply terminal 4, the second charging unit 30 can charge the QB node using the high-potential voltage VDD. Specifically, the second charging unit 30 may include QB charging transistors T4_a and T4_b, which charge the QB node using the high-potential voltage VDD. For example, the second charging unit 30 may include a first QB charging transistor T4_a having a gate electrode and a drain electrode connected to the first power supply terminal 4, and a source electrode connected to the drain electrode of the second QB charging transistor T4_b. For example, the drain electrode of the first QB charging transistor T4_a is applied with a high-potential voltage VDD. Furthermore, the second charging unit 30 may include a second QB charging transistor T4_b having a gate electrode connected to the first power supply terminal 4, a drain electrode connected to the source electrode of the first QB charging transistor T4_a, and a source electrode connected to the QB node.

[0159] According to one embodiment of this disclosure, the QB charging transistors T4_a and T4_b may include... Figures 1 to 6C The thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700 are shown. For example, the first QB charging transistor T4_a can be the second thin-film transistor T12 on the thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700, and the second QB charging transistor T4_b can be the first thin-film transistor T11 on the thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700.

[0160] When the first QB charging transistor T4_a is the second thin-film transistor T12 of the thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700, and the second QB charging transistor T4_b is the first thin-film transistor T11 of the thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700, degradation of the first QB charging transistor T4_a, which is subjected to a high potential voltage, can be prevented.

[0161] The second discharge unit 40 can discharge the QB node to the gate cutoff voltage VSS of the second power supply terminal 8 in response to the control of the Q node. The second discharge unit 40 can also discharge the QB node to the gate cutoff voltage VSS of the second power supply terminal 8 in response to the control of the set terminal 2 providing the start signal VST or the output CRn-4 of the preceding stage. The output CRn-4 of the preceding stage can be the gate output OUTn-4 from the previous (n-4)th stage.

[0162] The second discharge unit 40 may include a first QB discharge transistor T5q, which has a gate electrode connected to the Q node, a source electrode connected to the second power supply terminal 8, and a drain electrode connected to the QB node. The second discharge unit 40 may further include a second QB discharge transistor T5c, which has a gate electrode connected to the set terminal 2, a source electrode connected to the second power supply terminal 8, and a drain electrode connected to the QB node.

[0163] Output unit 50 includes a pull-up transistor T6 and a pull-down transistor T7. Pull-up transistor T6 is pulled up by the control of the Q node and outputs a clock signal CLKn applied to the first clock terminal 12 via output terminal 14 as the gate output OUTn. Pull-down transistor T7 is pulled down by the control of the QB node opposite to the Q node and outputs a gate cutoff voltage VSS from the second power supply terminal 8 via output terminal 14 as the gate output OUTn. Pull-up transistor T6 may have a gate electrode connected to the Q node, a source electrode connected to the output terminal 14, and a drain electrode connected to the first clock terminal 12. For example, pull-up transistor T6 can be turned on during the conduction period of the Q node and output the clock signal CLKn from the first clock terminal 12 via output terminal 14 as a scan signal for gate output OUTn. For example, pull-up transistor T6 can be pulled up by the control of the Q node to output the clock signal CLKn as an input to the output terminal 14 via the first clock terminal 12.

[0164] The output unit 50 further includes a first capacitor CB connected between the gate electrode Q node and the source electrode (output terminal 14) of the pull-up transistor T6.

[0165] The pull-down transistor T7 may have a gate electrode connected to the QB node, a source electrode connected to the second power supply terminal 8, and a drain electrode connected to the output terminal 14. For example, the pull-down transistor T7 can be turned on during the on-time of the QB node corresponding to the off-time of the Q node, and can output the gate off-time voltage VSS from the second power supply terminal 8 as the gate output OUTn via the output terminal 14. For example, the pull-down transistor T7 can be pulled down to the output terminal 14 by the control of the QB node.

[0166] The QB stabilization circuit 60 can stably discharge the QB node to the gate cutoff voltage VSS during the Q node's conduction period in response to the inverted clock signal CLK_B applied through the second clock terminal 5 and the output CRn-2 of the previous (n-2)th stage applied through the control terminal 7.

[0167] The QB stabilization circuit 60 may include two transistors T8 and T9 and two capacitors C1 and C2. The QB stabilization circuit 60 may include a first capacitor C1 connected between the second clock terminal 5 and the connection node A to transmit the inverted clock signal CLK_B to the connection node A, and a second capacitor C2 connected between the control terminal 7 and the connection node A to transmit the output CRn-2 of the previous (n-2)th stage to the connection node A.

[0168] The QB stabilization circuit 60 may include a QB discharge transistor T9 and an initialization transistor T8. The QB discharge transistor T9 is controlled by the connection node A to discharge the QB node to the gate cutoff voltage VSS of the second power supply terminal 8. The initialization transistor T8 is controlled by a stabilization signal (STB) applied to the stabilization terminal 18 to initialize the connection node A to the gate cutoff voltage VSS of the second power supply terminal 8. The QB discharge transistor T9 may have a gate electrode connected to the connection node A, a source electrode connected to the second power supply terminal 8, and a drain electrode connected to the QB node. The initialization transistor T8 may have a gate electrode connected to the stabilization terminal 18, a source electrode connected to the second power supply terminal 8, and a drain electrode connected to the connection node A.

[0169] Figure 10 The circuit diagram is an equivalent circuit diagram of the pixel P of the display device 1000, which includes an organic light-emitting diode (OLED) as a display element 710.

[0170] refer to Figure 10 Pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710. Specifically, a display device 1000 according to an embodiment of the present disclosure may include a pixel driving circuit PDC on a substrate 110.

[0171] Figure 10 The pixel driving circuit PDC includes a first thin-film transistor TR1 as a switching transistor and a second thin-film transistor TR2 as a driving transistor.

[0172] According to one embodiment of this disclosure, in a driving transistor, current can flow in one direction, and in a switching transistor, current can flow in two directions. According to another embodiment of this disclosure, the aforementioned thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700 can be used as… Figure 10 The pixel driving circuit PDC shown has a driving transistor. The thin-film transistor substrate 800 described above can be used as... Figure 10The pixel driving circuit PDC shown has a switching transistor. Specifically, in the driving transistor where the current flows in one direction, asymmetric thin-film transistor substrates 100, 200, 300, 400, 500, 600, and 700 can be used, and in the switching transistor where the current flows in two directions, a symmetric thin-film transistor substrate 800 can be used.

[0173] According to another embodiment of this disclosure, the thin-film transistors 100, 200, 300, and 400 described above can be used as... Figure 10 The pixel driving circuit PDC shown has a driving transistor.

[0174] The following advantages can be obtained according to this disclosure.

[0175] According to an embodiment of the present disclosure, a thin-film transistor substrate can reduce the stress applied to the thin-film transistor due to high drain bias by forming a large channel region of the thin-film transistor to which a high potential voltage is applied.

[0176] According to one embodiment of the present disclosure, a thin-film transistor substrate can reduce the stress applied to the thin-film transistor due to high drain bias by allowing the drain electrode of the thin-film transistor, to which a high potential voltage is applied, to have an area in the plane that is much larger than that of the source electrode.

[0177] According to one embodiment of the present disclosure, a thin-film transistor substrate can achieve a narrow bezel by having a circular structure, wherein the drain and source electrodes of different thin-film transistors are shared with each other.

[0178] In addition to the effects described above, other features and advantages of this disclosure will be described below, or may be clearly understood by those skilled in the art to which this disclosure pertains from such description and explanation.

[0179] It will be apparent to those skilled in the art that this disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications, and variations can be made to this disclosure without departing from its spirit or scope. Therefore, the scope of this disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this disclosure.

Claims

1. A thin-film transistor substrate, comprising: Substrate; as well as The first thin-film transistor and the second thin-film transistor are disposed on the substrate and connected in series with each other. The first thin-film transistor includes: A first active layer having a first channel portion; A first gate electrode configured to be spaced apart from and overlapping the first active layer; and The first source electrode and the first drain electrode are configured to be in contact with the first active layer and spaced apart from each other. The second thin-film transistor includes: A second active layer having a second channel portion; A second gate electrode configured to be spaced apart from and overlapping the second active layer; and The second source electrode and the second drain electrode are configured to be in contact with the second active layer and spaced apart from each other. The first drain electrode and the second source electrode are integrally formed and disposed on the same layer.

2. The thin-film transistor substrate according to claim 1, wherein, The first gate electrode and the second gate electrode are integrally formed into a closed-loop shape in a plane.

3. The thin-film transistor substrate according to claim 2, wherein, The first drain electrode and the second source electrode are disposed inside the first gate electrode and the second gate electrode, which are integrally formed in a plane.

4. The thin-film transistor substrate according to claim 1, wherein, The first active layer includes: A first source conductor portion disposed on one side of the first channel portion; and A first drain conductor portion disposed on the other side of the first channel portion; The second active layer includes: A second source conductor portion disposed on one side of the second channel portion; and A second drain conductor portion is disposed on the other side of the second channel portion; An opening is provided between the first channel portion and the second channel portion.

5. The thin-film transistor substrate according to claim 4, wherein, The first channel portion has a first length and a first width that is perpendicular to the first length and extends along the first channel portion. The second channel portion has a second length and a second width that is perpendicular to the second length and extends along the second channel portion. Wherein, the second width is longer than the first width, and Wherein, the first length and the second length are equal.

6. The thin-film transistor substrate according to claim 5, wherein, The first width narrows in the plane from the first source conductor portion to the first drain conductor portion, and The second width widens in the plane from the second source conductor portion to the second drain conductor portion.

7. The thin-film transistor substrate according to claim 1, wherein, The second channel portion has a larger area in the plane than the first channel portion.

8. The thin-film transistor substrate according to claim 4, wherein, The second drain electrode has a larger area in the plane than the first source electrode, and the first source electrode has a larger area in the plane than the first drain electrode.

9. The thin-film transistor substrate according to claim 1, wherein, The first channel portion is formed in a U-shape, and The second channel portion is formed as a U-shape rotated 180°.

10. The thin-film transistor substrate according to claim 1, wherein, The first gate electrode is formed in a U-shape, and the second gate electrode is formed in a U-shape rotated 180°.

11. The thin-film transistor substrate according to claim 4, wherein, The first source electrode is formed in a U-shape, and the second drain electrode is formed in a U-shape rotated 180°.

12. The thin-film transistor substrate according to claim 1, wherein, The first gate electrode and the second gate electrode are integrally formed in a plane as any one of a circular ring, an elliptical ring, and a rectangular ring with rounded corners, and Each edge of the inner surface of the first source electrode and the inner surface of the second drain electrode has a rounded shape in a plane.

13. The thin-film transistor substrate according to claim 1, wherein, The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the same layer, but on a different layer than the first gate electrode and the second gate electrode.

14. The thin-film transistor substrate according to claim 13, wherein, The first active layer is disposed between the substrate and the first gate electrode, and the second active layer is disposed between the substrate and the second gate electrode.

15. The thin-film transistor substrate according to claim 14, wherein, The first thin-film transistor includes a first light-blocking layer disposed between the substrate and the first active layer. The second thin-film transistor includes a second light-blocking layer disposed between the substrate and the second active layer. The first light-blocking layer has a closed-loop shape and overlaps with the first gate electrode. The second light-blocking layer has a closed-loop shape and overlaps with the second gate electrode.

16. The thin-film transistor substrate according to claim 15, wherein, The first light-blocking layer is electrically connected to the first gate electrode, and the second light-blocking layer is electrically connected to the second gate electrode.

17. The thin-film transistor substrate according to claim 1, wherein, The first gate electrode is disposed between the substrate and the first active layer, and The second gate electrode is disposed between the substrate and the second active layer.

18. A display device comprising a thin-film transistor substrate according to any one of claims 1 to 17.

19. The display device of claim 18, further comprising a gate driver having multiple stages, each driving multiple gate lines and pixel driving circuits. in, Each of the plurality of levels includes: The output unit includes a pull-up transistor controlled by a Q node to pull up a first clock signal input through a first clock terminal from a plurality of clocks to an output terminal, and a pull-down transistor controlled by a QB node to pull down the output terminal; and a pull-down transistor controlled by a QB node to pull down the output terminal. A control unit that charges and discharges the Q node, and in turn charges and discharges the QB node in the opposite direction. The control unit includes a QB charging transistor, which charges the QB node using a high-potential voltage. The QB charging transistor includes a first QB charging transistor and a second QB charging transistor. The high potential voltage is applied to the drain electrode of the first QB charging transistor, and the source electrode of the second QB charging transistor is connected to the QB node. Wherein, the first QB charging transistor is the second thin-film transistor, and the second QB charging transistor is the first thin-film transistor.

20. The display device according to claim 19, wherein, The control unit includes a Q discharge transistor, which discharges the Q node to its gate cutoff voltage under the control of the QB node. The Q discharge transistor includes a third thin-film transistor and a fourth thin-film transistor connected in series with each other. The third thin-film transistor includes: The third active layer has a third channel portion; A third gate electrode configured to be spaced apart from and overlapping the third active layer; and The third source electrode and the fourth drain electrode are configured to be in contact with the third active layer and spaced apart from each other. The fourth thin-film transistor includes: The fourth active layer has a fourth channel portion; A fourth gate electrode configured to be spaced apart from and overlapping the fourth active layer; and The fourth source electrode and the fourth drain electrode are configured to be in contact with the fourth active layer and spaced apart from each other. The third gate electrode and the fourth gate electrode are integrally formed and disposed on the same layer. The third drain electrode and the fourth source electrode are integrally formed, and the third channel portion has the same area as the fourth channel portion in the plane.

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