Light emitting diode with improved heat dissipation and method of manufacturing the same
By employing planar electrodes and groove structures in light-emitting diodes (LEDs), the problems of hot spots and solder voids caused by finger electrodes are solved, resulting in better heat dissipation and current distribution, and improving the performance and reliability of LEDs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HC SEMITEK ZHEJIANG CO LTD
- Filing Date
- 2026-01-16
- Publication Date
- 2026-06-09
AI Technical Summary
Existing LEDs suffer from issues such as localized hot spots caused by finger electrodes, solder voids, and insufficient thermal conductivity, which affect luminous efficiency and lifespan.
A flat electrode is used to replace the finger electrode, covering more than 70% of the top surface of the epitaxial layer to form a full-area heat conduction channel. A groove is set on the top surface of the epitaxial layer to expose the light-emitting area. The current and heat distribution are optimized by combining a transparent conductive layer and a current blocking layer.
It improves heat dissipation, increases welding yield, reduces manufacturing costs, enhances current and light emission uniformity, and extends service life.
Smart Images
Figure CN122180223A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode with improved heat dissipation and a method for its fabrication. Background Technology
[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. Due to their high luminous efficiency, high power, and excellent heat dissipation, LED chips are widely used in lighting and display fields.
[0003] The flip-chip light-emitting diode in related technologies includes an epitaxial layer and finger electrodes located on the epitaxial layer. When the light-emitting diode is operating, the current extends laterally through the finger electrodes to the active region of the epitaxial layer.
[0004] Because finger electrodes are typically thin, the heat generated by the epitaxial layer beneath them can only be conducted to the pads above through a narrow path. This can easily create localized hot spots in the finger electrode area, thus affecting the luminous efficiency and lifespan of the LED. Furthermore, the presence of finger electrodes creates an uneven structure on the chip surface. During subsequent soldering, this unevenness can easily lead to solder voids, reducing soldering yield and weakening overall thermal conductivity. Summary of the Invention
[0005] This disclosure provides a light-emitting diode with improved heat dissipation and its fabrication method, which can enhance the heat dissipation effect of the epitaxial layer and improve the problem of solder voids. The technical solution is as follows: On one hand, this disclosure provides a light-emitting diode, which includes an epitaxial layer and a planar electrode. The planar electrode is located on the top surface of the epitaxial layer, and the ratio of the projected area of the planar electrode on the top surface of the epitaxial layer to the area of the top surface of the epitaxial layer is greater than or equal to 0.7.
[0006] In one implementation of this disclosure, the top surface of the epitaxial layer has a groove, the flat electrode is located outside the groove, and the ratio of the orthographic projection area of the groove on the bottom surface of the epitaxial layer to the area of the bottom surface of the epitaxial layer is less than or equal to 0.2.
[0007] In another implementation of this disclosure, the groove is located at the peripheral edge of the top surface of the epitaxial layer; the light-emitting diode further includes a finger electrode located within the groove.
[0008] In another implementation of the embodiments of this disclosure, the flat electrode includes at least one of an Ag layer, an Al layer, and an aluminum alloy layer.
[0009] In another implementation of the present disclosure, the light-emitting diode further includes a transparent conductive layer located on the top surface of the epitaxial layer, and the planar electrode located on the surface of the transparent conductive layer away from the epitaxial layer; the orthographic projection of the planar electrode on the top surface of the epitaxial layer is located within the orthographic projection of the transparent conductive layer on the top surface of the epitaxial layer.
[0010] In another implementation of the present disclosure, the light-emitting diode further includes a current blocking layer located on the top surface of the epitaxial layer, and the planar electrode located on the surface of the current blocking layer away from the epitaxial layer; the current blocking layer is in the form of a mesh; or, the current blocking layer includes a plurality of spaced block structures; or, the current blocking layer includes a plurality of concentrically arranged annular structures.
[0011] In another implementation of the present disclosure, the surface of the flat electrode has a plurality of spaced through holes, and the through holes are filled with an ohmic contact material layer.
[0012] In another implementation of this disclosure, the light-emitting diode further includes a passivation layer and a pad. The passivation layer is located on the top surface of the epitaxial layer and on the planar electrode. The surface of the passivation layer has a via that exposes the planar electrode. The pad is located on the surface of the passivation layer and is connected to the planar electrode through the via. The projected area of the pad on the bottom surface of the epitaxial layer is smaller than the projected area of the planar electrode on the bottom surface of the epitaxial layer.
[0013] In another implementation of this disclosure, the distribution density of the vias on the flat plate electrode located within the orthogonal projection of the pad on the flat plate electrode is less than the distribution density of the vias on the flat plate electrode located outside the orthogonal projection of the pad on the flat plate electrode.
[0014] On the other hand, embodiments of this disclosure provide a method for fabricating a light-emitting diode, the method comprising: fabricating an epitaxial layer on a substrate; forming a planar electrode on the top surface of the epitaxial layer, wherein the ratio of the projected area of the planar electrode on the top surface of the epitaxial layer to the area of the top surface of the epitaxial layer is greater than or equal to 0.7.
[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The light-emitting diode provided in this embodiment uses a planar electrode instead of a finger electrode. The planar electrode covers more than 70% of the top surface of the epitaxial layer, forming a global heat conduction channel. Compared to the limitation of finger electrodes, which conduct heat only through narrow paths, the large-area planar electrode allows heat from the light-emitting area to diffuse directly to the substrate through a low-resistance path, significantly reducing the chip junction temperature. Furthermore, eliminating the finger electrode creates a flat and continuous electrode plane on the chip surface. During eutectic bonding, the molten solder can spread evenly, avoiding solder bridging or void defects caused by unevenness in traditional finger electrodes, effectively improving bonding yield. Simultaneously, the flat interface enhances heat conduction efficiency, further optimizing heat dissipation.
[0016] Meanwhile, during the spot testing process, the probe can directly act on the robust and flat planar electrode, completely avoiding the risk of damage caused by the probe accidentally touching the fragile finger electrode in related technologies. This not only reduces probe wear but also improves chip testing yield and reduces manufacturing costs. Moreover, the wide-range characteristics of the planar electrode enable uniform current distribution from the chip center to the edge, overcoming the edge current congestion problem caused by the lateral resistance difference of the finger electrode. Especially in large-size chips, it can effectively improve horizontal current spreading efficiency and improve light emission uniformity. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure; Figure 2 It is along Figure 1 A cross-sectional view of the light-emitting diode taken from section AA; Figure 3 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure; Figure 4 This is a top view of various different types of current blocking layers provided in the embodiments of this disclosure; Figure 5 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure; Figure 6 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure.
[0019] The markings in the diagram are explained as follows: 10. Epitaxial layer; 11. First semiconductor layer; 12. Multiple quantum well layer; 13. Second semiconductor layer; 14. Groove; 20. Flat plate electrode; 21. Through hole; 22. Ohmic contact material layer; 30. Finger electrodes; 41. Transparent conductive layer; 42. Current blocking layer; 43. Passivation layer; 50. Solder pads; 60. Substrate. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0021] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0022] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 It is along Figure 1 A cross-sectional view of the light-emitting diode taken from section AA.
[0023] like Figure 1 , 2 As shown, the light-emitting diode includes an epitaxial layer 10 and a planar electrode 20, with the planar electrode 20 located on the top surface of the epitaxial layer 10.
[0024] The ratio of the projected area of the planar electrode 20 on the top surface of the epitaxial layer 10 to the area of the top surface of the epitaxial layer 10 is greater than or equal to 0.7.
[0025] The light-emitting diode provided in this embodiment uses a planar electrode 20 instead of a finger electrode 30. The planar electrode 20 covers more than 70% of the top surface area of the epitaxial layer 10, forming a global heat conduction channel. Compared to the limitation of the finger electrode 30, which conducts heat only through a narrow path, the large-area planar electrode 20 allows heat from the light-emitting area to diffuse directly to the substrate through a low-resistance path, significantly reducing the chip junction temperature. Furthermore, eliminating the finger electrode 30 results in a flat and continuous electrode plane on the chip surface. During eutectic bonding, the molten solder can spread evenly, avoiding solder bridging or void defects caused by unevenness in the traditional finger electrode 30, effectively improving bonding yield. Simultaneously, the flat interface enhances heat conduction efficiency, further optimizing heat dissipation.
[0026] Meanwhile, during the spot testing process, the probe can directly act on the robust and flat planar electrode 20, completely avoiding the risk of damage caused by the probe accidentally touching the fragile finger electrode 30 in related technologies. This not only reduces probe wear but also improves chip testing yield and reduces manufacturing costs. Moreover, the wide-range characteristics of the planar electrode 20 enable uniform current distribution from the chip center to the edge, overcoming the edge current congestion problem caused by the lateral resistance difference of the finger electrode 30. Especially in large-size chips, it can effectively improve horizontal current expansion efficiency and improve light emission uniformity.
[0027] Optionally, such as Figure 2 As shown, the light-emitting diode also includes a substrate 60, and an epitaxial layer 10 is located on the surface of the substrate 60.
[0028] For example, the substrate is a sapphire substrate. Sapphire substrates have high light transmittance, meaning they are transparent. Furthermore, sapphire material is relatively hard and chemically stable, giving the light-emitting diode (LED) good luminous efficacy and stability.
[0029] Optionally, such as Figure 2 As shown, the epitaxial layer 10 includes a first semiconductor layer 11, a multiple quantum well layer 12, and a second semiconductor layer 13 stacked sequentially. The surface of the second semiconductor layer 13 has a groove 14 exposing the first semiconductor layer 11. That is, the top surface of the epitaxial layer 10 has a groove 14.
[0030] In this embodiment of the present disclosure, one of the first semiconductor layer 11 and the second semiconductor layer 13 is a p-type layer, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 is an n-type layer.
[0031] For example, the first semiconductor layer 11 is an n-type layer and the second semiconductor layer 13 is a p-type layer.
[0032] In this embodiment of the disclosure, the first semiconductor layer 11 is an AlxGa1-xN material layer, wherein X is greater than or equal to 0 and less than or equal to 1.
[0033] For example, when X is 0, the first semiconductor layer 11 is a GaN layer. For instance, the first semiconductor layer 11 is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.
[0034] Optionally, the multi-quantum-well layer 12 includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer 12 may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.
[0035] As an example, in an embodiment of this disclosure, the multi-quantum-well layer 12 includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.
[0036] Optionally, the thickness of the multiple quantum well layer 12 can be from 150 nm to 200 nm.
[0037] Optionally, the second semiconductor layer 13 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.
[0038] Optionally, such as Figure 1 , 2 As shown, the flat plate electrode 20 is located outside the groove 14, and the ratio of the orthographic projection area of the groove 14 on the bottom surface of the epitaxial layer 10 to the bottom surface area of the epitaxial layer 10 is less than or equal to 0.2.
[0039] The groove 14 exposes the first semiconductor layer 11. Only the area outside the groove 14 contains the light-emitting multi-quantum-well layer 12. Therefore, the area outside the groove 14 is actually the light-emitting region of the epitaxial layer 10. By positioning the planar electrode 20 directly opposite the light-emitting region, the planar electrode 20 precisely covers the light-emitting region outside the groove 14. This allows current to be directly injected into the light-emitting region through the planar electrode 20, shortening the lateral expansion path, further enhancing current uniformity, and improving the light-emitting consistency of large-size chips. Furthermore, the planar electrode 20 covers the heat-generating light-emitting region, continuing the large-area, low-resistance heat conduction path, efficiently dissipating heat, and suppressing junction temperature rise.
[0040] Meanwhile, the projection area of the groove 14 on the bottom surface of the epitaxial layer 10 is ≤0.2, meaning the non-light-emitting area accounts for a very small proportion, while the light-emitting area accounts for ≥80%. The small area of the groove 14 has a negligible impact on the effective light-emitting area, resulting in a small impact on the overall luminous intensity of the chip. The large proportion of the light-emitting area also results in a larger projected area of the planar electrode 20, continuing the advantages of heat dissipation, soldering, and avoiding damage to the ejector pins.
[0041] Optionally, such as Figure 1 As shown, the groove 14 is located at the peripheral edge of the top surface of the epitaxial layer 10; the light-emitting diode also includes a finger electrode 30, which is located within the groove 14.
[0042] For example, such as Figure 1 As shown, the groove 14 is elongated and extends along one side of the top surface of the epitaxial layer 10.
[0043] By placing the groove 14 at the periphery of the top surface of the epitaxial layer 10 and arranging the finger electrode 30 within the groove 14, the light-emitting area is positioned in the center of the top surface of the epitaxial layer 10, remaining flat and fully covered by the flat plate electrode 20, ensuring that light extraction, heat dissipation, and welding performance are not affected. The finger electrode 30 is placed in the peripheral groove 14, physically separated from the light-emitting area, avoiding its interference with the light field and current. Since the finger electrode 30 also performs the function of current introduction, arranging the finger electrode 30 in the peripheral non-light-emitting area not only avoids occupying the area of the light-emitting area but also shortens the current introduction path and improves the current injection efficiency.
[0044] For example, the width of the finger electrode 30 is 4 μm to 10 μm.
[0045] The width of the finger electrode 30 refers to the width of its orthographic projection onto the bottom surface of the epitaxial layer 10. Furthermore, the width direction of the finger electrode 30 is perpendicular to its extension direction, meaning the width direction is perpendicular to its length.
[0046] By setting the width of the finger electrode 30 to 4μm to 10μm, it avoids the problem that excessive narrowness can increase resistance and cause Joule heat concentration, and avoids the problem that excessive width can limit the lateral diffusion range of current and aggravate congestion.
[0047] Optionally, both the flat plate electrode 20 and the finger electrode 30 include at least one of Ag layer, Al layer and aluminum alloy layer.
[0048] For example, both the planar electrode 20 and the finger electrode 30 include an Ag layer.
[0049] The Ag layer possesses extremely high visible light reflectivity, enabling efficient reflection of light emitted from the active region and improving light extraction efficiency. Simultaneously, its excellent conductivity reduces electrode resistance and Joule heating. As a highly reflective metal, its optical and electrical properties are synergistically optimized, making it suitable for applications requiring high light extraction efficiency.
[0050] For example, both the flat plate electrode 20 and the finger electrode 30 include an Al layer.
[0051] The Al layer has moderate reflectivity, lower cost than Ag, and mature technology; it adheres well to the epitaxial layer 10 and is not easily peeled off. Its surface natural oxide film is transparent, does not affect reflection, and also has a certain degree of corrosion resistance.
[0052] For example, both the flat plate electrode 20 and the finger electrode 30 include an aluminum alloy layer, wherein the aluminum alloy layer may be an AlCu alloy.
[0053] While maintaining the high reflectivity of Al, AlCu alloys enhance strength and resistance to electromigration through Cu solid solution strengthening, reducing the risk of electrode failure under long-term high current. The resistivity is slightly higher than that of pure Al but still relatively low, balancing reflectivity, conductivity, and reliability.
[0054] For example, both the planar electrode 20 and the finger electrode 30 include an Ag layer, an Al layer and an AlCu layer stacked sequentially.
[0055] Optionally, such as Figure 1 , 2 As shown, the light-emitting diode also includes a transparent conductive layer 41, which is located on the top surface of the epitaxial layer 10. The planar electrode 20 is located on the surface of the transparent conductive layer 41 away from the epitaxial layer 10. The orthographic projection of the planar electrode 20 onto the top surface of the epitaxial layer 10 lies within the orthographic projection of the transparent conductive layer 41 onto the top surface of the epitaxial layer 10.
[0056] The transparent conductive layer 41 has high lateral conductivity, which can diffuse the current evenly within the light-emitting area, making up for the insufficient lateral conductivity of the epitaxial layer 10 itself, so that the current is more evenly distributed from the center of the chip to the edge, and improving the light emission consistency of large-size chips.
[0057] Furthermore, the planar electrode 20 does not directly contact the epitaxial layer 10, reducing the risk of metal atom diffusion or process damage, and improving interface stability and device lifespan. The projection of the planar electrode 20 is entirely within the transparent conductive layer 41, ensuring that all current is homogenized through the transparent layer before flowing into the electrode, avoiding local current concentration, while maintaining the advantages of large-area heat dissipation and flat welding of the planar electrode 20.
[0058] For example, the transparent conductive layer 41 may be an ITO (Indium Tin Oxide) layer or an IZO (Indium Zinc Oxide) layer.
[0059] Figure 3 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. For example... Figure 3 As shown, the light-emitting diode also includes a current blocking layer 42, which is located on the top surface of the epitaxial layer 10, and the planar electrode 20 is located on the surface of the current blocking layer 42 away from the epitaxial layer 10.
[0060] The current blocking layer 42 is located on the top surface of the epitaxial layer 10, and the planar electrode 20 covers the current blocking layer 42. This forces the current to diffuse to a specific area, improving current utilization and luminous efficiency. At the same time, it can block part of the heat diffusion path, help optimize heat distribution, and alleviate local hot spots. The planar electrode 20 covers the outside of the current blocking layer 42, and can also maintain a large-area flat structure to continue the advantages of excellent heat dissipation, welding, and avoiding damage to the ejector pin.
[0061] For example, Figure 4 This is a top view of various types of current blocking layers 42 provided in embodiments of this disclosure. For example... Figure 4 As shown, the current blocking layer 42 is in the form of a mesh. The plate electrode 20 covers the mesh-shaped current blocking layer 42 and extends into the mesh of the current blocking layer 42.
[0062] The grid, composed of crisscrossing lines, can evenly divide the current channels in the plane, allowing the current to spread evenly between the grid nodes and avoiding local accumulation.
[0063] For example, such as Figure 4 As shown, the current blocking layer 42 includes multiple spaced block structures.
[0064] The dispersed arrangement of block structures allows for flexible positioning based on hotspots in the light-emitting area or regions requiring enhanced current, enabling non-uniform current guidance. For example, placing block structures in high-heat-generating areas forces current to flow around them for cooling. The high degree of freedom in the arrangement of block structures facilitates targeted optimization of chip performance, while the larger gaps between blocks minimize light loss.
[0065] For example, such as Figure 4 As shown, the current blocking layer 42 includes multiple concentrically arranged annular structures.
[0066] The rings are nested from the inside out, guiding the current to expand radially from the center outwards, forming a symmetrical annular current distribution, which is particularly suitable for circular or near-circular chips. This type of current blocking layer 42 can reduce the current difference between the center and the edge, improve the uniformity of light emission in a circular wafer, and maintain good light transmission by utilizing the annular gaps, thus maintaining stable optical performance while achieving current confinement.
[0067] Figure 5 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. For example... Figure 5 As shown, the surface of the flat plate electrode 20 has a plurality of spaced through holes 21, and the through holes 21 are filled with an ohmic contact material layer 22.
[0068] For example, the ohmic contact material layer 22 may include an ITO layer, an IZO layer, a Ti layer, a Pt layer, an Au composite layer, or a metal silicide layer.
[0069] Since the planar electrode 20 is a metal layer, direct contact between the metal and the semiconductor material of the epitaxial layer 10 is prone to forming a Schottky barrier due to work function mismatch, resulting in high contact resistance and uneven current injection. By setting a via 21 on the planar electrode 20 and filling the via 21 with a highly adaptable ohmic contact material, a low-resistance interface can be constructed between the planar electrode 20 and the semiconductor material, effectively reducing local contact resistance, promoting efficient current injection into the light-emitting region, and reducing energy loss.
[0070] Optionally, such as Figure 5 As shown, the light-emitting diode also includes a passivation layer 43 and a pad 50. The passivation layer 43 is located on the top surface of the epitaxial layer 10 and the plate electrode 20. The surface of the passivation layer 43 has a via that exposes the plate electrode 20. The pad 50 is located on the surface of the passivation layer 43 and is connected to the plate electrode 20 through the via.
[0071] Optionally, the passivation layer 43 includes at least one of an aluminum oxide layer, a silicon oxide layer, a titanium oxide layer, and a silicon oxynitride layer.
[0072] For example, the passivation layer 43 includes an aluminum oxide layer.
[0073] Alumina has extremely high dielectric strength, which can effectively withstand the high voltage during LED operation, reduce the risk of passivation layer breakdown, and prevent short circuits between electrodes and solder joints. Furthermore, alumina is chemically stable, resistant to acid and alkali corrosion, and does not easily undergo hydrolysis or oxidation reactions in the humid and hot environment of chip packaging, maintaining its insulating properties over a long period.
[0074] As an example, the thickness of the alumina layer can be from 100 nm to 500 nm.
[0075] For example, the passivation layer 43 includes a silicon oxide layer.
[0076] Silicon oxide has a good match with the thermal expansion coefficient of epitaxial layer 10, resulting in low stress after deposition, which can reduce the risk of cracking or peeling of passivation layer 43 due to thermal stress. Although the dielectric strength of silicon oxide is slightly lower than that of aluminum oxide, the insulation requirements of LEDs can still be met by increasing the thickness, for example, by controlling the thickness of silicon oxide to be more than 1 μm.
[0077] As an example, the thickness of the silicon oxide layer can be from 0.5 μm to 2 μm.
[0078] For example, the passivation layer 43 includes a titanium oxide layer.
[0079] Titanium oxide has a high dielectric constant and can act as a field plate in the passivation layer 43. By dispersing the electric field concentration effect at the electrode edge through the high dielectric constant material, the probability of insulation breakdown caused by local high electric field is reduced.
[0080] As an example, the thickness of the titanium oxide layer can be from 50 nm to 200 nm.
[0081] Among them, the positive projection area of the pad 50 on the bottom surface of the epitaxial layer 10 is smaller than the positive projection area of the flat electrode 20 on the bottom surface of the epitaxial layer 10.
[0082] In the above implementation, the flat electrode 20 has a large area, which allows the current to spread evenly and improves the current injection efficiency.
[0083] The small area of the pad 50 concentrates the localized heat generation area during soldering with the substrate. Heat can then be rapidly dissipated through the large-area planar electrode 20 below, preventing the pad 50 itself from becoming a heat-concentrated area. Simultaneously, the smaller pad 50 applies stress more evenly to the passivation layer 43, reducing the risk of cracking of the passivation layer 43 or detachment of the pad 50 due to thermal expansion mismatch. The smaller pad 50 occupies less space on the packaging substrate, facilitating high-density integration or multi-chip array layouts. Furthermore, the pad 50 only needs to be partially connected to the planar electrode 20 via vias, reducing the precision requirements for via processing.
[0084] Optionally, such as Figure 5 As shown, the distribution density of vias 21 on the plate electrode 20 located within the orthogonal projection of the pad 50 on the plate electrode 20 is less than the distribution density of vias 21 on the plate electrode 20 located outside the orthogonal projection of the pad 50 on the plate electrode 20.
[0085] Among them, the distribution density refers to the number of through holes 21 per unit area, which is used to measure the density of through holes 21 on the plane.
[0086] By controlling the via density of the vias 21 on the planar electrode 20 within the orthographic projection region of the pad 50 to be lower than the via density of the vias 21 outside the orthographic projection region of the pad 50, current injection efficiency can be optimized. The outer projection region requires a large number of vias 21 to enhance current injection and uniformity; therefore, a high-density arrangement can improve current spread efficiency. However, the inner projection region (the connection area of the pad 50) functions to inject current. If the vias 21 are too dense, it will increase unnecessary contact resistance and process complexity, and will also cause the current to be too concentrated, affecting heat dissipation.
[0087] Optionally, the pad 50 may include at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.
[0088] The aforementioned metallic materials have excellent heat dissipation properties. Therefore, solder joints prepared using these materials also have excellent heat dissipation properties, which can improve the heat dissipation effect of light-emitting diodes.
[0089] Optionally, the pad 50 includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked sequentially.
[0090] For example, the thickness of the first Ti layer is 20 to 100 angstroms. For instance, the thickness of the first Ti layer is 50 angstroms.
[0091] For example, the thickness of the Al layer is between 10,000 and 20,000 angstroms. For instance, the thickness of the Al layer is 15,000 angstroms.
[0092] For example, the thickness of the second Ti layer is between 500 angstroms and 1500 angstroms. For instance, the thickness of the second Ti layer is 1000 angstroms.
[0093] For example, the thickness of the Pt layer is between 500 angstroms and 1500 angstroms. For instance, the thickness of the Pt layer is 1000 angstroms.
[0094] For example, the thickness of the Ni layer is between 60,000 and 80,000 angstroms. For instance, the thickness of the Ni layer is 70,000 angstroms.
[0095] For example, the thickness of the Au layer is between 1500 angstroms and 2500 angstroms. For instance, the thickness of the Au layer is 2000 angstroms.
[0096] Figure 6 This is a flowchart illustrating a method for fabricating a light-emitting diode according to an embodiment of this disclosure. Figure 6 As shown, the preparation method includes: S11: Prepare an epitaxial layer on the substrate.
[0097] The epitaxial layer may include a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer sequentially stacked on the substrate.
[0098] S12: A planar electrode is formed on the top surface of the epitaxial layer.
[0099] Among them, the ratio of the projected area of the planar electrode on the top surface of the epitaxial layer to the area of the top surface of the epitaxial layer is greater than or equal to 0.7.
[0100] The light-emitting diode (LED) fabricated by the method disclosed in this embodiment uses a planar electrode instead of a finger electrode. The planar electrode covers more than 70% of the top surface of the epitaxial layer, forming a global heat conduction channel. Compared to the limitation of finger electrodes, which conduct heat only through narrow paths, the large-area planar electrode allows heat from the light-emitting area to diffuse directly to the substrate through a low-resistance path, significantly reducing the chip junction temperature. Furthermore, eliminating the finger electrode results in a flat and continuous electrode plane on the chip surface. During eutectic bonding, the molten solder can spread evenly, avoiding solder bridging or void defects caused by unevenness in traditional finger electrodes, effectively improving bonding yield. Simultaneously, the flat interface enhances heat conduction efficiency, further optimizing heat dissipation.
[0101] Meanwhile, during the spot testing process, the probe can directly act on the robust and flat planar electrode, completely avoiding the risk of damage caused by the probe accidentally touching the fragile finger electrode in related technologies. This not only reduces probe wear but also improves chip testing yield and reduces manufacturing costs. Moreover, the wide-range characteristics of the planar electrode enable uniform current distribution from the chip center to the edge, overcoming the edge current congestion problem caused by the lateral resistance difference of the finger electrode. Especially in large-size chips, it can effectively improve horizontal current spreading efficiency and improve light emission uniformity.
[0102] The process of preparing the epitaxial layer in step S11 may include the following steps: First, a substrate is provided.
[0103] The substrate can be a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.
[0104] As an example, in this embodiment of the disclosure, the substrate is a sapphire substrate. Sapphire substrates are a commonly used substrate, with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a flat sapphire substrate.
[0105] The sapphire substrate can be pretreated by placing it in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking it for 12 to 18 minutes. As an example, in this embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.
[0106] Specifically, the baking temperature can be from 1000℃ to 1200℃, and the pressure inside the MOCVD reaction chamber during baking can be from 100mbar to 200mbar.
[0107] Growing an epitaxial layer on a substrate can include: sequentially forming a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer on a sapphire substrate using MOCVD technology.
[0108] The first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.
[0109] Optionally, the first semiconductor layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.
[0110] The growth temperature of the n-type GaN layer can be from 1000℃ to 1100℃, and the growth pressure of the n-type GaN layer can be from 100 torr to 300 torr.
[0111] Optionally, the multi-quantum-well layer includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.
[0112] When growing multiple quantum well layers, the MOCVD reaction chamber pressure is controlled at 200 torr. When growing InGaN quantum well layers, the reaction chamber temperature is 760℃ to 780℃. When growing GaN quantum barrier layers, the reaction chamber temperature is 860℃ to 890℃.
[0113] As an example, in an embodiment of this disclosure, the multi-quantum-well layer includes five alternating stacked InGaN quantum-well layers and GaN quantum-barrier layers.
[0114] Optionally, the thickness of the multi-quantum well layer can be from 150 nm to 200 nm.
[0115] Optionally, the second semiconductor layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.
[0116] When growing p-type GaN layers, the growth pressure of p-type GaN layers can be from 200 Torr to 600 Torr, and the growth temperature of p-type GaN layers can be from 800℃ to 1000℃.
[0117] Then, the second semiconductor layer is etched to form a groove that exposes the first semiconductor layer.
[0118] Next, a transparent conductive layer is formed on the surface of the second semiconductor layer.
[0119] In the example selection, the transparent conductive layer can be an ITO layer or an IZO layer.
[0120] Step S12 may include: sequentially depositing an Ag layer, an Al layer, and an AlCu layer on the transparent conductive layer.
[0121] The evaporation process must be performed on photoresist with defined electrode patterns. The area of the electrode pattern must be such that its projected area on the top surface of the epitaxial layer is greater than or equal to 0.7, in order to achieve large-area current collection and heat dissipation. Afterwards, the photoresist and its redundant metal are removed by a stripping process, leaving only the metal stack in the electrode pattern area to form the final planar electrode.
[0122] In step S12, the preparation of the flat plate electrode can also be done by preparing the finger electrode within the groove.
[0123] Specifically, this can include depositing highly reflective metallic materials (such as Ag, Al, or AlCu alloys) within the grooves via magnetron sputtering or electron beam evaporation. During deposition, the geometric constraints of the photoresist mask openings are utilized to ensure the metal layer is deposited within the grooves.
[0124] Optionally, the width of the finger electrode is 4 μm to 10 μm.
[0125] The width of the finger electrode refers to the width of its orthographic projection onto the surface of the epitaxial layer. Furthermore, the width direction of the finger electrode is perpendicular to its extension direction, meaning it is perpendicular to its length.
[0126] The following steps are included after step S12: The first step is to form a passivation layer in the groove, on the finger electrode, and on the plate electrode.
[0127] Optionally, the passivation layer includes at least one of an aluminum oxide layer, a silicon oxide layer, a titanium oxide layer, and a silicon oxynitride layer.
[0128] For example, the passivation layer is a DBR layer, which includes multiple silicon oxide layers and multiple titanium oxide layers. The thickness of the DBR layer is 3 μm to 4 μm.
[0129] The second step is to etch the passivation layer to form vias on the surface of the passivation layer that expose the finger electrode and the plate electrode.
[0130] The third step is to form at least two pads on the passivation layer, and the at least two pads are connected to the plate electrode and the finger electrode through vias, respectively.
[0131] Optionally, the pad includes a first Ti layer, an Al layer, a second Ti layer, a Pt layer, a Ni layer, and an Au layer stacked sequentially.
[0132] For example, the thickness of the first Ti layer is 20 to 100 angstroms. For instance, the thickness of the first Ti layer is 50 angstroms.
[0133] For example, the thickness of the Al layer is between 10,000 and 20,000 angstroms. For instance, the thickness of the Al layer is 15,000 angstroms.
[0134] For example, the thickness of the second Ti layer is between 500 angstroms and 1500 angstroms. For instance, the thickness of the second Ti layer is 1000 angstroms.
[0135] For example, the thickness of the Pt layer is between 500 angstroms and 1500 angstroms. For instance, the thickness of the Pt layer is 1000 angstroms.
[0136] For example, the thickness of the Ni layer is 6,000 to 8,000 angstroms. For instance, the thickness of the Ni layer is 7,000 angstroms.
[0137] For example, the thickness of the Au layer is between 1500 angstroms and 2500 angstroms. For instance, the thickness of the Au layer is 2000 angstroms.
[0138] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A light-emitting diode, characterized in that, The light-emitting diode includes an epitaxial layer (10) and a planar electrode (20). The planar electrode (20) is located on the top surface of the epitaxial layer (10). The ratio of the projected area of the planar electrode (20) on the top surface of the epitaxial layer (10) to the area of the top surface of the epitaxial layer (10) is greater than or equal to 0.
7.
2. The light-emitting diode according to claim 1, characterized in that, The top surface of the epitaxial layer (10) has a groove (14), and the flat plate electrode (20) is located outside the groove (14). The ratio of the orthographic projection area of the groove (14) on the bottom surface of the epitaxial layer (10) to the bottom surface area of the epitaxial layer (10) is less than or equal to 0.
2.
3. The light-emitting diode according to claim 2, characterized in that, The groove (14) is located at the peripheral edge of the top surface of the epitaxial layer (10); The light-emitting diode also includes a finger electrode (30) located within the groove (14).
4. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The flat plate electrode (20) includes at least one of Ag layer, Al layer and aluminum alloy layer.
5. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The light-emitting diode further includes a transparent conductive layer (41), which is located on the top surface of the epitaxial layer (10), and the planar electrode (20) is located on the surface of the transparent conductive layer (41) away from the epitaxial layer (10). The orthographic projection of the flat plate electrode (20) on the top surface of the epitaxial layer (10) lies within the orthographic projection of the transparent conductive layer (41) on the top surface of the epitaxial layer (10).
6. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The light-emitting diode further includes a current blocking layer (42), which is located on the top surface of the epitaxial layer (10), and the planar electrode (20) is located on the surface of the current blocking layer (42) away from the epitaxial layer (10). The current blocking layer (42) is in the form of a mesh; or, The current blocking layer (42) comprises a plurality of spaced-apart block structures; or, The current blocking layer (42) includes multiple concentrically arranged annular structures.
7. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The surface of the flat electrode (20) has a plurality of spaced through holes (21), and the through holes (21) are filled with an ohmic contact material layer (22).
8. The light-emitting diode according to claim 7, characterized in that, The light-emitting diode further includes a passivation layer (43) and a pad (50). The passivation layer (43) is located on the top surface of the epitaxial layer (10) and the planar electrode (20). The surface of the passivation layer (43) has a via that exposes the planar electrode (20). The pad (50) is located on the surface of the passivation layer (43) and is connected to the planar electrode (20) through the via. The positive projection area of the pad (50) on the bottom surface of the epitaxial layer (10) is smaller than the positive projection area of the flat electrode (20) on the bottom surface of the epitaxial layer (10).
9. The light-emitting diode according to claim 8, characterized in that, The distribution density of the vias (21) on the flat electrode (20) located within the orthographic projection of the pad (50) on the flat electrode (20) is less than the distribution density of the vias (21) on the flat electrode (20) located outside the orthographic projection of the pad (50) on the flat electrode (20).
10. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: An epitaxial layer (10) is prepared on a substrate (60); A planar electrode (20) is formed on the top surface of the epitaxial layer (10), and the ratio of the projected area of the planar electrode (20) on the top surface of the epitaxial layer (10) to the area of the top surface of the epitaxial layer (10) is greater than or equal to 0.7.