Display module, preparation method of display module and display device

Abstract

This application provides a display module, a method for fabricating the display module, and a display device, solving the technical problem of low bonding yield between the display module and the CMOS chip, and avoiding the cumbersome process and yield loss caused by the three-time bonding and three-time substrate removal required for the three-color light-emitting layer. In this display module, a filler layer surrounds and forms a pixel window; multiple light-emitting structures within the pixel window are stacked vertically, and the epitaxial buffer layer and the side of each light-emitting structure facing away from the substrate have connection areas; a bonding layer is disposed on the side of the filler layer facing away from the substrate; multiple electrodes penetrate the bonding layer and are connected to the corresponding connection areas; the side of the bonding layer facing away from the substrate has a bonding surface, and the ends of the multiple electrodes facing away from the substrate are flush with the bonding surface. This application uses a filler layer to achieve selective growth of the light-emitting region, realizing etching-free formation of the light-emitting structure, reducing sidewall damage of the light-emitting structure, and improving luminous efficiency; in addition, it improves the bonding yield between the display module and the CMOS chip.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display module, a method for preparing the display module, and a display device. Background Technology

[0002] Micro LED displays, compared to other display technologies currently on the market for augmented reality (AR) products, offer advantages such as high brightness, low power consumption, fast response speed, high contrast, high resolution, and high color saturation. Furthermore, they can be integrated with CMOS chips such as complementary metal-oxide-semiconductor (CMOS) monoliths, making them one of the most ideal light-emitting technologies for AR displays in the industry.

[0003] In related technologies, Micro LED display devices include a substrate and a three-color light-emitting epitaxial layer disposed on the substrate. The three-color light-emitting epitaxial layer includes a blue light-emitting structure, a green light-emitting structure and a red light-emitting structure stacked sequentially. The blue light-emitting structure is disposed on the side close to the light-emitting surface. The blue light-emitting structure, the green light-emitting structure and the red light-emitting structure are respectively metal-bonded to CMOS chips such as CMOS chips through their corresponding electrodes.

[0004] However, in related technologies, the tri-color emitting epitaxial layers are stacked by metal layer bonding, which requires three wafer bonding and substrate removal processes, which is cumbersome and affects the mass production yield. Summary of the Invention

[0005] In view of the above problems, this application provides a display module, a method for manufacturing the display module, and a display device, which can improve the bonding efficiency between the display module and the CMOS chip.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] The first aspect of this application provides a display module, including:

[0008] Substrate;

[0009] Epitaxial buffer layer;

[0010] A fill layer is used to enclose and form a pixel window;

[0011] The pixel window has multiple light-emitting structures, which are stacked sequentially along a direction perpendicular to the substrate. The epitaxial buffer layer and the side of each light-emitting structure facing away from the substrate have connection areas, and each connection area is not covered by other light-emitting structures.

[0012] A bonding layer is disposed on the side of the filler layer opposite to the substrate;

[0013] Multiple electrodes, each of which penetrates the bonding layer and is connected to a corresponding connection region, with one electrode corresponding to one connection region;

[0014] The bonding layer has a bonding surface on the side facing away from the substrate, and the ends of the plurality of electrodes facing away from the substrate are flush with the bonding surface. The bonding surface is configured to bond with the CMOS chip.

[0015] In some embodiments, the filling layer is provided with a plurality of filling portions;

[0016] Multiple filling portions are disposed within the pixel window, and the multiple filling portions are respectively disposed on multiple connection areas and connected to the bonding layer; one filling portion is correspondingly disposed on one connection area.

[0017] Each electrode passes through the corresponding filling portion and is connected to the corresponding connection area.

[0018] In some embodiments, the cross-sectional shape of the pixel window is polygonal along the direction parallel to the substrate, and the projections of the connection areas of the plurality of light-emitting structures within the pixel window are respectively located at different corners of the polygon along the direction perpendicular to the substrate.

[0019] In some embodiments, the plurality of light-emitting structures include, from the substrate upward, a blue light-emitting structure, a green light-emitting structure, and a red light-emitting structure stacked sequentially;

[0020] The epitaxial buffer layer has a first connection region; the blue light emitting structure has a second connection region, the green light emitting structure has a third connection region, and the red light emitting structure has a fourth connection region;

[0021] Along the direction parallel to the substrate, the cross-sectional shape of the pixel window is a quadrilateral, and the projections of the first connection area, the second connection area, the third connection area and the fourth connection area in the pixel window are respectively located at the four corners of the quadrilateral;

[0022] The plurality of filling portions include a first filling portion, a second filling portion, a third filling portion, and a fourth filling portion, wherein the first filling portion is disposed in the first connecting region, the second filling portion is disposed in the second connecting region, the third filling portion is disposed in the third connecting region, and the fourth filling portion is disposed in the fourth connecting region.

[0023] In some embodiments, the epitaxial buffer layer includes a buffer layer, a doped layer, and a first N-type doped conductive layer stacked sequentially, wherein the connection region on the epitaxial buffer layer is disposed on the surface of the first N-type doped conductive layer facing away from the substrate; and / or,

[0024] The light-emitting structure includes a light-emitting layer, a P-type doped layer, and a second N-type doped conductive layer stacked sequentially; the connection region on the light-emitting structure is disposed on the surface of the second N-type doped conductive layer facing away from the substrate.

[0025] A second aspect of this application provides a method for manufacturing a display module, comprising:

[0026] An epitaxial buffer layer is formed on a substrate, the epitaxial buffer layer having a connection region;

[0027] A fill layer is formed on the epitaxial buffer layer, and the fill layer is patterned to form a pixel window, the pixel window exposing the connection area of ​​the epitaxial buffer layer;

[0028] Multiple light-emitting structures are formed within the pixel window. The multiple light-emitting structures are stacked sequentially along a direction perpendicular to the substrate. The multiple light-emitting structures do not cover the connection area of ​​the epitaxial buffer layer. Each light-emitting structure has a connection area on the side facing away from the substrate. Each connection area is not covered by other light-emitting structures.

[0029] A bonding layer is formed on the filler layer, and the bonding layer has a bonding surface on the side opposite to the substrate;

[0030] Multiple electrodes are formed, each of which penetrates the bonding layer and is connected to each of the connection regions. Each electrode corresponds to one connection region, and the end of each electrode facing away from the substrate is flush with the bonding surface. The bonding surface is configured to bond with the CMOS chip.

[0031] In some embodiments, before forming a plurality of light-emitting structures within the pixel window, the method further includes:

[0032] A filling portion is formed in the connection area on the epitaxial buffer layer, and the filling portion is connected to the inner wall of the pixel window.

[0033] In some embodiments,

[0034] Multiple light-emitting structures are formed within the pixel window, including blue light-emitting structures, green light-emitting structures, and red light-emitting structures stacked sequentially. The specific method includes:

[0035] A blue light-emitting structure is formed within the pixel window using an epitaxial growth process and a deposition process.

[0036] A filling portion is formed on the connection area of ​​the blue light-emitting structure using a deposition process. The filling portion covers the connection area of ​​the blue light-emitting structure and is connected to the inner wall of the pixel window.

[0037] A green light-emitting structure is formed on the surface of the blue light-emitting structure exposed within the pixel window using an epitaxial growth process.

[0038] A filling portion is formed on the connection area of ​​the green light-emitting structure using a deposition process, and the filling portion covers the connection area of ​​the green light-emitting structure.

[0039] A red light-emitting structure is formed on the green light-emitting structure exposed within the pixel window using an epitaxial growth process;

[0040] A filling portion is formed in the connection area of ​​the red light-emitting structure using a deposition process.

[0041] In some embodiments, after forming a bonding layer on the filler layer, the method further includes:

[0042] An etching process is used to form multiple electrode holes, each of which penetrates the bonding layer and exposes the connection region of the corresponding light-emitting structure.

[0043] Conductive material is formed within each of the electrode holes to form an electrode;

[0044] The bonding layer is planarized on the side away from the substrate using CMP process to form a bonding surface, and the ends of the multiple electrodes formed that are away from the substrate are flush with the bonding surface.

[0045] In some embodiments, prior to forming a conductive material within each of the electrode holes, the method further includes:

[0046] An ohmic contact layer is formed in each of the electrode holes using a metal electrode evaporation or sputtering process;

[0047] A barrier layer is formed on the surface of the ohmic contact layer within each of the electrode holes and on the inner wall of the electrode holes.

[0048] The third aspect of this application provides a display device, a CMOS chip, and a display module as provided in the above embodiments, or a display module formed by the manufacturing method of the display module provided in the above embodiments;

[0049] The CMOS chip and the display module are bonded together using a metal bonding process.

[0050] In the display module provided in this application embodiment, a filling layer disposed on an epitaxial buffer layer is formed into a pixel window. Multiple light-emitting structures are stacked sequentially along a direction perpendicular to the substrate. Both the epitaxial buffer layer and the side of each light-emitting structure facing away from the substrate have connection areas. The connection areas of the epitaxial buffer layer are not covered by the multiple light-emitting structures, and the connection areas on each light-emitting structure are not covered by other light-emitting structures. A bonding layer is disposed on the side of the filling layer facing away from the substrate. Multiple electrodes penetrate the bonding layer and are connected to the multiple connection areas, with one electrode corresponding to one connection area. The side of the bonding layer facing away from the substrate has a bonding surface. By designing a bonding layer, the ends of the multiple electrodes facing away from the substrate are flush with the bonding surface. Thus, the multiple electrodes can be bonded to the CMOS chip through the bonding surface of the bonding layer using a single bonding process, enabling the multiple electrodes to be electrically connected to the CMOS chip. The three color light-emitting structures are connected through epitaxial growth and a tunnel junction method, enabling mass production-ready one-time wafer-level metal bonding. Compared to the three-color light-emitting structure which is connected to the CMOS chip through a three-time bonding process, this significantly reduces the number of process steps and improves the bonding yield between the display module and the CMOS chip. In addition, the one-time bonding process reduces the failure points of multiple bonding processes, while improving the uniformity of the bonding interface and the overall yield.

[0051] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the display module, the method for preparing the display module, and the display device provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of a display module provided in an embodiment of this application;

[0054] Figure 2 A schematic diagram of a structure in which a display module and a CMOS chip are bonded together, as provided in an embodiment of this application;

[0055] Figure 3 This is a schematic flowchart of a method for manufacturing a display module provided in an embodiment of this application;

[0056] Figure 4 This is a top view schematic diagram of the formation of an epitaxial buffer layer on a substrate in the preparation method provided in the embodiments of this application;

[0057] Figure 5 for Figure 4 Schematic diagram of the cross section at point AA;

[0058] Figure 6 This is a top view schematic diagram of the blue light-emitting structure formed in the preparation method provided in the embodiments of this application;

[0059] Figure 7 for Figure 6 Schematic diagram of the cross section at point AA;

[0060] Figure 8 This is a top view schematic diagram of the preparation method for forming a green light-emitting structure provided in the embodiments of this application;

[0061] Figure 9 for Figure 8 Schematic diagram of the cross section at point AA;

[0062] Figure 10 This is a top view schematic diagram of the preparation method for forming a red light-emitting structure provided in the embodiments of this application;

[0063] Figure 11 for Figure 10 Schematic diagram of the cross section at point BB;

[0064] Figure 12 This is a top view schematic diagram of the formation of the bonding layer and electrode holes in the preparation method provided in the embodiments of this application;

[0065] Figure 13 for Figure 12 Schematic diagram of the cross section at point AA;

[0066] Figure 14 for Figure 12 Schematic diagram of the cross section at point BB;

[0067] Figure 15 This is a cross-sectional schematic diagram of the bonding layer formed in the preparation method provided in the embodiments of this application;

[0068] Figure 16This is a cross-sectional schematic diagram of the electrode hole formed in the preparation method provided in the embodiments of this application;

[0069] Figure 17 This is a cross-sectional schematic diagram of the formation of an ohmic contact layer in the electrode hole in the preparation method provided in the embodiments of this application;

[0070] Figure 18 This is a cross-sectional schematic diagram of the barrier layer formed in the electrode hole in the preparation method provided in the embodiments of this application.

[0071] Figure label:

[0072] 100 - Display module; 110 - Substrate;

[0073] 120 - Epitaxial buffer layer; 121 - Buffer layer; 122 - Doped layer; 123 - First N-type doped conductive layer;

[0074] 130 - Filler layer; 131 - Filler portion; 131a - First filler portion; 131b - Second filler portion;

[0075] 131c - Third padding section; 131d - Fourth padding section; 132 - Pixel window;

[0076] 140 - Light-emitting structure; 140a - Blue light-emitting structure; 140b - Green light-emitting structure; 140c - Red light-emitting structure;

[0077] 141 - Connection region; 141a - First connection region; 141b - Second connection region; 141c - Third connection region;

[0078] 141d - Fourth Connection Region;

[0079] 142 - Emissive layer; 142a - Blue emissive layer; 142b - Green emissive layer; 142c - Red emissive layer;

[0080] 143 - P-type doped layer; 144 - Second N-type doped conductive layer;

[0081] 150 - Bonding layer; 151 - Electrode hole; 151a - First electrode hole; 151b - Second electrode hole; 151c - Third electrode hole; 151d - Fourth electrode hole;

[0082] 160 - Electrode; 160a - First electrode; 160b - Second electrode; 160c - Third electrode; 160d - Fourth electrode;

[0083] 170-ohm contact layer; 180-barrier layer;

[0084] 200-CMOS chip. Detailed Implementation

[0085] In related technologies, Micro LED display devices include a substrate and a three-color light-emitting epitaxial layer disposed on the substrate. The three-color light-emitting epitaxial layer includes a blue light-emitting structure, a green light-emitting structure, and a red light-emitting structure stacked sequentially. The blue light-emitting structure is disposed on the side closer to the light-emitting surface. The blue light-emitting structure, the green light-emitting structure, and the red light-emitting structure are bonded to the CMOS chip through their corresponding electrodes. During the bonding process, the three electrodes corresponding to the three-color light-emitting epitaxial layer need to be bonded to the CMOS chip through three bonding processes. Each bonding may cause damage to the interlayer interface, which increases the complexity of the process and leads to technical problems such as low manufacturing efficiency and low yield.

[0086] To address the aforementioned problems, the inventors of this application provide a display module that overcomes the need for multiple bonding processes for multiple light-emitting layers. This module comprises a bonding layer disposed on a filler layer surrounding a pixel window. The bonding layer has a bonding surface on its side facing away from the filler layer. Multiple electrodes pass through the bonding layer and connect to the connection areas of each light-emitting structure within the pixel window. The ends of the electrodes facing away from the filler layer are flush with the bonding surface of the bonding layer, ensuring that the ends to be bonded are located on the same bonding plane. This allows for a single bonding process between the bonding surface and the CMOS chip, enabling electrical conduction between the electrodes and the CMOS chip. The three-color light-emitting structures are connected via epitaxial growth and tunnel junctions, achieving mass production through a single wafer-level metal bonding process. Compared to connecting the three-color light-emitting structures to the CMOS chip via a three-step bonding process, this significantly reduces process steps and improves the bonding yield between the display module and the CMOS chip. Furthermore, the single-step bonding process reduces failure points associated with multiple bonding processes and improves the uniformity of the bonding interface and overall yield.

[0087] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0088] Please refer to Figure 1 and Figure 2 As shown, this application embodiment provides a display module 100, which includes, but is not limited to, a Micro LED display module. The display module 100 includes a substrate 110, wherein the substrate 110 includes, but is not limited to, a sapphire substrate.

[0089] An epitaxial buffer layer 120 is formed on the substrate 110. For example, the epitaxial buffer layer 120 includes a buffer layer 121, a doped layer 122 and a first N-type doped conductive layer 123 stacked sequentially along a direction perpendicular to the substrate 110. The buffer layer 121 may be an aluminum nitride (AlN) layer, the doped layer 122 may be a gallium nitride (GaN) layer, and the first N-type doped conductive layer 123 may be an aluminum gallium nitride (AlGaN) conductive layer doped with n-type ions.

[0090] In some embodiments, the thickness of the first N-type doped conductive layer 123 can be about 1 μm. When all the light-emitting structures 140 on the epitaxial buffer layer 120 are lit, all the current flows through the layer and is conducted out along the direction parallel to the substrate 110 to achieve current expansion.

[0091] Please continue to refer to Figure 1 and Figure 2 As shown, a filling layer 130 is provided on the epitaxial buffer layer 120. The filling layer 130 has a plurality of pixel windows 132 arranged in an array. Each pixel window 132 has a plurality of light-emitting structures 140. The plurality of light-emitting structures 140 are stacked sequentially along a direction perpendicular to the substrate 110.

[0092] For example, the plurality of light-emitting structures 140 include a blue light-emitting structure 140a, a green light-emitting structure 140b and a red light-emitting structure 140c stacked in sequence, wherein the blue light-emitting structure 140a is disposed on the side close to the substrate 110, and the green light-emitting structure 140b is disposed between the blue light-emitting structure 140a and the red light-emitting structure 140c.

[0093] In some embodiments, please refer to Figure 15 As shown, the light-emitting structure 140 includes a light-emitting layer 142, a P-type doped layer 143, and a second N-type doped conductive layer 144 stacked sequentially along the direction perpendicular to the substrate 110; the connection region 141 on the light-emitting structure 140 is disposed on the surface of the second N-type doped conductive layer 144 on the side away from the substrate 110, wherein the light-emitting layer 142 is a light-emitting layer 142 corresponding to each light-emitting structure 140 that can emit different colors of light; for example, the blue light-emitting structure 140a includes a blue light-emitting layer 142a, a P-type doped layer 143, and a second N-type doped conductive layer 144 stacked sequentially; the green light-emitting structure 140b includes a green light-emitting layer 142b, a P-type doped layer 143, and a second N-type doped conductive layer 144 stacked sequentially; and the red light-emitting structure 140c includes a red light-emitting layer 142c, a P-type doped layer 143, and a second N-type doped conductive layer 144 stacked sequentially.

[0094] The P-type doped layer 143 includes at least one layer of aluminum gallium nitride (AlGaN) doped with P-type ions and at least two layers of gallium nitride (GaN) doped with P-type ions. The concentration of P-type ions in the at least two layers of gallium nitride (GaN) doped with P-type ions is different. For example, the doping concentration of the at least two layers of gallium nitride (GaN) doped with P-type ions gradually increases from bottom to top along the direction perpendicular to the substrate 110. The second N-type doped conductive layer 144 includes at least one layer of indium gallium nitride (InGaN) doped with n-type ions and at least one layer of aluminum gallium nitride (AlGaN) doped with n-type ions stacked sequentially. The thickness of the aluminum gallium nitride (AlGaN) layer doped with n-type ions can be 0.4 μm, and the thickness of the indium gallium nitride (InGaN) layer doped with n-type ions can be 30 nm.

[0095] In this embodiment, by providing a second N-type doped conductive layer 144 above each light-emitting structure 140 and a first N-type doped conductive layer 123 above the epitaxial buffer layer 120, compared to the traditional gallium nitride (GaN) layer doped with P-type ions, the second N-type doped conductive layer 144 and the first N-type doped conductive layer 123 respectively contact the corresponding electrode 160, resulting in lower resistivity and better lateral current expansion, thereby improving the current injection uniformity of the light-emitting area and the electro-optical conversion efficiency of the entire display module 100.

[0096] In addition, the epitaxial buffer layer 120 and each light-emitting structure 140 have a connection region 141 on the side away from the substrate 110. The connection region 141 on the epitaxial buffer layer 120 is located within the pixel window 132 but is not covered by the multiple light-emitting structures 140 within the pixel window 132, and the connection region 141 on each light-emitting structure 140 is not covered by other light-emitting structures 140 located on that light-emitting structure 140.

[0097] In some embodiments, please continue to refer to Figure 15 As shown, along the direction parallel to the substrate 110, the cross-sectional shape of each pixel window 132 is polygonal, and the projections of the connection areas 141 of the multiple light-emitting structures 140 in the direction perpendicular to the substrate 110 are respectively located at different corners of the polygon; for example, along the direction parallel to the substrate 110, the cross-sectional shape of the pixel window 132 is quadrilateral, the epitaxial buffer layer 120 has a first connection area 141a; the blue light-emitting structure 140a has a second connection area 141b, the green light-emitting structure 140b has a third connection area 141c, and the red light-emitting structure 140c has a fourth connection area 141d; the projections of the first connection area 141a, the second connection area 141b, the third connection area 141c, and the fourth connection area 141d in the pixel window 132 are respectively located at the four corners of the quadrilateral.

[0098] In some embodiments, a plurality of filling portions 131 are provided on the filling layer 130. The plurality of filling portions 131 are disposed within the pixel window 132 and are respectively disposed on a plurality of connection regions 141. One filling portion 131 corresponds to one connection region 141. By providing filling portions 131 on the connection regions 141, when fabricating each layer of light-emitting structure 140 within the pixel window 132, filling portions 131 can be first fabricated on the epitaxial buffer layer 120 of the previous layer or on the connection region 141 of the light-emitting structure 140 to pattern the image within the pixel window 132. Then, the next layer of light-emitting structure 140 is deposited. In this way, the pattern within the pixel window 132 can be changed by the filling portions 131. The formation of multiple layers of light-emitting structure 140 can be achieved by deposition alone, without the need to etch each light-emitting structure 140. This reduces the etching damage to the sidewalls of the light-emitting structure 140 and improves the yield of the display module 100.

[0099] It should be noted that the filling portion 131 is a structure in the filling layer 130 used to cover the connection area 141, which serves to prevent the etching from damaging the light-emitting structure 140, and at the same time provides a mask for the selective growth of the multilayer light-emitting structure 140.

[0100] In this embodiment, the filling portion 131 supports precise patterning by optimizing its shape and distribution, avoiding damage to the sidewalls caused by traditional etching processes, and improving luminous efficiency.

[0101] In some embodiments, the display module 100 further includes a bonding layer 150 and a plurality of electrodes 160. The bonding layer 150 is disposed on the filling layer 130 and connected to each filling portion 131. The side of the bonding layer 150 facing away from the substrate 110 has a bonding surface. The plurality of electrodes 160 are respectively disposed in one-to-one correspondence with the plurality of filling portions 131, that is, one electrode 160 corresponds to one filling portion 131. The plurality of electrodes 160 sequentially penetrate the bonding layer 150 and the corresponding filling portion 131 and are connected to the corresponding connection area 141. The end of the plurality of electrodes 160 facing away from the substrate 110 is flush with the bonding surface. The bonding surface is configured to be bonded to the CMOS chip 200.

[0102] The bonding surface is the surface of the bonding layer 150 that contacts the external CMOS chip, and electrical connection is achieved through metal bonding process.

[0103] In this embodiment, the bonding surface is formed by a planarization process (CMP), enabling multiple electrodes 160 to be bonded together in one step on the same plane.

[0104] Therefore, in this embodiment, by providing a bonding layer 150 on the filling layer 130, multiple electrodes 160 sequentially penetrate the bonding layer 150 and their corresponding filling portions 131 to connect to the connection area 141 on the corresponding light-emitting structure 140. The ends of the multiple electrodes 160 facing away from the substrate 110 are flush with the bonding surface of the bonding layer 150. In this way, the multiple electrodes 160 can be bonded to the CMOS chip 200 through the bonding surface of the bonding layer 150 in a single bonding process, so that the multiple electrodes 160 are electrically connected to the CMOS chip 200 respectively. This eliminates the need for the multiple electrodes 160 to be bonded to the CMOS chip 200 through multiple bonding processes, thereby achieving mass production wafer-level metal bonding and improving the efficiency and yield of bonding between the display module 100 and the CMOS chip 200.

[0105] This application also provides a method for manufacturing a display module, which can be used to manufacture the display module 100 provided in the above embodiments. Please refer to [link / reference]. Figure 3 As shown, the preparation method includes:

[0106] Step S101: An epitaxial buffer layer is formed on the substrate, the epitaxial buffer layer having a connection region.

[0107] Step S102: A fill layer is formed on the epitaxial buffer layer, and the fill layer is patterned to form a pixel window, which exposes the connection area of ​​the epitaxial buffer layer.

[0108] Step S103: Multiple light-emitting structures are formed within the pixel window. The multiple light-emitting structures are stacked sequentially along a direction perpendicular to the substrate. The multiple light-emitting structures do not cover the connection area of ​​the epitaxial buffer layer. Each light-emitting structure has a connection area on the side facing away from the substrate. Each connection area is not covered by other light-emitting structures.

[0109] Step S104: Form a bonding layer on the filler layer, the side of the bonding layer opposite to the substrate having a bonding surface.

[0110] Step S105: Form multiple electrodes, each of which penetrates the bonding layer and connects to a connection region. Each electrode corresponds to a connection region, and the end of each electrode facing away from the substrate is flush with the bonding surface. The bonding surface is configured to bond with the CMOS chip.

[0111] Please combine Figures 4 to 18 , Figure 1 and Figure 2 As shown, before forming multiple light-emitting structures 140 within the pixel window 132, the method further includes: forming a filling portion 131 in the connection region 141 on the epitaxial buffer layer 120, wherein the filling portion 131 is connected to the inner wall of the pixel window 132.

[0112] In addition, before epitaxially growing the next layer of light-emitting structure 140 on the light-emitting structure 140 already formed by epitaxial growth process within the pixel window 132, a corresponding filling portion 131 is first deposited on the connection area 141 of the already epitaxially grown light-emitting structure 140. In this way, the filling portion 131 can be used as a mask, and then the next layer of light-emitting structure 140 can be grown by epitaxial growth process. That is, the filling portion 131 is used to achieve selective growth of the light-emitting area, without the need to use etching process to etch the light-emitting structure 140, thereby avoiding the damage to the sidewall of the light-emitting structure 140 caused by etching, thereby improving the yield and working performance of the display module 100 and improving the luminous efficiency.

[0113] In some embodiments, after forming the bonding layer 150 on the filler layer 130, the method further includes: using an etching process to form a plurality of electrode holes 151, each electrode hole 151 penetrating the bonding layer 150 and exposing the connection region 141 of each corresponding light-emitting structure 140; forming a conductive material in each electrode hole 151 to form an electrode 160; and then using a mechanical polishing process to planarize the surface of the bonding layer 150 on the side away from the substrate 110 to form a bonding surface, and making the end of the plurality of electrodes 160 away from the substrate 110 flush with the bonding surface.

[0114] In addition, in some embodiments, before forming conductive material in each electrode hole 151, an ohmic contact layer 170 is formed in each electrode hole 151 by evaporation or sputtering of a metal electrode 160; and a barrier layer 180 is formed on the surface of the ohmic contact layer 170 in each electrode hole 151 and on the inner wall of the electrode hole 151.

[0115] The following will describe in detail the fabrication method of the above-mentioned display module 100 using multiple light-emitting structures 140, including a blue light-emitting structure 140a, a green light-emitting structure 140b, and a red light-emitting structure 140c, as an example. For ease of description, the connection region 141 on the epitaxial buffer layer 120 is referred to as the first connection region 141a, the connection region 141 on the blue light-emitting structure 140a is referred to as the second connection region 141b, and the connection region 141 on the green light-emitting structure 140b is referred to as the third connection region 141a. The connection region 141c is referred to as the fourth connection region 141d on the red light emitting structure 140c. The filling portion 131 located on each connection region 141 is also referred to as the first filling portion 131a, the second filling portion 131b, the third filling portion 131c and the fourth filling portion 131d respectively. The electrode 160 used to connect each connection region 141 is also referred to as the first electrode 160a, the second electrode 160b, the third electrode 160c and the fourth electrode 160d respectively.

[0116] Please combine Figure 4 and Figure 5As shown, firstly, a buffer layer 121 is grown on a substrate 110. The buffer layer 121 includes, but is not limited to, an AlN buffer layer 121. A doped layer 122 is formed on the buffer layer 121. The material of the doped layer 122 includes, but is not limited to, GaN. Then, a first N-type doped conductive layer 123 is formed on the doped layer 122. The buffer layer 121, the doped layer 122, and the first N-type doped conductive layer 123, which are stacked sequentially, together form an epitaxial buffer layer 120.

[0117] When all three light-emitting structures—blue light-emitting structure 140a, green light-emitting structure 140b, and red light-emitting structure 140c—are lit, all the current flows out laterally through the first N-type doped conductive layer 123. Therefore, a thickness of 1 μm is required for current extension.

[0118] Please combine Figure 6 and Figure 7 As shown, after forming the epitaxial buffer layer 120 on the substrate 110 and before growing the blue light-emitting structure 140a on the epitaxial buffer layer 120, firstly, a filling layer 130 is formed on the substrate 110, for example, silicon dioxide (SiO2), on the first N-type doped conductive layer 123. Photoresist is then coated on the filling layer 130, and the photoresist is patterned. Using the patterned photoresist as a mask, the filling layer 130 is patterned to form a plurality of pixel windows 132 arranged in an array on the filling layer 130. Thus, the retained filling layer 130 can be used to cover the areas between different pixels, and the filling material of the connection region 141 on the first N-type doped conductive layer 123 is retained to form the first filling portion 131a (e.g., ...). Figure 6 As shown in the diagram, the location of the first filling portion 131a is the area where the first electrode 160a is subsequently formed.

[0119] Understandably, each pixel window 132 exposes an area to be grown and formed into a light-emitting structure 140, while the area to be subsequently formed into the first electrode 160a is covered by the reserved filling layer 130 (i.e., the first filling portion 131a). The aspect ratio of the width of each pixel window 132 formed in the filling layer 130 in the horizontal direction to the depth of the first electrode 160a in the direction perpendicular to the substrate 110 can be controlled within the range of 2:1 to 3:1, which conforms to the actual process capabilities of current semiconductor technology.

[0120] Please continue to combine Figure 6 and Figure 7As shown, after forming the pixel window 132, i.e., the first filling portion 131a located within the pixel window 132, a blue light-emitting structure 140a is grown within the pixel window 132 by an epitaxial growth process. For example, firstly, a blue light-emitting layer 142a is formed on the first N-type doped conductive layer 123. The material of the blue light-emitting layer 142a includes, but is not limited to, blue indium gallium nitride (InGaN) material. Then, a P-type doped layer 143 and a second N-type doped conductive layer 144 are deposited on the blue light-emitting layer 142a. For example, the P-type doped layer 143 includes an electron blocking layer (e.g., an aluminum gallium nitride layer), a p-type doped conductive layer, and a p+ type highly doped layer with a thickness of 10 nm stacked sequentially. The second N-type doped conductive layer 144 includes an n-type doped layer with a thickness of 30 nm and an n-type doped conductive layer with a thickness of 0.4 μm.

[0121] In this structure, a tunnel junction is formed between the 30nm thick n-type doped layer and the 10nm thick p-type highly doped layer, meaning that electrons are injected from the n-type doped layer into the p-type highly doped layer through the quantum tunneling principle, generating holes.

[0122] Please combine Figure 8 and Figure 9 As shown, after forming the blue light-emitting structure 140a and before growing the green light-emitting structure 140b, silicon dioxide material is first deposited in the connection region 141 of the blue light-emitting structure 140a to form a second filling portion 131b. The second filling portion 131b covers and reserves the area for the subsequent formation of the second electrode 160b (e.g., ...). Figure 8 (as shown in the image).

[0123] Next, using the second filling portion 131b as a mask, a green light-emitting structure 140b is grown on the blue light-emitting structure 140a exposed within the pixel window 132. Please refer to... Figure 9 As shown, the green light-emitting structure 140b includes a green light-emitting layer 142b. The material of the green light-emitting layer 142b includes green indium gallium nitride (InGaN) material. Subsequently, a P-type doped layer 143 and a second N-type doped conductive layer 144 are deposited on the green light-emitting layer 142b. For example, the P-type doped layer 143 includes an electron blocking layer (e.g., an aluminum gallium nitride layer), a p-type doped conductive layer, and a p+ type highly doped layer with a thickness of 10 nm stacked sequentially. The second N-type doped conductive layer 144 includes an n-type doped layer with a thickness of 30 nm and an n-type doped conductive layer with a thickness of 0.4 μm.

[0124] In this structure, a tunnel junction is formed between the 30nm thick n-type doped layer and the 10nm thick p-type highly doped layer. Electrons are injected from the n-type doped layer into the p-type highly doped layer through the quantum tunneling principle, generating holes and achieving conductivity.

[0125] Please combine Figure 10 and Figure 11 As shown, after forming the green light-emitting structure 140b and before growing the red light-emitting structure 140c, silicon dioxide material is deposited in the connection region 141 of the green light-emitting structure 140b to form the third filling portion 131c. The third filling portion 131c covers and reserves the area for the subsequent formation of the third electrode 160c (e.g., ...). Figure 10 (as shown in the image).

[0126] Next, using the third filling portion 131c as a mask, a red light emitting structure 140c is grown on the green light emitting structure 140b exposed within the pixel window 132. Please refer to... Figure 11 As shown, the red light-emitting structure 140c includes a red light-emitting layer 142c. The material of the red light-emitting layer 142c includes red indium gallium nitride (InGaN). Subsequently, a P-type doped layer 143 and a second N-type doped conductive layer 144 are deposited on the red light-emitting layer 142c. For example, the P-type doped layer 143 includes an electron blocking layer (e.g., an aluminum gallium nitride layer), a p-type doped conductive layer, and a 10 nm thick p+ type highly doped layer stacked sequentially. The second N-type doped conductive layer 144 includes a 30 nm thick n-type doped layer and a 0.4 μm thick n-type doped conductive layer. A tunnel junction is formed between the 30 nm thick n-type doped layer and the 10 nm thick p-type highly doped layer, that is, electrons are injected from the n-type doped layer into the p-type highly doped layer through the quantum tunneling principle, generating holes and achieving conductivity.

[0127] It should be noted that a tunnel junction is a structure based on the quantum mechanical tunneling effect, typically composed of highly doped p-type and n-type semiconductor layers. Through the quantum tunneling effect, electrons can tunnel from the n-type layer to the p-type layer under reverse voltage, creating holes.

[0128] By using a tunnel junction to bring the metal electrode into contact with the n-type doped AlGaN, it exhibits lower resistivity and better lateral current spread characteristics compared to the traditional p-type GaN layer.

[0129] Please combine Figure 15 As shown, silicon dioxide material is then deposited on the red light-emitting structure 140 to form a fourth filling portion 131d in the connection region 141 of the red light-emitting structure 140. The fourth filling portion 131d covers and reserves the area for the subsequent formation of the fourth electrode 160d. Then, silicon dioxide material is deposited again to form a bonding layer 150, so that the bonding covers the entire wafer (e.g., Figure 15 As shown in the figure, the bonding layer 150 is located in the filling layer 130 and covers the filling layer 130 and all light-emitting structures 140, etc. It should be noted that the deposition of the fourth filling part 131d and the subsequent formation of the bonding layer 150 can be formed simultaneously.

[0130] After the bonding layer 150 is formed, the surface of the bonding layer 150 can be planarized by chemical mechanical polishing (CMP) to facilitate subsequent photolithography processes.

[0131] It is understandable that the thickness of silicon dioxide material is uneven when depositing it on the whole surface. The surface planarization required for photolithography can also be achieved through CMP process. The planarized surface can also be used as the bonding surface of bonding layer 150 so that bonding layer 150 can be bonded to CMOS chip 200 in the future.

[0132] Please combine Figure 12 , Figure 13 , Figure 14 and Figure 16 As shown, an etching process can then be used to form a photoresist layer on the bonding layer 150, and the photoresist layer can be patterned. Using the photoresist layer as a mask, the four corners of each pixel window 132 can be etched (e.g., ...). Figure 12 As shown in the diagram, a through-bonding layer 150 and a corresponding filling portion 131 are formed to form a first electrode hole 151a, a second electrode hole 151b, a third electrode hole 151c, and a fourth electrode hole 151d, respectively. The first electrode hole 151a, the second electrode hole 151b, the third electrode hole 151c, and the fourth electrode hole 151d expose the n-type doped AlGaN current spreading layer surfaces at these four locations. That is, the first electrode hole 151a exposes the surface of the first N-type doped conductive layer 123, and the second electrode hole 151b, the third electrode hole 151c, and the fourth electrode hole 151d expose the surface of the corresponding second N-type doped conductive layer 144.

[0133] It is understandable that, compared to p-type doped AlGaN or GaN surfaces, n-type doped AlGaN surfaces are more likely to achieve ohmic contact with common Micro LED electrode materials such as Au and Al, thereby improving device performance and reducing contact voltage and device power consumption.

[0134] Since the first electrode hole 151a, the second electrode hole 151b, the third electrode hole 151c, and the fourth electrode hole 151d have different depths in the direction perpendicular to the substrate 110, the etching gas used in the etching process of electrode hole 151 can have a high etching selectivity with the first N-type doped conductive layer 123 (AlGaN layer) and the second N-type doped conductive layer 144 (AlGaN layer). For example, the etching gas is fluoride ions (F-). In this way, when the bonding layer 150 and the corresponding first filling portion 131a, second filling portion 131b, third filling portion 131c, and fourth filling portion 131d are etched simultaneously, although the etching depths of the first electrode hole 151a, the second electrode hole 151b, the third electrode hole 151c, and the fourth electrode hole 151d are different, the electrode hole 151 that is etched first can be etched and remain on the surface of the corresponding N-type doped conductive layer until the deepest electrode hole 151 is etched.

[0135] The bonding layer 150, the first filling part 131a, the second filling part 131b, the third filling part 131c and the fourth filling part 131d are all made of silicon dioxide.

[0136] Therefore, in the embodiments of this application, the first electrode hole 151a, the second electrode hole 151b, the third electrode hole 151c and the fourth electrode hole 151d can be completed by synchronous etching, reducing the fabrication process and thus shortening the manufacturing cycle.

[0137] Please combine Figure 17 As shown, after forming the first electrode hole 151a, the second electrode hole 151b, the third electrode hole 151c, and the fourth electrode hole 151d, an ohmic contact layer 170 can be formed in each of these holes using a single metal electrode 160 vapor deposition process. Since the first electrode hole 151a, the second electrode hole 151b, the third electrode hole 151c, and the fourth electrode hole 151d all expose the same epitaxial layer, namely an n-type doped AlGaN surface, the same metal electrode 160 material (e.g., Al, Au, etc.) can be used in a single process. This further reduces the fabrication process and shortens the manufacturing cycle.

[0138] For the three light-emitting structures 140 (red, green, and blue), current injection occurs through a tunnel junction formed between a 30nm thick n-type doped layer and a 10nm thick p-type highly doped layer. Electrons are injected from the n-type doped layer into the p-type highly doped layer via quantum tunneling, creating holes. Compared to a traditional p-type GaN layer, in this embodiment, the n-type doped AlGaN in contact with the metal electrode 160 has a lower resistivity, which facilitates lateral current expansion, thereby improving the current injection uniformity in the light-emitting region and the overall electro-optical conversion efficiency of the device.

[0139] Please combine Figure 18 As shown, materials such as TiW and TiN are deposited on the surface of each ohmic contact layer 170 and on the sidewalls of the first electrode hole 151a, the second electrode hole 151b, the third electrode hole 151c, and the fourth electrode hole 151d to form a barrier layer 180 (e.g., TiW, TiN). Figure 18 (As shown in the diagram), then, conductive materials such as copper are electroplated into the first electrode hole 151a, the second electrode hole 151b, the third electrode hole 151c, and the fourth electrode hole 151d to form the first electrode 160a, the second electrode 160b, the third electrode 160c, and the fourth electrode 160d, respectively. Then, a CMP process is used to planarize the side of the bonding layer 150 facing away from the substrate 110, so that each electrode 160 is flush with the bonding surface of the bonding layer 150 (e.g., ...). Figure 1 and Figure 2 As shown in the figure, finally, the bonding layer 150 can be bonded to the CMOS chip 200 through a bonding process so that each electrode 160 is electrically connected to the CMOS chip 200.

[0140] In summary, the display module and fabrication method provided in this application firstly achieve selective growth and stacking of blue, green and red light-emitting structures through patterned filling layers; secondly, through the current injection method of tunnel junctions, each electrode is placed on an n-type doped AlGaN layer of the same material, and ohmic contact can be formed with an epitaxial layer of the same light-emitting structure through one-time metal deposition. Compared to traditional p-type GaN layers, the n-type doped AlGaN in contact with the metal electrodes in this embodiment has lower resistivity, which is more conducive to the lateral expansion of current, thereby improving the current injection uniformity and electro-optic conversion efficiency of the light-emitting region, and enhancing the luminous stability and brightness consistency of the device. In addition, during the epitaxial growth process, each filling part is used as a mask to avoid etching of each light-emitting structure, thus avoiding damage to the sidewalls of the light-emitting structure caused by etching and improving luminous efficiency. Finally, the surface of the final bonding layer is planarized to form a bonding surface. The bonding surface can be bonded to CMOS chips such as CMOS chips through a wafer-level process that is suitable for mass production, so that each electrode is electrically connected to the CMOS chip. In this way, multiple electrodes can be bonded to the CMOS chip through the bonding surface of the bonding layer in a single bonding process, so that multiple electrodes are electrically connected to the CMOS chip separately, without the need for multiple electrodes to be bonded to the CMOS chip through multiple bonding processes. This achieves wafer-level metal bonding suitable for mass production and improves the yield of bonding between the display module and the CMOS chip.

[0141] This application also provides a display device, which includes a device body and a display module provided in the above embodiments, or a display module formed by the above-described display module preparation method.

[0142] The display module and its preparation method have been described in detail in the above embodiments and will not be repeated here.

[0143] The device body includes mobile phones, computers, tablets, televisions, LCD display devices, etc. The device body includes CMOS chips such as CMOS chips. The CMOS chips are bonded to the above-mentioned display modules using a bonding process to achieve electrical conduction between the display modules and the CMOS chips.

[0144] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0145] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display module, characterized in that, include: Substrate; Epitaxial buffer layer; A fill layer is used to enclose and form a pixel window; The pixel window has multiple light-emitting structures, which are stacked sequentially along a direction perpendicular to the substrate. The epitaxial buffer layer and the side of each light-emitting structure facing away from the substrate have connection areas, and each connection area is not covered by other light-emitting structures. A bonding layer is disposed on the side of the filler layer opposite to the substrate; Multiple electrodes, each of which penetrates the bonding layer and is connected to a corresponding connection region, with one electrode corresponding to one connection region; The bonding layer has a bonding surface on the side facing away from the substrate, and the ends of the plurality of electrodes facing away from the substrate are flush with the bonding surface. The bonding surface is configured to bond with the CMOS chip.

2. The display module according to claim 1, characterized in that, The filling layer is provided with multiple filling portions; Multiple filling portions are disposed within the pixel window, and the multiple filling portions are respectively disposed on multiple connection areas and connected to the bonding layer; one filling portion is correspondingly disposed on one connection area. Each electrode passes through the corresponding filling portion and is connected to the corresponding connection area.

3. The display module according to claim 2, characterized in that, Along the direction parallel to the substrate, the cross-sectional shape of the pixel window is polygonal, and along the direction perpendicular to the substrate, the projections of the connection areas of the plurality of light-emitting structures within the pixel window are respectively located at different corners of the polygon.

4. The display module according to claim 3, characterized in that, The plurality of light-emitting structures, from the substrate upward, include a blue light-emitting structure, a green light-emitting structure, and a red light-emitting structure stacked sequentially; The epitaxial buffer layer has a first connection region; the blue light emitting structure has a second connection region, the green light emitting structure has a third connection region, and the red light emitting structure has a fourth connection region; Along the direction parallel to the substrate, the cross-sectional shape of the pixel window is a quadrilateral, and the projections of the first connection area, the second connection area, the third connection area and the fourth connection area in the pixel window are respectively located at the four corners of the quadrilateral; The plurality of filling portions include a first filling portion, a second filling portion, a third filling portion, and a fourth filling portion, wherein the first filling portion is disposed in the first connecting region, the second filling portion is disposed in the second connecting region, the third filling portion is disposed in the third connecting region, and the fourth filling portion is disposed in the fourth connecting region.

5. The display module according to any one of claims 1-4, characterized in that, The epitaxial buffer layer comprises a buffer layer, a doped layer, and a first N-type doped conductive layer stacked sequentially, wherein the connection region on the epitaxial buffer layer is disposed on the surface of the first N-type doped conductive layer facing away from the substrate; and / or, The light-emitting structure includes a light-emitting layer, a P-type doped layer, and a second N-type doped conductive layer stacked sequentially; the connection region on the light-emitting structure is disposed on the surface of the second N-type doped conductive layer facing away from the substrate.

6. A method for manufacturing a display module, characterized in that, include: An epitaxial buffer layer is formed on a substrate, the epitaxial buffer layer having a connection region; A fill layer is formed on the epitaxial buffer layer, and the fill layer is patterned to form a pixel window, the pixel window exposing the connection area of ​​the epitaxial buffer layer; Multiple light-emitting structures are formed within the pixel window. The multiple light-emitting structures are stacked sequentially along a direction perpendicular to the substrate. The multiple light-emitting structures do not cover the connection area of ​​the epitaxial buffer layer. Each light-emitting structure has a connection area on the side facing away from the substrate. Each connection area is not covered by other light-emitting structures. A bonding layer is formed on the filler layer, and the bonding layer has a bonding surface on the side opposite to the substrate; Multiple electrodes are formed, each of which penetrates the bonding layer and is connected to each of the connection regions. Each electrode corresponds to one connection region, and the end of each electrode facing away from the substrate is flush with the bonding surface. The bonding surface is configured to bond with the CMOS chip.

7. The method for preparing a display module according to claim 6, characterized in that, Before forming multiple light-emitting structures within the pixel window, the method further includes: The connection area on the epitaxial buffer layer forms a filling portion.

8. The method for preparing a display module according to claim 7, characterized in that, Multiple light-emitting structures are formed within the pixel window, including blue light-emitting structures, green light-emitting structures, and red light-emitting structures stacked sequentially. The specific method includes: A blue light-emitting structure is formed within the pixel window using an epitaxial growth process. A filling portion is formed on the connection area of ​​the blue light-emitting structure using a deposition process, and the filling portion covers the connection area of ​​the blue light-emitting structure. A green light-emitting structure is formed on the surface of the blue light-emitting structure exposed within the pixel window using an epitaxial growth process. A filling portion is formed on the connection area of ​​the green light-emitting structure using a deposition process, and the filling portion covers the connection area of ​​the green light-emitting structure. A red light-emitting structure is formed on the green light-emitting structure exposed within the pixel window using an epitaxial growth process; A filling portion is formed in the connection area of ​​the red light-emitting structure using a deposition process.

9. The preparation method according to claim 6, characterized in that, After forming a bonding layer on the filler layer, the method further includes: An etching process is used to form multiple electrode holes, each of which penetrates the bonding layer and exposes the connection region of the corresponding light-emitting structure. Conductive material is formed within each of the electrode holes to form an electrode; The bonding layer is planarized on the side away from the substrate using CMP process to form a bonding surface, and the ends of the multiple electrodes formed that are away from the substrate are flush with the bonding surface.

10. The preparation method according to claim 9, characterized in that, Before forming conductive material within each of the electrode holes, the process further includes: An ohmic contact layer is formed in each of the electrode holes using a metal electrode evaporation or sputtering process; A barrier layer is formed on the surface of the ohmic contact layer within each of the electrode holes and on the inner wall of the electrode holes.

11. A display device, comprising: A CMOS chip and a display module as described in any one of claims 1-5, or a display module formed by the method for preparing a display module as described in any one of claims 6-10; The CMOS chip and the display module are bonded together using a metal bonding process.

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