A longitudinal copolymer organic field effect transistor of planar grid structure and a preparation method thereof
By fabricating longitudinal copolymer organic field-effect transistors through planar gate structure design and spin coating evaporation process, the problem of dependence on high-precision micromachining technology is solved, and low-cost, high-efficiency device fabrication and improved electrical performance are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING UNIV OF POSTS & TELECOMM
- Filing Date
- 2026-03-18
- Publication Date
- 2026-06-09
Smart Images
Figure CN122180236A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of organic electronic device technology, specifically relating to an organic field-effect transistor, and more particularly to a longitudinal copolymer organic field-effect transistor with a planar gate structure and its preparation method. Background Technology
[0002] Organic field-effect transistors (OFETs), as a core component of organic electronic devices, have shown broad application prospects in flexible displays, wearable electronics, and smart sensing due to their advantages such as flexibility, low manufacturing cost, and good large-area integration, becoming a research hotspot in the electronics field. Vertically structured OFETs, with their longitudinally distributed channels, effectively shorten the carrier transport path, exhibiting significant performance advantages in current density and switching speed compared to traditional lateral structure devices, making them an important structural design direction for improving the performance of OFET devices.
[0003] However, the fabrication and structural design of existing vertical polymer organic field-effect transistors still face numerous technical bottlenecks. On the one hand, the gates of traditional vertical organic field-effect transistors mostly employ non-planar gate structures, requiring high-precision microfabrication processes such as etching and photolithography. This not only places high demands on equipment and complicates the fabrication process but also significantly increases production costs. On the other hand, when fabricating non-planar gates, the photolithography process is limited by the compatibility between photolithography materials and organic materials, resulting in insufficient photolithography precision and low success rates. During etching, the excessive softness of the organic semiconductor layer material leads to extremely poor etching precision and severely damages the semiconductor layer material.
[0004] In addition, the existing source and drain electrode layout limits the way the channel length can be controlled, and it relies heavily on high-precision electrode patterning processes, resulting in poor controllability of device fabrication and difficulty in ensuring batch consistency. At the same time, the structure of the electrodes can also easily reduce the carrier transport efficiency, affecting the stability of the device's electrical performance.
[0005] In summary, there is an urgent need to develop a vertical polymer organic field-effect transistor with a reasonable structural design, simplified fabrication process, and process and material compatibility. By optimizing the electrode layout, gate structure, and fabrication process, we can overcome the problems of high-precision process dependence, high fabrication difficulty, and poor performance consistency in the existing technology, so as to realize the low-cost and large-scale fabrication of vertical organic field-effect transistors and promote their practical application in the field of organic electronic devices. Summary of the Invention
[0006] In view of this, the present invention proposes a longitudinal copolymer organic field-effect transistor with a planar gate structure and its fabrication method. This device adopts a top-gate structure, with the drain located at the bottom layer and the source at the middle layer of electrode distribution. The planar gate structure is achieved through a strip-shaped interdigitated electrode design. The channel length between the source and drain is determined by the semiconductor thickness, avoiding high-precision photolithography and etching processes, simplifying the fabrication process, while maintaining good electrical performance. It has significant practical value and promising prospects for widespread application.
[0007] The objective of this invention is achieved through the following technical solution:
[0008] In a first aspect, the present invention provides a longitudinal copolymer organic field-effect transistor with a planar gate structure. The structure of the longitudinal copolymer organic field-effect transistor includes, in sequence, a substrate, a drain, an organic semiconductor layer, a source, an organic dielectric layer, and a gate. The electrode positions are distributed such that the gate is located on the top layer, the drain is located on the bottom layer, and the source is located on the middle layer. The drain forms a fully covered planar electrode above the substrate. The source and gate are composed of multiple parallel, equally spaced strip electrodes arranged in an interdigitated pattern. The channel length between the source and drain is the thickness of the organic semiconductor layer, which is determined by the concentration of the organic solution and the spin coating speed. The channel length is 40 nm to 300 nm.
[0009] Preferably, the substrate is selected from any one of glass substrate, flexible plastic, bulk silicon SOI, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, or germanium silicon material.
[0010] Preferably, the organic semiconductor material is any one of the conjugated polymers P3HT, DPPT-TT, and N2200; and the solvent of the conjugated polymer solution is chlorobenzene CB or dichlorobenzene DCB.
[0011] Preferably, the organic insulating material is any one of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), cyanoethyl pullulan (CEP), and polyvinylidene fluoride (PVDF).
[0012] Secondly, the present invention provides a method for fabricating a longitudinal copolymer organic field-effect transistor with a planar gate structure. The method involves fabricating a source, drain, gate, organic semiconductor layer, and organic dielectric layer. The electrode positions are distributed as follows: the gate is located on the top layer, the drain on the bottom layer, and the source in the middle layer. The drain is a fully covered planar electrode. The source and gate are composed of multiple electrodes arranged in an alternating pattern. The fabrication method includes the following steps:
[0013] Step S1, design the mask layout;
[0014] Step S2: Clean the substrate and mask, ultrasonically clean them and dry them with nitrogen gas to ensure that no moisture or impurities remain.
[0015] Step S3: The drain electrode is prepared on the substrate by electron beam evaporation.
[0016] Step S4: Prepare an organic semiconductor layer by spin-coating an organic semiconductor material solution and then anneal it;
[0017] Step S5: The source electrode is prepared on the organic semiconductor layer by electron beam evaporation.
[0018] Step S6: Prepare an organic dielectric layer by spin-coating an organic insulating material solution;
[0019] Step S7: The gate is prepared by electron beam evaporation.
[0020] Preferably, in step S3, the step of fabricating a metal drain on the substrate includes: adsorbing a mask onto the substrate and placing it in an evaporation apparatus, and sequentially evaporating Ni and Au to form a metal drain; specifically, evaporating 5 nm of Ni and 45 nm of Au, wherein the 5 nm of Ni is evaporated at a rate of 0.1 Å / s, then the 5 nm of Au is evaporated at a rate of 0.1 Å / s, then the 35 nm of Au is evaporated at a rate of 0.5 Å / s, and finally the 5 nm of Au is evaporated at a rate of 0.1 Å / s;
[0021] Step S4: Prepare an organic semiconductor layer by spin-coating an organic semiconductor material solution and then anneal it. Specifically, the organic semiconductor material solution is a DPPT-TT / DCB solution. The spin-coating parameters of the DPPT-TT / DCB solution are set as follows: the initial spin-coating speed is 0 rpm, accelerating to 500 rpm at an acceleration of 200 rpm / s, with the acceleration and constant speed period lasting for 10 s; then accelerating to 1500 rpm at an acceleration of 500 rpm / s, with the acceleration and constant speed period lasting for 60 s; then decelerating to 0 rpm at an acceleration of 500 rpm / s, with the deceleration and stopping period lasting for 5 s; then heating at 80°C for 5 min, followed by annealing at 150°C for 1 h to form an organic semiconductor layer.
[0022] In step S5, a metal source electrode is fabricated on the organic semiconductor layer. Specifically, 50 nm of metal Au is deposited by evaporation, wherein 5 nm of metal Au is deposited at a rate of 0.1 Å / s, followed by 35 nm of metal Au at a rate of 0.5 Å / s, and finally 5 nm of metal Au is deposited at a rate of 0.1 Å / s. In step S7, specifically, 80 nm of metal Cu is deposited by evaporation, wherein 5 nm of metal Cu is deposited at a rate of 0.5 Å / s, followed by 70 nm of metal Cu at a rate of 0.5 Å / s, and finally 5 nm of metal Cu is deposited at a rate of 0.1 Å / s.
[0023] Step S6: Prepare an organic dielectric layer by spin-coating an organic insulating material solution and then anneal it. Specifically, the organic insulating material solution is a PMMA / NBA solution. The spin-coating parameters of the PMMA / NBA solution are set as follows: the initial spin-coating speed is 0 rpm, accelerating to 500 rpm at an acceleration of 200 rpm / s, with the acceleration and constant speed period lasting for 3 seconds; then accelerating to 1500 rpm at an acceleration of 500 rpm / s, with the acceleration and constant speed period lasting for 60 seconds; then decelerating to 0 rpm at an acceleration of 500 rpm / s, with the deceleration and stopping period lasting for 5 seconds; and then annealing at 150°C for 2 hours to form the organic dielectric layer.
[0024] The beneficial effects of this invention are as follows:
[0025] This invention adopts a planar gate structure design, which eliminates the need for high-precision microfabrication processes such as photolithography and etching in gate fabrication. This avoids the problems of poor compatibility between photolithography materials and organic materials and the easy damage to soft organic semiconductor layers caused by etching in traditional non-planar gate fabrication. It significantly reduces process complexity and equipment requirements, while improving the accuracy and success rate of device fabrication, which is conducive to achieving low-cost, large-scale production.
[0026] In this invention, the channel length between the source and drain electrodes is determined by the thickness of the organic semiconductor layer, which can be controlled by adjusting the concentration of the organic solution and the spin coating speed. This design can achieve a short channel without relying on high-precision photolithography technology, thus improving the controllability and consistency of the device.
[0027] The drain electrode of this structure is a fully covered planar electrode, while the source and gate are multiple parallel and equally spaced strip-shaped staggered electrodes. Combined with the channel design with longitudinal current distribution, the contact interface between the electrode and the organic layer is optimized, the carrier transport efficiency is improved, and the good electrical performance stability of the device is ensured. Attached Figure Description
[0028] Figure 1 This is a structural diagram of the longitudinal copolymer organic field-effect transistor with a planar gate structure in this invention;
[0029] Figure 2 This is a flowchart of the longitudinal copolymer organic field-effect transistor with a planar gate structure in this invention;
[0030] Figure 3 This is the design layout of the longitudinal copolymer organic field-effect transistor with a planar gate structure in this invention;
[0031] Figure 4 The output characteristic curve of the longitudinal copolymer organic field-effect transistor with planar gate structure in this invention;
[0032] Figure 5These are the output characteristic curves of different polymer semiconductor materials used in this invention. Detailed Implementation
[0033] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments, but the invention is not limited to these embodiments. The invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of the invention. To provide the public with a thorough understanding of the invention, specific details are described in detail in the following embodiments, but those skilled in the art will fully understand the invention even without these details.
[0034] The sources of the reagent kit materials used in the following examples and test cases are shown below:
[0035] DPPT-TT: Nanjing Zhiyan Technology Co., Ltd.; 1,2-Dichlorobenzene (DCB) solution: Sigma-Aldrich; PMMA: Shanghai Hans Chemical Co., Ltd.; Butyl acetate (NBA) solution: Sigma-Aldrich;
[0036] P3HT: Shenzhen Ruixun Optoelectronic Materials Technology Co., Ltd.
[0037] The following example demonstrates the fabrication of a longitudinal copolymer organic field-effect transistor with a planar top-gate structure. The transistor structure diagram is shown below. Figure 1 As shown, the production flowchart is as follows: Figure 2 As shown, the structure in the following embodiments sequentially includes a substrate 1, a drain 2, an organic semiconductor layer 3, a source 4, an organic dielectric layer 5, and a gate 6. The substrate is a glass substrate; the source, drain, and gate are metal electrodes, with Au used for the drain and source, and Cu used for the gate; the organic semiconductor layer is a thin film of organic semiconductor material; the organic dielectric layer is an organic insulating thin film; and the adhesion layer of the drain is composed of Ni. The transistor design layout is shown below. Figure 3 As shown, in the mask layout design, the source, drain, and gate extend beyond the effective device area. The source and gate pads are staggered in horizontal projection, preventing overlap. Each strip of source electrode converges at its end to the source test pad, and similarly, each strip of gate electrode converges at its opposite end to the gate test pad. This structure ensures that the source and gate are electrically independent while simultaneously enabling unified injection of external driving voltage.
[0038] Example 1
[0039] Example 1 provides a longitudinal copolymer organic field-effect transistor with a planar gate structure.
[0040] Step S1, design the mask layout;
[0041] Step S2: Clean the substrate and mask, ultrasonically clean them and dry them with nitrogen gas to ensure that no moisture or impurities remain.
[0042] Step S3: The drain electrode is fabricated on the substrate using electron beam evaporation. Specifically, the operation for fabricating the drain electrode is as follows: a mask is adsorbed on the substrate and placed in an evaporation apparatus, and metals Ni and Au are deposited sequentially to form a metal drain electrode; specifically, 5 nm of metal Ni is deposited at a rate of 0.1 Å / s, followed by 5 nm of metal Au at a rate of 0.1 Å / s, then 35 nm of metal Au at a rate of 0.5 Å / s, and finally 5 nm of metal Au at a rate of 0.1 Å / s; ultimately, 5 nm of metal Ni and 45 nm of metal Au are deposited as the drain electrode.
[0043] Step S4: Prepare an organic semiconductor layer by spin-coating an organic semiconductor material solution and then anneal it. Specifically, the organic semiconductor material solution is a DPPT-TT / DCB solution or a P3HT / DCB solution. The spin-coating parameters of the organic semiconductor material solution are set as follows: the initial spin-coating speed is 0 rpm, accelerating to 500 rpm at an acceleration of 200 rpm / s, with the acceleration and constant speed period lasting 10 s; then accelerating to 1500 rpm at an acceleration of 500 rpm / s, with the acceleration and constant speed period lasting 60 s; then decelerating to 0 rpm at an acceleration of 500 rpm / s, with the deceleration and stopping period lasting 5 s; then heating at 80°C for 5 min, followed by annealing at 150°C for 1 h to form the organic semiconductor layer.
[0044] Step S5: The source electrode is prepared by electron beam evaporation on the organic semiconductor layer; specifically, 5 nm of metal Au is deposited at a rate of 0.1 Å / s, followed by 35 nm of metal Au at a rate of 0.5 Å / s, and finally 5 nm of metal Au is deposited at a rate of 0.1 Å / s; finally, 50 nm of metal Au is deposited as the source electrode.
[0045] Step S6: Prepare an organic dielectric layer by spin-coating an organic insulating material solution and then anneal it. Specifically, the organic insulating material solution is a PMMA / NBA solution. The spin-coating parameters of the PMMA / NBA solution are set as follows: the initial spin-coating speed is 0 rpm, accelerating to 500 rpm at an acceleration of 200 rpm / s, with the acceleration and constant speed period lasting for 3 seconds; then accelerating to 1500 rpm at an acceleration of 500 rpm / s, with the acceleration and constant speed period lasting for 60 seconds; then decelerating to 0 rpm at an acceleration of 500 rpm / s, with the deceleration and stopping period lasting for 5 seconds; finally, anneal at 150°C for 2 hours to form the organic dielectric layer.
[0046] Step S7: Electron beam evaporation is used to prepare the gate. Specifically, 5 nm of metal Cu is deposited at a speed of 0.5 Å / s, followed by 70 nm of metal Cu at a speed of 0.5 Å / s, and finally 5 nm of metal Cu is deposited at a speed of 0.1 Å / s. Finally, 80 nm of metal Cu is deposited as the gate.
[0047] The DPPT-TT used in Example 1 is a bipolar copolymer semiconductor with a highest occupied molecular orbital (HOMO) energy level typically between -5.1 eV and -5.3 eV. The work function of Au is approximately -5.1 eV, and their energy levels are quite close. When selecting other semiconductor and electrode materials, it is essential to ensure that their energy levels are similar to guarantee material compatibility. This facilitates the effective injection of charge carriers from the electrode into the organic semiconductor layer, thereby achieving higher mobility and switching current. Figure 4 As can be seen, when a voltage of 30V is applied to both the gate and drain, I DS The result can reach 1.9 μA, which fully demonstrates the carrier transport characteristics of the material system combined with the electrode structure.
[0048] In this embodiment, when spin-coating the organic insulating material solution, masking tape or a special mask is used to shield the lead-out terminals of the source and drain electrodes to ensure that the source and drain pads are not covered by the insulating material, thus preventing a sharp increase in contact resistance and achieving electrical connection with external circuits.
[0049] Example 2
[0050] The only difference between this embodiment and Embodiment 1 is that the organic semiconductor material used in step S4 is a P3HT / DCB solution; all other steps are the same as in Embodiment 1.
[0051] Figure 5 As can be seen from the data, when the copolymer semiconductor P3HT is used as the organic semiconductor layer, and a voltage of 30V is applied to both the gate and drain, I DS It can reach 1.5μA, also exhibiting good electrical response.
[0052] Comparative Example 1
[0053] Patent document CN116761479A provides a method for fabricating a longitudinal copolymer organic device with a vertical gate trench structure. In this patent, etching processes are required in steps S4 and S6 of the fabrication process to achieve the trench morphology. This increases the difficulty of the fabrication process and raises the fabrication cost and time. At the same time, due to the lack of sufficient compatibility between photolithography and etching processes and organic materials, the accuracy may be insufficient.
[0054] In summary, the core advantages of this invention lie in the optimization of fabrication process and device performance. First, by adopting a planar gate structure, gate fabrication does not require high-precision microfabrication processes such as photolithography and etching, avoiding the problems of poor material compatibility and easy damage to the organic semiconductor layer by etching in traditional non-planar gate fabrication. This significantly reduces process complexity and equipment requirements, improves fabrication accuracy and success rate, and facilitates low-cost, large-scale production. Second, the channel length between the source and drain is determined by the thickness of the organic semiconductor layer, which can be flexibly controlled by adjusting the concentration of the organic solution and the spin coating speed. Short channels can be achieved without relying on high-precision photolithography, effectively improving the controllability and batch consistency of device fabrication. Third, by adopting a planar electrode with full coverage at the bottom drain and multiple parallel, equally spaced, interdigitated strip-shaped electrodes in the middle layer of the source and the top layer of the gate, combined with a channel design with longitudinal current distribution, the contact interface between the electrodes and the organic layer is optimized, improving carrier transport efficiency and ensuring good and stable electrical performance of the device.
Claims
1. A planar grid structure of a longitudinal copolymer organic field effect transistor, characterized in that, The structure of the longitudinal copolymer organic field-effect transistor includes a substrate, a drain, an organic semiconductor layer, a source, an organic dielectric layer, and a gate, wherein the gate is located on the top layer, the drain is located on the bottom layer, and the source is located on the middle layer. The drain forms a fully covered planar electrode above the substrate. The source and gate are composed of multiple parallel, equally spaced strip electrodes in an interdigitated distribution. The channel length between the source and drain is the thickness of the organic semiconductor layer, which is determined by the concentration of the organic solution and the spin coating speed. The channel length is 40nm~300nm.
2. A planar grid structure of a longitudinal copolymer organic field effect transistor as claimed in claim 1, characterized in that, The substrate is selected from any one of glass substrate, flexible plastic, bulk silicon SOI, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, or germanium silicon material.
3. The longitudinal copolymer organic field-effect transistor with a planar gate structure as described in claim 1, characterized in that, The organic semiconductor material is any one of the conjugated polymers P3HT, DPPT-TT, and N2200.
4. The longitudinal copolymer organic field-effect transistor with a planar gate structure as described in claim 3, characterized in that, The solvent for the conjugated polymer solution is chlorobenzene CB or dichlorobenzene DCB.
5. The longitudinal copolymer organic field-effect transistor with a planar gate structure as described in claim 1, characterized in that, The organic insulating material is any one of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), cyanoethyl pullulan (CEP), and polyvinylidene fluoride (PVDF).
6. A method for fabricating a longitudinal copolymer organic field-effect transistor with a planar gate structure as described in claim 1, characterized in that, Its preparation method includes the following steps: Step S1, design the mask layout; Step S2: Clean the substrate and mask, ultrasonically clean them and dry them with nitrogen gas to ensure that no moisture or impurities remain. Step S3: The drain electrode is prepared on the substrate by electron beam evaporation. Step S4: Prepare an organic semiconductor layer by spin-coating an organic semiconductor material solution and then anneal it; Step S5: The source electrode is prepared on the organic semiconductor layer by electron beam evaporation. Step S6: Prepare an organic dielectric layer by spin-coating an organic insulating material solution; Step S7: The gate is prepared by electron beam evaporation.
7. The preparation method according to claim 6, characterized in that, In step S3, the step of fabricating the metal drain on the substrate includes: adsorbing a mask onto the substrate and placing it in an evaporation apparatus, and sequentially evaporating Ni and Au to form the metal drain; specifically, evaporating 5 nm of Ni and 45 nm of Au, wherein the 5 nm of Ni is evaporated at a rate of 0.1 Å / s, then the 5 nm of Au is evaporated at a rate of 0.1 Å / s, then the 35 nm of Au is evaporated at a rate of 0.5 Å / s, and finally the 5 nm of Au is evaporated at a rate of 0.1 Å / s.
8. The preparation method according to claim 6, characterized in that, Step S4: Prepare an organic semiconductor layer by spin-coating an organic semiconductor material solution and then anneal it. Specifically, the organic semiconductor material solution is a DPPT-TT / DCB solution. The spin-coating parameters of the DPPT-TT / DCB solution are set as follows: the initial spin-coating speed is 0 rpm, accelerating to 500 rpm at an acceleration of 200 rpm / s, with the acceleration and constant speed period lasting for 10 s; then accelerating to 1500 rpm at an acceleration of 500 rpm / s, with the acceleration and constant speed period lasting for 60 s; then decelerating to 0 rpm at an acceleration of 500 rpm / s, with the deceleration and stopping period lasting for 5 s; then heating at 80°C for 5 min, followed by annealing at 150°C for 1 h to form the organic semiconductor layer.
9. The preparation method according to claim 6, characterized in that, In step S5, a metal source electrode is fabricated on the organic semiconductor layer. Specifically, 50 nm of metal Au is deposited by evaporation, wherein 5 nm of metal Au is deposited at a rate of 0.1 Å / s, followed by 35 nm of metal Au at a rate of 0.5 Å / s, and finally 5 nm of metal Au is deposited at a rate of 0.1 Å / s. In step S7, specifically, 80 nm of metal Cu is deposited by evaporation, wherein 5 nm of metal Cu is deposited at a rate of 0.5 Å / s, followed by 70 nm of metal Cu at a rate of 0.5 Å / s, and finally 5 nm of metal Cu is deposited at a rate of 0.1 Å / s.
10. The preparation method according to claim 6, characterized in that, Step S6: Prepare an organic dielectric layer by spin-coating an organic insulating material solution and then anneal it. Specifically, the organic insulating material solution is a PMMA / NBA solution. The spin-coating parameters of the PMMA / NBA solution are set as follows: the initial spin-coating speed is 0 rpm, accelerating to 500 rpm at an acceleration of 200 rpm / s, with the acceleration and constant speed period lasting for 3 seconds; then accelerating to 1500 rpm at an acceleration of 500 rpm / s, with the acceleration and constant speed period lasting for 60 seconds; then decelerating to 0 rpm at an acceleration of 500 rpm / s, with the deceleration and stopping period lasting for 5 seconds; and then annealing at 150°C for 2 hours to form the organic dielectric layer.