Display device partition structure and preparation method, and silicon-based OLED display device

Abstract

The application discloses a display device partition structure, which comprises a pixel definition layer, the pixel definition layer is a laminated structure composed of a plurality of inorganic layers, the pixel definition layer is provided with a pixel opening area and a partition groove, the partition groove is located between adjacent pixel opening areas, a plurality of partition parts are arranged in the partition groove, and the partition parts are asymmetrically arranged. The display device partition structure of the application adopts asymmetric partition parts, prevents optical crosstalk between adjacent pixels, and improves display effect. The application further discloses a preparation method of the display device partition structure and a silicon-based OLED display device.

Description

Technical Field

[0001] This invention belongs to the field of optical display technology. Specifically, this invention relates to a display device partition structure and its preparation method, and a silicon-based OLED display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are a type of display technology that has emerged in recent years, with silicon-based OLEDs being one example. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve lightweight design. Silicon-based OLEDs are fabricated using mature complementary metal-oxide-semiconductor (CMOS) integrated circuit technology, offering advantages such as small size, high resolution (Pixels Per Inch, PPI), and high refresh rate. They are widely used in near-eye displays for virtual reality (VR) and augmented reality (AR).

[0003] In the manufacturing of silicon-based OLEDs, the ideal operating condition is for the R, G, and B cells to emit light independently without interfering with each other. However, in actual product design, due to increasingly finer linewidths and spacings, current interference can occur between two light-emitting cells. This current interference can cause adjacent display cells to emit light intermittently, affecting the product's display performance.

[0004] A display device isolation structure is provided, particularly for preventing optical crosstalk between adjacent pixels and improving the display effect. Summary of the Invention

[0005] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the present invention provides a display device isolation structure to prevent optical crosstalk between adjacent pixels and improve the display effect.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a display device partition structure, including a pixel definition layer, the pixel definition layer is a stacked structure composed of multiple inorganic layers, a pixel opening area and a partition groove are provided on the pixel definition layer, the partition groove is located between adjacent pixel opening areas, and multiple partition parts are provided in the partition groove, the partition parts are arranged asymmetrically.

[0007] The partition is connected to the inorganic layer.

[0008] The plurality of inorganic layers include a first inorganic layer, a second inorganic layer, ... and an nth inorganic layer arranged sequentially. Except for the nth inorganic layer, the remaining inorganic layers are all connected to the partition.

[0009] The two partitions connected to the two adjacent inorganic layers are staggered.

[0010] The three partitions are connected to the three consecutive inorganic layers. The partition connected to the middle inorganic layer is staggered from the other two partitions. A slope is formed between the other two partitions, and the slope is opposite to the partition connected to the middle inorganic layer.

[0011] The plurality of inorganic layers include a first inorganic layer, a second inorganic layer, a third inorganic layer, a fourth inorganic layer, and a fifth inorganic layer arranged sequentially. The first inorganic layer, the third inorganic layer, and the fifth inorganic layer are made of the same material, and the second inorganic layer and the fourth inorganic layer are made of the same material.

[0012] The present invention also provides a silicon-based OLED display device, including a driving circuit substrate, an anode metal layer and the display device isolation structure, wherein the pixel definition layer is disposed on the anode metal layer.

[0013] The present invention also provides a method for fabricating a partition structure for a display device, comprising the following steps:

[0014] S1. Provide a driving circuit substrate;

[0015] S2. An anode metal layer is formed on one side of the driving circuit substrate;

[0016] S3. A pixel definition layer is formed on the side of the anode metal layer away from the driving circuit substrate;

[0017] S4. A pixel opening area and a partition are formed on the pixel definition layer.

[0018] Step S4 includes:

[0019] S401. Form the pixel opening region on the pixel definition layer;

[0020] S402, Each of the partition portions is formed sequentially on the pixel definition layer.

[0021] The method for preparing the display device isolation structure further includes the following steps:

[0022] S5. A light-emitting layer is formed on the side of the pixel definition layer away from the driving circuit substrate;

[0023] S6. An encapsulation layer is formed on the side of the light-emitting layer away from the driving circuit substrate;

[0024] S7. A planarization layer is formed on the side of the encapsulation layer away from the driving circuit substrate.

[0025] The display device isolation structure of the present invention adopts an asymmetrical isolation portion to prevent optical crosstalk between adjacent pixels, improve the display effect, and also improve the problem of cathode breakage. Attached Figure Description

[0026] This manual includes the following figures, which illustrate the following:

[0027] Figure 1 This is a schematic diagram of the partition structure of the display device of the present invention;

[0028] Figure 2 This is a schematic diagram of the structure of a silicon-based OLED display device;

[0029] Figures 3-19 This is a schematic diagram of the fabrication process of a silicon-based OLED display device;

[0030] The following labels are used in the diagram: 1. First inorganic layer; 2. Second inorganic layer; 3. Third inorganic layer; 4. Fourth inorganic layer; 5. Fifth inorganic layer; 6. Driving circuit substrate; 7. Anode metal layer; 8. Pixel aperture area; 9. Partition groove; 10. Light-emitting layer; 11. First partition; 12. Second partition; 13. Third partition; 14. Fourth partition; 15. First cavity; 16. Second cavity; 17. Third cavity; 18. Encapsulation layer; 19. Planarization layer; 20. MASK1; 21. MASK2; 22. MASK3; 23. MASK4; 24. MASK5; 25. MASK6; 26. MASK6; 100. First material layer; 200. Second material layer. Detailed Implementation

[0031] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, in order to help those skilled in the art to have a more complete, accurate and in-depth understanding of the concept and technical solutions of the present invention, and to facilitate its implementation.

[0032] Firstly, such as Figure 1 As shown, this embodiment of the invention provides a display device partition structure, including a pixel definition layer, which is a stacked structure composed of multiple inorganic layers. The pixel definition layer is provided with pixel opening areas 8 and partition grooves 9. The partition grooves 9 are located between adjacent pixel opening areas 8. Multiple partition parts are provided in the partition grooves 9, and the partition parts are arranged asymmetrically.

[0033] Specifically, such as Figure 1 and Figure 2As shown, the pixel definition layer in the OLED structure is mainly used to isolate electrical crosstalk between adjacent pixels. The pixel definition layer, except for the light-emitting layer 10, directly contacts the anode metal layer 7. The pixel definition layer is disposed on the anode metal layer 7, which is disposed on the driving circuit substrate 6. The pixel definition layer has multiple pixel opening regions 8 corresponding to the anode metal layer 7, and multiple isolation grooves 9. An isolation groove 9 is disposed between two adjacent pixel opening regions 8. The isolation groove 9 and the pixel opening region 8 are grooves disposed on the pixel definition layer.

[0034] like Figure 1 and Figure 2 As shown, the inorganic layer is made of inorganic material. Multiple inorganic layers include a first inorganic layer 1, a second inorganic layer 2, ..., and an nth inorganic layer, arranged sequentially along the thickness direction of the pixel definition layer, where n is an odd number. Except for the nth inorganic layer, all other inorganic layers are connected to the partition portion. The first inorganic layer 1 is located on the side of the second inorganic layer 2 away from the driving circuit substrate 6. The nth inorganic layer is in contact with the anode metal layer 7 and the driving circuit substrate 6. The nth inorganic layer corresponds to multiple partition grooves 9, and is located between the driving circuit substrates 6 in the partition grooves 9. The pixel opening region 8 extends from the top surface of the first inorganic layer 1 to the anode metal layer 7, and the partition groove 9 extends from the top surface of the first inorganic layer 1 to the nth inorganic layer. The first inorganic layer 1, the third inorganic layer 3, ... and the nth inorganic layer are made of the same material. The second inorganic layer 2, ... and the (n-1)th inorganic layer are made of the same material. The first inorganic layer 1 and the second inorganic layer 2 are made of different materials.

[0035] The two partitions connected to the two adjacent inorganic layers of the pixel definition layer are staggered. This staggered arrangement means that the projections of the two partitions on the projection plane perpendicular to the thickness direction of the pixel definition layer do not coincide and their positions are opposite. The partition groove 9 is located between the two partitions. The three partitions connected to the three consecutive inorganic layers are staggered with the partition connected to the middle inorganic layer and the other two partitions. A cavity is formed between the other two partitions. The inner wall of the cavity is a sloped plane that extends downwards. The sloped plane is opposite to the partition connecting the middle inorganic layer. The cavity is connected to the partition groove 9. For example, three inorganic layers continuously arranged along the thickness direction of the pixel definition layer are the m-th inorganic layer, the (m+1)-th inorganic layer, and the (m+2)-th inorganic layer, where m+2 is less than n. Each of the m-th, (m+1)-th, and (m+2)-th inorganic layers is connected to a partition. A cavity is formed between the two partitions connected to the m-th and (m+2)-th inorganic layers. The partition connected to the (m+1)-th inorganic layer and the cavity are arranged opposite to each other. The partition groove 9 is located between the cavity and the partition connected to the (m+1)-th inorganic layer. The two partitions connected to the m-th and (m+1)-th inorganic layers are staggered. The two partitions connected to the (m+1)-th and (m+2)-th inorganic layers are staggered. The two partitions connected to the m-th and (m+2)-th inorganic layers are located on one side of the partition groove 9, and the partition connected to the (m+1)-th inorganic layer is located on the other side of the partition groove 9. The partition is made of the same material as the connected inorganic layer.

[0036] In embodiments of the present invention, such as Figure 1 and Figure 2As shown, n=5, the multiple inorganic layers that make up the pixel definition layer include the first inorganic layer 1, the second inorganic layer 2, the third inorganic layer 3, the fourth inorganic layer 4 and the fifth inorganic layer 5 arranged in sequence. The first inorganic layer 1, the third inorganic layer 3 and the fifth inorganic layer 5 have the same material, and the second inorganic layer 2 and the fourth inorganic layer 4 have the same material. The first inorganic layer 1 is connected to the first partition 11, the second inorganic layer 2 is connected to the second partition 12, the third inorganic layer 3 is connected to the third partition 13, and the fourth inorganic layer 4 is connected to the fourth partition 14. The first partition 11 and the third partition 13 are located on one side of the partition groove 9, and the second partition 12 and the fourth partition 14 are located on the other side of the partition groove 9. The first partition 11 and the second partition 12 are staggered, the second partition 12 and the third partition 13 are staggered, and the third partition 13 and the fourth partition 14 are staggered, so that all the partitions are asymmetrically distributed. A first cavity 15 is formed between the first partition 11 and the third partition 13, a second cavity 16 is formed between the third partition 13 and the fifth inorganic layer 5, and a third cavity 17 is formed between the second partition 12 and the fourth partition 14. The first cavity 15 is opposite to the second partition 12, the second cavity 16 is opposite to the fourth partition 14, the third cavity 17 is opposite to the third partition 13, and the fourth partition 14 is in contact with the fifth inorganic layer 5.

[0037] Secondly, such as Figure 2 As shown, this embodiment of the invention also provides a silicon-based OLED display device, including a driving circuit substrate 6, an anode metal layer 7, and a display device isolation structure with the above-described structure, wherein a pixel definition layer is disposed on the anode metal layer 7.

[0038] like Figure 2 As shown, the silicon-based OLED display device of this embodiment of the invention further includes an emissive layer 10, an encapsulation layer 18, and a planarization layer 19. The emissive layer 10 is located on the side of the pixel definition layer away from the driving circuit substrate 6, the encapsulation layer 18 is located on the side of the emissive layer 10 away from the driving circuit substrate 6, and the planarization layer 19 is located on the side of the encapsulation layer 18 away from the driving circuit substrate 6.

[0039] like Figure 1 and Figure 2 As shown, the first inorganic layer 1, the second inorganic layer 2, the third inorganic layer 3, the fourth inorganic layer 4 and the fifth inorganic layer 5 of the pixel definition layer are in contact with the light-emitting layer 10. The fifth inorganic layer 5 is in contact with the anode metal layer 7 and the driving circuit substrate 6, and fills the gaps between the anode metal layers 7.

[0040] Thirdly, embodiments of the present invention also provide a method for preparing a display device partition structure, comprising the following steps:

[0041] S1. Provide a driving circuit substrate 6;

[0042] S2. An anode metal layer 7 is formed on one side of the driving circuit substrate 6;

[0043] S3. A pixel definition layer is formed on the side of the anode metal layer 7 away from the driving circuit substrate 6;

[0044] S4. Form pixel opening area 8 and partition portion on pixel definition layer;

[0045] S5. An emissive layer 10 is formed on the side of the pixel definition layer away from the driving circuit substrate 6;

[0046] S6. An encapsulation layer 18 is formed on the side of the light-emitting layer 10 away from the driving circuit substrate 6;

[0047] S7. A planarization layer 19 is formed on the side of the encapsulation layer 18 away from the driving circuit substrate 6.

[0048] In step S2 above, as Figures 3 to 5 As shown, the wafer is cleaned, then an anode film layer is deposited, and then an anode pattern is created by exposure, development and etching processes to form an anode metal layer 7.

[0049] In step S3 above, such as Figure 6 and Figure 7 As shown, three first material layers 100 and two second material layers 200 are deposited using a PECVD device, followed by sequential coating, exposure, development, and curing. Each second material layer 200 is located between two adjacent first material layers 100. The first material layers 100 and 200 are made of inorganic materials and are made of different materials. The bottom first material layer 100 is in contact with the anode metal layer 7 and the driving circuit substrate 6, and fills the gaps between the anode metal layers 7.

[0050] Step S4 above includes:

[0051] S401. Form a pixel opening region 8 on the pixel definition layer;

[0052] S402. Form each partition in sequence on the pixel definition layer.

[0053] In step S401 above, as Figure 8 and Figure 9As shown, a pixel opening region 8 is formed on the pixel definition layer through an etching process. The pixel opening region 8 extends downward from the top surface of the top first material layer 100 to the anode metal layer 7. Then, PR (photoresist) is coated on the pixel opening region 8 as a mask for subsequent exposure and development. Then, exposure, development and curing are performed in sequence. The three first material layers 100 are formed as the first inorganic layer 1, the third inorganic layer 3 and the fifth inorganic layer 5, respectively. The two second material layers 200 are formed as the second inorganic layer 2 and the fourth inorganic layer 4, respectively.

[0054] In step S402 above, as Figure 10 and Figure 11 As shown, a first partition portion 11 is formed on the first inorganic layer 1 by an etching process; then photoresist is coated on the pixel opening area 8 as a mask for subsequent exposure and development, and then exposure, development and curing are performed in sequence.

[0055] In step S402 above, as Figure 12 and Figure 13 As shown, a second partition portion 12 is formed on the second inorganic layer 2 by an etching process; then photoresist is coated on the pixel opening area 8 as a mask for subsequent exposure and development, and then exposure, development and curing are performed in sequence.

[0056] In step S402 above, as Figure 14 and Figure 15 As shown, a first cavity 15 is formed between the first partition 11 and the third inorganic layer 3 by etching process using high etching selectivity conditions; then photoresist is coated on the pixel opening area 8 as a mask for subsequent exposure and development, and then exposure, development and curing are performed in sequence.

[0057] In step S402 above, as Figure 16 and Figure 17 As shown, a third partition 13 is formed on the third inorganic layer 3 by an etching process. The third partition 13 is located below the first cavity 15. Then, photoresist is coated on the pixel opening area 8 as a mask for subsequent exposure and development. Then, exposure, development and curing are performed in sequence.

[0058] In step S402 above, as Figure 18 As shown, a second cavity 16 is formed between the second partition 12 and the fourth inorganic layer 4 by etching process using high etching selectivity conditions; then photoresist is coated on the pixel opening area 8 as a mask for subsequent exposure and development, and then exposure, development and curing are performed in sequence.

[0059] In step S402 above, as Figure 19As shown, a fourth partition 14 is formed on the fourth inorganic layer 4 by an etching process. The fourth partition 14 is located below the second cavity 16. Then, photoresist is coated on the pixel opening area 8 as a mask for subsequent exposure and development. Then, exposure, development and curing are performed in sequence.

[0060] In step S402 above, as Figure 19 As shown, a third cavity 17 is formed between the third partition portion 13 and the fifth inorganic layer 5 by etching process using a high etching selectivity condition. The third cavity 17 is opposite to the fourth partition portion 14.

[0061] After multiple photolithography (PHO) and etching processes, a multi-layer inorganic structure is formed, which ultimately creates multiple asymmetric partitions and multiple tapered structures.

[0062] In step S5 above, OLED material is deposited using a vapor deposition machine to form the light-emitting layer 10.

[0063] In step S6 above, the encapsulation layer 18 is fabricated by a thin film deposition process.

[0064] In step S7 above, a planarization layer 19 is completed on the encapsulation layer 18.

[0065] The present invention has been described above by way of example with reference to the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution; or the direct application of the inventive concept and technical solution to other situations without modification, are all within the protection scope of the present invention.

Claims

1. A display device partition structure, comprising a pixel definition layer, the pixel definition layer being a stacked structure composed of multiple inorganic layers, wherein pixel opening areas and partition grooves are provided on the pixel definition layer, the partition grooves being located between adjacent pixel opening areas, characterized in that, The partition groove is provided with multiple partition sections, which are arranged asymmetrically.

2. The display device partition structure according to claim 1, characterized in that, The partition is connected to the inorganic layer.

3. The display device partition structure according to claim 2, characterized in that, The plurality of inorganic layers include a first inorganic layer, a second inorganic layer, ... and an nth inorganic layer arranged sequentially. Except for the nth inorganic layer, the remaining inorganic layers are all connected to the partition.

4. The display device partition structure according to claim 3, characterized in that, The two partitions connected to the two adjacent inorganic layers are staggered.

5. The display device partition structure according to claim 4, characterized in that, The three partitions are connected to the three consecutive inorganic layers. The partition connected to the middle inorganic layer is staggered from the other two partitions. A slope is formed between the other two partitions, and the slope is opposite to the partition connected to the middle inorganic layer.

6. The display device partition structure according to any one of claims 1 to 5, characterized in that, The plurality of inorganic layers include a first inorganic layer, a second inorganic layer, a third inorganic layer, a fourth inorganic layer, and a fifth inorganic layer arranged sequentially. The first inorganic layer, the third inorganic layer, and the fifth inorganic layer are made of the same material, and the second inorganic layer and the fourth inorganic layer are made of the same material.

7. A silicon-based OLED display device, characterized in that, It includes a driving circuit substrate, an anode metal layer, and a display device isolation structure as described in any one of claims 1 to 6, wherein the pixel definition layer is disposed on the anode metal layer.

8. The method for preparing the display device partition structure as described in any one of claims 1 to 7, characterized in that, Including the following steps: S1. Provide a driving circuit substrate; S2. An anode metal layer is formed on one side of the driving circuit substrate; S3. A pixel definition layer is formed on the side of the anode metal layer away from the driving circuit substrate; S4. A pixel opening area and a partition are formed on the pixel definition layer.

9. The method for preparing the display device partition structure according to claim 8, characterized in that, Step S4 includes: S401. Form the pixel opening region on the pixel definition layer; S402, Each of the partition portions is formed sequentially on the pixel definition layer.

10. The method for preparing the display device partition structure according to claim 8, characterized in that, It also includes the following steps: S5. A light-emitting layer is formed on the side of the pixel definition layer away from the driving circuit substrate; S6. An encapsulation layer is formed on the side of the light-emitting layer away from the driving circuit substrate; S7. A planarization layer is formed on the side of the encapsulation layer away from the driving circuit substrate.

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