Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided, the display device including: a substrate including a display area and a non-display area adjacent to the display area; a light emitting element over the substrate and in the display area; an output pad over the substrate and in the non-display area; an input pad over the substrate and in the non-display area and spaced apart from the output pad in a plan view; a first groove adjacent to the output pad; and a driving chip bonded to the output pad and the input pad.

Description

Technical Field

[0001] This disclosure relates to a display device for providing visual information and an electronic device including the display device. Background Technology

[0002] A display device is a device that displays images to provide visual information to a user. Among display devices, organic light-emitting diode (OLED) displays have recently attracted attention.

[0003] A display device may include pixels, input pads (also known as solder pads or solder pads), and output pads. Each pixel can emit light. Each of the input and output pads can be bonded to a driver chip. Therefore, the driver chip can provide signals to the pixels through the input and output pads. Summary of the Invention

[0004] Embodiments of this disclosure provide a display device in which the generation and propagation of cracks are suppressed.

[0005] Embodiments of this disclosure provide an electronic device including a display device.

[0006] A display device according to one or more embodiments includes: a substrate including a display area and a non-display area adjacent to the display area; a light-emitting element above the substrate and in the display area; an output pad above the substrate and in the non-display area; an input pad above the substrate and in the non-display area, and spaced apart from the output pad in a plan view; a first recess adjacent to the output pad; and a driver chip coupled to the output pad and the input pad.

[0007] The first groove can be adjacent to the corresponding output pad in the output pad at the outermost position.

[0008] The corresponding output pad in the output pad at the outermost position may include stacked conductive patterns, wherein the first groove accommodates some of the conductive patterns.

[0009] The corresponding output pad in the output pad at the outermost position may include a first conductive pattern, a second conductive pattern above the first conductive pattern, a third conductive pattern above the second conductive pattern, and a fourth conductive pattern above the third conductive pattern, wherein the first groove accommodates at least a portion of the fourth conductive pattern.

[0010] The first groove can be spaced apart from the third conductive pattern in the plan view.

[0011] The display device may further include: a first touch electrode above the light-emitting element; and a second touch electrode above the first touch electrode, wherein the fourth conductive pattern and the second touch electrode are on the same layer.

[0012] The output pads may include output pads in the first row, output pads in the second row, and output pads in the third row, wherein the first recess is adjacent to the output pad in the first row.

[0013] The display device may also include a second recess adjacent to the output pad in the third row of the output pad.

[0014] The output pads in the third row may include stacked conductive patterns, wherein the second groove accommodates some of the conductive patterns.

[0015] The output pad in the third row may include a first conductive pattern, a second conductive pattern above the first conductive pattern, a third conductive pattern above the second conductive pattern, and a fourth conductive pattern above the third conductive pattern, wherein the second groove accommodates at least a portion of the fourth conductive pattern and is spaced apart from the third conductive pattern in the plan view.

[0016] The display device may also include a third recess adjacent to the input pad, the input pad comprising stacked conductive patterns, wherein the third recess accommodates some of the conductive patterns.

[0017] The first groove can be arranged repeatedly in an island shape.

[0018] A display device according to one or more embodiments includes: a substrate including a display area and a non-display area adjacent to the display area; a light-emitting element above the substrate and in the display area; an output pad above the substrate and in the non-display area; an input pad above the substrate and in the non-display area, and spaced apart from the output pad in a plan view; a first recess adjacent to the input pad; and a driver chip coupled to the output pad and the input pad.

[0019] The input pad may include stacked conductive patterns, wherein a first groove accommodates some of the conductive patterns.

[0020] The input pad may include a first conductive pattern, a second conductive pattern above the first conductive pattern, a third conductive pattern above the second conductive pattern, and a fourth conductive pattern above the third conductive pattern, wherein a first groove accommodates at least a portion of the fourth conductive pattern.

[0021] The first groove can be spaced apart from the third conductive pattern in the plan view.

[0022] The display device may further include: a first touch electrode above the light-emitting element; and a second touch electrode above the first touch electrode, wherein the fourth conductive pattern and the second touch electrode are on the same layer.

[0023] An electronic device according to one or more embodiments includes: a substrate including a display area and a non-display area adjacent to the display area; a light-emitting element above the substrate and in the display area; an output pad above the substrate and in the non-display area; an input pad above the substrate and in the non-display area, and spaced apart from the output pad in a plan view; a first recess adjacent to the output pad; a driver chip coupled to the output pad and the input pad; and a memory device configured to store data information.

[0024] The first groove can be adjacent to the corresponding output pad in the output pad at the outermost position.

[0025] The corresponding output pad in the output pad at the outermost position may include stacked conductive patterns, wherein the first groove accommodates some of the conductive patterns.

[0026] Therefore, when the driver chip is bonded to the substrate, the generation and propagation of cracks around the first groove can be reduced or prevented. Attached Figure Description

[0027] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 This is a plan view showing a display device according to an embodiment.

[0029] Figure 2 It is shown Figure 1 An enlarged plan view of an example of region A.

[0030] Figure 3 It is along Figure 2 A sectional view of the display device taken along line I-I'.

[0031] Figure 4 It is along Figure 2 A sectional view of the display device taken from line II-II'.

[0032] Figure 5 It is shown Figure 3 An enlarged cross-sectional view of an example of region B.

[0033] Figure 6 It is shown that it includes Figure 1 A cross-sectional view of pixels in a display device.

[0034] Figure 7 It is shown Figure 3 An enlarged cross-sectional view of an example of region B.

[0035] Figure 8 It is shown Figure 1 An enlarged plan view of an example of region A.

[0036] Figure 9 It is shown Figure 1 An enlarged plan view of an example of region A.

[0037] Figure 10 This is a block diagram illustrating an electronic device according to an embodiment.

[0038] Figure 11 It is shown that Figure 10 The diagram shows an example of an electronic device implemented as a smartphone. Detailed Implementation

[0039] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are unnecessary for a person of ordinary skill in the art to fully understand aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, designations, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated description may be omitted.

[0040] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the terms "can," "may," or "may not" correspond to one or more embodiments of this disclosure.

[0041] It will be understood by those skilled in the art that, in view of the entire disclosure, each suitable feature of the various embodiments of the disclosure may be combined in part or in whole or in combination with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently or in combination with one another in any suitable manner.

[0042] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto because the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of description. Furthermore, the use of crosshairs and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, scale, commonalities between the elements shown, and / or any other characteristics, properties, or characteristics of the elements.

[0043] Various embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of examples and / or intermediate structures. Thus, variations in the shapes shown in the illustrations will be anticipated due to factors such as manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes shown for elements, layers, or regions, but will include deviations in shape due to factors such as manufacturing processes.

[0044] For example, an injection region shown as rectangular will typically have circular or curved features and / or a gradient of injectant concentration at its edges, rather than a binary variation from the injection region to the non-injection region. Similarly, a buried region formed by injection can result in some injection in the region between the buried region and the surface through which the injection occurs.

[0045] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “above,” “overall,” “higher,” “upper side,” “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this indicates that the first part is arranged on the upper or lower side of the second part, and is not limited to the upper side based on the direction of gravity.

[0046] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting a portion of the object from the side. The terms "overlapping" or "overlapping" mean that the first object may be above or below the second object, or to the side of the second object, and vice versa. Furthermore, the term "overlapping" can include stacking, facing or oriented, extending across, covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separated from," "offset from," or "deviated from," and any other suitable equivalent as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "facing" can mean that the first object may be directly or indirectly opposite the second object. In cases where a third object is located between the first and second objects, although the first and second objects still face each other, they can be understood as being indirectly opposite each other.

[0047] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as "formed on," "on," "connected to," or "(operably, functionally, or communicatively) incorporated into" another component, layer, region, or assembly, that component, layer, region, or assembly may be directly formed on, directly on, directly connected to, or directly incorporated into, the other component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into, the other component, layer, region, or assembly, such that one or more intermediary components, layers, regions, or assemblies may exist. Furthermore, this can be collectively referred to as direct or indirect incorporation or connection, and integral or non-integral incorporation or connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, that layer, region, or component may be directly electrically connected or directly bonded to said other layer, region, and / or component, or one or more intermediary layers, regions, or components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, the connection is not limited to the connections shown in the accompanying drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on..." means that a component is directly connected or directly bonded to another component or directly on another component, without any intermediate components.

[0048] Furthermore, in this specification, when a portion of a layer, film, region, or plate is formed on another portion, the formation direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate is formed "below" another portion, this includes not only the case where the portion is "directly" "below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing the relationship between components, such as "between," "immediately between," or "adjacent to," and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0049] For the purposes of this disclosure, when expressions such as “at least one of…” or “any one of…” or “one or more of…” follow a list of elements, they modify the entire list of elements without modifying any individual elements within the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ) or any variations thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when expressions such as “at least one of…”, “multiple (species / beings)…”, “one of…”, and other prepositional phrases precede / follow a list of elements, they modify the entire list of elements, not individual elements within the list. When “C to D” is stated, unless otherwise specified, it means C or greater and D or less.

[0050] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, section, or part from another element, component, assembly, region, area, layer, section, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively mean “first category (or first group),” “second category (or second group),” etc.

[0051] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0052] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms, and the plural forms are intended to include the singular forms. It will also be understood that when the terms “comprising,” “having,” “including,” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0053] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree, intended to explain the inherent deviations of measured or calculated values ​​that would be recognized by those skilled in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. “About” or “approximately” as used herein includes the stated value and means within an acceptable range of deviation from the specific value as determined by those skilled in the art, taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that is tolerable to those skilled in the art. Other expressions may also be derived from those in which “substantially” has been omitted.

[0054] In some embodiments, well-known structures and arrangements may be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, wiring connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Furthermore, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Additionally, in some embodiments, blocks, units, and / or modules may be physically divided into two or more interacting individual blocks, units, and / or modules without departing from the scope of this disclosure. Furthermore, in some embodiments, without departing from the scope of this disclosure, blocks, units, and / or modules may be physically combined into more complex blocks, units, and / or modules.

[0055] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0056] Figure 1 This is a plan view showing a display device according to an embodiment.

[0057] Reference Figure 1 The display device DD according to the embodiment may include a substrate SUB, a driver chip IC, and a circuit board PCB.

[0058] The substrate SUB can include a display area DA and a non-display area NDA. The display area DA can be defined as the area used to emit light. The non-display area NDA can be defined as the area where components for transmitting signals to the display area DA are present.

[0059] Pixels PX can be located on a substrate SUB. Pixels PX can be located within a display area DA. Each of the pixels PX can emit light based on a signal applied from a non-display area NDA. Pixels PX can be repeatedly positioned within the display area DA along a first direction DR1 and along a second direction DR2 intersecting the first direction DR1. Therefore, the display area DA can emit light throughout its corresponding area.

[0060] The non-display area NDA may be adjacent to the display area DA. For example, the non-display area NDA may contact the display area DA. For example, the non-display area NDA may (e.g., in a plan view) be located around the display area DA. In one or more embodiments, the non-display area NDA may surround at least a portion of the display area DA. For example, the non-display area NDA may (e.g., in a plan view) entirely surround the display area DA, but this disclosure is not limited thereto. Drivers for driving pixels PX may be located in the non-display area NDA. For example, gate drivers, light-emitting drivers, and / or power voltage generators may be located in the non-display area NDA.

[0061] The driver chip IC can be positioned (or bonded) on the substrate SUB (as used herein, "on" can mean "above"). The driver chip IC can be located in the non-display area NDA. The driver chip IC can be spaced apart from the display area DA in a plan view. For example, the driver chip IC can be spaced apart from the display area DA in a second direction DR2, but this disclosure is not limited thereto. The driver chip IC can convert digital signals in the drive signals into analog data signals. The driver chip IC can provide analog data signals to the pixel PX. In one or more embodiments, the number of driver chip ICs can be one. However, this disclosure is not limited thereto, and the number of driver chip ICs can vary depending on the embodiment. For example, the number of driver chip ICs can be two or more.

[0062] The circuit board (PCB) can be positioned (or bonded) on the substrate SUB. For example, the PCB can be positioned (or bonded) on one end of the substrate SUB. The PCB can be located in the non-display area NDA. The PCB can be spaced apart from the driver chip IC in a plan view. For example, the PCB can be spaced apart from the driver chip IC in a second direction DR2, but this disclosure is not limited thereto. The PCB can provide drive signals and / or drive voltages, etc., to the driver chip IC and the pixel PX. In one or more embodiments, the number of PCBs can be one. However, this disclosure is not limited thereto, and the number of PCBs can vary depending on the embodiment. For example, the number of PCBs can be two or more.

[0063] In one or more embodiments, a first direction DR1 and a second direction DR2 intersecting the first direction DR1 may be defined. For example, the second direction DR2 may be substantially perpendicular to the first direction DR1. However, this disclosure is not limited thereto, and the second direction DR2 may form an acute or obtuse angle with the first direction DR1. Furthermore, a third direction DR3 intersecting the plane formed by the first direction DR1 and the second direction DR2 may be defined. For example, the third direction DR3 may be substantially perpendicular to the plane formed by the first direction DR1 and the second direction DR2. However, this disclosure is not limited thereto, and the third direction DR3 may form an acute or obtuse angle with the plane formed by the first direction DR1 and the second direction DR2.

[0064] Figure 2 It is shown Figure 1 An enlarged plan view of an example of region A.

[0065] Reference Figure 2The output pad (OP), input pad (IP), and test circuitry (PC) can be located on the substrate (SUB). The output pad (OP), input pad (IP), and test circuitry (PC) can be located in the non-display area (NDA). The output pad (OP), input pad (IP), and test circuitry (PC) can be stacked with the driver chip (IC) in a plan view.

[0066] The driver chip IC can be bonded to the output pad OP. For example, the driver chip IC can be bonded to a conductive film (e.g., Figure 3 A conductive film (ACF) is bonded to the output pad OP. The output pad OP can be repeatedly positioned along a first direction DR1 and a second direction DR2. In one or more embodiments, the output pad OP can be arranged in three rows and n columns (where n is a natural number greater than 0). For example, the output pad OP may include a first output pad OP1 located in the first row, a second output pad OP2 located in the second row, and a third output pad OP3 located in the third row. In this case, the output pad located at the outermost position relative to the second direction DR2 among the output pads OP can be the first output pad OP1 and the third output pad OP3.

[0067] However, this disclosure is not limited thereto, and in one or more embodiments, the output pads OP can be arranged in two rows and n columns (where n is a natural number greater than 0). In this case, among the output pads OP, the output pad located at the outermost position relative to the second direction DR2 can be the output pad located in the first row and the output pad located in the second row.

[0068] In one or more embodiments, the output pads OP can be arranged in one row and n columns (where n is a natural number greater than 0). In this case, the output pad located at the outermost position in the second direction DR2 of the output pads OP can be the output pad located in the first row.

[0069] In one or more embodiments, the output pads OP can be arranged in m rows (where m is a natural number greater than 3) and n columns (n ​​is a natural number greater than 0). In this case, among the output pads OP, the output pad located at the outermost position in the second direction DR2 can be the output pad located in the first row and the output pad located in the m-th row.

[0070] In summary, the output pads OP can be arranged in m rows (where m is a natural number greater than 0) and n columns (where n is a natural number greater than 0). In this case, the output pad located at the outermost position in the second direction DR2 within the output pads OP can be the output pad located in the first row and the output pad located in the m-th row.

[0071] The driver chip IC can be bonded to the input pad IP. For example, the driver chip IC can be bonded to a conductive film (e.g., Figure 5 A conductive film (ACF) is bonded to the input pad IP. The input pad IP may be spaced apart from the output pad OP in a planar view. For example, the input pad IP may be spaced apart from the output pad OP in a second direction DR2. In one or more embodiments, the input pad IP may be arranged in one row and n columns (where n is a natural number greater than 0). For example, the input pad IP may be repeatedly positioned along a first direction DR1. However, this disclosure is not limited to this, and in one or more embodiments, the input pad IP may also be arranged in m rows (where m is a natural number greater than 1) and n columns (where n is a natural number greater than 0). For example, the input pad IP may be arranged in two rows and n columns, where n is a natural number greater than 0.

[0072] In the plan view, the test circuit section PC can be located between the output pad OP and the input pad IP. For example, in the plan view, the test circuit section PC can be located between the output pad OP and the input pad IP at the outermost position on the second direction DR2. For example, in the plan view, the test circuit section PC can be located between the third output pad OP3 and the input pad IP. The test circuit section PC can be positioned in the display area (e.g., before the final product is shipped) before the final product is shipped. Figure 1 The display area DA) provides a testing area for display devices (e.g., Figure 1 The signal indicating the operating status of the display device (DD). Although not in Figure 2 As shown, the display device may also include test leads connecting some of the test circuit section PC and the output pads OP. The test circuit section PC can provide signals for testing the operating status of the display device to the display area through the test leads and some of the output pads OP.

[0073] In one or more embodiments, the display device may include a first recess GR1, a second recess GR2, and a third recess GR3. Each of the first recess GR1, the second recess GR2, and the third recess GR3 may be located in a non-display area NDA. Each of the first recess GR1, the second recess GR2, and the third recess GR3 may be at least partially superimposed on a driver chip IC in a plan view.

[0074] In one or more embodiments, the first recess GR1 may be positioned adjacent to the output pad OP. In one or more embodiments, the first recess GR1 may be positioned adjacent to the output pad OP located at its outermost position in the second direction DR2. For example, as Figure 2As shown, the first groove GR1 can be positioned adjacent to the first output pad OP1. In one or more embodiments, the first groove GR1 can extend in the first direction DR1. The first groove GR1 can overlap with some of the output pads OP in the second direction DR2 or can be aligned with some of the output pads OP in the second direction DR2, and can not overlap with other output pads OP in the second direction DR2 (e.g., it can be offset from other output pads OP relative to the first direction DR1 and the second direction DR2). For example, as... Figure 2 As shown, the first groove GR1 can be stacked on the second direction DR2 without overlapping the output pads in the first column and the output pads in the nth column of the output pads OP arranged in three rows and n columns (where n is a natural number greater than 2) (e.g., simultaneously overlapping with the output pads in other columns).

[0075] In one or more embodiments, the second recess GR2 may be positioned adjacent to the output pad OP. In one or more embodiments, the second recess GR2 may be positioned adjacent to the output pad OP located at its outermost position in the second direction DR2. For example, as Figure 2 As shown, the second recess GR2 can be positioned adjacent to the third output pad OP3. As described above, the output pads OP can be arranged in m rows (where m is a natural number greater than 0) and n columns (where n is a natural number greater than 0), and in this case, the second recess GR2 can be positioned adjacent to the output pad located in the m-th row. In one or more embodiments, the second recess GR2 can extend in the first direction DR1. The second recess GR2 can overlap with some of the output pads OP in the second direction DR2 (e.g., it can be aligned with some of the output pads OP in the second direction DR2), and can not overlap with other output pads OP in the second direction DR2 (e.g., it can be offset from other output pads OP in the first direction DR1 and the second direction DR2). For example, as Figure 2 As shown, the second groove GR2 can be stacked on the second direction DR2 without overlapping the output pads in the first column and the output pads in the nth column of the output pads OP arranged in three rows and n columns (where n is a natural number greater than 2).

[0076] In one or more embodiments, the third recess GR3 may be positioned adjacent to the input pad IP. In one or more embodiments, the third recess GR3 may extend in the first direction DR1. The third recess GR3 may overlap with some of the input pad IPs in the second direction DR2, and may not overlap with other input pad IPs in the second direction DR2. For example, as... Figure 2As shown, the third groove GR3 can be stacked on the second direction DR2 without overlapping the input pads in the first column and the input pads in the nth column of the input pads IP arranged in a row and n columns (where n is a natural number greater than 2).

[0077] Figure 3 It is along Figure 2 A sectional view of the display device taken along line I-I'. Figure 4 It is along Figure 2 A sectional view of the display device taken from line II-II'.

[0078] Reference Figure 3 and Figure 4 The display device according to the embodiments of the present disclosure (e.g., Figure 1 The display device (DD) may include a substrate SUB, a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, a fifth insulating layer IL5, a sixth insulating layer IL6, a first touch insulating layer TIL1, a second touch insulating layer TIL2, a first bump electrode BM1, a second bump electrode BM2, a third bump electrode BM3, a fourth bump electrode BM4, a conductive film ACF, a first groove GR1 and a second groove GR2, a second groove GR2, a third groove GR3, a first output pad OP1, a second output pad OP2, a third output pad OP3, an input pad IP, a test circuit section PC, and a driver chip IC.

[0079] The substrate SUB can be the base material of the display device. The substrate SUB can include transparent or opaque materials. The substrate SUB can be formed from a transparent resin substrate. Examples of transparent resin substrates include polyimide substrates. In this case, the polyimide substrate can include a first organic layer, a first barrier layer, and / or a second organic layer, etc. Optionally, the substrate SUB can include a quartz substrate (e.g., a synthetic quartz substrate, a fluorine-doped quartz substrate), a calcium fluoride substrate, a soda-lime glass substrate, and / or an alkali-free glass substrate, etc. These materials can be used alone or in combination with each other.

[0080] The first insulating layer IL1 may be located on the substrate SUB. The first insulating layer IL1 may include an inorganic material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) and / or silicon dioxide (SiO2) x C y These materials can be used individually or in combination with each other.

[0081] The second insulating layer IL2 may be located on the first insulating layer IL1. The second insulating layer IL2 may include inorganic materials, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) and / or silicon dioxide (SiO2) x C y These materials can be used individually or in combination with each other.

[0082] The first conductive pattern 110 of the first output pad OP1, the first conductive pattern 210 of the second output pad OP2, the first conductive pattern 310 of the third output pad OP3, and the first conductive pattern 410 of the input pad IP can be located on the second insulating layer IL2. The first conductive patterns 110, 210, 310, and 410 can be spaced apart from each other in a planar view.

[0083] A third insulating layer IL3 may be located on the second insulating layer IL2. The third insulating layer IL3 may cover the first conductive patterns 110, 210, 310, and 410. The third insulating layer IL3 may define a first opening, a second opening, a third opening, and a fourth opening. The first opening may expose at least a portion of the upper surface of the first conductive pattern 110. The second opening may expose at least a portion of the upper surface of the first conductive pattern 210. The third opening may expose at least a portion of the upper surface of the first conductive pattern 310. The fourth opening may expose at least a portion of the upper surface of the first conductive pattern 410. The third insulating layer IL3 may include an inorganic material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) and / or silicon dioxide (SiO2) x C y These materials can be used individually or in combination with each other.

[0084] A fourth insulating layer IL4 may be located on top of a third insulating layer IL3. The fourth insulating layer IL4 may define a fifth, sixth, seventh, and eighth opening. The fifth opening may be superimposed on a first opening in a plan view. For example, the first and fifth openings may communicate with each other to form a first via. The sixth opening may be superimposed on a second opening in a plan view. For example, the second and sixth openings may communicate with each other to form a second via. The seventh opening may be superimposed on a third opening in a plan view. For example, the third and seventh openings may communicate with each other to form a third via. The eighth opening may be superimposed on a fourth opening in a plan view. For example, the fourth and eighth openings may communicate with each other to form a fourth via. The fourth insulating layer IL4 may comprise an inorganic material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) and / or silicon dioxide (SiO2) x C y These materials can be used individually or in combination with each other.

[0085] The second conductive pattern 120 may be located on the first conductive pattern 110. The second conductive pattern 120 may fill at least a portion of the first through-hole. The second conductive pattern 120 may contact the upper surface of the first conductive pattern 110. The third conductive pattern 130 may be located on the second conductive pattern 120. The third conductive pattern 130 may fill at least a portion of the first through-hole. The third conductive pattern 130 may contact the upper surface of the second conductive pattern 120. The fourth conductive pattern 140 may be located on the third conductive pattern 130. The fourth conductive pattern 140 may fill at least a portion of the first through-hole. The fourth conductive pattern 140 may contact the upper surface of the third conductive pattern 130. The first output pad OP1 may include the first conductive pattern 110, the second conductive pattern 120, the third conductive pattern 130, and the fourth conductive pattern 140. For example, the first output pad OP1 may be a portion in which the first conductive pattern 110, the second conductive pattern 120, the third conductive pattern 130, and the fourth conductive pattern 140 are superimposed on each other in a plan view.

[0086] The second conductive pattern 220 may be located on the first conductive pattern 210. The second conductive pattern 220 may fill at least a portion of the second through-hole. The second conductive pattern 220 may contact the upper surface of the first conductive pattern 210. The third conductive pattern 230 may be located on the second conductive pattern 220. The third conductive pattern 230 may fill at least a portion of the second through-hole. The third conductive pattern 230 may contact the upper surface of the second conductive pattern 220. The fourth conductive pattern 240 may be located on the third conductive pattern 230. The fourth conductive pattern 240 may fill at least a portion of the second through-hole. The fourth conductive pattern 240 may contact the upper surface of the third conductive pattern 230. The second output pad OP2 may include the first conductive pattern 210, the second conductive pattern 220, the third conductive pattern 230, and the fourth conductive pattern 240. For example, the second output pad OP2 may be a portion in which the first conductive pattern 210, the second conductive pattern 220, the third conductive pattern 230, and the fourth conductive pattern 240 are superimposed on each other in a plan view.

[0087] The second conductive pattern 320 may be located on the first conductive pattern 310. The second conductive pattern 320 may fill at least a portion of the third through-hole. The second conductive pattern 320 may contact the upper surface of the first conductive pattern 310. The third conductive pattern 330 may be located on the second conductive pattern 320. The third conductive pattern 330 may fill at least a portion of the third through-hole. The third conductive pattern 330 may contact the upper surface of the second conductive pattern 320. The fourth conductive pattern 340 may be located on the third conductive pattern 330. The fourth conductive pattern 340 may fill at least a portion of the third through-hole. The fourth conductive pattern 340 may contact the upper surface of the third conductive pattern 330. The third output pad OP3 may include the first conductive pattern 310, the second conductive pattern 320, the third conductive pattern 330, and the fourth conductive pattern 340. For example, the third output pad OP3 may be a portion in which the first conductive pattern 310, the second conductive pattern 320, the third conductive pattern 330, and the fourth conductive pattern 340 are superimposed on each other in a plan view.

[0088] The second conductive pattern 420 may be located on the first conductive pattern 410. The second conductive pattern 420 may fill at least a portion of the fourth through-hole. The second conductive pattern 420 may contact the upper surface of the first conductive pattern 410. The third conductive pattern 430 may be located on the second conductive pattern 420. The third conductive pattern 430 may fill at least a portion of the fourth through-hole. The third conductive pattern 430 may contact the upper surface of the second conductive pattern 420. The fourth conductive pattern 440 may be located on the third conductive pattern 430. The fourth conductive pattern 440 may fill at least a portion of the fourth through-hole. The fourth conductive pattern 440 may contact the upper surface of the third conductive pattern 430. The input pad IP may include the first conductive pattern 410, the second conductive pattern 420, the third conductive pattern 430, and the fourth conductive pattern 440. For example, the input pad IP may be a portion in which the first conductive pattern 410, the second conductive pattern 420, the third conductive pattern 430, and the fourth conductive pattern 440 are superimposed on each other in a plan view.

[0089] The fifth insulating layer IL5 may be located on the fourth insulating layer IL4. The fifth insulating layer IL5 may not be located in the area where the first output pad OP1, second output pad OP2, third output pad OP3, and input pad IP are located (or the fifth insulating layer IL5 may be omitted from the area where the first output pad OP1, second output pad OP2, third output pad OP3, and input pad IP are located, or the fifth insulating layer IL5 may be separate from the area where the first output pad OP1, second output pad OP2, third output pad OP3, and input pad IP are located). For example, the fifth insulating layer IL5 may define a fifth via overlapping the first output pad OP1, second output pad OP2, and third output pad OP3 in a plan view. Furthermore, the fifth insulating layer IL5 may define a sixth via overlapping the input pad IP in a plan view. The fifth insulating layer IL5 may include organic materials such as phenolic resin, polyacrylate resin, polyimide resin, polyamide resin, silicone resin, and / or epoxy resin. These materials may be used alone or in combination with each other.

[0090] The sixth insulating layer IL6 may be located on the fifth insulating layer IL5. The sixth insulating layer IL6 may not be located in the area where the first output pad OP1, second output pad OP2, third output pad OP3, and input pad IP are located (e.g., it may be separate from the area where the first output pad OP1, second output pad OP2, third output pad OP3, and input pad IP are located). For example, the sixth insulating layer IL6 may define a seventh via overlapping the first output pad OP1, second output pad OP2, and third output pad OP3 in a plan view. The fifth and seventh vias may communicate with each other. Furthermore, the sixth insulating layer IL6 may define an eighth via overlapping the input pad IP in a plan view. The sixth and eighth vias may communicate with each other. The sixth insulating layer IL6 may comprise organic materials such as phenolic resin, polyacrylate resin, polyimide resin, polyamide resin, silicone resin, and / or epoxy resin. These materials may be used alone or in combination with each other.

[0091] The first touch insulating layer TIL1 may be located on the sixth insulating layer IL6. The first touch insulating layer TIL1 may cover at least a portion of each of the fifth insulating layer IL5 and the sixth insulating layer IL6. For example, the first touch insulating layer TIL1 may cover the side surface of the fifth insulating layer IL5 that is exposed by or defines the fifth and sixth vias.

[0092] Furthermore, the first touch insulating layer TIL1 may cover the side surfaces of the sixth insulating layer IL6 that are exposed by or define the seventh and eighth vias. The first touch insulating layer TIL1 may also cover the upper surface of the sixth insulating layer IL6. The first touch insulating layer TIL1 may cover at least a portion of the third conductive patterns 130, 230, 330, and 430. For example, the first touch insulating layer TIL1 may cover the sides of the third conductive patterns 130, 230, 330, and 430.

[0093] The first touch insulating layer TIL1 may be defined in a ninth via stacked with the first output pad OP1 in a plan view. The fourth conductive pattern 140 may cover the side surface of the first touch insulating layer TIL1 exposed by or defining the ninth via. The first touch insulating layer TIL1 may be defined in a tenth via stacked with the second output pad OP2 in a plan view. The fourth conductive pattern 240 may cover the side surface of the first touch insulating layer TIL1 exposed by the tenth via. The first touch insulating layer TIL1 may be defined in an eleventh via stacked with the third output pad OP3 in a plan view. The fourth conductive pattern 340 may cover the side surface of the first touch insulating layer TIL1 exposed by the eleventh via. The first touch insulating layer TIL1 may be defined in a twelfth via stacked with the input pad IP in a plan view. The fourth conductive pattern 440 may cover the side surface of the first touch insulating layer TIL1 exposed by the twelfth via. The first touch insulating layer TIL1 may include an inorganic material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) and / or silicon dioxide (SiO2) x C y These materials can be used individually or in combination with each other.

[0094] The second touch insulating layer TIL2 may be located on the first touch insulating layer TIL1. The second touch insulating layer TIL2 may be defined in the thirteenth via overlapping the first output pad OP1 in the plan view. The fourth conductive pattern 140 may cover the side surface of the second touch insulating layer TIL2 exposed by the thirteenth via. The ninth and thirteenth vias may communicate with each other. The second touch insulating layer TIL2 may be defined in the fourteenth via overlapping the second output pad OP2 in the plan view. The fourth conductive pattern 240 may cover the side surface of the second touch insulating layer TIL2 exposed by the fourteenth via. The tenth and fourteenth vias may communicate with each other. The second touch insulating layer TIL2 may be defined in the fifteenth via overlapping the third output pad OP3 in the plan view. The fourth conductive pattern 340 may cover the side surface of the second touch insulating layer TIL2 exposed by the fifteenth via. The eleventh and fifteenth vias may communicate with each other. The second touch insulating layer TIL2 may be defined in the sixteenth via overlapping the input pad IP in the plan view. The fourth conductive pattern 440 may cover the side surface of the second touch insulating layer TIL2 exposed by the sixteenth via. The twelfth and sixteenth vias may be interconnected. The second touch insulating layer TIL2 may include an inorganic material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiC) x), silicon oxynitride (SiO) x N y ) and / or silicon dioxide (SiO2) x C y These materials can be used individually or in combination with each other.

[0095] The first bump electrode BM1, the second bump electrode BM2, the third bump electrode BM3, and the fourth bump electrode BM4 can be located on the driver chip IC. For example, the first bump electrode BM1, the second bump electrode BM2, the third bump electrode BM3, and the fourth bump electrode BM4 can be located on the surface of the driver chip IC facing the substrate SUB. The first bump electrode BM1 can be bonded to the first output pad OP1. For example, the first bump electrode BM1 can be bonded to the first output pad OP1 via a conductive film ACF. The second bump electrode BM2 can be bonded to the second output pad OP2. For example, the second bump electrode BM2 can be bonded to the second output pad OP2 via a conductive film ACF. The third bump electrode BM3 can be bonded to the third output pad OP3. For example, the third bump electrode BM3 can be bonded to the third output pad OP3 via a conductive film ACF. The fourth bump electrode BM4 can be bonded to the input pad IP. For example, the fourth bump electrode BM4 can be bonded to the input pad IP via a conductive film ACF. Since the first bump electrode BM1 is bonded to the first output pad OP1, the second bump electrode BM2 is bonded to the second output pad OP2, the third bump electrode BM3 is bonded to the third output pad OP3, and the fourth bump electrode BM4 is bonded to the input pad IP, the driver chip IC can be bonded to the substrate SUB. For example, the driver chip IC can be bonded to the first output pad OP1, the second output pad OP2, the third output pad OP3, and the input pad IP.

[0096] In one or more embodiments, the conductive film ACF may include an adhesive member AL and conductive spheres BL. The adhesive member AL may include an insulating polymer. For example, the adhesive member AL may include epoxy resin and / or acrylic resin, etc. These materials may be used alone or in combination with each other. Each of the conductive spheres BL may include conductive fine particles. For example, the conductive fine particles may include a first portion (e.g., a core portion) and a second portion surrounding (or coating) the first portion. Each of the first and second portions may include a metal, metal oxide, and / or metal nitride, etc. These materials may be used alone or in combination with each other.

[0097] In one or more embodiments, the test circuit portion PC may include a first test pattern PC1 and a second test pattern PC2. The first test pattern PC1 may be located on a fourth insulating layer IL4. The second test pattern PC2 may be located on a fifth insulating layer IL5. The first test pattern PC1 and the second test pattern PC2 may be connected to each other through an opening formed in the fifth insulating layer IL5. However, the disclosure is not limited thereto, and the cross-sectional structure of the test circuit portion PC may vary depending on the embodiment.

[0098] The cross-sectional structures of the first groove GR1, the second groove GR2, and the third groove GR3 will be described below.

[0099] In one or more embodiments, a first touch insulating layer TIL1 may define a first hole H1. The first hole H1 may be a portion removed from the upper surface to the lower surface of the first touch insulating layer TIL1. A second touch insulating layer TIL2 may define a second hole H2. The second hole H2 may be a portion removed from the upper surface to the lower surface of the second touch insulating layer TIL2. The first hole H1 and the second hole H2 may communicate with each other to form a first groove GR1. For example, the first groove GR1 may include the first hole H1 and the second hole H2.

[0100] In one or more embodiments, a first touch insulating layer TIL1 may define a third hole H3. The third hole H3 may be a portion removed from the upper surface to the lower surface of the first touch insulating layer TIL1. A second touch insulating layer TIL2 may define a fourth hole H4. The fourth hole H4 may be a portion removed from the upper surface to the lower surface of the second touch insulating layer TIL2. The third hole H3 and the fourth hole H4 may communicate with each other to form a second groove GR2. For example, the second groove GR2 may include the third hole H3 and the fourth hole H4.

[0101] In one or more embodiments, a first touch insulating layer TIL1 may define a fifth hole H5. The fifth hole H5 may be a portion removed from the upper surface to the lower surface of the first touch insulating layer TIL1. A second touch insulating layer TIL2 may define a sixth hole H6. The sixth hole H6 may be a portion removed from the upper surface to the lower surface of the second touch insulating layer TIL2. The fifth hole H5 and the sixth hole H6 may communicate with each other to form a third groove GR3. For example, the third groove GR3 may include the fifth hole H5 and the sixth hole H6.

[0102] When the driver chip IC is bonded to the substrate SUB, an impact may be applied to the first touch insulating layer TIL1 and the second touch insulating layer TIL2 due to the pressure from the conductive ball BL. For example, the impact may be applied to the first touch insulating layer TIL1 and the second touch insulating layer TIL2 due to the pressure of the conductive ball BL on the first touch insulating layer TIL1 and the second touch insulating layer TIL2. Therefore, cracks may appear in the first touch insulating layer TIL1 and the second touch insulating layer TIL2. Impurities such as moisture may penetrate into the fifth insulating layer IL5 and the sixth insulating layer IL6 through the cracks. As a result, the fifth insulating layer IL5 and the sixth insulating layer IL6 may expand, and delamination may occur between the first touch insulating layer TIL1 and the fourth insulating layer IL4. For example, a space may be formed between the first touch insulating layer TIL1 and the fourth insulating layer IL4. In this case, impurities such as moisture may penetrate through the space into the output pad (e.g., Figure 2 Output pads (OP) and / or input pads (e.g., OP) and / or input pads (e.g., Figure 2 Corrosion can occur in the input pads (IP, etc.) and / or output pads.

[0103] Because the display device includes a first recess GR1 and a second recess GR2, impurities such as moisture that may have seeped into the space formed between the first touch insulating layer TIL1 and the fourth insulating layer IL4 can be reduced or prevented from penetrating into the output pad. Furthermore, because the display device includes a third recess GR3, impurities such as moisture that may have seeped into the space formed between the first touch insulating layer TIL1 and the fourth insulating layer IL4 can be reduced or prevented from penetrating into the input pad. For example, each of the first recess GR1, the second recess GR2, and the third recess GR3 can block or impede the penetration path of impurities such as moisture.

[0104] Figure 5 It is shown Figure 3 An enlarged cross-sectional view of an example of region B.

[0105] Reference Figures 3 to 5 In one or more embodiments, as described above, the first recess GR1 may be positioned adjacent to the first output pad OP1. In one or more embodiments, the first recess GR1 may accommodate some of the conductive patterns included in the first output pad OP1. For example, as... Figure 3 and Figure 5As shown, the first groove GR1 can accommodate at least a portion of the fourth conductive pattern 140. However, this disclosure is not limited thereto, and in one or more embodiments, the first groove GR1 can accommodate at least a portion of each of the third conductive pattern 130 and the fourth conductive pattern 140. In one or more embodiments, the first groove GR1 can accommodate at least a portion of each of the second conductive pattern 120, the third conductive pattern 130, and the fourth conductive pattern 140.

[0106] In one or more embodiments, such as Figure 2 and Figure 3 As shown, the first groove GR1 may be spaced apart from the first conductive pattern 110 in a plan view. In one or more embodiments, the first groove GR1 may be spaced apart from the second conductive pattern 120 in a plan view. In one or more embodiments, the first groove GR1 may be spaced apart from the third conductive pattern 130 in a plan view.

[0107] As described above, the second recess GR2 can be positioned adjacent to the third output pad OP3. In one or more embodiments, the second recess GR2 can accommodate some of the conductive patterns included in the third output pad OP3. For example, as Figure 3 As shown, the second groove GR2 can accommodate at least a portion of the fourth conductive pattern 340. However, this disclosure is not limited thereto, and in one or more embodiments, the second groove GR2 can accommodate at least a portion of each of the third conductive pattern 330 and the fourth conductive pattern 340. In one or more embodiments, the second groove GR2 can accommodate at least a portion of each of the second conductive pattern 320, the third conductive pattern 330, and the fourth conductive pattern 340.

[0108] In one or more embodiments, such as Figure 2 and Figure 3 As shown, the second groove GR2 may be spaced apart from the first conductive pattern 310 in a plan view. In one or more embodiments, the second groove GR2 may be spaced apart from the second conductive pattern 320 in a plan view. In one or more embodiments, the second groove GR2 may be spaced apart from the third conductive pattern 330 in a plan view.

[0109] As described above, the third recess GR3 can be positioned adjacent to the input pad IP. In one or more embodiments, the third recess GR3 can accommodate some of the conductive patterns included in the input pad IP. For example, as Figure 4As shown, the third groove GR3 can accommodate at least a portion of the fourth conductive pattern 440. However, this disclosure is not limited thereto, and in one or more embodiments, the third groove GR3 can accommodate at least a portion of each of the third conductive pattern 430 and the fourth conductive pattern 440. In one or more embodiments, the third groove GR3 can accommodate at least a portion of each of the second conductive pattern 420, the third conductive pattern 430, and the fourth conductive pattern 440.

[0110] In one or more embodiments, such as Figure 2 and Figure 4 As shown, the third groove GR3 may be spaced apart from the first conductive pattern 410 in a plan view. In one or more embodiments, the third groove GR3 may be spaced apart from the second conductive pattern 420 in a plan view. In one or more embodiments, the third groove GR3 may be spaced apart from the third conductive pattern 430 in a plan view.

[0111] Also refer to Figure 2 When the driver chip IC is bonded to the substrate SUB, stress can be applied to the substrate SUB and the insulating layer located on the substrate SUB. For example, as... Figure 2 As shown, when the test circuit portion PC includes a first surface facing the second groove GR2, a second surface facing the third groove GR3, a third surface facing the first direction DR1, and a fourth surface facing the direction opposite to the first direction DR1 in the plan view, tensile stress can be concentrated on the insulating layer located around the first surface and the insulating layer located around the second surface when the driver chip IC is bonded to the substrate SUB.

[0112] Therefore, when the second groove GR2 is located around the first surface, tensile stress may concentrate on the second groove GR2. In this case, cracks may appear in the insulating layer surrounding the second groove GR2. The cracks may propagate along the fourth insulating layer IL4 and / or the third insulating layer IL3, and may reach the first conductive pattern 310, the second conductive pattern 320, and / or the third conductive pattern 330, etc. Therefore, the first conductive pattern 310, the second conductive pattern 320, and / or the third conductive pattern 330, etc., may be damaged.

[0113] According to one or more embodiments of this disclosure, when the second recess GR2 is alternatively positioned adjacent to the third output pad OP3, tensile stress may not be applied to the second recess GR2 when the driver chip IC is bonded to the substrate SUB. For example, when the second recess GR2 is positioned adjacent to the third output pad OP3, compressive stress may be applied to the second recess GR2 when the driver chip IC is bonded to the substrate SUB. Therefore, the generation and propagation of cracks around the second recess GR2 can be reduced or prevented. For example, crack generation in the insulating layer surrounding the second recess GR2 can be reduced or prevented, and crack propagation along the insulating layer can also be reduced or prevented.

[0114] When the third groove GR3 is located around the second surface, tensile stress may concentrate on the third groove GR3. In this case, cracks may appear in the insulating layer surrounding the third groove GR3. The cracks may propagate along the fourth insulating layer IL4 and / or the third insulating layer IL3, and reach the first conductive pattern 410, the second conductive pattern 420, and / or the third conductive pattern 430, etc. Therefore, the first conductive pattern 410, the second conductive pattern 420, and / or the third conductive pattern 430, etc., may be damaged.

[0115] According to one or more embodiments of this disclosure, when the third recess GR3 is alternatively positioned adjacent to the input pad IP, tensile stress may not be applied to the third recess GR3 when the driver chip IC is bonded to the substrate SUB. For example, when the third recess GR3 is positioned adjacent to the input pad IP, compressive stress may be applied to the third recess GR3 when the driver chip IC is bonded to the substrate SUB. Therefore, the initiation and propagation of cracks around the third recess GR3 can be reduced or prevented. For example, crack formation in the insulating layer surrounding the third recess GR3 can be reduced or prevented, and crack propagation along the insulating layer can also be reduced or prevented.

[0116] According to one or more embodiments of this disclosure, when the first recess GR1 is positioned adjacent to the first output pad OP1, tensile stress may not be applied to the first recess GR1 when the driver chip IC is bonded to the substrate SUB. For example, when the first recess GR1 is positioned adjacent to the first output pad OP1, compressive stress may be applied to the first recess GR1 when the driver chip IC is bonded to the substrate SUB. Therefore, the generation and propagation of cracks around the first recess GR1 can be reduced or prevented. For example, crack generation in the insulating layer surrounding the first recess GR1 can be reduced or prevented, and crack propagation along the insulating layer can also be reduced or prevented.

[0117] As described above, the first groove GR1 can accommodate at least a portion of the fourth conductive pattern 140. The fourth conductive pattern 140 can reduce or prevent the generation and propagation of cracks around the first groove GR1. For example, the fourth conductive pattern 140 can reduce or prevent the generation of cracks in the fourth insulating layer IL4 located around the first groove GR1. This may be because, when the driver chip IC is pressed onto the substrate SUB, the fourth conductive pattern 140 can reduce or prevent stress from being applied to the fourth insulating layer IL4 exposed through the first groove GR1.

[0118] As described above, the second groove GR2 can accommodate at least a portion of the fourth conductive pattern 340. The fourth conductive pattern 340 can reduce or prevent the generation and propagation of cracks around the second groove GR2. For example, the fourth conductive pattern 340 can reduce or prevent the generation of cracks in the fourth insulating layer IL4 located around the second groove GR2. This may be because, when the driver chip IC is pressed onto the substrate SUB, the fourth conductive pattern 340 can reduce or prevent stress from being applied to the fourth insulating layer IL4 exposed through the second groove GR2.

[0119] As described above, the third groove GR3 can accommodate at least a portion of the fourth conductive pattern 440. The fourth conductive pattern 440 can reduce or prevent the generation and propagation of cracks around the third groove GR3. For example, the fourth conductive pattern 440 can reduce or prevent the generation of cracks in the fourth insulating layer IL4 located around the third groove GR3. This may be because, when the driver chip IC is pressed onto the substrate SUB, the fourth conductive pattern 440 can reduce or prevent stress from being applied to the fourth insulating layer IL4 exposed through the third groove GR3.

[0120] Figure 6 It is shown that it includes Figure 1 A cross-sectional view of pixels in a display device.

[0121] In description Figure 6 When referring to pixel PX, the same reference numerals are used in conjunction with the reference numerals. Figure 3 The components described are essentially similar to those described, and their detailed descriptions can be omitted.

[0122] Reference Figure 6 The pixel PX may include a substrate SUB, a transistor TR, a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, a fifth insulating layer IL5, a sixth insulating layer IL6, a second gate electrode GE2, a connection electrode CNE, a light-emitting element LED, a pixel defining layer PDL, a packaging layer TFE, a first touch insulating layer TIL1, a second touch insulating layer TIL2, a touch electrode TE, and a third touch insulating layer TIL3.

[0123] The transistor TR may include an active pattern ACT, a first gate electrode GE1, a first contact electrode SE, and a second contact electrode DE. The capacitor CST may include a first gate electrode GE1 and a second gate electrode GE2. The light-emitting element LED may include a pixel electrode PE, a light-emitting layer EML, and a common electrode CE. The touch electrode TE may include a first touch electrode TE1 and a second touch electrode TE2.

[0124] The active pattern ACT can be located on the first insulating layer IL1. The active pattern ACT can include a first contact region, a second contact region, and a channel region located between the first and second contact regions. The active pattern ACT can include inorganic semiconductors (e.g., amorphous silicon, polycrystalline silicon, metal oxide semiconductors) and / or organic semiconductors. These materials can be used alone or in combination with each other. The metal oxide semiconductor can include binary compounds (ABs) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), and / or magnesium (Mg). x ), ternary compounds (AB) x C y ) and / or quaternary compounds (AB) x C y D z These materials can be used alone or in combination with each other. For example, metal oxide semiconductors can include zinc oxide (ZnO). x Gallium oxide (GaO) x ), Tin oxide (SnO) x Indium oxide (InO) x Indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), and indium gallium zinc oxide (IGZO). These materials can be used individually or in combination with each other.

[0125] The second insulating layer IL2 may cover the active pattern ACT. The first gate electrode GE1 may be located on the second insulating layer IL2. The first gate electrode GE1 may be superimposed on the channel region of the active pattern ACT in a planar view. The first gate electrode GE1 may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and / or scandium (Sc). These materials may be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide. These materials may be used alone or in combination with each other. Furthermore, examples of metal nitrides may include aluminum nitride (AlN). x ), Tungsten nitride (WN)x ) and / or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0126] In one or more embodiments, the first gate electrode GE1, the first conductive pattern (e.g., Figure 3 The first conductive patterns 110, 210 and 310 and Figure 4 The first conductive pattern 410 may include substantially the same material and may be located in the same layer. A third insulating layer IL3 may cover the first gate electrode GE1. A second gate electrode GE2 may be located on the third insulating layer IL3. The second gate electrode GE2 may be superimposed on the first gate electrode GE1 in a planar view. A capacitor CST can be formed by superimposing the first gate electrode GE1 and the second gate electrode GE2 in a planar view. For example, the capacitor CST may include the first gate electrode GE1 and the second gate electrode GE2. The second gate electrode GE2 may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials, etc. Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and / or scandium (Sc), etc. These materials may be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide, etc. These materials may be used alone or in combination with each other. Furthermore, examples of metal nitrides may include aluminum nitride (AlN). x ), Tungsten nitride (WN) x ) and / or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0127] The fourth insulating layer IL4 may cover the second gate electrode GE2. The first contact electrode SE and the second contact electrode DE may be located on the fourth insulating layer IL4. The first contact electrode SE may be connected to the first contact area of ​​the active pattern ACT through a contact hole that penetrates the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4 (or defines a contact hole that penetrates the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4, or is defined by the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4). The second contact electrode DE may be connected to the second contact area of ​​the active pattern ACT through a contact hole that penetrates (or defines a contact hole that penetrates) the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. For example, each of the first contact electrode SE and the second contact electrode DE may include a metal, an alloy, a metal nitride, a conductive metal oxide, and / or a transparent conductive material, etc. Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and / or scandium (Sc), etc. These materials can be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide, etc. These materials can be used alone or in combination with each other. Furthermore, examples of metal nitrides may include aluminum nitride (AlN). x ), Tungsten nitride (WN) x ) and / or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0128] In one or more embodiments, the first contact electrode SE, the second contact electrode DE, and the second conductive pattern (e.g., Figure 3 The second conductive patterns 120, 220 and 320 and Figure 4 The second conductive pattern 420 may include substantially the same material as each other and may be located in the same layer as each other.

[0129] The fifth insulating layer IL5 may cover the first contact electrode SE and the second contact electrode DE. The connection electrode CNE may be located on the fifth insulating layer IL5. The connection electrode CNE can be connected to the transistor TR through a contact hole penetrating (or defining a connection through) the fifth insulating layer IL5. For example, the connection electrode CNE can be connected to the second contact electrode DE through a contact hole penetrating (or defining a connection through) the fifth insulating layer IL5. The connection electrode CNE may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and / or scandium (Sc). These materials may be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide. These materials may be used alone or in combination with each other. Furthermore, examples of metal nitrides may include aluminum nitride (AlN). x ), Tungsten nitride (WN) x ) and / or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0130] In one or more embodiments, the connecting electrode CNE, the third conductive pattern (e.g., Figure 3 The third conductive patterns 130, 230 and 330 and Figure 4 The third conductive pattern (430) may include substantially the same material as each other and may be located in the same layer as each other.

[0131] The sixth insulating layer IL6 may cover the connection electrode CNE. The pixel electrode PE may be located on the sixth insulating layer IL6. The pixel electrode PE may be connected to the connection electrode CNE through contact holes penetrating (or defining a path through) the sixth insulating layer IL6. The pixel electrode PE may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials, etc. These materials may be used alone or in combination with each other. In one or more embodiments, the pixel electrode PE may have a stacked structure including ITO / Ag / ITO. For example, the pixel electrode PE may be used as the anode of a light-emitting element LED.

[0132] The pixel defining layer (PDL) may be located on the sixth insulating layer (IL6). The PDL may cover the side of the pixel electrode (PE). For example, a pixel opening may be defined in the PDL to expose a portion of the upper surface of the pixel electrode (PE). In one or more embodiments, the PDL may comprise inorganic or organic materials. In one or more embodiments, the PDL may comprise organic materials, such as epoxy resins and / or silicone resins. These materials may be used alone or in combination with each other. In one or more embodiments, the PDL may also comprise a light-blocking material containing black pigments and / or black dyes.

[0133] The emissive layer (EML) may be located on the pixel electrode (PE). The emissive layer (EML) may include an organic material that emits light of a selected color. For example, the emissive layer (EML) may include an organic material that emits red light. However, this disclosure is not limited thereto.

[0134] The common electrode (CE) can be located on the light-emitting layer (EML). The common electrode (CE) can include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. These materials can be used individually or in combination. The common electrode (CE) can be used as the cathode of an LED (light-emitting element).

[0135] The encapsulation layer TFE can be located on the common electrode CE. The encapsulation layer TFE can reduce or prevent external impurities (such as moisture) from penetrating into the pixel electrode PE, the light-emitting layer EML, and the common electrode CE. The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the inorganic layer may include silicon oxide, silicon nitride, and / or silicon oxynitride, etc. These materials may be used alone or in combination with each other. The organic layer may include polymeric materials (such as polyacrylate).

[0136] The first touch insulating layer TIL1 may be located on the encapsulation layer TFE. The first touch electrode TE1 may be located on the first touch insulating layer TIL1. The first touch electrode TE1 may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and / or scandium (Sc). These materials may be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide. These materials may be used alone or in combination with each other. Furthermore, examples of metal nitrides may include aluminum nitride (AlN). x ), Tungsten nitride (WN) x ) and / or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0137] The second touch insulating layer TIL2 may cover the first touch electrode TE1. The second touch electrode TE2 may be located on the second touch insulating layer TIL2. In one or more embodiments, the second touch electrode TE2 may be connected to the first touch electrode TE1 through a contact hole penetrating (or defining a path through) the second touch insulating layer TIL2. The second touch electrode TE2 may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials, etc. Examples of metals may include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and / or scandium (Sc), etc. These materials may be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide, etc. These materials may be used alone or in combination with each other. In addition, examples of metal nitrides may include aluminum nitride (AlN). x ), Tungsten nitride (WN) x ) and / or chromium nitride (CrN) x These materials can be used individually or in combination with each other.

[0138] In one or more embodiments, the second touch electrode TE2, the fourth conductive pattern (e.g., Figure 3 The fourth conductive patterns 140, 240 and 340 and Figure 4 The fourth conductive pattern (440) may include substantially the same material as each other and may be located in the same layer as each other.

[0139] The third touch insulating layer TIL3 may be located on the second touch insulating layer TIL2 to cover the second touch electrode TE2. In one or more embodiments, the third touch insulating layer TIL3 may be located in the display area (e.g., Figure 1 The display area (DA) is located in the driver chip (e.g., Figure 1 The third touch insulating layer TIL3 is omitted from the portion where the driver chip IC is located. However, this disclosure is not limited thereto, and in one or more embodiments, the third touch insulating layer TIL3 may also be located in the portion where the driver chip is located. The third touch insulating layer TIL3 may comprise an inorganic material, such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) and / or silicon dioxide (SiO2) x C y These materials can be used individually or in combination with each other.

[0140] Reference Figure 6 One or more embodiments of the pixel PX have been described. However, the pixel PX is not limited to... Figure 6 The structure shown is illustrated. For example, a pixel PX can include any structure that receives electrical signals and emits light with a brightness corresponding to the intensity of the electrical signals.

[0141] Figure 7 It is shown Figure 3 An enlarged cross-sectional view of an example of region B.

[0142] When compared with reference Figure 5 When comparing the described components, refer to Figure 7 The components described may differ only in terms of the side insulation layer SL. Therefore, redundant explanations can be omitted or simplified.

[0143] Reference Figure 7 The display device according to the embodiment (e.g., Figure 1 The display device (DD) may further include a side insulating layer SL. The side insulating layer SL may cover at least a portion of the third conductive pattern 130. For example, the side insulating layer SL may cover a side surface of the third conductive pattern 130. The side insulating layer SL may be used to protect the third conductive pattern 130. For example, when an insulating layer is formed by an etching process (e.g., ...), Figure 3 The first touch insulating layer (TIL1) and conductive patterns (e.g., Figure 3 When the fourth conductive pattern 140 is formed, the side insulating layer SL can protect the third conductive pattern 130 from being etched, thereby reducing or preventing damage to the third conductive pattern 130.

[0144] Figure 7 An example in which the side insulating layer SL covers the side surface of the third conductive pattern 130 can be shown. However, this disclosure is not limited to this, and the side insulating layer SL can cover the third conductive pattern (e.g., Figure 3 The third conductive patterns 230 and 330 and Figure 4 The side surface of the third conductive pattern 430.

[0145] Figure 8 It is shown Figure 1 An enlarged plan view of an example of region A.

[0146] When compared with reference Figure 2 When comparing the described components, refer to Figure 8 The components described may differ only in the first groove GR1', the second groove GR2', and the third groove GR3'. Therefore, redundant explanations can be omitted or simplified.

[0147] Reference Figure 8The display device may include a first recess GR1', a second recess GR2', and a third recess GR3'. The first recess GR1' may be positioned adjacent to the first output pad OP1, the second recess GR2' may be positioned adjacent to the third output pad OP3, and the third recess GR3' may be positioned adjacent to the input pad IP.

[0148] In one or more embodiments, the first recess GR1' may be arranged repeatedly in an island shape. For example, the first recess GR1' may be arranged repeatedly in an island shape along a first direction DR1. For example, the first recess GR1' may include a plurality of first recesses that repeat in an island shape, and each of the plurality of first recesses may be stacked with or aligned with a corresponding output pad in the first output pad OP1 in the second direction DR2.

[0149] In one or more embodiments, the second recess GR2' may be arranged repeatedly in an island shape. For example, the second recess GR2' may be arranged repeatedly in an island shape along the first direction DR1. For example, the second recess GR2' may include a plurality of second recesses that repeat in an island shape, and each of the plurality of second recesses may be stacked on the second direction DR2 with a corresponding output pad in the third output pad OP3, or may be aligned on the second direction DR2 with a corresponding output pad in the third output pad OP3.

[0150] In one or more embodiments, the third recess GR3' may be arranged repeatedly in an island shape. For example, the third recess GR3' may be arranged repeatedly in an island shape along the first direction DR1. For example, the third recess GR3' may include a plurality of third recesses that repeat in an island shape, and each of the plurality of third recesses may be stacked with or aligned with a corresponding input pad in the input pad IP in the second direction DR2.

[0151] The cross-sectional structures of the first groove GR1' and the second groove GR2' can be compared with those of the reference groove. Figure 3 The cross-sectional structures of the first groove GR1 and the second groove GR2 are substantially similar. The cross-sectional structure of the third groove GR3' can be compared with that of the reference. Figure 4 The cross-sectional structure of the third groove GR3 described is basically similar.

[0152] Figure 9 It is shown Figure 1 An enlarged plan view of an example of region A.

[0153] When compared with reference Figure 2 When comparing the described components, refer to Figure 9The components described may differ only in the first groove GR1'', the second groove GR2'', and the third groove GR3''. Therefore, redundant explanations can be omitted or simplified.

[0154] Reference Figure 9 The display device may include a first recess GR1'', a second recess GR2'', and a third recess GR3''. The first recess GR1'' may be positioned adjacent to the first output pad OP1, the second recess GR2'' may be positioned adjacent to the third output pad OP3, and the third recess GR3'' may be positioned adjacent to the input pad IP.

[0155] In one or more embodiments, the first groove GR1'' may be stacked with the output pad OP in the second direction DR2. For example, each of the output pads OP may be stacked with a corresponding portion of the first groove GR1'' in the second direction DR2, or may be aligned with a corresponding portion of the first groove GR1'' in the second direction DR2. For example, when the output pads OP are arranged in m rows (where m is a natural number greater than 0) and n columns (where n is a natural number greater than 1), the first groove GR1'' may extend in the first direction DR1 from the portion of the output pad in the first column where it is located to the portion of the output pad in the nth column where it is located.

[0156] In one or more embodiments, the second groove GR2'' may be stacked with the output pad OP in the second direction DR2. For example, each of the output pads OP may be stacked with a corresponding portion of the second groove GR2'' in the second direction DR2. For example, the second groove GR2'' may extend in the first direction DR1 from the portion where the output pad of the first column is located to the portion where the output pad of the nth column is located.

[0157] In one or more embodiments, the third groove GR3'' may be superimposed on the input pad IP in the second direction DR2. For example, each of the input pads IP may be superimposed on a corresponding portion of the third groove GR3'' in the second direction DR2. For example, the third groove GR3'' may extend in the first direction DR1 from the portion where the input pad of the first column is located to the portion where the input pad of the nth column is located.

[0158] The cross-sectional structures of the first groove GR1'' and the second groove GR2'' can be compared with those of the reference groove. Figure 3 The cross-sectional structures of the first groove GR1 and the second groove GR2 are substantially similar. The cross-sectional structure of the third groove GR3'' can be compared with the reference. Figure 4 The cross-sectional structure of the third groove GR3 described is basically similar.

[0159] Figure 10 This is a block diagram illustrating an electronic device according to an embodiment. Figure 11 It is shown that Figure 10 The diagram shows an example of an electronic device implemented as a smartphone.

[0160] Reference Figure 10 and Figure 11 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be... Figure 1 The display device DD. In addition, the electronic device 1000 may also include multiple ports that allow communication with devices such as video cards, sound cards, memory cards, USB devices or other systems.

[0161] In one or more embodiments, such as Figure 11 As shown, the electronic device 1000 can be implemented as a smartphone. However, this is merely an example, and the electronic device 1000 can be implemented as various devices depending on the embodiment. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation system, computer monitor, laptop computer and / or head-mounted display device, etc.

[0162] Processor 1010 may be a microprocessor, a central processing unit (“CPU”), and / or an application processor, etc. Processor 1010 may be connected to other components via address buses, control buses, and / or data buses, etc. In one or more embodiments, processor 1010 may also be connected to an expansion bus, such as a peripheral component interconnect (“PCI”) bus.

[0163] The memory device 1020 can store data suitable for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices (such as erasable programmable read-only memory (“EPROM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory devices, phase-change random access memory (“PRAM”), resistive random access memory (“RRAM”), nanofloating gate memory (“NFGM”), polymer random access memory (“PoRAM”), magnetic random access memory (“MRAM”), ferroelectric random access memory (“FRAM”) and / or volatile memory devices (such as dynamic random access memory (“DRAM”), static random access memory (“SRAM”) and / or mobile DRAM, etc.).

[0164] Storage device 1030 may include solid-state drives (“SSDs”), hard disk drives (“HDDs”), and / or CD-ROMs, etc.

[0165] Input / output device 1040 may include input methods (such as a keyboard, keypad, touchpad, touch screen, mouse) and / or output methods (such as a speaker, printer). In one or more embodiments, display device 1060 may be included in input / output device 1040.

[0166] The power supply 1050 can supply power suitable for the operation of the electronic device 1000. For example, the power supply 1050 can supply power for the operation of the display device 1060.

[0167] The display device 1060 can be connected to other components via a bus or other communication link.

[0168] This disclosure can be applied to various display devices. For example, this disclosure applies to various display devices, such as display devices for vehicles, ships and aircraft, display devices for portable communication devices, display devices for exhibitions or information transmission, and medical display devices, etc.

[0169] The foregoing is illustrative of the embodiments and should not be construed as limiting them. Although some embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the aspects of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It is therefore understood that the foregoing is illustrative of various embodiments and should not be construed as limiting oneself to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A display device, the display device comprising: The substrate includes a display area and a non-display area adjacent to the display area; A light-emitting element, located above the substrate and in the display area; An output pad, located above the substrate and in the non-display area; An input pad is located above the base and in the non-display area, and is spaced apart from the output pad in the plan view; The first groove is adjacent to the output pad; as well as The driver chip is coupled to the output pad and the input pad.

2. The display device according to claim 1, wherein, The first groove is adjacent to the corresponding output pad in the output pad at the outermost position.

3. The display device according to claim 2, wherein, The corresponding output pad in the output pad at the outermost position comprises stacked conductive patterns, and The first groove accommodates one or more of the conductive patterns.

4. The display device according to claim 2, wherein, The corresponding output pad in the output pad at the outermost position includes a first conductive pattern, a second conductive pattern above the first conductive pattern, a third conductive pattern above the second conductive pattern, and a fourth conductive pattern above the third conductive pattern. The first groove accommodates at least a portion of the fourth conductive pattern.

5. The display device according to claim 4, wherein, The first groove is spaced apart from the third conductive pattern in the plan view.

6. The display device according to claim 4, further comprising: The first touch electrode is located above the light-emitting element; as well as The second touch electrode is located above the first touch electrode. The fourth conductive pattern and the second touch electrode are on the same layer.

7. The display device according to claim 1, wherein, The output pads include the output pads in the first row, the output pads in the second row, and the output pads in the third row. The first groove is adjacent to the output pad of the output pad in the first row.

8. The display device according to claim 7, further comprising a second recess adjacent to the output pad in the third row of the output pad.

9. The display device according to claim 8, wherein, The output pads in the third row comprise stacked conductive patterns, and The second groove accommodates one or more of the conductive patterns.

10. The display device according to claim 8, wherein, The output pad in the third row includes a first conductive pattern, a second conductive pattern above the first conductive pattern, a third conductive pattern above the second conductive pattern, and a fourth conductive pattern above the third conductive pattern. The second groove accommodates at least a portion of the fourth conductive pattern and is spaced apart from the third conductive pattern in a plan view.

11. The display device of claim 1, further comprising a third recess adjacent to the input pad, the input pad comprising stacked conductive patterns. in, The third groove accommodates one or more of the conductive patterns.

12. The display device according to claim 1, wherein, The first groove is arranged in an island-like pattern.

13. A display device, the display device comprising: The substrate includes a display area and a non-display area adjacent to the display area; A light-emitting element, located above the substrate and in the display area; An output pad, located above the substrate and in the non-display area; An input pad is located above the base and in the non-display area, and is spaced apart from the output pad in the plan view; The first groove is adjacent to the input pad; as well as The driver chip is coupled to the output pad and the input pad.

14. The display device according to claim 13, wherein, The input pad comprises stacked conductive patterns, and The first groove accommodates one or more of the conductive patterns.

15. The display device according to claim 13, wherein, The input pad includes a first conductive pattern, a second conductive pattern above the first conductive pattern, a third conductive pattern above the second conductive pattern, and a fourth conductive pattern above the third conductive pattern. The first groove accommodates at least a portion of the fourth conductive pattern.

16. The display device according to claim 15, wherein, The first groove is spaced apart from the third conductive pattern in the plan view.

17. The display device according to claim 15, further comprising: The first touch electrode is located above the light-emitting element; as well as The second touch electrode is located above the first touch electrode. The fourth conductive pattern and the second touch electrode are on the same layer.

18. An electronic device, the electronic device comprising: The substrate includes a display area and a non-display area adjacent to the display area; A light-emitting element, located above the substrate and in the display area; An output pad, located above the substrate and in the non-display area; An input pad is located above the base and in the non-display area, and is spaced apart from the output pad in the plan view; The first groove is adjacent to the output pad; The driver chip is coupled to the output pad and the input pad; as well as A memory device is configured to store data information.

19. The electronic device according to claim 18, wherein, The first groove is adjacent to the corresponding output pad in the output pad at the outermost position.

20. The electronic device according to claim 19, wherein, The corresponding output pad in the output pad at the outermost position includes stacked conductive patterns, and The first groove accommodates one or more of the conductive patterns.

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