Display device

Abstract

Disclosed is a display device including: a substrate including a display area including a plurality of sub-pixels and a non-display area surrounding the display area; a power voltage line formed in a first mesh shape and disposed in the non-display area; an encapsulation layer disposed on the entire display area and a portion of the non-display area in which the power voltage line is disposed; and a light-blocking layer disposed on the encapsulation layer to overlap the power voltage line.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0180885, filed on December 6, 2024, which is incorporated herein by reference as fully set forth herein. Technical Field

[0002] This disclosure relates to display devices, and more specifically, to display devices having improved transparency and the ability to eliminate the sense of difference between areas. Background Technology

[0003] Display devices that display images in TVs, monitors, smartphones, tablets, and laptops are being used in a wide variety of ways and forms.

[0004] These display devices do not require a separate light source, but they do require compact and clear color display. Therefore, self-emissive display devices, such as organic light-emitting display devices and quantum dot light-emitting display devices, are considered competitive applications.

[0005] Furthermore, the self-emissive display device has a plurality of sub-pixels on a substrate, and each sub-pixel has a light-emitting diode, which has two electrodes facing each other and a light-emitting layer between the electrodes.

[0006] Recently, the application of transparent display devices that can simultaneously achieve both luminescence and transparent display by adopting such self-emissive display devices is being considered. Summary of the Invention

[0007] Therefore, this disclosure relates to display devices that substantially eliminate one or more problems caused by the limitations and disadvantages of related technologies.

[0008] A technical task of the display device according to the embodiments of this disclosure is to ensure a certain level or higher level of transmittance in the non-display area, including power supply voltage lines and circuitry, to have increased transmittance.

[0009] Another technical task of the display device according to the embodiments of this disclosure is to increase the transmissivity of the non-display area to have a transmissivity similar to that of the display area, and to improve the sense of difference.

[0010] Another technical task of the display device according to the embodiments of this disclosure is to prevent reflective visibility caused by the metal pattern having a connection with the power supply voltage line in the non-display area.

[0011] Another technical objective of the display device according to the embodiments of this disclosure is to increase pure transmittance without the visibility of objects or images located on the surface of the display device opposite to the display surface, such as diffraction or interference.

[0012] Another technical task of the display device according to the embodiments of this disclosure is to reduce cathode resistance and improve image quality through power supply voltage lines in the non-display area and the upper connection structure.

[0013] Another technical objective of the display device according to the embodiments of this disclosure is to achieve an environmentally friendly display device.

[0014] Other advantages, aspects, and features of this disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon study of the following, or may be learned by practice of this disclosure. The aspects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0015] To achieve these and other advantages, and for the purposes of this disclosure, as presented and broadly described herein, the display device includes: a substrate including a display area comprising a plurality of subpixels and a non-display area surrounding the display area; power supply voltage lines formed in a first grid shape and disposed in the non-display area; an encapsulation layer disposed throughout the portion of the display area and the non-display area where the power supply voltage lines are disposed; and a light-shielding layer disposed on the encapsulation layer to overlap the power supply voltage lines.

[0016] The light-shielding layer can be arranged in a second grid shape to overlap the entire power voltage line.

[0017] In each region corresponding to the power supply voltage line, the light-shielding layer may have a width greater than that of the power supply voltage line.

[0018] It should be understood that the foregoing general description and the following detailed description of this disclosure are both exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0019] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and constituting a part of this application, illustrate embodiments of this disclosure and, together with the specification, serve to illustrate the principles of this disclosure. In the drawings:

[0020] Figure 1 This is a plan view showing a display device according to one embodiment of the present disclosure;

[0021] Figure 2 yes Figure 1 A circuit diagram of a sub-pixel;

[0022] Figure 3 yes Figure 1 A magnified view of region A;

[0023] Figure 4 It is along Figure 3 A cross-sectional view taken from line I-I';

[0024] Figure 5 yes Figure 1 A magnified view of region B;

[0025] Figure 6 It is along Figure 5 A cross-sectional view taken from line II-II';

[0026] Figure 7 It shows the corresponding Figure 4 A plan view of the light-shielding layer of the power supply voltage line;

[0027] Figures 8 to 10 It is shown Figure 7 A plan view of the implementation scheme of the anode virtual pattern; and

[0028] Figure 11 This is a cross-sectional view showing a display device according to another embodiment of the present disclosure. Detailed Implementation

[0029] The advantages and features of this disclosure and its implementation methods will be illustrated by the embodiments described below with reference to the accompanying drawings. However, this disclosure may be presented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be comprehensive and complete, and will fully communicate the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0030] The same reference numerals denote the same constituent elements. To effectively describe the technical content, the thickness, proportions, and dimensions of the constituent elements may be exaggerated in the drawings. Furthermore, for ease of description, the dimensions and proportions of the constituent elements shown in the drawings differ from the actual dimensions and proportions, and therefore, the dimensional proportions of the constituent elements are not limited to those shown in the drawings.

[0031] It will be understood that when a component (or region, layer, part, etc.) is referred to as being "set on", "connected to", or "linked to" another component, a component can be directly connected to / linked to another component, or a third component can be set between two components.

[0032] The term "and / or" is used to include one or more combinations of related configurations.

[0033] It will be understood that while the terms “first,” “second,” etc., may be used herein to describe a wide variety of elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element mentioned in the following description may represent a second element. Similarly, a second element may represent a first element. Unless otherwise expressly stated, singular expressions include plural meanings.

[0034] Terms such as “below,” “under,” “above,” and “over” are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are interpreted based on the orientations shown in the drawings. For example, one or more other components may be positioned between two parts unless “directly” or “adjacent” is used. Spatially related terms such as “below,” “below,” “under,” “above,” and “over” can be used to readily describe the relationship between one device or component as shown in the drawings and other devices or components. These spatially relative terms should be understood to cover different orientations of the device during use or operation, in addition to the orientations shown in the drawings. For example, if one of the devices in the drawings is flipped, then the element described as “below” or “under” the other element will be oriented “over” the other element. Thus, the exemplary term “below” can cover both downward and upward directions.

[0035] In this specification, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, operations, elements, components or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, figures, steps, operations, elements, components or combinations thereof.

[0036] The various embodiments of this disclosure may be linked or combined with each other in part or in whole, and may operate differently from each other and be technically driven as will be fully understood by those skilled in the art. The embodiments of this disclosure may be carried out independently of each other or together in an interdependent relationship.

[0037] In the following, a detailed description of a display device according to an embodiment of the present disclosure will be given in conjunction with the accompanying drawings.

[0038] Figure 1 This is a plan view showing a display device according to one embodiment of the present disclosure, and Figure 2 yes Figure 1 A circuit diagram of a sub-pixel.

[0039] Reference Figure 1 and Figure 2 According to one embodiment of the present disclosure, a light-emitting display device 1000 may include a display panel DP. The display device 1000 may also include a housing accommodating a side surface of the display panel DP and a lower portion of the display panel DP. The non-active region NA of the display panel DP may be shielded by the housing or covered by a separate light-shielding film. A printed circuit film and / or a battery may be disposed between the lower portion of the display panel DP and the housing.

[0040] The display panel DP may include a substrate 110 and a driver connected to the substrate 110. The substrate 110 includes an active region AA and an active region NA surrounding the active region AA. The active region AA is also referred to as the display region, and the active region NA is also referred to as the non-display region. In some embodiments, the driver may be disposed in the active region NA of the substrate 110 to be integrated with a configuration of an array disposed in the active region AA, and / or the driver may be connected to the pad portion PAD of the substrate 110 in a chip-on-glass (COG) manner, and / or may be connected to a printed circuit board via a film or connector in a chip-on-film (COF) manner on the pad portion PAD of the substrate 110. Alternatively, the driver may include both a configuration integrated into the substrate 110 and an external configuration of COG or COF. Figure 1 In the example shown, an example of a gate-in-panel (GIP) type gate driver (GIP) is illustrated as a driver in the non-active region NA. As a data driver, a printed circuit board or COF film including a driver IC can be connected to the pad portion PAD of the substrate 110.

[0041] The active region AA is the area for displaying the image. A plurality of gate lines GL and a plurality of data lines DL are disposed within the active region AA of the display panel DP. Furthermore, the active region AA may include sub-pixels SP: SP1, SP2, SP3 (in... Figure 3 In the middle, each of the sub-pixels is connected to at least one of the plurality of gate lines GL and at least one of the plurality of data lines DL.

[0042] The region other than the active region AA can be the non-active region NA.

[0043] The non-active region NA can be located in the edge region surrounding the active region AA of the displayed image. At least one driver for driving a plurality of sub-pixels SP can be located in the non-active region NA. The at least one driver may include an in-panel gate (GIP). The in-panel gate (GIP) can be connected to a plurality of gate lines GL of the active region AA, and gate voltage signals can be sequentially supplied to the plurality of gate lines GL.

[0044] For example, based on a gate control signal input from a timing controller, a gate driver GIP configured as an in-panel gate (GIP) outputs a gate signal to a gate line GL. The in-panel gate (GIP) may include a plurality of transistors, and these transistors may be formed using the same process as the transistors of the sub-pixel SP.

[0045] Various additional elements for driving the sub-pixels SP in the active region AA can be further disposed in the passive region NA. For example, the passive region NA may include a power supply voltage line 142 surrounding the edge of the display panel DP outside the gate driver GIP. In the display device 1000 according to an embodiment of the present disclosure, the power supply voltage line 142 may be configured in a grid shape with openings, allowing light to pass through the openings to increase the transmittance of the passive region NA. In addition to the power supply voltage line 142 and the gate driver GIP, the passive region NA may also include a plurality of clock lines and other signal lines. The plurality of clock lines and other signal lines may be electrically connected to the gate driver GIP and / or the pad portion PAD.

[0046] The power supply line 142 can be connected to multiple locations to receive a uniform power supply voltage supplied from the pad portion PAD.

[0047] At least one sub-pixel SP from a plurality of pixels may include a first transistor T1, a second transistor T2, a storage capacitor Cst, a compensation circuit CC, and a light-emitting element ED, such as Figure 2 As shown.

[0048] For example, the first transistor T1 can be a switching transistor, and the second transistor T2 can be a driving transistor.

[0049] The first electrode (e.g., drain electrode) of the first transistor T1 is conductively connected to the data line DL, and the second electrode (e.g., source electrode) of the first transistor T1 is conductively connected to the first node N1. The gate electrode of the first transistor T1 is conductively connected to the gate line GL. The first transistor T1 transmits a data signal supplied via the data line DL to the first node N1 in response to a scan signal supplied via the gate line GL.

[0050] The storage capacitor Cst is conductively connected to the first node N1 and is charged by the voltage applied to the first node N1.

[0051] The first source-drain electrode (e.g., drain electrode) of the second transistor T2 receives a high potential voltage (high potential drive voltage) EVDD, and the second source-drain electrode (e.g., source electrode) of the second transistor T2 is conductively connected to the anode of the light-emitting element ED. The second transistor T2 can control the amount of drive current flowing to the light-emitting element ED based on the voltage difference between the gate electrode and the source electrode.

[0052] The semiconductor layer of the first transistor T1 and / or the second transistor T2 may contain silicon, such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or low-temperature polycrystalline silicon (poly-Si), or may contain oxide semiconductors.

[0053] In the display device of the embodiments of this disclosure, at least one of the transistors formed on the substrate 110 may comprise an oxide semiconductor layer. This can provide a variety of advantages, such as stable cutoff characteristics compared to other materials, formation at low temperatures, maintenance of amorphous properties, and high mobility.

[0054] The light-emitting element (ED) outputs light corresponding to the driving current. The ED has an anode connected to a second transistor T2 and a cathode connected to a first power supply voltage line, which is supplied with a ground voltage or a low-potential voltage (low-potential common voltage) EVSS. The ED can output light corresponding to one of the colors red, green, blue, and white in each sub-pixel.

[0055] The light-emitting element (ED) may include an anode, an intermediate layer disposed on the anode, and a cathode. The intermediate layer may include at least one light-emitting layer. In some embodiments, when an electric field is formed between the anode and the cathode, the intermediate layer may emit light of the same color, such as white light, for each sub-pixel, or may emit light of different colors, such as red, green, or blue light, for each sub-pixel SP. In addition to the light-emitting layer, the intermediate layer may include various types of common layers and functional layers to effectively supply holes and electrons to the light-emitting layer. The cathode is connected to a (first) power supply voltage line supplied with a low potential voltage EVSS or a ground voltage. In the second transistor T2 (which supplies drive current), the side of the second transistor T2 not connected to the light-emitting element ED may be connected to the second power supply voltage line and may be supplied with a high potential voltage EVDD. Furthermore, the first power supply voltage line and the second power supply voltage line are respectively disposed in each sub-pixel SP, and at least in the non-active region NA, there may be a connection between the pad portion PAD and the active region AA. As an example, Figure 1A power supply voltage line 142 is shown that supplies a low potential voltage EVSS to the cathode, and, for example, the power supply voltage line 142 may have a closed-loop shape surrounding the entire active region AA. The cathode of the light-emitting element ED is configured to have a large area over the entire active region AA, and a common voltage is applied to the cathode. Therefore, in order to maintain a uniform potential over the entire active region AA, it is desirable that the cathode be connected to the power supply voltage line 142 on each side of the non-active region NA, without bias towards a portion of the non-active region NA surrounding the active region AA, so as to maintain a uniform low potential voltage over the entire active region AA. That is, the power supply voltage line 142 that supplies a common voltage to the cathode with a large area may have a larger linewidth than other clock lines or signal lines. It is desirable that the power supply voltage line 142 be disposed on each side of the substrate 110 to apply a common voltage uniformly. For this purpose, as Figure 1 As shown, the power supply voltage line 142 can be provided without interruption to correspond to each side of the substrate 110. However, the display device according to the embodiments of this disclosure is not limited to the power supply voltage line 142 formed in a closed loop, and other configurations can be implemented.

[0056] Furthermore, the power supply voltage line 142 is a line that is constantly and continuously supplied with a low-potential common voltage, and may have a larger linewidth than a clock line or signal line that is supplied with a clock signal or a specific voltage at a specific time. In a display device 1000 according to one embodiment of the present disclosure, the power supply voltage line 142 has a plurality of openings. For example, the power supply voltage line 142 may be implemented in a grid shape including a plurality of openings, making light transmission through the openings possible. Therefore, the display device 1000 according to one embodiment of the present disclosure can improve the transmittance in the area where the power supply voltage line occupies a larger width than other clock lines or signal lines in the non-active region NA, and increase the transmittance of the non-active region NA. The power supply voltage line 142 and / or other signal lines may be formed with openings, for example, in a grid shape corresponding to the border area of ​​the non-active region NA of the substrate 110 where no pad portion PAD is provided, to improve transmittance. In this case, the display device 100 can obtain a visual effect similar to a borderless display, and in particular, the transmittance of the transparent display device can be improved by preventing the edges of the transparent display device from appearing opaque. When the substrate 110 has a generally rectangular shape, the grid shape provided in the power supply voltage line 142 can be applied at least to the left and right sides of the substrate 110. The grid shape can also be applied only to certain sides of the substrate 110 on which the power supply voltage line 142 is disposed. In a display device according to another embodiment of the present disclosure, the grid shape of the power supply voltage line 142 can also be applied to the lower side of the substrate 110. In a display device according to yet another embodiment of the present disclosure, the grid shape of the power supply voltage line 142 can also be applied to the upper side of the substrate 110. In some cases, the upper side of the substrate 110 includes a pad portion PAD, and a portion of the power supply voltage line 142 connected to the pad portion PAD may not employ a grid shape to prevent an increase in resistance.

[0057] Furthermore, the structure of the open-ended lines in the display device 1000 according to one embodiment of this disclosure can be applied not only to power supply voltage lines (supplying the aforementioned low potential voltage EVSS), but also to second power supply voltage lines (supplying the high potential voltage EVDD), or to other signal lines. In some embodiments, the second power supply voltage line (supplying the high potential voltage EVDD), or other signal lines, may not surround the entire active region AA, but may be provided only on certain sides of the substrate 110.

[0058] Furthermore, the dam section DAM can be set in the non-active area NA of the display device 1000. The dam section DAM is configured to surround the power supply voltage line 142 and prevent the leakage of liquid components used to protect the encapsulation layer for the light-emitting elements, etc.

[0059] A compensation circuit CC may be additionally provided in the sub-pixel SP to compensate for the threshold voltage of the second transistor T2, etc. The compensation circuit CC may include one or more transistors. The compensation circuit CC may include one or more transistors and capacitors, and can be configured in various ways depending on the compensation method. The sub-pixel SP including the compensation circuit CC may include one of various circuit structures (e.g., 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C) with different numbers of transistors and / or capacitors.

[0060] In the transistors located within sub-pixels, the switching transistors may require high-speed driving for rapid switching operations. The driving transistors may require high current outputs for high brightness expression by supplying high current to the light-emitting elements (EDs).

[0061] Furthermore, the display device according to an embodiment of this disclosure has a light-emitting region and a transmissive region in an active region AA, and improves transmittance by providing an opening in the power supply voltage line in the non-active region NA. A specific configuration of the display device will be described.

[0062] Figure 3 yes Figure 1 A magnified view of region A. Figure 4 It is along Figure 3 The cross-sectional view taken from line I-I'. Figure 5 yes Figure 1 A magnified view of region B. Figure 6 It is along Figure 5 The cross-sectional view taken from line II-II'. Figure 7 It shows the corresponding Figure 4 A plan view of the light-shielding layer of the power supply voltage line.

[0063] A display device 1000 according to one embodiment of the present disclosure includes a substrate 110 and a power supply line 142. The substrate 110 includes an active region AA comprising a plurality of sub-pixels SP1, SP2, and SP3, and a non-active region NA surrounding the active region AA (e.g., ...). Figures 1 to 4 As shown), the power supply voltage line 142 is formed into a first grid shape disposed in the non-active region NA (e.g. Figures 5 to 6 (As shown).

[0064] The first grid shape of the power supply voltage line 142 is configured such that, as Figure 5 As shown, the lines in the X direction and the lines in the Y direction are connected to intersect each other, and the region between the lines in the X direction and the lines in the Y direction defines a plurality of openings DTA1 and DTA2.

[0065] A display device 1000 according to one embodiment of the present disclosure may include a plurality of light-emitting regions EA: EA1, EA2 and EA3 in an active region AA, and a plurality of transmissive regions TA, such as Figure 3 As shown.

[0066] The transmissive region TA is disposed between the light-emitting regions EA1, EA2, and EA3, and does not overlap with wiring such as gate lines GL and data lines DL, to ensure transparency. The transmissive region TA can be configured to be separate from the first electrode 151. The first electrode 151 of the light-emitting element may not overlap with the transmissive region.

[0067] The first electrode of the light-emitting element (ED) can be referred to as the anode, and the second electrode of the light-emitting element (ED) can be referred to as the cathode.

[0068] Compared to the transmissive region TA, the light-emitting regions EA: EA1, EA2, and EA3 can intersect at least one of, for example, a gate line GL disposed in the X direction and a data line DL disposed in the Y direction. The light-emitting regions EA: EA1, EA2, and EA3 are disposed in the area where the wiring is located, thereby increasing the aperture ratio of the light-emitting regions EA: EA1, EA2, and EA3 in the display device 1000 and reducing ineffective areas.

[0069] Furthermore, the embankment 160 is provided between adjacent light-emitting regions EA:EA1, EA2 and EA3, between transmission regions TA, and between light-emitting regions EA:EA1, EA2 and EA3 and transmission region TA, thereby enabling the division of light-emitting regions EA:EA1, EA2 and EA3 and transmission region TA.

[0070] Each sub-pixel SP: SP1, SP2 or SP3 may have one of the light-emitting areas EA: EA1, EA2 and EA3.

[0071] The luminescent regions EA1, EA2, and EA3 can emit, for example, red, green, and blue light. Although Figure 3 An example of rectangular shapes for the light-emitting regions EA1, EA2, and EA3 is shown, but embodiments of this disclosure are not limited thereto. The shapes of the light-emitting regions EA1, EA2, and EA3 can be polygonal, such as rectangular, hexagonal, octagonal, decagonal, or dodecagonal, and in some cases, at least one corner of the shape can be rounded. Furthermore, the dimensions of the light-emitting regions EA1, EA2, and EA3 can vary depending on the efficiency of the light-emitting elements ED disposed in the light-emitting regions EA1, EA2, and EA3. For example, if the efficiency of the light-emitting element ED displaying a specific color is low, the size of that light-emitting region can be larger than the sizes of other light-emitting regions to compensate for the low efficiency.

[0072] Reference Figure 4The structure of the active region AA, including the configuration of the emitting region EA and the transmitting region TA, will be described.

[0073] First, the detailed configuration of the luminous area EA will be described.

[0074] Each light-emitting region EA includes a transistor TR and a light-emitting element ED on the substrate 110, and emits light through the light-emitting element ED when an electrical signal is supplied through the transistor TR.

[0075] A transistor (thin-film transistor, TFT) TR may include, for example, a light-shielding pattern 121, an active layer 122, a gate electrode 123, and a first source-drain electrode 124 and a second source-drain electrode 125.

[0076] The substrate 110 is used to support and protect the components disposed thereon. The substrate 110 may be transparent and may also be flexible. The substrate 110 may be formed of, for example, glass or plastic.

[0077] In one embodiment of this disclosure, substrate 110 may include a plurality of layers and may be configured, for example, to have interlayer inorganic films disposed between different flexible substrates.

[0078] In one embodiment of this disclosure, substrate 110 includes light-emitting regions EA and transmissive regions TA spaced apart from each other. The transmissive regions TA can be configured to not overlap components containing light-blocking metal materials, such as wiring including gate lines GL and data lines DL, and transistors TR, to increase the pure transmittance of light passing through substrate 110. Therefore, an object or image located below substrate 110 can be observed from the outside of the uppermost component of substrate 110. Compared to the transmissive regions TA, the light-emitting regions EA can include light-emitting elements ED and can overlap wiring including gate lines GL and data lines DL, and transistors TR, which are components below the light-emitting elements ED. Here, the light-emitting elements ED are formed by sequentially stacking a first electrode 151 disposed for each sub-pixel, an intermediate layer 152 on the first electrode 151, and a second electrode 153. Light-emitting regions EA1, EA2, and EA3 emit light generated from inside the light-emitting elements ED to above the second electrode 153, and an image depending on the operation of the light-emitting elements ED can be observed from the outside of the uppermost component of substrate 110.

[0079] The transistors (TFTs) TR disposed on the substrate 110 can be disposed on a first insulating film 111 on the substrate 110. The first insulating film 111 can be one or more insulating films. The first insulating film 111 can be configured to prevent impurities from entering the array configuration on the substrate 110 from the substrate 110 and to protect the array configuration on the substrate 110.

[0080] The transistor TR may include a light-shielding pattern 121 to prevent light transmitted from below the substrate 110 from entering the active layer 122. The light-shielding pattern 121 can prevent the generation of abnormalities, such as photocurrent, by blocking light from being transmitted from below the substrate 110 to the transistor TR.

[0081] A second insulating film 112 can be provided, which covers the first insulating film 111 with the light-shielding pattern 121 and achieves surface flattening.

[0082] The first insulating film 111 and the second insulating film 112 can protect the moisture-permeable structures on the substrate 110 from moisture penetration into the substrate 110 and make the surface of the substrate 110 planarized.

[0083] The active layer 122 may be disposed on the second insulating film 112. The active layer 122 may contain a semiconductor material. The semiconductor material may include a silicon-based semiconductor material or an oxide-based semiconductor material.

[0084] The third insulating film 113 is disposed on the second insulating film 112 on which the active layer 122 is disposed. The third insulating film 113 can be used as a gate insulating film between the active layer 122 and the gate electrode 123.

[0085] The fourth insulating film 114 and the fifth insulating film 115 may be disposed on the third insulating film 113 to cover the gate electrode 123. In some cases, the fourth insulating film 114 and the fifth insulating film 115 may be a single insulating film. The fourth insulating film 114 and the fifth insulating film 115 may perform interlayer insulation between the gate electrode 123 and the first source-drain electrode 124 and the second source-drain electrode 125.

[0086] The fifth insulating film 115, the fourth insulating film 114 and the third insulating film 113 may have a first contact hole CH1.

[0087] Furthermore, the first source-drain electrode 124 and the second source-drain electrode 125, formed of the first source-drain metal, can be connected to both sides of the upper surface of the active layer 122 through the first contact hole CH1. One of the first source-drain electrode 124 and the second source-drain electrode 125 can be a source electrode, and the other can be a drain electrode.

[0088] The light-shielding pattern 121 can be connected to one of the first source-drain electrode 124 and the second source-drain electrode 125 for potential stabilization. Alternatively, the light-shielding pattern 121 can be connected to the gate electrode 123 above the active layer 122 to serve as the bottom gate of the transistor TR.

[0089] Furthermore, each of the light-shielding pattern 121, the gate electrode 123, the first source-drain electrode 124, and the second source-drain electrode 125 may contain a metal selected from aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W).

[0090] Apart from Figure 4 In addition to the transistors shown, the sub-pixel may also include additional transistors with different functions. The storage capacitor storing the storage voltage of the sub-pixel can be formed together with the transistors included in the sub-pixel using the same process.

[0091] Each of the first to fifth insulating films 111, 112, 113, 114 and 115 may be an inorganic insulating film. The first to fifth insulating films 111, 112, 113, 114 and 115 may include, for example, silicon oxide (SiOx) films, silicon nitride (SiNx) films, silicon oxide nitride films, or multilayer films thereof.

[0092] An organic film PLN can be disposed on a transistor TR. The organic film PLN includes a first organic film 131 and a second organic film 132 that protect the transistor (TFT) TR.

[0093] The first organic film 131 can be disposed on the transistor TR or the fifth insulating film 115 to protect the transistor TR and mitigate the step caused by the transistor TR.

[0094] Furthermore, the connection electrode 141 connected to the first source-drain electrode 124 can be further disposed on the first organic membrane 131.

[0095] The connecting electrode 141 may have a second contact hole CH2 in the first organic film 131 to expose a portion of the upper surface of the first source-drain electrode 124, and may be connected to the first source-drain electrode 124 through the second contact hole CH2.

[0096] The second organic film 132 can be disposed on the first organic film 131. The second organic film 132 can be provided with a third contact hole CH3 that exposes a portion of the upper surface of the connecting electrode 141. The first electrode 151 of the light-emitting element ED can be connected to the connecting electrode 141 through the third contact hole CH3.

[0097] Furthermore, the first source-drain electrode 124 and the second source-drain electrode 125 of the aforementioned transistor (TFT) TR, as well as the connection electrode 141, can be located in the same layer as other signal lines, clock lines, and power supply voltage lines disposed in the active region AA and the non-active region NA.

[0098] The first organic film 131 and the second organic film 132 may cover the transistor TR and be disposed on the fifth insulating film 115 to provide a flat surface.

[0099] Each of the first organic membrane 131 and the second organic membrane 132 may contain an organic material. The organic material may include at least one of acrylic resins, phenolic resins, polyimide resins, unsaturated polyester resins, polyamide resins, benzocyclobutene, polystyrene resins, or polyphenylene sulfide resins.

[0100] In addition to the first to fifth insulating films 111, 112, 113, 114 and 115 mentioned above, organic or inorganic films with various functions can be further disposed between the substrate 110 and the first organic film 131.

[0101] The light-emitting element ED is disposed on the second organic film 132. The light-emitting element ED can be electrically connected to the transistor TR through the organic film PLN. The light-emitting element ED includes a first electrode 151, an intermediate layer 152, and a second electrode 153.

[0102] The first electrode 151 can be used as an anode. The first electrode 151 can be connected to the connecting electrode 141 through the third contact hole CH3 in the second organic film 132, and the connecting electrode 141 can be connected to the first source-drain electrode 124 through the second contact hole CH2, thereby connecting to the transistor TR. In some cases, the connecting electrode 141 and the second organic film 132 can be omitted, and the first source-drain electrode 124 and the first electrode 151 of the light-emitting element ED can be directly connected through the contact hole provided in the first organic film 131.

[0103] The first electrode 151 may comprise a metallic material with high reflectivity. For example, the first electrode 151 may be formed as a multilayer structure, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and ITO (ITO / Al / ITO), an APC (Ag / Pd / Cu) alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO), or a stacked structure of silver (Ag) and molybdenum-titanium alloy (Ag / MoTi), or may comprise a single-layer structure formed of an alloy material selected from one or more of silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), and barium (Ba). The first electrode 151 may be referred to as a reflective electrode or an anode.

[0104] An intermediate layer 152 is disposed on the first electrode 151. The intermediate layer 152 may include a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer. In some cases, the intermediate layer 152 may include a plurality of stacked bodies and a charge generation layer between the stacked bodies. If the intermediate layer 152 includes a plurality of stacked bodies, each stacked body may include at least one light-emitting layer, a hole transport common layer below the light-emitting layer, and an electron transport common layer above the light-emitting layer. Figure 4 An example is shown in which the intermediate layer 152 is disposed only in the light-emitting region EA. However, the display device 1000 according to one embodiment of the present disclosure is not limited thereto. The light-emitting layer in the intermediate layer 152 can be patterned to correspond to the light-emitting region EA. The hole injection layer, hole transport layer, electron transport layer and electron injection layer in the intermediate layer other than the light-emitting layer can be disposed as a common layer above a plurality of sub-pixels SP. In some cases, at least one of the common layers can be formed to extend to the transmissive region TA.

[0105] The edges of the first electrode 151 may overlap with the embankment 160. The area of ​​the first electrode 151 exposed from the embankment 160 can be defined as the light-emitting region EA. The embankment 160 can be located not only around the light-emitting region EA, but also around the transmission region TA. That is, the embankment 160 can be provided in a plurality of different light-emitting regions EA: the region between EA1, EA2, and EA3, the region between adjacent transmission regions TA, and the region between the light-emitting region EA and the transmission region TA.

[0106] The dam 160 may include a transparent insulating dam and / or an opaque insulating dam. The opaque insulating dam may contain a black material. If the dam 160 includes an opaque insulating dam, viewing angle characteristics can be improved by preventing oblique light passing through the side portions of the luminescent region EA from becoming visible, and the transparency of the transmissive region TA can be prevented from being reduced by light emitted from the adjacent luminescent region EA.

[0107] The area where dam 160 is located can be the non-luminous area NEA.

[0108] When a voltage is applied to the first electrode 151 and the second electrode 153, holes and electrons move to the organic light-emitting layer through the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer, respectively. The holes and electrons combine with each other to form excitons in the organic light-emitting layer, and the excitons fall from the excited state to the ground state, thereby causing light emission.

[0109] The intermediate layer 152 can be disposed across the entire active region AA. In some cases, one layer of the intermediate layer 152 may be selectively disposed in the light-emitting regions EA1, EA2, and EA3. In the light-emitting element ED, the intermediate layer 152 may have a series configuration in which a plurality of stacked bodies are disposed, and charge generation layers are disposed between the plurality of stacked bodies. Each of the plurality of stacked bodies includes a light-emitting layer, a hole transport common layer related to hole transport below the light-emitting layer, and an electron transport common layer related to electron transport on the light-emitting layer. In the series configuration, the individual layers of the intermediate layer 152 including the charge generation layers may be common layers disposed above the entire surface of the active region AA.

[0110] The intermediate layer 152 may include at least one of the following light-emitting layers: a red light-emitting layer that emits red light, a green light-emitting layer that emits green light, or a blue light-emitting layer that emits blue light. For example, in... Figure 4 In the intermediate layer 152, for each sub-pixel SP, a red light-emitting layer, a green light-emitting layer, or a blue light-emitting layer can be disposed on the first electrode 151. The red light-emitting layer can be patterned to be disposed in the red sub-pixel, the green light-emitting layer can be patterned to be disposed in the green sub-pixel, and the blue light-emitting layer can be patterned to be disposed in the blue sub-pixel, but this disclosure is not limited thereto, and at least two or more of the organic light-emitting layers of the red, green, and blue light-emitting layers can be stacked and disposed in one sub-pixel SP.

[0111] The intermediate layer 152 can be a white light-emitting layer that emits white light. In this case, the organic light-emitting layer of the intermediate layer 152 can be a common layer disposed above the sub-pixel SP, rather than a patterned layer.

[0112] The second electrode 153 can be used as a cathode in a light-emitting element (ED). The second electrode 153 can be a common layer that is commonly disposed above the sub-pixel SP and applies the same voltage to the sub-pixel SP. For this purpose, the second electrode 153 can be configured as a portion extending from the active region AA to the non-active region NA.

[0113] The second electrode 153 can be a transmission electrode. The second electrode 153 may include a transparent conductive material (TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO), which are transmissive to light, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 153 contains a semi-transmissive conductive material, the luminous efficiency can be improved through the microcavity. When the second electrode 153 contains a semi-transmissive conductive material, the thickness of the second electrode 153 can be thin enough to transmit light. For example, the thickness of the second electrode 153 can be 200 Å or less.

[0114] The first electrode 151 may include a reflective electrode to prevent light generated from the intermediate layer 152 from being transmitted to a light-shielding component below the first electrode 151. Light generated from the intermediate layer 152 can resonate between the second electrode 153 and the first electrode 151, and is ultimately emitted upwards through the second electrode 153. Because the first electrode 151 includes a reflective electrode, even if the first electrode 151 overlaps with wiring and transistors (TFTs), light emitted from the light-emitting elements ED in the light-emitting regions EA: EA1, EA2, and EA3 can be seen from above without affecting the arrangement of the wiring and transistors (TFTs).

[0115] Compared to the light-emitting region EA, the transmission region TA does not have a first electrode 151. The intermediate layer 152 and the second electrode 153 can be independently disposed in the transmission region TA. At least one of a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer in the intermediate layer 152 can extend laterally from the light-emitting regions EA1, EA2, or EA3, and can be disposed in the transmission region TA. Figure 4 As shown, the second electrode 153 can be disposed in the transmission region TA. In some cases, the second electrode 153 can be omitted from the transmission region TA to increase the transmittance of the transmission region TA.

[0116] When the intermediate layer 152 and the second electrode 153 are disposed in the transmission region TA, the use of a fine metal mask (FMM) that requires fine openings can be omitted when forming each layer, and increased yield and simplified process are expected.

[0117] An encapsulation layer 180 is disposed on the light-emitting element ED to protect and seal the light-emitting element ED.

[0118] The encapsulation layer 180 can be a single membrane or comprise a plurality of membranes. When the encapsulation layer 180 comprises a plurality of membranes, for example, inorganic encapsulation layers 181 and 183 and organic encapsulation layer 182 can be arranged in alternating pairs or more. The uppermost and lowermost layers of the inorganic encapsulation layer 180 can be advantageous in preventing external air, moisture, etc., from penetrating from the outside.

[0119] The encapsulation layer 180 flattens the surface roughness caused by the light-emitting element ED.

[0120] A light-shielding layer 210 corresponding to the non-emitting region NEA and a color filter 220 corresponding to at least the emitting region EA can be disposed on the encapsulation layer 180. In some cases, the color filter 220 can extend to the non-emitting region NEA to overlap the light-shielding layer 210. The light-shielding layer 210 and the color filter 220 can have the function of absorbing external light and preventing external light reflection. The protective film 230 can also be disposed to cover the light-shielding layer 210 and the color filter 220. The protective film 230 is transparent and has an upper surface planarization function to ensure that the display device 1000 has a flat surface without surface roughness when viewed from the outside. The protective film 230 can be a transparent organic film. The protective film 230 can also be used as a cover film.

[0121] The transmission region TA will be described.

[0122] The transmissive region TA may include the first to fifth insulating films 111, 112, 113, 114 and 115, the second electrode 153, the encapsulation layer 180 and the protective film 230 on the substrate 110 included in the light-emitting region EA.

[0123] like Figure 3 and Figure 4 As shown, the transmission region TA does not include light-shielding metals such as gate lines GL and data lines DL, in order to maximize the transmittance of light passing through from the bottom to the top of the substrate 110. In this case, the organic film PLN can be omitted from the transmission region TA to increase the lower transmittance.

[0124] In a display device 1000 according to one embodiment of the present disclosure, at least one of the first to fifth insulating films 111, 112, 113, 114 and 115 or the first organic film 131 and the second organic film 132 is removed from the transmission region TA to shorten the path of light in the region of transmission TA, thereby increasing the transparency of the transmission region TA. Figure 4 An example is shown in which the first organic film 131 and the second organic film 132 are omitted from the transmission region TA, but the embodiments of this disclosure are not limited thereto. One of the first to fifth insulating films 111, 112, 113, 114, and 115 may be omitted from the transmission region TA instead of the first organic film 131 and the second organic film 132, or at least one of the first to fifth insulating films 111, 112, 113, 114, or 115 may be omitted from the transmission region TA along with the first organic film 131 and the second organic film 132.

[0125] Furthermore, in the configuration of the light-emitting element ED, the intermediate layer 152 and the second electrode 153 can be independently disposed in the transmission region TA or omitted in the transmission region TA. Figure 4The illustration shows a configuration where the second electrode 153 is also located within the transmission region TA, but the embodiments disclosed herein are not limited thereto. When the second electrode 153 is disposed within the transmission region TA, the second electrode 153 can be formed to be integrated over the entire active region AA, and the resistance of the second electrode 153 can decrease as the area of ​​the second electrode 153 increases. Therefore, the potential of the second electrode 153 can be constant in the corresponding region, thereby improving image quality.

[0126] A display device 1000 according to one embodiment of the present disclosure is characterized in that the transmittance is increased even in the non-active region NA.

[0127] For this purpose, a display device 1000 according to one embodiment of the present disclosure may include: a power voltage line 142 formed in a first grid shape in an active region NA; an encapsulation layer 180 in the entire active region AA and the active region NA in which the power voltage line 142 is disposed; and a light-shielding layer 210 disposed on the encapsulation layer 180 to overlap the power voltage line 142.

[0128] The first grid shape of the power supply voltage line 142 represents a structure in which a plurality of horizontal lines and a plurality of vertical lines with thin linewidths repeat. Openings DTA1 and DTA2 are positioned between the horizontal and vertical lines with thin linewidths of the power supply voltage line 142 in the power supply voltage line region VSS in the non-active region NA, and can improve the transmittance in openings DTA1 and DTA2.

[0129] The power supply voltage line 142 can be formed in the same layer as the connection electrode 141 disposed in the active region AA. The power supply voltage line 142 can be disposed on the second organic film 132. In some cases, the power supply voltage line 142 can be located in the same layer as one of the electrodes forming the transistor TR, for example, in the same layer as the first source-drain electrode 124 and the second source-drain electrode 125 of the transistor TR disposed in the active region AA. The power supply voltage line 142 can be disposed on the first organic film 131.

[0130] Furthermore, the power supply voltage line 142 may contain a metal selected from aluminum (Al), titanium (Ti), copper (Cu), chromium (Cr), molybdenum (Mo), and tungsten (W). In this case, when the power supply voltage line 142 patterned in the first grid shape in the non-active region NA is only covered by a transparent insulating film, glinting caused by the patterned metal can be observed from above.

[0131] To prevent this, in a display device 1000 according to one embodiment of the present disclosure, light-shielding layers 210B and 210C are disposed on the encapsulation layer 180 to overlap the power supply voltage lines 142 having a first grid shape, such as... Figure 5 and Figure 6 As shown. The light-shielding layers 210B and 210C can be formed of black organic materials and contain light-shielding components such as black ink, carbon, etc., to prevent reflection caused by the underlying metal. Furthermore, as... Figure 7 As shown, the light-shielding layers 210B and 210C may have a linewidth greater than that of the first grid shape of at least the power supply voltage line 142, in order to prevent the first grid shape of the power supply voltage line 142 from being visible when viewed from different angles in the non-active region NA, or to prevent flickering due to side reflections.

[0132] The power supply voltage line 142 has a plurality of first openings DTA1 and DTA2, and the light-shielding layers 210B and 210C may have a second opening DTA3 corresponding to the plurality of first openings DTA1 and DTA2 that is smaller than each of the plurality of first openings DTA1 and DTA2.

[0133] In addition, Figure 5 and Figure 6 In the diagram, the non-active region NA represents the left and right sides of the substrate 110, and the gate driver GIP, line block LB, power supply voltage line region VSS, and dam DAM can be sequentially arranged in the plane from the active region AA to the terminal line SUBE of the substrate 110.

[0134] The gate driver GIP includes a plurality of transistors, storage capacitors, etc., and may include the same stack as the transistor (TFT) TR disposed in the active region AA.

[0135] The line group LB includes multiple clock lines and multiple signal lines 242, 243, 244 and 245, and can be connected to the gate driver GIP and the pad portion PAD.

[0136] The gate driver GIP, line group LB, and power supply voltage line 142 can be provided using the same process as the transistor TR disposed in the active region AA. An organic film PLN covers and protects stage 241 of the transistor (TFT) and gate driver GIP. The power supply voltage line 142 can be located above the organic film PLN in the non-active region NA.

[0137] The transistors disposed in the active region AA can have different stacking structures according to their functions, and can include different source-drain metal layers, such as a first source-drain metal layer on the first organic film 131 and a second source-drain metal layer on the second organic film 132. Therefore, as Figure 6 As shown, the power supply voltage line 142 can be formed by a second source-drain metal layer. The second source-drain metal layer can be located in the same layer as the connection electrode 141 in the active region AA.

[0138] Furthermore, the second electrode (cathode) 153 disposed in the active region AA can extend to the non-active region NA and be conductively connected to the power supply voltage line 142. In this case, in addition to supplying the power supply voltage through the pad portion PAD, the second electrode 153 also has a conductive connection with the power supply voltage line 142, which occupies a large area in the non-active region NA located on the left and right sides of the substrate 110, thereby preventing brightness non-uniformity between regions and reducing the resistance of the second electrode 153.

[0139] Furthermore, at each connection point where the power supply voltage line 142 and the second electrode 153 are connected, anode virtual patterns 251A and 251B can be further disposed between the power supply voltage line 142 and the second electrode 153, thereby improving the electrical characteristics of the connection point.

[0140] Here, the anode virtual patterns 251A and 251B can be located in the same layer as the first electrode 151.

[0141] Anode virtual patterns 251A and 251B can be arranged in a line or island shape in a plurality of spaced-apart regions to overlap the first grid-shaped power supply voltage line 142. Anode virtual patterns 251A and 251B are conductively connected to the first electrode 151 disposed in each sub-pixel SP of the active region AA. Anode virtual patterns 251A and 251B serve to conductively connect the power supply voltage line 142 with a low potential voltage applied and the second electrode 153, and function independently of the first electrode 151.

[0142] The anode virtual patterns 251A and 251B may overlap the power supply voltage line 142, but may have a smaller area than the power supply voltage line 142. The anode virtual patterns 251A and 251B may be formed of the same material as the first electrode 151 and may include reflective electrodes. To prevent visibility caused by the anode virtual patterns 251A and 251B, the light-shielding layers 210B and 210C on the anode virtual patterns 251A and 251B may have a larger width than the anode virtual patterns 251A and 251B.

[0143] The light-shielding layers 210B and 210C can be arranged along the shape of the anode virtual patterns 251A and 251B. The light-shielding layers 210B and 210C can cover the anode virtual patterns 251A and 251B.

[0144] The first organic membrane 131 and the second organic membrane 132 disposed in the active region AA extend to overlap the power supply voltage line 142 in the non-active region NA, and the power supply voltage line 142 may be disposed on the second organic membrane 132.

[0145] Anode virtual patterns 251A and 251B are disposed in the contact hole penetrating the second organic film 132, and the second electrode 153 can be connected to the power supply voltage line 142 by means of the anode virtual patterns 251A and 251B between the second electrode 153 and the power supply voltage line 142 in the contact hole.

[0146] Furthermore, when the planar gate driver GIP, line group LB, power supply voltage line 142, and dam DAM are sequentially arranged in a plane from the edge of the active region AA of the substrate 110 to the end line (edge) SUBE of the substrate 110, the power supply voltage line 142 may include a source-drain electrode layer located on a different layer than the clock line and signal lines 242, 243, 244, and 245 and the metal pattern of the gate driver GIP, line group LB, and metal pattern. Here, the source-drain electrode layer formed as a different layer may be located on the same layer as the connection electrode 141 connecting the transistor TR and the light-emitting element ED in the sub-pixel SP.

[0147] Schematic illustration Figure 5 and Figure 6 The gate driver GIP has a stage 241, and stage 241 may include a plurality of metal layers and an insulating layer between the plurality of metal layers.

[0148] Line group LB may include multiple clock lines and signal lines 242, 243, 244 and 245.

[0149] The light-shielding layer 210 corresponding to stage 241 of the gate driver GIP can have a relatively larger linewidth than light-shielding layers 210A, 210B, and 210C. Light-shielding layers 210A, 210B, and 210C are formed with a second grid shape corresponding to the clock lines and signal lines 242, 243, 244, and 245 of line group LB, and a first grid shape corresponding to the power supply voltage line region VSS. The light-shielding layer 210 corresponding to stage 241 of the gate driver GIP can overlap the gate driver GIP. Light-shielding layer 210A can overlap line groups including clock lines 242, 243, 244, and 245. Light-shielding layers 210B and 210C can overlap power supply voltage line 142. The light-shielding layer 210 disposed relative to the gate driver GIP can overlap the corresponding components with maximum width in the non-active region NA.

[0150] The power supply voltage line region VSS may include a first region VSSA with overlapping dams 160 and a second region VSSB without overlapping dams 160. Dams 160 are disposed in the first region VSSA such that the anode virtual pattern 251A can be disconnected from the second electrode 153. On the other hand, the dam end line BKE is located at the boundary between the first region VSSA and the second region VSSB such that the anode virtual pattern 251B can be directly connected to the second electrode 153 in the second region VSSB.

[0151] The dam 160 is located around the light-emitting region EA and the transmission region TA of the active region AA, and extends into the non-active region NA to be disposed in the first region VSSA of the gate driver GIP, the line group LB and the power supply voltage line region VSS, and can also serve to protect the circuit configuration and lines in the non-active region NA.

[0152] The first organic membrane 131 and the second organic membrane 132 can be located inside the dam section DAM disposed in the non-active region NA. Therefore, the edge of the organic membrane PLE can be located inside the plurality of dam patterns DM1, DM2 and DM3.

[0153] The dam section DAM may include a plurality of dam patterns DM1, DM2, and DM3. In the encapsulation layer 180, the organic encapsulation layer 182 is formed by applying a liquid material, and the dam patterns DM1, DM2, and DM3 of the dam section DAM can prevent the liquid material from diffusing to the outside during the formation process. The dam patterns DM1, DM2, and DM3 may include at least one layer, such as a first organic film 131, a second organic film 132, or a dam 160. The dam patterns DM1, DM2, and DM3 may have a shape that surrounds the active region AA outside the power supply voltage line 142 in the non-active region NA of the substrate 110.

[0154] Therefore, a plurality of dam patterns DM1, DM2 and DM3 surrounding the active region AA of the substrate 110 are disposed outside the first grid-shaped power supply voltage line 142, and the edge of the organic encapsulation layer 182 in the encapsulation layer 180 can be located between the plurality of dam patterns DM1, DM2 and DM3.

[0155] The linewidths of the light-shielding layers 210B and 210C of the overlapping power voltage line 142 are greater than or equal to the linewidth of the power voltage line 142, and the light-shielding layers 210B and 210C may include openings corresponding to the power voltage lines in the non-active region NA.

[0156] In the following, an embodiment of the anode virtual pattern of the display device of the present disclosure will be described.

[0157] Figures 8 to 10 To show Figure 7 A plan view of the implementation scheme for the virtual anode pattern.

[0158] like Figure 8 As shown, the anode virtual patterns 251A and 251B can be uniformly set as lines in the Y-axis direction in the first region VSSA and the second region VSSB of the power supply voltage line region VSS.

[0159] Here, the corresponding anode virtual patterns 251A and 251B can be separated from each other. The anode virtual patterns 251A and 251B are separated from each other, but connected to the first grid-shaped power supply voltage line 142 disposed below them and the second electrode 153 disposed on them, which extends from the active region AA to the non-active region NA power supply voltage line region VSS.

[0160] In the region occupied by the second electrode 153 in the non-active region NA, the conductivity of the second electrode 153 is improved by the first grid-shaped power supply voltage line 142 and the anode virtual patterns 251A and 251B connected thereto, and the resistance of the second electrode 153 disposed in the active region AA is also reduced.

[0161] Figure 8 The linewidths of the anode virtual patterns 251A and 251B can be equal to the linewidth of the first grid-shaped power supply voltage line 142 located below them in the Y-axis direction. This is for a stable connection between the power supply voltage line 142 and the anode virtual patterns 251A and 251B. Furthermore, the linewidths of the anode virtual patterns 251A and 251B can be smaller than the linewidths of the corresponding light-shielding layers 210B and 210C disposed above them in the Y-axis direction. This is to allow the light-shielding layers 210B and 210C to prevent the anode virtual patterns 251A and 251B from being visible from the outside.

[0162] like Figure 9 As shown, the anode virtual pattern 351A can be uniformly set as a line in the X-axis direction in the first region VSSA and the second region VSSB of the power supply voltage line region VSS.

[0163] Here, the corresponding anode virtual patterns 351A can be formed to be separate from each other. The anode virtual patterns 351A are spaced apart from each other, but connected to the first grid-shaped power supply voltage line 142 disposed below it and the second electrode 153 disposed on it, which extends from the active region AA to the non-active region NA power supply voltage line region VSS.

[0164] In the region occupied by the second electrode 153 in the non-active region NA, the conductivity of the second electrode 153 is improved by the first grid-shaped power supply voltage line 142 and the anode virtual pattern 351A connected thereto, and the resistance of the second electrode 153 disposed in the active region AA is also reduced.

[0165] Figure 9The linewidth of the anode virtual pattern 351A can be equal to the linewidth of the first grid-shaped power supply voltage line 142 located below it in the X-axis direction. This is for a stable connection between the power supply voltage line 142 and the anode virtual pattern 351A. Furthermore, the linewidth of the anode virtual pattern 351A can be smaller than the linewidth of the corresponding light-shielding layers 210B and 210C disposed above it in the X-axis direction. This is to allow the light-shielding layers 210B and 210C to prevent the anode virtual pattern 351A from being visible from the outside.

[0166] like Figure 10 As shown, the anode virtual pattern 451 can be uniformly arranged in the first region VSSA and the second region VSSB of the power supply voltage line region VSS in the shape of a third grid pattern.

[0167] Here, the corresponding anode virtual patterns 451 are connected to each other.

[0168] In the region occupied by the second electrode 153 in the non-active region NA, the conductivity of the second electrode 153 is improved by the first grid-shaped power supply voltage line 142 and the anode virtual pattern 451 connected thereto, and the resistance of the second electrode 153 disposed in the active region AA is also reduced.

[0169] Figure 10 At least one of the linewidths of the anode virtual pattern 451 in the X-axis and Y-axis directions can be equal to the linewidth of the first grid-shaped power supply voltage line 142 located below it in the X-axis direction or in the Y-axis direction. This is for a stable connection between the power supply voltage line 142 and the anode virtual pattern 451. Furthermore, the linewidth of the anode virtual pattern 451 in each of the X-axis and Y-axis directions can be smaller than the linewidth of the corresponding light-shielding layers 210B and 210C located above it in either the X-axis or Y-axis direction. This is to allow the light-shielding layers 210B and 210C to prevent the anode virtual pattern 451 from being visible from the outside.

[0170] The examples in which the light-shielding layer 210 and the color filter 220 are formed directly on the encapsulation layer 180 of the display device 1000 have been described above. However, the display device according to the embodiments of the present disclosure is not limited thereto. The display device 1000 according to one embodiment of the present disclosure has a power supply voltage line 142 arranged in a grid shape with openings to increase the transmittance of the non-active region NA, and a light-shielding layer 210 formed in a grid shape on the encapsulation layer 180 covering the power supply voltage line 142, thereby preventing the power supply voltage line 142 from becoming visible due to patterning.

[0171] The display device 1000 of one embodiment of this disclosure can be realized by applying a grid-shaped pattern to the structure of the power supply voltage line 142, the anode virtual patterns 251A and 251B, 351A or 451, and the light-shielding layers 210B and 210C without adding separate materials or processes. This reduces the production energy required to increase the manufacturing process to produce the display device 1000, reduces greenhouse gas emissions, and thus achieves environmental, social, and governance (ESG) goals.

[0172] In addition, the active region AA can be changed to another form, as long as the non-active region NA has the optical effects caused by the above-mentioned structural features.

[0173] In the following, a display device 1000 according to another embodiment of the present disclosure will be described.

[0174] Figure 11 A cross-sectional view of a display device according to another embodiment of the present disclosure is shown.

[0175] like Figure 11 As shown, a touch sensor may be included in the active region AA between the encapsulation layer 180, the light-shielding layer 210, and the color filter 220.

[0176] Therefore, the touch sensor disposed on the encapsulation layer 180 to detect external touch is disposed on the flat encapsulation layer 180, and may include, for example, a touch buffer film 305, a sensor electrode TE, a touch insulating film 320, and a touch protective film 340.

[0177] Each of the touch buffer film 305, the touch insulating film 320, and the touch protective film 340 may be formed as at least one of an inorganic insulating film or an organic insulating film.

[0178] Furthermore, the sensor electrode TE may include a bridging electrode 310 located on the touch buffer film 305, and a touch electrode 330 connected to the bridging electrode 310 through a touch contact hole formed through the touch insulating film 320 to expose the upper surface of the bridging electrode 310. The touch electrode 330 and the bridging electrode 310 may include metal and may be covered by a light-shielding layer 210 to prevent reflective visibility caused by the metal.

[0179] Furthermore, in the structure including the touch sensor, the non-active regions NA located on the left and right sides of the substrate 110 can have already been... Figure 5 and Figure 10The power supply voltage line 142, anode virtual patterns 251A and 251B, 351A or 451, and light-shielding layers 210B and 210C described herein. Here, at least one of the touch buffer film 305, touch insulating film 320, or touch protective film 340 of the touch sensor may also be disposed between the encapsulation layer 180 and the light-shielding layers 210B and 210C in the non-active region NA.

[0180] The aforementioned display device 1000, according to another embodiment of this disclosure, can be achieved by applying a grid-shaped patterning to the structure of the power supply voltage line 142, the anode virtual patterns 251A and 251B, 351A or 451, and the light-shielding layers 210B and 210C without adding separate materials or processes. This reduces the production energy required to produce the display device 1000 through any additional manufacturing processes, thereby reducing greenhouse gas emissions and achieving environmental, social, and governance (ESG) goals. Furthermore, even in the structure of the display device 1000 including a touch sensor, the transmittance of the non-active region NA can be improved.

[0181] A display device according to one embodiment of the present disclosure may include: a substrate, the substrate including a display area comprising a plurality of sub-pixels and a non-display area surrounding the display area; power voltage lines, the power voltage lines being in a first grid shape and disposed in the non-display area; an encapsulation layer, the encapsulation layer being located in the portion of the display area and the non-display area where the power voltage lines are disposed; and a light-shielding layer, the light-shielding layer overlapping the power voltage lines on the encapsulation layer.

[0182] In a display device according to one embodiment of the present disclosure, the light-shielding layer may be arranged in a second grid shape to overlap the entire power supply voltage line.

[0183] In a display device according to one embodiment of the present disclosure, the light-shielding layer may have a width greater than the width of the power supply voltage line at each region corresponding to the power supply voltage line.

[0184] In a display device according to one embodiment of the present disclosure, a power supply voltage line may have a plurality of first openings, and a light-shielding layer may have second openings corresponding to the plurality of first openings, the second openings being configured to be smaller than each of the plurality of first openings.

[0185] In a display device according to one embodiment of the present disclosure, the display area may further include a transmissive area. Each of the plurality of sub-pixels may include a transistor on a substrate and a light-emitting element connected to the transistor. The light-emitting element may include an anode, an intermediate layer, and a cathode. The cathode may extend into a non-display area to be conductively connected to a power supply voltage line. The anodes of the light-emitting elements do not overlap with the transmissive areas.

[0186] In a display device according to one embodiment of the present disclosure, a power supply voltage line can be connected to an anode virtual pattern on the same layer as the anode.

[0187] In a display device according to one embodiment of the present disclosure, the anode virtual pattern may overlap the power voltage lines of the first grid shape and be arranged in a plurality of spaced-apart regions in a line shape or an island shape.

[0188] In a display device according to one embodiment of the present disclosure, the anode virtual pattern may overlap the power supply voltage lines and has a smaller area than the power supply voltage lines.

[0189] In a display device according to one embodiment of the present disclosure, the light-shielding layer may be arranged along the shape of the anode virtual pattern.

[0190] In a display device according to one embodiment of the present disclosure, a first organic film and a second organic film may be sequentially disposed between a transistor and a light-emitting element. The first organic film and the second organic film may extend into a non-display area to overlap power supply voltage lines. The power supply voltage lines may be disposed on the first organic film.

[0191] In a display device according to one embodiment of the present disclosure, an anode virtual pattern may be disposed in at least one contact hole passing through the second organic film. The cathode may be connected to the power supply voltage line using the anode virtual pattern in the contact hole between the cathode and the power supply voltage line.

[0192] In a display device according to one embodiment of the present disclosure, the first organic film and the second organic film may be located inside a dam pattern disposed in a non-display area.

[0193] In a display device according to one embodiment of the present disclosure, the transistor may comprise an oxide semiconductor.

[0194] In a display device according to one embodiment of the present disclosure, the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. A light-shielding layer may be disposed on the second inorganic encapsulation layer.

[0195] In a display device according to one embodiment of the present disclosure, a plurality of dam patterns can be configured to surround the edge of a substrate outside power supply voltage lines in the shape of a first grid, and the edge of the organic encapsulation layer can be located between the plurality of dam patterns.

[0196] In a display device according to one embodiment of the present disclosure, the linewidth of the light-shielding layer configured to overlap power supply voltage lines may be greater than or equal to the linewidth of the power supply voltage lines. Furthermore, the light-shielding layer may include openings corresponding to openings in the power supply voltage lines in non-display areas.

[0197] In a display device according to one embodiment of the present disclosure, a gate driver, a clock line, a power supply voltage line, and a dam pattern may be sequentially arranged in a plane between the edge of the display area of ​​the substrate and the edge of the substrate. The power supply voltage line may include a source-drain electrode layer located on a different layer than the gate driver and the clock line, and the source-drain electrode layer may be located on the same layer as the connection electrode, which is configured to connect the transistor and the light-emitting element at each sub-pixel.

[0198] In a display device according to one embodiment of the present disclosure, the light-shielding layer may overlap the gate driver, clock line and power supply voltage line, and overlap the gate driver with the maximum width in the non-display area.

[0199] In a display device according to one embodiment of the present disclosure, each of the sub-pixels includes a transistor on a substrate, a light-emitting element connected to the transistor, and a dam at the edge of the anode of the overlapping light-emitting element.

[0200] The non-display area may include a virtual anode pattern set in the same layer as the anode and connected to the power supply voltage line.

[0201] The power supply voltage line may include a first region configured to overlap and a second region configured not to overlap.

[0202] The cathode of the light-emitting element can extend into the non-display area, which includes the first and second regions, thereby connecting to the anode virtual pattern in the second region.

[0203] In a display device according to one embodiment of the present disclosure, an organic protective film may also be disposed on the light-shielding layer.

[0204] As is apparent from the above description, the display device according to the embodiments of this disclosure has the following effects.

[0205] The display device of the present disclosure can apply a mesh structure with openings to the power supply voltage lines in an active region including power supply voltage lines and circuitry to achieve improved transmittance.

[0206] The display device of the present disclosure can increase the transmission area by means of a grid structure of power supply voltage lines in the non-active area, so as to have a transmittance similar to that of the active area and improve the sense of difference.

[0207] The display device of the present disclosure may include a light-shielding layer covering a metal pattern having a connection to a power supply voltage line in a non-active area to prevent reflective visibility or flickering at different viewing angles caused by the metal pattern disposed on the wiring.

[0208] The display device of the present disclosure can improve transmittance not only in the active region but also in the non-active region to improve the pure transmittance of objects or images on the surface opposite to the display surface of the display device throughout the entire region, rather than visibility such as diffraction or interference.

[0209] The display device of the present disclosure can prevent the resistance of the power supply voltage lines with a grid structure from increasing through the connection structure in the power supply voltage lines, anode pattern and cathode extension in the non-active area, and can reduce the resistance of the cathode, thereby homogenizing the voltage of the cathode throughout the active area and improving image quality.

[0210] The display device according to embodiments of this disclosure can pattern the power supply voltage lines, anode, cathode, and light-shielding layer disposed in the active region to use these components in the non-active region, thereby enabling an increase in the transmittance of the non-active region without adding separate materials or processes. Therefore, greenhouse gas emissions generated by adding layers or processes can be reduced, and process optimization can be achieved. Furthermore, the transmittance of the display device can be increased without adding processes, achieving sustainability and thus realizing environmental, social, and governance (ESG) effects.

[0211] The display device according to the embodiments of this disclosure can utilize the same process and minimize the occurrence of defects in the display device, thereby reducing the production energy required to produce the display device, reducing the use of hazardous production materials or controlled substances, and thus facilitating recycling.

[0212] From the above description, it will be apparent to those skilled in the art that various changes and modifications are possible without departing from the spirit of this disclosure. Therefore, the scope of this disclosure should not be limited to the detailed description above, but rather defined by the scope of the claims.

Claims

1. A display device, comprising: A substrate, the substrate including a display area comprising a plurality of sub-pixels and a non-display area surrounding the display area; Power supply voltage lines, which are in the shape of a first grid and are disposed in the non-display area; An encapsulation layer, the encapsulation layer being located in the portion of the entire display area and the non-display area where the power supply voltage lines are provided; and A light-shielding layer is provided on the encapsulation layer to overlap the power voltage lines.

2. The display device according to claim 1, wherein the light-shielding layer is arranged in a second grid shape to overlap the entire power supply voltage line.

3. The display device according to claim 2, wherein in each region corresponding to the power supply voltage line, the width of the light-shielding layer is greater than the width of the power supply voltage line.

4. The display device according to claim 1, wherein the power supply voltage line has a plurality of first openings, and the light-shielding layer has second openings corresponding to the plurality of first openings. Each of the plurality of second openings is configured to be smaller than the corresponding first opening among the plurality of first openings.

5. The display device according to claim 1, wherein: The display area also includes a transmissive area; Each of the plurality of sub-pixels includes a transistor on the substrate and a light-emitting element connected to the transistor; The light-emitting element includes an anode, an intermediate layer, and a cathode; The anode of the light-emitting element is not present in the transmission region; as well as The cathode extends into the non-display area and is conductively connected to the power supply voltage line.

6. The display device according to claim 5, wherein the power supply voltage line is connected to an anode virtual pattern on the same layer as the anode.

7. The display device of claim 6, wherein the anode virtual pattern overlaps the power supply voltage lines having a first grid shape, and The anode virtual pattern is arranged in a plurality of regions spaced apart from each other in a line or island shape.

8. The display device of claim 6, wherein the anode virtual pattern overlaps the power supply voltage line and has a smaller area than the power supply voltage line.

9. The display device according to claim 6, wherein the light-shielding layer is disposed along the shape of the anode virtual pattern.

10. The display device according to claim 6, wherein: A first organic film and a second organic film are sequentially disposed between the transistor and the light-emitting element; The first organic film and the second organic film extend into the non-display area to overlap the power supply voltage lines; as well as The power supply voltage line is disposed on the first organic membrane.

11. The display device according to claim 10, wherein: The anode virtual pattern is disposed in at least one contact hole passing through the second organic membrane; as well as The cathode is connected to the power voltage line via the anode virtual pattern in the contact hole, which is located between the cathode and the power voltage line.

12. The display device according to claim 10, wherein the first organic film and the second organic film are located inside a dam pattern disposed in the non-display area.

13. The display device of claim 5, wherein the transistor comprises an oxide semiconductor.

14. The display device according to claim 1, wherein: The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer; and The light-shielding layer is disposed on the second inorganic encapsulation layer.

15. The display device of claim 14, wherein a plurality of dam patterns configured to surround the edge of the substrate are provided outside the power supply voltage lines in the first grid shape, and the edge of the organic encapsulation layer is located between the plurality of dam patterns.

16. The display device according to claim 1, wherein: The linewidth of the light-shielding layer configured to overlap the power voltage line is greater than or equal to the linewidth of the power voltage line; and The light-shielding layer includes an opening corresponding to the opening of the power voltage line in the non-display area.

17. The display device according to claim 1, wherein: A gate driver, a clock line, a power supply voltage line, and a dam pattern are sequentially arranged in a plane between the edge of the display area of ​​the substrate and the edge of the substrate. The power supply voltage line includes a source-drain electrode layer located on a different layer from the gate driver and the clock line; as well as The source-drain electrode layer is located on the same layer as the connection electrode, which is configured to connect the transistor and light-emitting element at each of the plurality of sub-pixels.

18. The display device of claim 17, wherein the light-shielding layer overlaps the gate driver, the clock line and the power supply voltage line, and overlaps the gate driver with maximum width in the non-display area.

19. The display device according to claim 1, wherein: Each of the plurality of sub-pixels includes a transistor on the substrate, a light-emitting element connected to the transistor, and an overlapping embankment at the edge of the anode of the light-emitting element; The non-display area includes a virtual anode pattern disposed in the same layer as the anode and connected to the power supply voltage line; The power supply voltage line includes a first region configured to overlap the dike and a second region configured not to overlap the dike; as well as The cathode of the light-emitting element extends into the area of ​​the non-display region that includes the first region and the second region, thereby connecting to the anode virtual pattern in the second region.

20. The display device according to claim 19, wherein an organic protective film is further disposed on the light-shielding layer.

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