Process method for forming metal fuses and semiconductor structure
By utilizing the isolated pattern and micro-load effect of the top metal layer, a passivation layer residue is retained above the metal filament using a single etching process. This solves the cost and time problems caused by adding a photomask in the existing technology, and achieves cost reduction and cycle shortening.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-02-26
- Publication Date
- 2026-06-09
AI Technical Summary
In existing technologies, when fabricating metal filaments, an additional photomask is required to define the passivation layer residual film area, which leads to increased wafer fabrication costs and extended process cycles.
By utilizing the micro-load effect caused by the isolated pattern of the top metal layer, a passivation layer residual film of a predetermined thickness is retained above the metal filament through a single etching process, avoiding the need for additional photomasks, and etching control is achieved by combining the thickness difference of the photoresist layer.
Without increasing costs and time, precise preservation of the passivation layer residual film thickness was achieved, reducing wafer fabrication costs and shortening the manufacturing cycle.
Smart Images
Figure CN122180378A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a process for forming a metal filament and a semiconductor structure. Background Technology
[0002] In the manufacturing and packaging processes of semiconductor integrated circuits, metal fuses, as an important programmable element, are widely used in key process nodes such as redundancy repair of memory arrays, precision fine-tuning of analog circuits, and physical burning of chip digital identity information.
[0003] According to conventional device layout rules in existing technologies, metal fuses are typically placed on the layer below the top metal layer (i.e., the Top metal-1 layer). When performing dielectric etching processes on the Top metal-1 layer related to the metal fuse, to ensure sufficient stability of the metal fuse and prevent contamination from external harmful substances such as moisture in subsequent processes or the operating environment, while also providing necessary physical buffering during laser or electrical melting, a certain thickness of passivation film is often required above the metal fuse. To precisely control this film thickness and protect other areas that do not require etching, existing process routes must add a dedicated photomask to specifically define the area above the metal fuse where the passivation film is retained.
[0004] However, this traditional process faces significant obstacles in actual large-scale mass production: on the one hand, adding extra photomasks means that a series of complicated process steps such as photolithography, development, cleaning and measurement must be introduced, which greatly increases the direct production cost of wafer fabrication; on the other hand, the extra process steps significantly lengthen the overall process operation time, reduce wafer throughput efficiency and the overall capacity of the production line.
[0005] Therefore, there is an urgent need in this field for an improved process that can effectively prepare metal filaments and ensure residual film thickness without increasing production costs or lengthening the process cycle. Summary of the Invention
[0006] The technical problem to be solved by the present invention is that, in the prior art, when using the layer below the top metal to make metal wires, in order to retain a passivation layer residual film of a certain thickness, it is usually necessary to add an extra photomask to define the wire area, which leads to increased wafer fabrication cost and extended processing time.
[0007] To solve the above-mentioned technical problems, the present invention provides a process for forming a metal filament, comprising:
[0008] Step 1: Provide a semiconductor structure. A top metal layer is formed on the surface of the semiconductor structure. The top metal layer includes a bonding pad structure and a metal wire structure, and the metal wire structure is an isolated pattern.
[0009] Step 2: Form a passivation layer covering the top metal layer on the surface of the semiconductor structure;
[0010] Step 3: Coat a photoresist layer on the passivation layer surface and pattern the photoresist layer to expose the passivation layer that needs to be etched above the bonding pad structure, while ensuring that the patterned photoresist layer covers the metal filament structure. During the coating of the photoresist layer, due to the micro-load effect, the thickness of the photoresist layer above the isolated patterned metal filament structure is less than the thickness of the photoresist layer in the conventional patterned area.
[0011] Step 4: Perform a single etching process to remove the exposed passivation layer above the bonding pad structure, thereby exposing the bonding pad structure. Simultaneously, during the single etching process, a thinner photoresist layer above the metal filament structure is consumed. After the photoresist layer is completely consumed, continue etching downwards to remove part of the passivation layer above the metal filament structure, so as to retain a passivation layer residue of a predetermined thickness above the metal filament structure without adding an additional photomask.
[0012] Preferably, in step one, the thickness of the top metal layer is 0.6 μm to 1.2 μm.
[0013] Preferably, in step one, the width of the metal filament structure is 0.6 μm to 1.0 μm.
[0014] Preferably, in step one, there is a region with no other metal layer pattern extending 40µm to 80µm to the left and right of the metal filament structure as the center.
[0015] Preferably, in step two, the passivation layer thickness is 0.8 μm to 1.5 μm.
[0016] Preferably, in step three, due to the micro-load effect, the initial thickness of the photoresist layer covering the metal filament structure is 3.0 μm to 4.0 μm.
[0017] Preferably, in step four, the etching time for a single etching process is 200s to 300s.
[0018] Preferably, in step four, the thickness of the passivation layer residual film is 0.1 μm to 0.3 μm.
[0019] The present invention also provides a semiconductor structure with a metal filament, which is prepared by the process for forming the metal filament as described above. The semiconductor structure includes:
[0020] Substrate;
[0021] The top metal layer, located above the substrate, includes a bonding pad structure and a metal fuse structure used as a metal fuse, and no other metal layer patterns are arranged around the metal fuse structure to form an isolated pattern;
[0022] A passivation layer covers the substrate and part of the top metal layer; the passivation layer has an etched opening above the bonding pad structure and exposes the bonding pad structure; the passivation layer has a thinning region above the metal filament structure; the thinning region forms a passivation layer residue covering the metal filament structure; and the thinning region and the etched opening are formed simultaneously using a single etching process and micro-load effect.
[0023] Preferably, there are no other metal layer patterns within a range of 40um to 80um extending to the left and right of the isolated patterned metal filament structure as the center.
[0024] As described above, the process for forming the metal filament and the semiconductor structure of the present invention have the following beneficial effects:
[0025] By using the top-layer metal as the fuse material and cleverly leveraging the micro-loading effect caused by isolated patterns, the photoresist layer thickness above the metal fuse is naturally smaller than in conventional areas. Through a single etching process, full opening of the bonding pads is achieved, and thinning control of the passivation layer above the fuse is realized after the photoresist is consumed. This method eliminates the need for additional photomasks and achieves precise preservation of the residual passivation layer thickness without adding photolithography, development, and cleaning processes, significantly reducing wafer fabrication costs and shortening product manufacturing cycles. Attached Figure Description
[0026] Figure 1 The diagram shows a process flow diagram of the present invention for making metal filaments using top metal.
[0027] Figure 2 The diagram shows a semiconductor structure before etching in the process of making a metal filament using a top layer metal according to the present invention.
[0028] Figure 3 The diagram shows a semiconductor structure after etching in the process of making a metal filament using a top layer metal according to the present invention. Detailed Implementation
[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0030] refer to Figure 1 , Figure 1 A schematic diagram of the process for forming the metal filament 103.
[0031] The process for forming the metal filament 103 includes:
[0032] Step 1: Provide a semiconductor structure. A top metal layer is formed on the surface of the semiconductor structure. The top metal layer includes a bonding pad structure 102 and a metal fuse structure 103, and the metal fuse structure 103 is an isolated pattern. (Reference) Figure 2 , Figure 2 The cross-sectional morphology of the semiconductor structure before etching is shown.
[0033] This semiconductor structure typically includes a substrate 101, which can be single-crystal silicon, silicon-on-insulator (SiI), or a compound semiconductor material composed of group III-V elements. On top of the substrate 101, active devices such as transistors and wiring layouts consisting of multiple layers of interlayer insulating dielectrics and conductive plugs have been formed through preceding processes. The top metal layer, as the uppermost conductive layer of the chip, can be made of materials such as aluminum, copper, tungsten, or aluminum-copper alloys. In specific fabrication, a metal thin film can be sputtered onto the planarized dielectric layer surface, and then the film is diced into the required bonding pad structure 102 and metal fuse structure 103 using photolithography and dry metal etching equipment. The bonding pad structure 102 is configured as a bonding region for subsequent electrical connection with the outside. The metal fuse structure 103 serves as a programmable logic element, used to configure circuit parameters through physical melting during subsequent testing. Designing the metal filament structure 103 as an isolated, suspended island pattern, and deliberately leaving blank space around it, provides a structural basis for controlling the thickness of the photoresist layer 105 using the micro-load effect.
[0034] In some embodiments, the thickness of the top metal layer in step one is 0.6 μm to 1.2 μm. In a specific embodiment, the thickness of the top metal layer is 0.8 μm. By limiting the thickness of the top metal layer to a specific range, the relationship between conductivity and surface smoothness can be effectively balanced. If the metal layer is too thick, it may increase the difficulty of the subsequent passivation and encapsulation process; if the metal layer is too thin, it may affect the heat accumulation when the fuse burns out.
[0035] In some embodiments, in step one, the width of the metal fuse structure 103 is 0.6 μm to 1.0 μm. In a specific embodiment, the width of the metal fuse structure 103 is 0.8 μm. Setting the width of the metal fuse structure 103 within a specific range ensures that it generates sufficient local current density when receiving a programming voltage, thereby improving the accuracy of the fuse operation.
[0036] In some embodiments, in step one, there is a region with no other metal layer pattern extending 40µm to 80µm to the left and right of the metal filament structure 103 as the center. In a specific embodiment, refer to... Figure 2 Centered on the metal filament structure 103, there are no other metal layer patterns within a 60µm radius to the left and right. This wide blank area centered on the metal filament structure 103 ensures sufficient rheological space for the photoresist layer 105 during spin coating, thereby forming the target thin photoresist layer above the filament. This isolated distribution eliminates the dragging effect of dense patterns on the fluid, allowing the micro-loading effect to stably produce the expected thickness difference.
[0037] Step Two, Reference Figure 1 and Figure 2 A passivation layer 104 covering the top metal layer is formed on the surface of the semiconductor structure.
[0038] The passivation layer 104 can be composed of a single layer of dielectric material or a composite stacked structure formed by alternating deposition of multiple different dielectric materials. In terms of material selection, the passivation layer 104 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, undoped silicon glass, phosphosilicate glass, borosilicate glass, borosilicate phosphosilicate glass, or any combination of the above materials. For example, a composite passivation structure consisting of a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer can be used, where the silicon oxide layer is used to relieve stress, and the silicon nitride layer is used to provide high density barrier properties. Regarding the formation process, thin film growth is performed using chemical vapor deposition (CVD) equipment, specifically including atmospheric pressure CVD, low pressure CVD, plasma-enhanced CVD, or high-density plasma-enhanced CVD. As an alternative, atomic layer deposition (ALD) or spin-coating dielectric processes can also be used to form the passivation layer 104. In the specific deposition process, a semiconductor wafer is placed on a pedestal within a reaction chamber, and a silicon-containing precursor and reactive gas are introduced into the chamber. Under the excitation of radio frequency power or thermal energy, the aforementioned gas undergoes a chemical reaction on the surface of the top metal layer and deposits to form a dielectric film with conformal coverage properties. This dielectric film not only fills the gaps between the patterns of the top metal layer, but also climbs and covers along the surface contours of the metal filament structure 103 and the bonding pad structure 102. The passivation layer 104, as the outermost protective layer, can block the penetration of ambient moisture and free ions.
[0039] In some embodiments, in step two, the passivation layer 104 has a thickness of 0.8 μm to 1.5 μm. In a specific embodiment, refer to... Figure 2 The passivation layer 104 has a thickness of 1µm. Passivation media meeting this thickness requirement can provide the necessary physical and mechanical strength for the underlying metal and reserve sufficient process allowance for subsequent simultaneous thinning processes.
[0040] Step 3, Reference Figure 1 and Figure 2 A photoresist layer 105 is coated on the surface of the passivation layer 104 and patterned to expose the passivation layer 104 that needs to be etched above the bonding pad structure 102. At the same time, the patterned photoresist layer 105 covers the metal filament structure 103. When coating the photoresist layer 105, due to the micro-load effect, the thickness of the photoresist layer 105 above the isolated patterned metal filament structure 103 is less than the thickness of the photoresist layer 105 in the conventional patterned area.
[0041] The photoresist layer 105 is distributed in liquid form on the wafer surface using a spin coater. During the high-speed wafer rotation, driven by centrifugal force and surface tension, the liquid photoresist spontaneously expands towards the surrounding flat and low-lying areas. Since the metal filament structure 103 is located in the center of a large blank area, lacking the traction of surrounding dense patterns, the amount of photoresist directly above it will rapidly flow outwards. This micro-loading effect based on physical topographical differences results in a thinner photoresist layer 105 on the metal filament compared to other conventional areas. In this stage, a single mask is used to define the opening of the bonding pad structure 102 and the thin photoresist layer above the metal filament structure 103. This process strategy utilizes the topographically induced distribution differences of the photoresist layer 105, not only reducing the cost of a set of expensive mask fabrication but also shortening the processing time of the photolithography and development stage, effectively increasing the production line's output rate.
[0042] In some embodiments, in step three, due to the micro-loading effect, the initial thickness of the photoresist layer 105 covering the metal filament structure 103 is 3.0 μm to 4.0 μm. In a specific embodiment, refer to... Figure 2 The initial thickness of the photoresist layer 105 is 3.53 μm. By limiting the initial thickness range of this photoresist layer 105, it can serve as a suitable sacrificial layer in subsequent etching, thereby achieving precise control over the amount of thinning of the underlying dielectric.
[0043] Step 4, Reference Figure 1 and Figure 3 ,in Figure 3The cross-sectional morphology of the semiconductor structure after etching is shown. A single etching process is performed to remove part of the passivation layer 104 exposed above the bonding pad structure 102, thereby exposing the bonding pad structure 102. Simultaneously, in the single etching process, a thin photoresist layer 105 located above the metal filament structure 103 is consumed. After the photoresist layer 105 is completely consumed, the etching continues to etch down to the part of the passivation layer 104 above the metal filament structure 103, so as to retain a passivation layer residue of a predetermined thickness above the metal filament structure 103 without adding an additional photomask.
[0044] The single-pass etching process is performed in a vacuum ion etching machine, where a reactive gas containing, for example, fluorocarbons is introduced, generating anisotropic impacts in a plasma environment excited by radio frequency power. The ion beam removes the passivation layer 104 at the location of the bonding pad structure 102 until it reaches the surface of the bonding pad structure 102, while simultaneously stripping the photoresist layer 105 above the metal filament structure 103. Because the initial thickness of the photoresist layer 105 is small, it is exhausted before the etching task is completed, and then the remaining etching energy begins to thin the passivation layer 104 above the filament.
[0045] In some embodiments, the etching time for a single etching process in step four is 200s to 300s. In a specific embodiment, the etching time is 240s. Locking the etching time within a specific window ensures that the bonding pad structure 102 is completely cleaned while avoiding damage to the fuse body due to excessive etching.
[0046] In some embodiments, in step four, the thickness of the passivation layer residual film is 0.1 μm to 0.3 μm. In a specific embodiment, refer to... Figure 3 The passivation layer 104 leaves a residual film thickness of approximately 0.2 μm above the metal filament structure 103. Retaining this specific thickness range of the passivation layer residual film can both isolate external contaminants and provide the necessary physical constraint at the moment the filament burns out, preventing metal splashing.
[0047] The semiconductor structure with metal fuse 103 is fabricated using the process described above. (Reference) Figure 3 The semiconductor structure includes:
[0048] Substrate 101; Top metal layer, located above substrate 101, the top metal layer includes a bonding pad structure 102 and a metal fuse structure 103 serving as a metal fuse, and no other metal layer pattern is arranged around the metal fuse structure 103 to form an isolated pattern; Passivation layer 104, covering substrate 101 and part of the top metal layer; Passivation layer 104 has an etched opening on the bonding pad structure 102 and exposes the bonding pad structure 102, and has a thinning region above the metal fuse structure 103, the thinning region forming a passivation layer residue film covering the metal fuse structure 103, and the thinning region and the etched opening are formed simultaneously using a single etching process and micro-loading effect.
[0049] In some embodiments, an isolated patterned metal filament structure 103 is centered on a region extending 40µm to 80µm to the left and right without any other metal layer patterns. In a specific embodiment, this patternless region is 60µm wide. This width of patternless region ensures the consistency of the rheological behavior of the photoresist layer 105. This layout allows the passivation layer 104 above the metal filament structure 103 throughout the chip to achieve a nearly constant thinning depth, significantly improving the convergence of electrical programming metrics across the entire wafer, thereby improving product yield.
[0050] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0051] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A process for forming a molten metal wire, characterized in that, At least including: Step 1: Provide a semiconductor structure. A top metal layer is formed on the surface of the semiconductor structure. The top metal layer includes a bonding pad structure and a metal wire structure, and the metal wire structure is an isolated pattern. Step 2: Form a passivation layer covering the top metal layer on the surface of the semiconductor structure; Step 3: Coat a photoresist layer on the passivation layer surface and pattern the photoresist layer to expose the passivation layer that needs to be etched above the bonding pad structure, while ensuring that the patterned photoresist layer covers the metal filament structure. During the coating of the photoresist layer, due to the micro-load effect, the thickness of the photoresist layer above the isolated patterned metal filament structure is less than the thickness of the photoresist layer in the conventional patterned area. Step 4: Perform a single etching process to remove the exposed passivation layer above the bonding pad structure, thereby exposing the bonding pad structure. Simultaneously, during the single etching process, a thinner photoresist layer above the metal filament structure is consumed. After the photoresist layer is completely consumed, continue etching downwards to remove part of the passivation layer above the metal filament structure, so as to retain a passivation layer residue of a predetermined thickness above the metal filament structure without adding an additional photomask.
2. The process for forming a metal filament according to claim 1, characterized in that: In step one, the thickness of the top metal layer is 0.6 μm to 1.2 μm.
3. The process for forming a metal filament according to claim 1, characterized in that: In step one, the width of the metal filament structure is 0.6 μm to 1.0 μm.
4. The process for forming a metal filament according to claim 1, characterized in that: In step one, there is a region with no other metal layer pattern extending 40um to 80um to the left and right of the metal filament structure as the center.
5. The process for forming a metal filament according to claim 1, characterized in that: In step two, the passivation layer thickness is 0.8 μm to 1.5 μm.
6. The process for forming a metal filament according to claim 1, characterized in that: In step three, due to the micro-load effect, the initial thickness of the photoresist layer covering the metal filament structure is 3.0 μm to 4.0 μm.
7. The process for forming a metal filament according to claim 1, characterized in that: In step four, the etching time for a single etching process is 200s to 300s.
8. The process for forming a metal filament according to claim 1, characterized in that: In step four, the thickness of the passivation layer residual film is 0.1 μm to 0.3 μm.
9. A semiconductor structure having a metal fused wire, characterized in that, Prepared using the process method for forming a metal filament as described in any one of claims 1 to 8, comprising: Substrate; The top metal layer, located above the substrate, includes a bonding pad structure and a metal fuse structure used as a metal fuse, and no other metal layer patterns are arranged around the metal fuse structure to form an isolated pattern; A passivation layer covers the substrate and part of the top metal layer; the passivation layer has an etched opening above the bonding pad structure and exposes the bonding pad structure; the passivation layer has a thinning region above the metal filament structure; the thinning region forms a passivation layer residue covering the metal filament structure; and the thinning region and the etched opening are formed simultaneously using a single etching process and micro-load effect.
10. The semiconductor structure with a metal filament according to claim 9, characterized in that: Centered on an isolated pattern of metal filament structure, there are no other metal layer patterns extending 40um to 80um to the left and right.