Semiconductor device and method of manufacturing the same

Abstract

This disclosure provides a semiconductor device and a method for manufacturing the same. The device includes: a semiconductor layer; a body region located within the semiconductor layer; a source region and a drain region located within the body region and spaced apart from each other; a gate conductor located above the semiconductor layer and between the source and drain regions; a gate dielectric layer located between the gate conductor and the semiconductor layer; and a field oxide layer surrounding the source and drain regions, at least on the surface of the semiconductor layer. The semiconductor device also includes a doped ring located within the semiconductor layer, with the source and drain regions located within the doped ring, and the field oxide layer surrounding the doped ring. The body region and the doped ring are of a first doping type, and the source and drain regions are of a second doping type, with the first doping type being the opposite of the second doping type. By providing a doped ring with the opposite doping type to the source / drain regions around the source / drain regions, the source / drain regions are isolated from the field oxide layer, thereby solving the technical problems of source / drain punch-through induced by positive charge in the field oxide layer (DIT) and crosstalk between adjacent devices, as well as the large current problem caused by single-event flip-flops (SEE).

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device manufacturing, and more specifically, to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] In the field of radiation-hardened semiconductor device design, traditional CMOS structures face the dual challenges of total ionizing dose (TID) and single-event effect (SEE). In existing technologies, devices employing LOCOS or STI isolation structures accumulate fixed positive charges within and at the interface of their silicon dioxide insulating layer due to electron-hole pair separation under radiation conditions. This leads to phenomena such as negative threshold voltage drift in NMOS devices and positive threshold voltage drift in PMOS devices. More seriously, these trapped charges can induce parasitic channels at the edges of the field oxide region, causing a surge in off-state leakage current between the source / drain and the substrate, resulting in uncontrolled static power consumption and abnormal logic levels. Furthermore, radiation-induced leakage coupling and potential crosstalk can occur between different devices in BCD processes. In addition, when these traditional structures encounter single-event upsets, the transient charges generated by high-energy particles directly alter the potential state of sensitive nodes, leading to memory cell logic errors or triggering transient pulse interference circuitry. Summary of the Invention

[0003] This disclosure provides a semiconductor device and its manufacturing method. By setting a doped ring with the inverse of the source / drain region around the source / drain region, the source / drain region is isolated from the field oxide layer, thereby solving the technical problems of source / drain punch-through induced by positive charge of the field oxide layer DIT and crosstalk between adjacent devices.

[0004] According to one aspect of the present disclosure, a semiconductor device is provided, comprising:

[0005] Semiconductor layer;

[0006] The body region is located within the semiconductor layer;

[0007] The source region and the drain region are located in the body region and are spaced apart from each other;

[0008] A gate conductor is located above the semiconductor layer and between the source region and the drain region;

[0009] A gate dielectric layer is located between the gate conductor and the semiconductor layer; and

[0010] A field oxide layer surrounds the source region and the drain region at least on the surface of the semiconductor layer.

[0011] The semiconductor device further includes a doped ring located within the semiconductor layer, the source region and the drain region being located within the doped ring, and the field oxide layer surrounding the doped ring.

[0012] The body region and the doped ring are of the first doping type, and the source region and the drain region are of the second doping type. The first doping type is the opposite of the second doping type.

[0013] Optionally, the doped ring is located in the body region, and the doping concentration of the doped ring is higher than the doping concentration of the body region.

[0014] Optionally, it further includes a gate ring located above the semiconductor layer, and the gate ring is separated from the semiconductor layer by the gate dielectric layer.

[0015] The gate conductor is located inside the gate ring, and the doped ring surrounds the gate ring.

[0016] Optionally, the inner edge of the doped ring is connected to the source region and the drain region, and the outer edge of the doped ring is connected to the field oxide layer.

[0017] Optionally, the inner edge of the doped ring is located directly below the gate ring.

[0018] Optionally, the gate ring is connected to the gate conductor.

[0019] Optionally, the gate conductor is in the form of a strip extending along a first direction, with both ends connected to the gate ring.

[0020] Optionally, the number of gate conductors is multiple, and they are arranged at intervals along the second direction.

[0021] The first direction, the second direction, and the thickness direction of the semiconductor layer are all perpendicular to each other.

[0022] Optionally, the gate dielectric layer is morphologically matched with the gate conductor and the gate ring, respectively.

[0023] Optionally, the gate dielectric layer is separated from the field oxide layer.

[0024] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided for forming the semiconductor device as described above.

[0025] One of the above technical solutions has the following beneficial effects:

[0026] By setting a doped ring with the opposite doping type to the source / drain region around the source / drain region, and having the field oxide layer laterally surround the doped ring, the doped ring separates the source / drain region from the sidewall of the field oxide layer. Due to the opposite doping type of the doped ring to the source / drain region, a potential barrier is formed under radiation environment, blocking the formation path of parasitic channels caused by the accumulation of positive charge on the surface of the field oxide layer. This solves the technical problem of source / drain punch-through induced by DIT positive charge and crosstalk between adjacent devices in the field oxide layer.

[0027] In some alternative embodiments, the risk of DIT-induced punch-through can be further reduced because the doped ring is located in the same type of body region and has a higher doping concentration. At the same time, when the device generates a large current due to single-event upset (SEE), the high-concentration doped ring will absorb part of the current first, reducing the current peak value. Then, when the current flows to other structures, its impact on the device will be greatly reduced.

[0028] In some alternative embodiments, by adding a gate ring connected to the gate conductor, the gate ring conductor and the gate conductor adopt a continuous extension structure of the same material, and the two together cover the gate dielectric layer and form a capacitive coupling region. This design can increase the gate capacitance, thereby absorbing the transient charge generated by single-particle incident, thereby suppressing the potential fluctuation of sensitive nodes.

[0029] The semiconductor device disclosed herein achieves a synergistic effect of multiple radiation resistance mechanisms through an innovative ring structure layout: First, the adjacent design of the doped ring and the source / drain regions ensures that the carrier transport path is always surrounded by a high doping barrier, avoiding radiation-induced surface leakage channels; second, the integrated design of the gate ring and gate conductor maintains device symmetry while effectively attenuating transient current peaks caused by single-event upsets by increasing the equivalent capacitance of the gate system; third, the localized distribution strategy of the gate dielectric layer (existing only below the gate conductor and gate ring) eliminates the defect-sensitive region at the interface between the field oxide and gate oxide layers in traditional devices. This three-dimensional protective structure, while maintaining CMOS process compatibility, simultaneously solves key technical challenges such as threshold voltage drift caused by TID, surge in off-state leakage current, and single-event upsets caused by SEE, making it particularly suitable for BCD process integration scenarios requiring high reliability. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0031] Figure 1 A top view of a semiconductor device structure in the related art is shown.

[0032] Figure 2 It shows along Figure 1 A cross-sectional view of the section cut by line AA.

[0033] Figure 3 A three-dimensional structural schematic diagram of a semiconductor device according to a first embodiment of the present disclosure is shown.

[0034] Figure 4 A schematic cross-sectional view of a semiconductor device according to a first embodiment of this disclosure is shown.

[0035] Figure 5 A top view of the semiconductor device according to a second embodiment of the present disclosure is shown.

[0036] Figure 6 It shows along Figure 5 A cross-sectional view taken along line BB. Detailed Implementation

[0037] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.

[0038] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0039] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".

[0040] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.

[0041] This disclosure may be presented in various forms, as will be described below. Figures 1 to 6 Describe some of these examples.

[0042] like Figure 1 and Figure 2 As shown, in some related technologies, a semiconductor device includes: a semiconductor layer 201, a source region 211, a drain region 212, a field oxide layer 240, a gate dielectric layer (not shown), and a gate conductor 261. A field oxide layer 240 is formed on the surface of the semiconductor layer 201, thereby creating a region division on the surface of the semiconductor layer 201. The region on the surface of the semiconductor layer 201 covered by the field oxide layer 240 serves as a field region for electrical isolation between devices, while the region not covered by the field oxide layer 240 serves as an active area. The active area retains the surface of the semiconductor layer 201 for forming device structures such as source / drain / gate.Figure 1 and Figure 2 The diagram shows two active regions, a first active region 21 and a second active region 22, with a field oxide layer 240 laterally surrounding both regions, thereby separating them. A source region 211, a drain region 212, a gate dielectric layer (not shown), and a gate conductor 261 are formed in each active region. The source region 211 and the drain region 212 are adjacent to the field oxide layer 240.

[0043] When the device is exposed to radiation, the field oxide layer 240 traps a large number of positive charges internally and at the silicon / silicon dioxide interface due to the total ionizing dose (TID) effect. These positive charges form a transverse electric field on the device surface, inducing parasitic channels and causing unintended leakage current paths between the source and drain regions or between adjacent devices. Taking an NMOS device as an example, the source region 211 and drain region 212 are N-type doped, and the semiconductor layer 201 is P-type doped. The positive charges formed on the sidewalls of the field oxide layer 240 due to TID attract electrons to form conductive channels, causing punch-through between the source region 211 and drain region 212, such as... Figure 1 As shown by the dashed arrow. For devices formed within adjacent first active regions 21 and second active regions 22, the positive charges on the sidewalls and bottom of the field oxide layer 240 attract electrons to form conductive channels, inducing punch-through between adjacent devices, such as... Figure 2 As shown. Regarding single-event effects (SEE), if the transient charges generated by high-energy particle incident are collected by the source-drain region, they will directly change the potential state of sensitive nodes, such as logic flips in SRAM memory cells or transient pulse interference in analog circuits. Moreover, traditional structures lack effective charge buffering mechanisms, making it difficult to suppress errors.

[0044] Figure 3 A three-dimensional structural schematic diagram of the semiconductor device according to the first embodiment of this disclosure is shown. Figure 4 A schematic cross-sectional view of a semiconductor device according to a first embodiment of this disclosure is shown.

[0045] like Figure 3 and Figure 4As shown, the semiconductor device of the first embodiment of this disclosure includes: a semiconductor layer 101, a body region 110, a source region 121, a drain region 122, a doped ring 130, a field oxide layer 140, a gate dielectric layer 150, a gate conductor 161, and a gate ring 162. The body region 110 and the doped ring 130 are of a first doping type, and the source region 121 and the drain region 122 are of a second doping type, with the first doping type being the opposite of the second doping type. The doping concentration of the doped ring 130 is greater than the doping concentration of the body region 110. The first doping type is selected from either P-type doping or N-type doping, and the second doping type is selected from either P-type doping or N-type doping. The semiconductor layer 101 is, for example, a semiconductor substrate, an epitaxial layer located on a substrate, or a semiconductor substrate and an epitaxial layer together serving as the semiconductor layer 101. In the following description, the semiconductor layer 101 will be described as a semiconductor substrate, and the doping type of this semiconductor substrate may be the opposite of that of the body region 110.

[0046] In this embodiment, the field oxide layer 140 adopts an STI structure, extending from the surface of the semiconductor layer 101 into the interior of the semiconductor layer 101, thereby embedding itself within the semiconductor layer 101. A specific example is provided where the field oxide layer 140 laterally surrounds the surface of the semiconductor layer 101, thus dividing it into two adjacent first active regions 11 and second active regions 12. Of course, this embodiment is not limited to this; those skilled in the art can make other configurations to the structure of the field oxide layer 140 as needed, for example, using LOCOS. Furthermore, the number of active regions can also be set as needed.

[0047] In the first active region 11, the body region 110 is located in the semiconductor layer 101 and is laterally surrounded. The source region 121, drain region 122, and doped ring 130 are all located in the body region 110. The source region 121 and drain region 122 are spaced apart from each other and located within the doped ring 130. The inner edge of the doped ring 130 is connected (tangentially) to the source region 121 and drain region 122, and the outer edge of the doped ring 130 is connected to the field oxide layer 140. In some specific embodiments, the source region 121 and drain region 122 are rectangular, and all edges except the adjacent edges of the source region 121 and drain region 122 are connected to the doped ring 130. Gate conductor 161 and gate ring 162 are located above semiconductor layer 101. Gate conductor 161 extends along the Y-axis (first direction), source region 121 and drain region 122 are located on both sides of gate conductor 161 along the X-axis (second direction), and gate ring 162 laterally surrounds gate conductor 161, source region 121 and drain region 122. The X-axis, Y-axis and Z-axis (thickness direction of semiconductor layer 101) are mutually perpendicular. In this embodiment, gate ring 162 is connected to both ends of gate conductor 161, and the inner edge of doped ring 130 is located directly below gate ring 162. Gate conductor 161 and gate ring 162 can be formed together in the same layer, and their material is, for example, polysilicon. The gate dielectric layer 150 is located between the gate conductor 161 and the semiconductor layer 101, and also between the gate ring 162 and the semiconductor layer 101. The gate dielectric layer 150 matches the morphology of the gate conductor 161 and the gate ring 162. That is, the gate dielectric layer 150 is located only directly below the gate conductor 161 and its annular extension structure gate ring 162, and the gate dielectric layer 150 is not connected to the field oxide layer 140.

[0048] The device structure in the second active region 12 can be the same as or different from the device structure in the first active region 11. Figure 3 and Figure 4 The same situation is shown, in which the volume regions 110 in the two active regions are not connected to each other.

[0049] Taking an NMOS device in the active region as an example, this embodiment achieves a breakthrough improvement in radiation resistance through a multi-layered protection design in three-dimensional space. When encountering the total ionization dose effect, the positive charge generated by radiation-induced on the sidewall of the field oxide layer 140 is completely covered and isolated by the P+ doped ring 130, and the dynamic hole barrier formed by it effectively blocks the formation path of parasitic channels. For single-event effect scenarios, the extended gate structure formed by the gate ring 162 and the gate conductor 161 increases the equivalent capacitance of the gate system in terms of physical size. When high-energy particles are incident and transient charges are generated, the charge collection area below the gate dielectric layer 150 expands to the entire annular area covered by the gate ring 162, making the charge density distribution more uniform, thereby reducing the amplitude of local potential fluctuations. At the same time, the adjacent interface between the P+ doped ring 130 and the N+ source / drain region forms an asymmetric carrier collection mechanism under radiation conditions, in which the high-concentration P+ region of the doped ring 130 preferentially absorbs electrons in the electron-hole pairs generated by SEE, forming a transient current I. SEE The primary buffer layer is constructed using this structure. This layout not only solves the source-drain punch-through problem caused by the DIT effect in the field oxide layer 140, but also significantly reduces the peak value of single-particle-induced transient current through the synergistic effect of ring doping and extended gate. Furthermore, the completely symmetrical design of the source region 121 and drain region 122 allows for interchangeable source and drain terminals in circuit applications, ensuring consistency in electrical characteristics. The vertical alignment of the gate ring 162 and the doped ring 130 utilizes the high etching precision of polysilicon to achieve precise control of device dimensions, saving chip area while improving process compatibility.

[0050] Figure 5 A top view of the semiconductor device according to a second embodiment of this disclosure is shown. Figure 6 It shows along Figure 5 A cross-sectional view taken along line BB.

[0051] like Figure 5 and Figure 6 As shown, there are multiple gate conductors 161 arranged at intervals along the X-axis to form a multi-finger gate array. Each gate conductor 161 extends along the Y-axis, and its two ends are connected to annularly extending gate rings 162, forming a continuous polysilicon conductive network. This multi-finger structure maintains the symmetry of the device while significantly improving the equivalent capacitance of the gate system by paralleling and superimposing the capacitance effects of multiple gate conductors 161 through the annular arrangement of the gate rings 162. When encountering a single-event event, the transient charge generated by the incident particle is collected over a large area by the gate dielectric layer 150 below the gate rings 162, and the charge diffusion path is confined to the annular region, thereby reducing the peak charge density per unit area.

[0052] This disclosure presents a dual-shielding structure of "doped ring-gate ring" by setting a doped ring with the inverse of the source / drain region around the source / drain region and placing a gate ring integrated with the gate conductor above it. This structure blocks parasitic channels induced by positive charge in the field oxide layer under the total ionization dose effect, significantly suppressing source / drain punch-through and crosstalk between adjacent devices. Under the single-event effect, the synergistic effect of charge shunting by the high-concentration doped ring and charge absorption by the extended gate capacitance reduces the transient current peak by more than an order of magnitude, thereby simultaneously solving the problems of TID threshold drift, off-state leakage surge, and excessive SEE switching current.

[0053] The present disclosure has been described in detail above with reference to specific embodiments, but the present disclosure is not limited to the details of the above embodiments. Without departing from the spirit and scope of the present disclosure, those skilled in the art can make various equivalent modifications, substitutions or variations to the technical solutions of the present disclosure, and such modifications, substitutions or variations should all be covered within the protection scope defined by the claims of the present disclosure.

Claims

1. A semiconductor device, comprising: Semiconductor layer; The body region is located within the semiconductor layer; The source region and the drain region are located in the body region and are spaced apart from each other; A gate conductor is located above the semiconductor layer and between the source region and the drain region; A gate dielectric layer is located between the gate conductor and the semiconductor layer; as well as A field oxide layer surrounds the source region and the drain region at least on the surface of the semiconductor layer. The semiconductor device further includes a doped ring located within the semiconductor layer, the source region and the drain region being located within the doped ring, and the field oxide layer surrounding the doped ring. The body region and the doped ring are of the first doping type, and the source region and the drain region are of the second doping type. The first doping type is the opposite of the second doping type.

2. The semiconductor device according to claim 1, wherein, The doped ring is located in the body region, and the doping concentration of the doped ring is higher than that of the body region.

3. The semiconductor device of claim 1, further comprising a gate ring located above the semiconductor layer, wherein the gate ring is separated from the semiconductor layer by the gate dielectric layer. in, The gate conductor is located inside the gate ring, and the doped ring surrounds the gate ring.

4. The semiconductor device according to claim 3, wherein, The inner edge of the doped ring is connected to the source region and the drain region, and the outer edge of the doped ring is connected to the field oxide layer.

5. The semiconductor device according to claim 4, wherein, The inner edge of the doped ring is located directly below the gate ring.

6. The semiconductor device according to claim 3, wherein, The gate ring is connected to the gate conductor.

7. The semiconductor device according to claim 6, wherein, The gate conductor is in the form of a strip extending along a first direction, with both ends connected to the gate ring.

8. The semiconductor device according to claim 7, wherein, The number of gate conductors is multiple, and they are arranged at intervals along the second direction. The first direction, the second direction, and the thickness direction of the semiconductor layer are all perpendicular to each other.

9. The semiconductor device according to any one of claims 3 to 8, wherein, The gate dielectric layer is morphologically matched with the gate conductor and the gate ring, respectively.

10. The semiconductor device according to any one of claims 3 to 8, wherein, The gate dielectric layer is separated from the field oxide layer.

11. A method for manufacturing a semiconductor device, for forming the semiconductor device as described in any one of claims 1 to 10.

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