Phase change material switch and method of manufacturing the same

Abstract

A phase change material switch includes a phase change layer disposed on a metal liner. A gate dielectric layer is disposed on the phase change layer. A metal gate liner is disposed on the gate dielectric layer.

Description

Technical Field

[0001] This invention generally relates to memory devices. This disclosure generally relates to phase change material switches, and more specifically to non-volatile four-terminal phase change material switches. Background Technology

[0002] Currently, the emerging memory device technology is phase-change memory (PCM). PCM is a type of non-volatile random access memory (RAM). PCM utilizes the properties of phase change materials, which can transform between a crystalline phase and an amorphous phase in response to an electric current passing through them. Typically, in PCM manufacturing, phase change materials include chalcogenides, such as germanium-antimony-tellurium (GST).

[0003] The PCM includes a phase change material region disposed between the bottom electrode contact and the top electrode contact. The phase change material has low resistivity in its crystalline phase and high resistivity in its amorphous phase. To position the PCM in the amorphous phase, the phase change material is first melted and then rapidly quenched for a short time by applying a large current pulse, leaving an amorphous, high-resistivity region in the PCM cell. To position the PCM in the crystalline phase, a medium current pulse is applied to anneal the phase change material at a temperature between the crystallization temperature and the melting temperature for a sufficiently long period to allow the phase change material with relatively low resistivity to crystallize. To read the state of the PCM, the resistivity of the cell is measured by passing a low current signal that does not interfere with the state of the phase change material through the cell. Furthermore, PCM technology has the ability to realize multiple different intermediate states, thus providing the PCM with the ability to hold multiple bits in a single cell, thereby providing increased memory density. Summary of the Invention

[0004] From a first aspect, the present invention provides a phase change material switch, comprising: a phase change layer disposed on a metal pad; a gate dielectric layer disposed on the phase change layer; and a metal gate pad disposed on the gate dielectric layer.

[0005] In another aspect, the present invention provides a phase change material bridge device, comprising: a phase change material switch of the present invention; an electrode including an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer; and a metal pad disposed on a portion of the inner metal dielectric layer and the at least two metal contact vias; wherein the gate dielectric layer is further disposed on the metal pad and the phase change layer, the at least two metal contact vias, and the remaining portion of the inner metal dielectric layer, wherein the metal pad and the phase change layer include a horizontal bridge between the at least two metal contact vias.

[0006] In another aspect, the present invention provides a semiconductor structure comprising: a phase change material switch of the present invention; a semiconductor substrate; an electrode disposed on the semiconductor substrate, wherein the electrode comprises an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer; and a metal pad disposed on a portion of the at least two metal contact vias and a portion of the inner metal dielectric layer, wherein the metal pad and the phase change layer comprise a horizontal bridge between the at least two metal contact vias.

[0007] In another aspect, the present invention provides a phase change material bridge device, comprising: an electrode including an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer; a metal pad disposed on the at least two metal contact vias and a portion of the inner metal dielectric layer; a phase change layer disposed on the metal pad; a gate dielectric layer disposed on the metal pad, the phase change layer, and the remaining portion of the at least two metal contact vias and the inner metal dielectric layer, wherein the metal pad and the phase change layer comprise a horizontal bridge between the at least two metal contact vias; and a metal gate pad disposed on the gate dielectric layer.

[0008] In another aspect, the present invention provides a semiconductor structure comprising: a semiconductor substrate; electrodes disposed on the semiconductor substrate, wherein the electrodes include an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer; a metal pad disposed on the at least two metal contact vias and a portion of the inner metal dielectric layer; a phase change layer disposed on the metal pad; wherein the metal pad and the phase change layer include a horizontal bridge between the at least two metal contact vias; a gate dielectric layer disposed on the phase change layer; and a metal gate pad disposed on the gate dielectric layer.

[0009] In another aspect, the present invention provides a method comprising: forming a metal pad on an electrode, the electrode including an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer; forming a phase change layer on the metal pad; forming a first hard mask on the phase change layer; selectively removing a portion of the metal pad, the phase change layer, and the first hard mask to expose a portion of the inner metal dielectric layer and each of the at least two metal contact vias, wherein the remaining portions of the metal pad, the phase change layer, and the first hard mask form a horizontal bridge between the at least two metal contact vias; forming a gate dielectric layer on the outer surfaces of the metal pad, the phase change layer, and the first hard mask, and on the outer surfaces of each of the at least two metal contact vias and the exposed portion of the inner metal dielectric layer; and forming a metal gate pad on the gate dielectric layer.

[0010] In another aspect, the present invention provides a method comprising: forming a metal pad on an electrode, the electrode including an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer; forming a sacrificial layer on the metal pad; forming a first hard mask on the sacrificial layer; selectively removing a portion of the sacrificial layer, the first hard mask, and the metal pad to expose each of the at least two metal contact vias and a portion of the inner metal dielectric layer, wherein the remaining portions of the sacrificial layer, the first hard mask, and the metal pad form a bridge between the at least two metal contact vias; removing the first hard mask; and removing the exposed portions of each of the at least two metal contact vias and the inner metal dielectric layer, as well as the metal pad. A gate dielectric layer is formed on the pad, and a metal gate pad is formed on the gate dielectric layer; a second hard mask is formed on the metal gate pad; the second hard mask is etched to expose a portion of the metal gate pad; the exposed portion of the metal gate pad is removed to expose the gate dielectric layer; the exposed portion of the gate dielectric layer is removed to expose the sacrificial layer and each of the at least two metal contact vias and a portion of the inner metal dielectric layer; the sacrificial layer is removed to expose the metal pad and form an air gap defined between the top surface of the metal pad and the bottom surface of the gate dielectric layer; and a phase change layer is deposited on the inner metal dielectric layer and each of the at least two metal contact vias and the exposed portion of the metal pad.

[0011] The illustrative embodiments of this application include techniques for semiconductor manufacturing. In one illustrative embodiment, a phase change material switch includes a phase change layer disposed on a metal pad. The phase change material switch also includes a gate dielectric layer disposed on the phase change layer. The phase change material switch further includes a metal gate pad disposed on the gate dielectric layer.

[0012] In another illustrative embodiment, the phase change material (PCM) bridge device includes electrodes comprising an inner metal dielectric layer and at least two metal contact vias within the inner metal dielectric layer. The PCM bridge device further includes a metal pad disposed on the at least two metal contact vias and a portion of the inner metal dielectric layer. The PCM bridge device also includes a PCM layer disposed on the metal pad. The PCM bridge device further includes a gate dielectric layer disposed on the metal pad, the at least two metal contact vias, and the remaining portion of the inner metal dielectric layer. The metal pad and the PCM layer form a horizontal bridge between the at least two metal contact vias. The PCM bridge device further includes a metal gate pad disposed on the gate dielectric layer.

[0013] In another illustrative embodiment, the semiconductor structure includes a semiconductor substrate. The semiconductor structure also includes electrodes disposed on the semiconductor substrate. The electrodes include an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer. The semiconductor structure also includes metal pads disposed on the at least two metal contact vias and a portion of the inner metal dielectric layer. The semiconductor structure further includes a phase change layer disposed on the metal pads. The metal pads and the phase change layer include a horizontal bridge between the at least two metal contact vias. The semiconductor structure also includes a gate dielectric layer disposed on the phase change layer. The semiconductor structure further includes a metal gate pad disposed on the gate dielectric layer.

[0014] In another illustrative embodiment, a method includes forming a metal pad on an electrode having an inner metal dielectric layer and at least two metal contact vias. The method further includes forming a phase change layer on the metal pad. The method further includes forming a first hard mask on the phase change layer. The method further includes selectively removing portions of the metal pad, the phase change layer, and the first hard mask to expose each of the at least two metal contact vias and a portion of the inner metal dielectric layer. The remaining portions of the metal pad, the phase change layer, and the first hard mask form a horizontal bridge between the at least two metal contact vias. The method further includes forming a gate dielectric layer on the outer surfaces of the metal pad, the phase change layer, and the first hard mask, as well as on the exposed portions of each of the at least two metal contact vias and the inner metal dielectric layer. The method further includes forming a metal gate pad on the gate dielectric layer.

[0015] In another illustrative embodiment, a method includes forming an electrode including an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer. The method further includes forming a metal pad on the electrode. The method further includes forming a sacrificial layer on the metal pad. The method further includes forming a first hard mask on the sacrificial layer. The method further includes selectively removing a portion of the metal pad, the sacrificial layer, and the first hard mask to expose each of the at least two metal contact vias and a portion of the inner metal dielectric layer. Remaining portions of the metal pad, the sacrificial layer, and the first hard mask form a bridge between the at least two metal contact vias. The method further includes removing the first hard mask. The method further includes forming a gate dielectric layer on the exposed portions of the metal pad, each of the at least two metal contact vias, and the inner metal dielectric layer. The method further includes forming a metal gate pad on the gate dielectric layer. The method further includes forming a second hard mask on the metal gate pad. The method further includes etching the second hard mask to expose a portion of the metal gate pad. The method further includes removing the exposed portions of the metal gate pad to expose the gate dielectric layer. The method further includes removing an exposed portion of the gate dielectric layer to expose the sacrificial layer and each of the at least two metal contact vias and a portion of the inner metal dielectric layer. The method further includes removing the sacrificial layer to expose the metal pad and forming an air gap defined between the top surface of the metal pad and the bottom surface of the gate dielectric layer. The method further includes depositing a phase change layer in the air gap and on the inner metal dielectric layer, each of the at least two metal contact vias, and the exposed portion of the metal pad.

[0016] Other embodiments will be described in the following detailed description of the embodiments, which are read in conjunction with the accompanying drawings. Attached Figure Description

[0017] The invention will now be described by way of example only with reference to preferred embodiments, as shown in the following figures:

[0018] Figure 1 A plan view of the structure is depicted, indicating the X-section and Y-section positions for the following figures.

[0019] Figure 2 This is according to the first intermediate manufacturing stage of the illustrative embodiment. Figure 1 A cross-sectional view of the structure.

[0020] Figure 3 This is according to the illustrative embodiment in the second intermediate manufacturing stage. Figure 1 A cross-sectional view of the structure.

[0021] Figure 4This is according to the illustrative embodiment in the third intermediate manufacturing stage. Figure 1 A cross-sectional view of the structure.

[0022] Figure 5 This is according to the illustrative embodiment in the fourth intermediate manufacturing stage. Figure 1 A cross-sectional view of the structure.

[0023] Figure 6 This is according to the first intermediate manufacturing stage of an alternative illustrative embodiment. Figure 1 A cross-sectional view of the structure.

[0024] Figure 7 This is according to an alternative illustrative embodiment in the second intermediate manufacturing stage. Figure 1 A cross-sectional view of the structure.

[0025] Figure 8 This is according to an alternative illustrative embodiment in the third intermediate manufacturing stage. Figure 1 A cross-sectional view of the structure.

[0026] Figure 9 This is according to an alternative illustrative embodiment in the fourth intermediate manufacturing stage. Figure 1 A cross-sectional view of the structure.

[0027] Figure 10 This is according to an alternative illustrative embodiment in the fifth intermediate manufacturing stage. Figure 1 A cross-sectional view of the structure.

[0028] Figure 11 This is according to another illustrative embodiment in the sixth intermediate manufacturing stage. Figure 1 A cross-sectional view of the structure.

[0029] Figure 12 According to another illustrative embodiment Figure 1 The cross-sectional view of the structure in the seventh intermediate manufacturing stage.

[0030] Figure 13 According to another illustrative embodiment Figure 1 The cross-sectional view of the structure in the eighth intermediate manufacturing stage. Detailed Implementation

[0031] Exemplary embodiments of the invention will now be discussed in more detail with respect to phase change material switches. Phase change materials have been used in non-volatile memory devices due to the resistance difference between different phase states resulting from Joule heating. When amorphous, phase change materials exhibit high resistance (open circuit), while when recrystallized, they exhibit low resistance (closed circuit). Therefore, the threshold voltage is a function of the amorphization volume. Current structures use only two terminals, which are used for both programming and reading, making them less useful as electrical switching devices.

[0032] Therefore, illustrative embodiments provide a single 4-terminal switching device using at least a phase change material and a surrounding gate dielectric layer and a metal gate pad (also referred to as a heater), wherein the gate dielectric layer is located between the phase change material and the metal gate pad. The metal gate pad and the gate dielectric layer are configured orthogonal to the phase change layer to form the 4-terminal switching device. By forming such a device, the control circuitry and signal circuitry can be completely separated, thereby allowing for a wider range of applications.

[0033] It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic diagrams not drawn to scale. Furthermore, for ease of interpretation, one or more layers, structures, and regions of types typically used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown have been omitted from an actual semiconductor structure.

[0034] Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, regarding semiconductor processing steps, it is emphasized that the description provided herein is not intended to include all processing steps that may be necessary to form a functional semiconductor integrated circuit device. Rather, for the sake of economics, certain processing steps commonly used in forming such devices are not intentionally described herein.

[0035] Furthermore, the same or similar reference numerals are used in all the accompanying drawings to denote the same or similar features, elements, or structures; therefore, detailed explanations of the same or similar features, elements, or structures will not be repeated for each drawing. It should be understood that the terms “about” or “substantially” used herein with respect to thickness, width, percentage, range, etc., are intended to indicate approximation, but not precision. For example, as used herein, the terms “about” or “substantially” imply that a small margin of error may exist, such as less than 1% or less of the stated amount.

[0036] References to the principles of this specification as "one embodiment" or "embodiment" and other variations mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of the principles. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, and any other variations, do not necessarily refer to the same embodiment. The term "located" means that a first element (e.g., a first structure) is present on a second element (e.g., a second structure), wherein an intermediate element, such as an interface structure or an interface layer, may be present between the first and second elements. The term "direct contact" means that the first element (e.g., the first structure) and the second element (e.g., the second structure) are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0037] It should be understood that although the terms first, second, etc., can be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the scope of this concept, the first element discussed below can be referred to as the second element.

[0038] As used herein, “height” refers to the vertical dimension of a component (e.g., layer, trench, hole, opening, etc.) measured in a cross-sectional view from the bottom surface of the component to the top surface and / or relative to the surface on which the component is located. Conversely, “depth” refers to the vertical dimension of a component (e.g., layer, trench, hole, opening, etc.) in a cross-sectional view measured from the top surface to the bottom surface of the component. Where indicated, terms such as “thickness,” “thickness,” “thin,” or their derivatives may be used instead of “height.”

[0039] As used herein, “width” or “length” refers to the dimension of an element (e.g., layer, trench, hole, opening, etc.) in a drawing, measured from the side surface of the element to the opposite surface. Where indicated, terms such as “thickness,” “thickness,” “thin,” or their derivatives may be used instead of “width” or “length.”

[0040] The following will be referenced Figures 1 to 13 Illustrative embodiments for manufacturing phase change material switching devices are described. Note that the same reference numeral (100) is used to denote... Figures 1 to 5 The structures of the various intermediate manufacturing stages shown are indicated by reference numeral (200). Figures 6-13 The structures of the various intermediate manufacturing stages are shown. It should also be noted that the phase change material switching devices described herein can also be considered as semiconductor devices and / or integrated circuits or parts thereof. For clarity, the factors leading to such… Figure 1-13 The diagram illustrates some manufacturing steps involved in the production of a phase change material switching device. In other words, one or more well-known processing steps not included in the drawings but which are known to those skilled in the art are not shown.

[0041] Figure 1-5 An embodiment of the present invention is shown. Figure 1 Partial structure 100 (in plan view) is shown, which shows hard mask 112 and indicates the X-section and Y-section positions for identification purposes. Figure 2 This shows the first intermediate manufacturing stage. Figure 1Structure 100. Structure 100 first includes a substrate 102. Generally, substrate 102 may include one or more different types of semiconductor substrate structures and materials, as well as any previously processed layers. For example, in one embodiment, substrate 102 may be a bulk semiconductor substrate (e.g., a wafer) formed from silicon (Si) or germanium (Ge) or other types of substrate materials commonly used in bulk semiconductor manufacturing processes (e.g., silicon-germanium alloys, compound semiconductor materials (e.g., III-V)), an active semiconductor layer of an SOI (silicon-on-insulator) substrate, a GeOI (germanium-on-insulator) substrate, or other types of semiconductor-on-insulator substrates, which includes an insulating layer (e.g., an oxide layer) disposed between a base substrate layer (e.g., a silicon substrate) and an active semiconductor layer (e.g., Si, Ge, etc.), wherein active circuit elements are formed as part of the FEOL, and some BEOL layers prior to the formation of switching devices.

[0042] Structure 100 also includes a memory electrode 103 formed on substrate 102. The memory electrode 103 includes interconnects 106 in a dielectric layer 104. The dielectric layer 104, for example, serves as an interconnect dielectric (ICD) layer, in which interconnects are formed. A down-etch stop layer (not shown) may be disposed below the ICD layer. The down-etch stop layer may include various types of materials. In one embodiment, the down-etch stop layer includes a dielectric material. In one embodiment, the down-etch stop layer may include nitrogen-doped BLOK (NBLOK) or low-k NBLOK. Other types of etch stop materials, such as silicon nitride, may also be used.

[0043] In one embodiment, the ICD includes a lower portion and an upper portion. The lower portion serves as an interlayer dielectric (ILD) layer, while the upper portion serves as an internal metal dielectric (IMD) layer. The dielectric layers can be a single layer or a multilayer stack. For example, a single layer can serve as both an ILD and an IMD, or a separate layer can be used for both ILD and IMD. In some cases, an etch stop layer can be formed between the ILD and the IMD.

[0044] The dielectric layer may include, for example, silicon oxide. Other types of dielectric materials may also be used. For example, the dielectric layer may include silicon nitride, silicon dioxide, silicon oxynitride, SiCN, SiOCN, SiOC, SiBCN, dielectric metal oxides, dielectric metal nitrides, doped silicon oxide such as fluorinated silicon oxide (FSG), undoped or doped silicate glasses such as borosilicate glass (BPSG) and phosphate silicate glass (PSG), undoped or doped thermally grown silicon oxide, undoped or doped TEOS deposited silicon oxide, and low-k and ultra-low-k dielectric materials. Low-k dielectric materials have a nominal dielectric constant less than that of SiO2, which is approximately 4 (e.g., the dielectric constant of thermally grown silicon dioxide may be in the range of 3.9 to 4.0). In one embodiment, the low-k dielectric material may have a dielectric constant less than 3.7. Suitable low-k dielectric materials include, for example, fluorinated silicon glass (FSG), carbon-doped oxides, polymers, low-k materials containing SiCOH, non-porous low-k materials, porous low-k materials, spin-on dielectric (SOD) low-k materials, or any other suitable low-k dielectric materials. Ultra-low-k dielectric materials have a nominal dielectric constant of less than 2.5. Suitable ultra-low-k dielectric materials include, for example, SiOCH, porous pSiCOH, pSiCNO, carbon-rich silicon carbon nitride (C-rich SiCN), porous silicon carbon nitride (pSiCN), boron and phosphorus-doped SiCOH / pSiCOH, etc. In one embodiment, at least the IMD layer comprises a low-k or ultra-low-k dielectric material.

[0045] Interconnect 106 is formed in the ICD layer. Interconnects may include a plurality of interconnects. In one embodiment, an interconnect includes a conductor 106a located in the upper portion or IMD, while a contact 106b is formed in the lower portion or interlayer dielectric layer. Interconnects include a conductive material. For example, the conductive material can be any metal or alloy. In one embodiment, the interconnect may comprise copper, aluminum, tungsten, alloys thereof, or combinations thereof. It should be understood that the contact and conductor may include the same or different materials. The contact connects the conductor to an underlying contact area. Depending on the ICD level, the contact area may be another metal wire or device, such as a diffusion region or the gate of a transistor or the plate of a capacitor.

[0046] Metal pad 108 is formed on dielectric layer 104 and interconnect 106. Metal pad 108 is a high-resistivity metal pad. Suitable materials for metal pad 108 include, for example, TaN, TiN, etc. Metal pad 108 can be deposited by conventional techniques such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), sputtering deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, and other similar processes. In one exemplary embodiment, metal pad 108 may have a thickness ranging from about 1 nanometer (nm) to about 10 nm.

[0047] A phase change layer 110 comprising a phase change material is formed on a metal substrate 108 using conventional techniques such as CVD, pulsed CVD, and ALD. In a phase change memory, information is stored in a material that can be manipulated into different phases. Each of these phases exhibits different electrical properties that can be used to store information. Amorphous and crystalline phases are typically the two phases used for bit storage (1 and 0) because they have a detectable difference in resistance. Specifically, the amorphous phase has a higher resistance than the crystalline phase.

[0048] In one embodiment, suitable phase change materials include, for example, glass chalcogenides. This group of materials comprises chalcogenides (Group 16 / VIA of the periodic table) and elements with stronger positive charge. For example, selenium (Se) and tellurium (Te) are two of the most common semiconductors in the group used to generate glass chalcogenides when producing phase change layers. Representative examples would be Ge₂Sb₂Te₅ (GST), SbTe, and In₂Se₃. However, some phase change materials do not use chalcogenides, such as GeSb. Therefore, a variety of materials can be used as phase change material layers, as long as they can maintain separate amorphous and crystalline states.

[0049] The hard mask 112 is formed on the phase change layer 110 using any conventional technique. For example, the hard mask 112 can be deposited using processes such as CVD, PECVD, PVD, ALD, and other similar methods. The hard mask 112 can then be planarized, for example, by chemical mechanical planarization (CMP).

[0050] Then, the hard mask 112 is patterned to form as shown. Figure 2 The fins are shown. The patterning of the hard mask 112 is achieved by first applying a conventional photoresist (not shown) to the hard mask 112. After the photoresist is applied to the hard mask 112, the photoresist is subjected to a photolithography step, which includes exposing the photoresist in a patterned manner to the desired pattern of radiation and developing the exposed photoresist using a conventional photoresist developer. The patterned photoresist protects a portion of the hard mask 112 while leaving at least one other portion unprotected. The unprotected portions of the hard mask 112, as well as the phase change layer 110 and the metal pad 108, are then removed by etching, excluding the patterned photoresist. Any etching process can be used that selectively removes the unprotected portions of the hard mask 112 to form the patterned photoresist. Typically, reactive ion etching (RIE) or other similar dry etching processes are used. As shown in the figure, the etching process stops on top of a portion of the upper surface of the dielectric layer 104 and the interconnect structure 106, such that the remaining portion of the phase change layer 110 and the metal pad 108 under the hard mask 112 forms a bridge 111 between the two interconnect structures 106 (see figure). Figure 1The photoresist used in forming the patterned hard mask 112 is typically stripped off after the etching process.

[0051] Figure 3 Structure 100 in a second intermediate stage is shown. During this stage, a gate dielectric layer 114 is formed on the exposed surfaces of dielectric layer 104, interconnect 106, metal pad 108, phase change layer 110, and hard mask 112. Gate dielectric layer 114 advantageously protects the sidewalls of phase change layer 110. Suitable gate dielectric materials for gate dielectric layer 114 include, for example, dielectric materials that are the same as or different from those of dielectric layer 104. Typically, dielectric layers 104 and 114 are made of silicon oxide. Gate dielectric layer 114 is typically formed using conventional deposition processes, such as CVD. In one embodiment, gate dielectric layer 114 has a thickness ranging from about 1 nm to about 5 nm.

[0052] Then, using conventional deposition processes such as CVD, ALD, electroplating, and other similar processes, a metal gate pad 116 is formed on the gate dielectric layer 114. In one embodiment, the metal gate pad 116 and the gate dielectric layer 114 are configured orthogonal to the phase change layer 110. The metal gate pad 116 is configured as a resistance heater, comprising, for example, a metal or metal alloy material exhibiting resistivity and relatively high thermal conductivity. For example, the metal gate pad 116 can be formed from niobium (Nb), tungsten (W), platinum (Pt), nickel-chromium (NiCr), titanium-tungsten (TiW), TaN, TiN, or TaSiN, or any of various similar metals or metal alloys. Thus, the metal gate pad 116 can be configured to receive current to switch the phase change layer 110 between a crystalline and amorphous state. In this case, the phase change is achieved by passing current through the metal gate pad 116, which is located above the phase change layer 110 and electrically insulated from the phase change layer 110 by the gate dielectric layer 114. When current passes through the "resistance heater," the heater heats up due to the Joule effect, and the heat conduction generated by the "resistance heater" indirectly changes the state of the phase change layer 110. The metal gate pad 116 has a thickness ranging from about 4 nm to about 10 nm.

[0053] Next, the hard mask 118 is formed on the metal gate pad 116 using any conventional technique, such as CVD, PECVD, PVD, ALD, and other similar processes. Suitable materials for the hard mask 118 can be SiN, TEOS, or any other non-conductive film. The hard mask 118 can then be planarized, for example, by CMP. The hard mask 118 is then patterned and subjected to an etching process such as RIE to remove a portion of the hard mask 118, thereby exposing a portion of the metal gate pad 116.

[0054] Figure 4Structure 100 in a third intermediate stage is shown. During this stage, the exposed portion of the metal gate pad 116 is selectively removed, leaving a portion of the metal gate pad 116 on the gate dielectric layer 114 beneath the bottom surface of the hard mask 118. Removing the metal gate pad 116 may include applying an etchant in an etching process (e.g., a RIE process) that is selective for the dielectric layer 114. For example, etching the exposed portion of the metal gate pad 116 may be a dry etching performed using an etching gas. In an illustrative embodiment, the etching gas used for the dry etching process may include fluorine-containing gases and H2O vapor, which may be, for example, CxFy, CHxFy, etc.

[0055] Figure 5 Structure 100 in the fourth intermediate stage is shown. During this stage, a dielectric filler 120 is formed on the gate dielectric layer 114 and over the hard mask layer 118. The dielectric filler 120 can be made of any known dielectric material, such as silicon oxide, silicon nitride, silicon hydride carbon oxide, low-k dielectric, ultra-low-k dielectric, flowable oxide, porous dielectric, or organic dielectric including porous organic dielectrics. Low-k and ultra-low-k dielectric materials can be any of those materials discussed above with respect to the dielectric layer. The dielectric filler 120 can be formed by any suitable deposition technique known in the art, including ALD, CVD, PECVD, PVD, or other similar processes. The dielectric filler 120 can then undergo a planarization process, such as a CMP process.

[0056] Next, a metal contact including a metal gate contact 122 is formed. For example, the metal gate contact 122 is an electrical connection to the gate. Conductive vias or trenches are first formed using methods known in the art, such as selective etching through a hard mask 118 via RIE, to form the metal gate contact 122, such that the vias or trenches communicate with corresponding components; for example, the conductive vias or trenches for the metal gate contact 122 communicate with corresponding metal gate pads 116. Conductive material is then deposited within the vias or trenches. The conductive material used for the metal gate contact 122 includes any suitable conductive material, such as polycrystalline or amorphous silicon, germanium, silicon-germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The conductive material may further include dopants incorporated during or after deposition. An annealing step may be performed or accompanied by the deposition step.

[0057] Figure 6-13 An alternative embodiment starting with structure 200 is shown. Figure 6Structure 200 at a first intermediate manufacturing stage is shown. Structure 200 first includes a substrate 202. Generally, substrate 202 may include one or more different types of semiconductor substrate structures and materials as described above with respect to substrate 102. Structure 200 also includes a storage electrode 203 formed on substrate 202. Storage electrode 203 includes interconnects 206 in dielectric layer 204. As discussed above, dielectric layer 104 serves as an ICD layer, for example, in which interconnects are formed. In one embodiment, the ICD includes a lower portion and an upper portion. The lower portion serves as an ILD layer, and the upper portion serves as an IMD layer. The dielectric layer may be a single layer or a multilayer stack. For example, a single layer may serve as both an ILD and an IMD, or a separate layer may be used for both the ILD and the IMD. In some cases, an etch stop layer may be formed between the ILD and the IMD.

[0058] Dielectric layer 204 can be deposited in a similar manner and with the same material as dielectric layer 104 described above. Interconnect 206 is formed in the ICD layer. The interconnect can include a plurality of interconnects. In one embodiment, the interconnect includes a conductor 206a in the upper portion or IMD, and a contact 206b formed in the lower portion or ILD. Interconnect 206 includes the conductive material used for interconnect 106 as described above.

[0059] Metal pad 208 is formed on dielectric layer 204 and interconnect 206. Metal pad 208 is a high-resistance metal pad. Metal pad 208 can be deposited in a similar manner and with the same material as metal pad 108 described above. In one exemplary embodiment, metal pad 208 may have a thickness ranging from about 1 nm to about 10 nm.

[0060] A sacrificial layer 210 is formed on the metal liner 208 using conventional techniques such as CVD and ALD. Suitable materials for the sacrificial layer 210 include, for example, any amorphous material, such as amorphous silicon (a-Si) or amorphous silicon-germanium (a-SiGe). In one embodiment, the amorphous layer 210 may have a thickness ranging from about 10 nm to about 100 nm.

[0061] The hard mask 212 is formed on the sacrificial layer 210 using any conventional techniques described above for hard mask 112. The hard mask 212 can then be planarized, for example, by CMP processing. The hard mask 212 is then patterned to form a shape as described above. Figure 6 The fins are shown. The hard mask 212 is patterned as described above. As shown, the etching process stops on top of a portion of the upper surface of the dielectric layer 204 and the interconnect 206, such that the remaining portion of the sacrificial layer 210 and the metal pad 208 under the hard mask 212 forms a bridge between the two interconnects 206, for example, bridge 111 (see Figure 111). Figure 1 The photoresist used in forming the patterned hard mask 212 is typically stripped off after the etching process.

[0062] Figure 7 The structure 200 in the second intermediate stage is shown. During this stage, the hard mask 212 is first removed using conventional techniques. Next, a gate dielectric layer 214 is formed on the exposed surfaces of the dielectric layer 204, interconnect 206, metal pad 208, and sacrificial layer 210. The gate dielectric layer 214 can be deposited in a similar manner and with the same material as the gate dielectric layer 114 described above. In one embodiment, the gate dielectric layer 214 is a relatively thin layer, for example, a layer having a thickness ranging from about 1 nm to about 5 nm.

[0063] Figure 8 The structure 200 in the third intermediate stage is shown. During this stage, a metal gate pad 216 is formed on the gate dielectric layer 214. The metal gate pad 216 can be deposited in a similar manner and with the same material as the metal gate pad 116 described above. Like the metal gate pad 116, the metal gate pad 216 is configured as a resistance heater, comprising, for example, a metal or metal alloy material exhibiting resistivity and relatively high thermal conductivity. Therefore, the metal gate pad 216 can be configured to receive current to switch the phase transition layer 224 between a crystalline and amorphous state, as described below. In one embodiment, the metal gate pad 216 is a relatively thin layer, for example, a layer having a thickness ranging from about 4 nm to about 10 nm.

[0064] Next, a hard mask 218 is formed on the metal gate pad 216 using any conventional technique, such as CVD, PECVD, PVD, ALD, and other similar processes. The hard mask 218 can be deposited in a similar manner and with the same material as discussed above for the hard mask 118. The hard mask 218 can then undergo a planarization process, such as a CMP process. The hard mask 218 is then patterned and subjected to an etching process such as RIE to remove a portion of the hard mask 218, thereby exposing a portion of the metal gate pad 216. The exposed portion of the metal gate pad 216 is selectively removed along with the gate dielectric layer 214, leaving a portion of the metal gate pad 216 on the gate dielectric layer 214 beneath the bottom surface of the hard mask 218. Removal of the metal gate pad 116 can include applying an etchant in an isotropic etching process, such as a RIE process, which is selective for the dielectric layer 214. The dielectric layer 214 is then removed by applying an etchant in an isotropic etching process, such as a RIE process, making it selective for the dielectric layer 204, interconnect 206, and sacrificial layer 210.

[0065] Figure 9Structure 200 in the fourth intermediate stage is shown. It should be understood that the dashed lines in the Y-section represent supports for connecting elements 214, 216, and 220 to structure 200, as illustrated in the X-section. During this stage, gate spacer 220 is formed at least on the sidewalls of gate dielectric layer 214, metal gate pad 216, and hard mask 218. Suitable materials for gate spacer 220 include, for example, Si3N4, SiBCN, SiNC, SiN, SiCO, SiO2, and SiNOC. Gate spacer 220 can be formed by any conventional technique, such as CVD, PECVD, PVD, ALD, etc. Next, sacrificial layer 210 is selectively removed, leaving an air gap 222 defined between metal pad 208 and gate dielectric layer 214. If the sacrificial material is an a-Si compound, sacrificial layer 210 is selectively removed by, for example, hot ammonia or tetramethylammonium hydroxide (TMAH).

[0066] Figure 10 Structure 200 in the fifth intermediate stage is shown. During this stage, a phase change layer 224 comprising a phase change material is formed on the exposed surfaces of interconnect 206, dielectric layer 204, and sidewalls of gate spacer 220 using conventional techniques (e.g., CVD). Phase change layer 224 is also formed in an air gap 222 defined between metal pad 208 and gate dielectric layer 214. Phase change layer 224 can be the same phase change material as phase change layer 110 discussed above. Phase change layer 224 can then be planarized, for example, by CMP processing.

[0067] Figure 11 Structure 200 in the sixth intermediate stage is shown. During this stage, the phase change layer 224 is first recessed by, for example, RIE. A dielectric capping layer 226 is formed on the exposed surface of the phase change layer 224 and the sidewalls of the gate spacer 220 by uniform-thickness or non-selective CVD. Suitable materials for the dielectric capping layer 226 include, for example, silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiNO), or amorphous silicon nitride (SiCxNx:H). In one embodiment, the dielectric capping layer 226 has a thickness ranging from about 5 nm to about 50 nm.

[0068] Figure 12Structure 200 in the seventh intermediate stage is shown. During this stage, an organic planarization layer (OPL) 228 is deposited on the dielectric capping layer 226 using, for example, a spin coating process. OPL 228 may be a self-planarizing organic material comprising carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. In one embodiment, the self-planarizing organic material may be a polymer with sufficiently low viscosity so that the upper surface of the applied polymer forms a flat, horizontal surface. In one embodiment, OPL 228 may comprise a transparent organic polymer. In one embodiment, OPL may be a standard CxHy polymer. Non-limiting examples of OPL materials include, but are not limited to, CHM701B, commercially available from Cheil Chemical Co., HM8006 and HM8014, commercially available from JSR Corporation, and ODL-102 or ODL-401 Ltd, commercially available from ShinEtsu Chemical Co.

[0069] Then, OPL 228 is patterned and subjected to standard photolithography to remove the dielectric capping layer 226, phase change layer 224, metal pad 208, and a portion of OPL 228 to expose the dielectric layer 204 and a portion of the interconnect 206, such that the dielectric capping layer 226 and the phase change layer 224 under OPL 228 form a bridge between the two interconnects 206.

[0070] Figure 13 Structure 200 in the eighth intermediate stage is shown. During this stage, OPL 228 (not shown) is removed by OPL ash based on standard O2 or N2 / H2. Dielectric fill 230 is formed on dielectric layer 204 and interconnect 206, and on dielectric capping layer 226. The dielectric filler 120 can be deposited in a similar manner and with the same material as dielectric filler 120. Dielectric filler 220 can then undergo a planarization process, such as CMP. Next, a metal contact including a metal gate contact 232 is formed. For example, the metal gate contact 232 is an electrical connection to a gate. Conductive vias or trenches are first formed to form the metal contact 232 by methods known in the art, such as selective etching through hard mask 218 via RIE, such that the vias communicate with corresponding components, for example, the conductive vias or trenches for the metal contact 232 communicate with the corresponding metal gate pad 216. Conductive material is then deposited within the vias. The conductive material used for the metal gate contact 232 can be any conductive material discussed above for the metal gate contact 122. An annealing step may follow the deposition step or be accompanied by an annealing step.

[0071] It should be understood that the methods discussed herein for manufacturing low-resistivity metal interconnect structures (e.g., copper BEOL interconnect structures) can be incorporated into semiconductor processing techniques for manufacturing other types of semiconductor structures and integrated circuits having various analog and digital circuits or mixed-signal circuits. In particular, integrated circuit dies can be manufactured using various devices, such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. Integrated circuits according to the invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones), solid-state media storage devices, functional circuits, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, those skilled in the art will be able to conceive of other implementations and applications of the invention's technology.

[0072] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these precise embodiments, and that various other changes and modifications may be made therein by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A phase change material switch, comprising: A metal pad is disposed on at least two metal contact vias in the dielectric layer and on a portion of the dielectric layer; A phase change layer is disposed on the metal gasket; A gate dielectric layer is disposed on the dielectric layer and the phase transition layer; as well as A metal gate pad is disposed on the gate dielectric layer. The metal gasket and the phase change layer include a bridge between the at least two metal contact vias.

2. The phase change material switch according to claim 1, wherein the phase change layer comprises a phase change material.

3. The phase change material switch according to claim 2, wherein the phase change material comprises one of selenium and tellurium.

4. The phase change material switch according to claim 2, wherein the phase change material is Ge2Sb2Te5.

5. The phase change material switch according to any one of claims 1 to 4, further comprising: A hard mask disposed on the metal gate pad; One or more trenches are disposed in the hard mask and configured to expose the metal gate pads; as well as A conductive material is disposed in the one or more trenches.

6. The phase change material switch according to claim 5 further includes sidewall spacers disposed on the hard mask, the metal gate pad, and the gate dielectric layer.

7. The phase change material switch according to any one of claims 1 to 4 and 6, wherein, The metal gate pad and the gate dielectric layer are configured to be orthogonal to the phase change layer.

8. The phase change material switch according to claim 7, wherein it is in the form of a four-terminal phase change material switch.

9. A phase change material bridge device, comprising: Phase change material switch according to any one of claims 1 to 8; The electrode includes the dielectric layer and the at least two metal contact vias within the dielectric layer. The gate dielectric layer is further disposed on the metal pad and the phase change layer, as well as the at least two metal contact vias and the remainder of the dielectric layer.

10. A semiconductor structure comprising: Phase change material switch according to any one of claims 1 to 8; Semiconductor substrate; An electrode is disposed on the semiconductor substrate, wherein the electrode includes the dielectric layer and the at least two metal contact vias in the dielectric layer.

11. A method for manufacturing a semiconductor structure, comprising: A metal pad is formed on the electrode, the electrode including an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer; A phase change layer is formed on the metal pad; A first hard mask is formed on the phase transition layer; Selectively remove a portion of the phase change layer, the first hard mask, and the metal pad to expose a portion of each of the inner metal dielectric layer and the at least two metal contact vias, wherein the remaining portions of the phase change layer, the first hard mask, and the metal pad form a horizontal bridge between the at least two metal contact vias; A gate dielectric layer is formed on the outer surfaces of the metal pad, the phase change layer, and the first hard mask, as well as on the exposed portions of each of the at least two metal contact vias and the inner metal dielectric layer; and A metal gate pad is formed on the gate dielectric layer.

12. The method of claim 11, further comprising: A second hard mask is formed on the metal gate pad; The second hard mask is etched to expose a portion of the metal gate pad; as well as Remove the exposed portion of the metal gate pad to expose the gate dielectric layer.

13. The method of claim 12, further comprising: One or more metal gate contacts are formed by forming one or more trenches in the second hard mask to expose the metal gate pads; as well as A conductive material is deposited in one or more trenches.

14. The method according to any one of claims 11 to 13, wherein the phase change layer comprises Ge2Sb2Te5.

15. A method for manufacturing a semiconductor structure, comprising: A metal pad is formed on the electrode, the electrode including an inner metal dielectric layer and at least two metal contact vias in the inner metal dielectric layer; A sacrificial layer is formed on the metal gasket; A first hard mask is formed on the sacrificial layer; Selectively remove a portion of the sacrificial layer, the first hard mask, and the metal pad to expose each of the at least two metal contact vias and a portion of the internal metal dielectric layer, wherein the remaining portions of the sacrificial layer, the first hard mask, and the metal pad form a bridge between the at least two metal contact vias; Remove the first hard mask; A gate dielectric layer is formed on each of the at least two metal contact vias, the exposed portion of the inner metal dielectric layer, and the metal pad. A metal gate pad is formed on the gate dielectric layer; A second hard mask is formed on the metal gate pad; The second hard mask is etched to expose a portion of the metal gate pad; Remove the exposed portion of the metal gate pad to expose the gate dielectric layer; Remove the exposed portion of the gate dielectric layer to expose the sacrificial layer and each of the at least two metal contact vias, as well as a portion of the inner metal dielectric layer; Remove the sacrificial layer to expose the metal pad and form an air gap defined between the top surface of the metal pad and the bottom surface of the gate dielectric layer; and A phase change layer is deposited in the air gap, on each of the inner dielectric layer of the metal and the at least two metal contact vias, and on the exposed portion of the metal liner.

16. The method of claim 15, further comprising forming sidewall spacers on the sidewalls of the second hard mask and on the metal gate pad and the gate dielectric layer below the second hard mask before removing the sacrificial layer.

17. The method of claim 16, further comprising: The phase change layer on the inner dielectric layer of the metal, each of the at least two metal contact vias, and the exposed portion of the metal pad is recessed; A dielectric capping layer is formed on the recessed phase transition layer; This causes the dielectric cap layer to be recessed; An organic planarization layer is formed on the recessed dielectric cap layer; The organic planarization layer is patterned to expose each of the at least two metal contact vias and a portion of the inner metal dielectric layer; The one or more metal gate contacts are formed by forming one or more trenches in the second hard mask to expose the metal gate pads; as well as A conductive material is deposited in one or more trenches.

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