Differential interfacial layer

Abstract

Described are methods of forming a semiconductor structures. A first interfacial layer of a first gate dielectric is formed on a first semiconductor channel of a first transistor. The first interfacial layer has a first thickness. A second interfacial layer of a second gate dielectric is formed on a second semiconductor channel of a second transistor. The second interfacial layer has a second thickness that is greater than the first thickness.

Description

Attorney Docket No.: 44025427WO01 PATENTDIFFERENTIAL INTERFACIAL LAYERTECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to semiconductor devices, systems, processes, equipment, and fabrication. More particularly, embodiments relate to treatments to enhance device performance in gate structures.BACKGROUND

[0002] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.

[0003] The transistor is a key component of most integrated circuits. Since the drive current, and therefore speed, of a transistor is proportional to the gate width of the transistor, faster transistors generally require larger gate width. Thus, there is a tradeoff between transistor size and speed.

[0004] The metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage is used for amplifying or switching electronic signals.

[0005] The MOSFET is by far the most common transistor in digital circuits, as hundreds of thousands or millions of MOSFETs may be included in a memory chip or microprocessor. Since MOSFETs can be made with either p-type or n-type semiconductors, complementary pairs of MOS transistors can be used to make switching circuits with very low power consumption, in the form of complementary metal- oxide-semiconductor (CMOS) logic.

[0006] Negative-bias temperature instability (NBTI), a type of transistor aging, is a key reliability issue in MOSFETs. NBTI is an increase in the absolute threshold voltage for a p-type transistor, and, therefore, the degradation of the drain current of MOSFETs. More specifically, over time, positive charges in the transistor channel become trapped at the oxide-semiconductor boundary underneath the gate of a MOSFET. TheseAttorney Docket No.: 44025427WO01 PATENT trapped positive charges subsequently increase the gate voltage that is required to turn on the transistor channel, and, therefore, increase the threshold voltage. The problem has become more acute as transistors have shrunk due to increases in electrical field. Thus, there is a need for transistors and methods of manufacture which improve NBTLSUMMARY

[0007] One or more embodiments of the disclosure are directed to methods of forming a semiconductor structure. In one or more embodiments, the method comprises: forming a first interfacial layer of a first gate dielectric on a first semiconductor channel of a first transistor of the semiconductor device, the first interfacial layer having a first thickness; and forming a second interfacial layer of a second gate dielectric on a second semiconductor channel of a second transistor of the semiconductor device, the second interfacial layer having a second thickness greater than the first thickness.

[0008] One or more embodiments of the disclosure are directed to methods of forming a semiconductor structure. In one or more embodiments, the method comprises: forming a first interfacial layer of a first gate dielectric on a first semiconductor channel of an n-type transistor, the first interfacial layer having a first thickness; forming a second interfacial layer of a second gate dielectric on a second semiconductor channel of a p-type transistor, the second interfacial layer having a second thickness greater than the first thickness; and forming a first high-K dielectric layer on the first interfacial layer and a second high-K dielectric layer on the second interfacial layer.

[0009] Further embodiments of the disclosure are directed to semiconductor devices. In one or more embodiments, a semiconductor device comprises: a first transistor having a first semiconductor channel and a first gate dielectric layer, wherein the first gate dielectric layer comprises a first interfacial layer and a first high-k dielectric layer; and a second transistor having a second semiconductor channel and a second gate dielectric layer, wherein the second gate dielectric layer comprises a second interfacial layer and a second high-k dielectric layer, wherein the second interfacial layer is thicker than the first interfacial layer.Attorney Docket No.: 44025427WO01 PATENTBRIEF DESCRIPTION OF THE DRAWINGS

[0010] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

[0011] FIG. 1 illustrates a schematic top-view diagram of an example multi-chamber processing system according to one or more embodiments;

[0012] FIG. 2A illustrates a cross-sectional schematic of an n-type transistor and a p-type transistor according to one or more embodiments;

[0013] FIG. 2B illustrates an enlarged view of a portion of the cross-sectional schematic of the transistors depicted in FIG. 2A according to one or more embodiments;

[0014] FIG. 3 illustrates a cross-sectional schematic of portions of transistor structures being processed according to the method of one or more embodiments;

[0015] FIG. 4 illustrates a cross-sectional schematic of portions of transistor structures being processed according to the method of one or more embodiments;

[0016] FIG. 5 illustrates a cross-sectional schematic of portions of transistor structures being processed according to the method of one or more embodiments; and

[0017] FIG. 6 illustrates a cross-sectional schematic of portions of transistor structures being processed according to the method of one or more embodiments.

[0018] To facilitate understanding, identical reference numerals have been used, when possible, to designate elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0019] Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.Attorney Docket No.: 44025427WO01 PATENT

[0020] As used in this specification and the appended claims, the term "substrate" refers to a surface, or portion of a surface, upon which a process acts. It will also be understood by those skilled in the art that reference to a substrate can also refer to only a portion of the substrate unless the context clearly indicates otherwise. Additionally, reference to depositing on a substrate can mean both a bare substrate and a substrate with one or more films or features deposited or formed thereon.

[0021] A "substrate" as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft target chemical moieties to impart chemical functionality), anneal and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayer as the context indicates. Thus, for example, where a film / layer or partial film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface comprises will depend on what films are to be deposited, as well as the particular chemistry used.

[0022] As used in this specification and the appended claims, the terms "precursor", "reactant", "reactive gas", and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0023] "Epitaxy" is a process by which a deposited film is forced into a high degree of crystallographic alignment with the substrate. Epitaxial growth is broadly defined as the condensation of gas precursors to form a film on a substrate. Liquid precursors may also be used. Vapor precursors may be obtained by chemical vapor deposition (CVD)Attorney Docket No.: 44025427WO01 PATENT and laser ablation. Several epitaxy techniques are now available, such as molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0024] Transistors are circuit components or elements that are often formed on semiconductor devices. Depending upon the circuit design, in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, transistors are formed on a semiconductor device. Generally, a transistor includes a gate formed between source and drain regions. In one or more embodiments, the source and drain regions include a doped region of a substrate and exhibit a doping profile suitable for a particular application. The gate is positioned over the channel region and includes a gate dielectric interposed between a gate electrode and the channel region in the substrate.

[0025] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement mode field effect transistors generally display very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field in the device, which is generated by a voltage difference between the body and the gate of the device. The FET’s three terminals are source (S), through which the carriers enter the channel; drain (D), through which the carriers leave the channel; and gate (G), the terminal that modulates the channel conductivity. Conventionally, current entering the channel at the source (S) is designated Is and current entering the channel at the drain (D) is designated ID. Drain-to-source voltage is designated VDS. By applying voltage to gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0026] The metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, whose voltage determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage is used for amplifying or switching electronic signals. A MOSFET is based on the modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to the MOS capacitor, the MOSFET includes two additional terminals (source and drain), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they are both of the same type, and ofAttorney Docket No.: 44025427WO01 PATENT opposite type to the body region. The source and drain (unlike the body) are highly doped as signified by a "+" sign after the type of doping.

[0027] If the MOSFET is an n-channel or nMOS FET, then the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are p+ regions and the body is an n region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0028] As used herein, the term "fin field-effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate where the gate is placed on two or three sides of the channel, forming a double- or triple-gate structure. FinFET devices have been given the generic name FinFETs because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current density.

[0029] As used herein, the term "gate all-around (GAA)," is used to refer to an electronic device, e.g., a transistor, in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor may include nanowires or nano-slabs or nano-sheets, bar-shaped channels, or other suitable channel configurations known to one of skill in the art. In one or more embodiments, the channel region of a GAA device has multiple horizontal nanowires or horizontal bars vertically spaced, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0030] One example of gate-all-around (GAA) technology is complementary field effect transistor (CFET). As used herein, the term "complementary field-effect transistor (CFET)" refers to a transistor that includes NMOS FET devices and PMOS FET devices stacked on each other. Each of the NMOS FET devices and the PMOS FET devices that form the CFET are GAA transistors or hGAA transistors. CFET transistors have increased on-chip device density and reduced area consumption when compared to GAA transistors.

[0031] As used herein, the term "nanowire" refers to a nanostructure, with a diameter on the order of a nanometer (10“9meters). Nanowires can also be defined as the ratio of the length to width being greater than 1000. Alternatively, nanowires can be defined as structures having a thickness or diameter constrained to tens of nanometers or lessAttorney Docket No.: 44025427WO01 PATENT and an unconstrained length. Nanowires are used in transistors and some laser applications, and, in one or more embodiments, are made of semiconducting materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPU, GPU, MPU, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure with a thickness in a scale ranging from about 0.1 nm to about 1000 nm.

[0032] As used herein, the term "negative-bias temperature instability (NBTI)" refers to a type of transistor aging that results in an increase in the absolute threshold voltage for p-type transistors (PFETs), and a degradation of drain current of MOSFETs. One or more embodiments advantageously provide methods of forming a thick interfacial layer on a PFET device and a corresponding thin interfacial layer on an NFET device to boost the overall CMOS performance and alleviate NBTI issue of PFET.

[0033] The embodiments of the disclosure are described by way of the Figures, which illustrate devices (e.g., transistors) and processes for forming transistors in accordance with one or more embodiments of the disclosure. The processes shown are merely illustrative possible uses for the disclosed processes, and the skilled artisan will recognize that the disclosed processes are not limited to the illustrated applications.

[0034] FIG. 1 is a schematic top-view diagram of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 1 16, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers in the processing system 100 can be processed in and transferred between the various chambers without exposing the wafers to an ambient environment exterior to the processing system 100 (e.g., an atmospheric ambient environment such as may be present in a fab). In other embodiments, it is desired that the wafers be exposed to the ambient environment between processing steps, as will be detailed below.

[0035] In one or more embodiments, the wafers can be processed in and transferred between the various chambers in a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environmentAttorney Docket No.: 44025427WO01 PATENT between various processes performed on the wafers in the processing system 100. Accordingly, the processing system 100 may provide for an integrated solution for some processing of wafers. Any suitable processing system known to the skilled artisan may be used.

[0036] In the illustrated example of FIG. 1 , the factory interface 102 includes a docking station 140 and factory interface robots 142 to facilitate transfer of wafers. The docking station 140 is configured to accept one or more front opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 generally comprises a blade 148 disposed on one end of the respective factory interface robot 142 configured to transfer the wafers from the factory interface 102 to the load lock chambers 104, 106.

[0037] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 116, 118 and respective ports 162, 164 coupled to processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 166, 168 coupled to the holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to processing chambers 124, 126, 128, 130. The ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 can be, for example, slit valve openings with slit valves for passing wafers therethrough by the transfer robots 112, 114 and for providing a seal between respective chambers to prevent a gas from passing between the respective chambers. Generally, any port is open for transferring a wafer therethrough. Otherwise, the port is closed.

[0038] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically illustrated). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo-pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, a factory interface robot 142 transfers a wafer from a FOUP 144 through a port 150 or 152 to a load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108,Attorney Docket No.: 44025427WO01 PATENT110 and holding chambers 116, 118 with an interior low pressure or vacuum environment (which may include an inert gas). Hence, the pumping down of the load lock chamber 104 or 106 facilitates passing the wafer between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0039] With the wafer in the load lock chamber 104 or 106 that has been pumped down, the transfer robot 112 transfers the wafer from the load lock chamber 104 or 106 into the transfer chamber 108 through the port 154 or 156. The transfer robot 112 is then capable of transferring the wafer to and / or between any of the processing chambers 120, 122 through the respective ports 162, 164 for processing and the holding chambers 116, 118 through the respective ports 158, 160 for holding to await further transfer. Similarly, the transfer robot 114 is capable of accessing the wafer in the holding chamber 116 or 118 through the port 166 or 168 and is capable of transferring the wafer to and / or between any of the processing chambers 124, 126, 128, 130 through the respective ports 170, 172, 174, 176 for processing and the holding chambers 116, 118 through the respective ports 166, 168 for holding to await further transfer. The transfer and holding of the wafer within and among the various chambers can be in the low pressure or vacuum environment provided by the gas and pressure control system.

[0040] The processing chambers 120, 122, 124, 126, 128, 130 can be any appropriate chamber for processing a wafer. In some embodiments, the processing chamber 120 can be capable of performing an annealing process, the processing chamber 122 can be capable of performing a cleaning process, and the processing chambers 124, 126, 128, 130 can be capable of performing epitaxial growth processes. In some examples, the processing chamber 122 can be capable of performing a cleaning process, the processing chamber 120 can be capable of performing an etch process, and the processing chambers 124, 126, 128, 130 can be capable of performing respective epitaxial growth processes. The processing chamber 122 may be any suitable preclean chamber known to the skilled artisan. The processing chamber 120 may be any suitable etch chamber known to the skilled artisan.

[0041] A system controller 190 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 190 may control the operation of the processing system 100 using a directAttorney Docket No.: 44025427WO01 PATENT control of the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. In operation, the system controller 190 enables data collection and feedback from the respective chambers to coordinate performance of the processing system 100.

[0042] The system controller 190 generally includes a central processing unit (CPU) 192, memory 194, and support circuits 196. The CPU 192 may be one of any form of a general-purpose processor that can be used in an industrial setting. The memory 194, or non-transitory computer-readable medium, is accessible by the CPU 192 and may be one or more of memory such as random-access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 196 are coupled to the CPU 192 and may comprise cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be implemented under the control of the CPU 192 by the CPU 192 executing computer instruction code stored in the memory 194 (or in memory of a particular process chamber) as, for example, a software routine. When the computer instruction code is executed by the CPU 192, the CPU 192 controls the chambers to perform processes in accordance with the various methods.

[0043] Other processing systems can be in other configurations. For example, more or fewer processing chambers may be coupled to a transfer apparatus. In the illustrated example, the transfer apparatus includes the transfer chambers 108, 110 and the holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus in a processing system.

[0044] FIG. 2A is a partial cross-sectional schematic of an n-type transistor 210 and a p-type transistor 220 according to one or more embodiments. In more specific embodiments, FIG. 2A depicts gate-all-around (GAA) transistors. FIG. 2B is an enlarged view of portion A and portion B of the cross-sectional schematic of the transistors depicted in FIG. 2A. FIGS. 3 to 6 illustrate partial cross-sectional schematic views of portion A and portion B of transistor structures being processed according to the methods of one or more embodiments to form the semiconductor devices of FIGS. 2A- 2B. It should be understood that FIGS. 2B to 6 illustrate only partial schematic views ofAttorney Docket No.: 44025427WO01 PATENT the semiconductor structures, e.g., transistors, and the semiconductor structures may contain any number of transistor sections and additional materials having aspects as illustrated in the figures. It should also be noted that although the method steps illustrated in FIGS. 3 to 6 are described sequentially, other process sequences that include one or more method steps that have been omitted and / or added, and / or has been rearranged in another desirable order, fall within the scope of the embodiments of the disclosure provided herein.

[0045] Referring to FIGS. 2A and 2B, in one or more embodiments, an n-type transistor 210 and a p-type transistor 220 are formed, for example gate-all-around transistors. In one or more embodiments, a first semiconductor channel 202 is provided for the n-type transistor 210, and a second semiconductor channel 212 is provided for the p-type transistor 220. As used in this specification and the appended claims, the term "provided" means that the semiconductor channel 202,212 is made available for processing (e.g., positioned in a processing chamber).

[0046] In one or more embodiments, the semiconductor channel 202, 212 can be any suitable material known to the skilled artisan. As used in this specification and the appended claims, the term "semiconductor channel" or "channel" refers to a layer of electron-rich material in a transistor, e.g., a metal-oxide semiconductor, or a gate-all- around (GAA), or a CFET, that allows current to flow between the source and drain terminals.

[0047] In one or more embodiments, the semiconductor channel 202, 212 comprises silicon (Si).

[0048] With reference to FIGS. 2A and 2B, in one or more embodiments, a first gate dielectric 205 is formed on the first transistor 210 and a second gate dielectric 215 is formed on the second transistor 220. In some embodiments, the first gate dielectric 205 includes a first interfacial layer 204 surrounding a first semiconductor channel 202, and a first high-K dielectric layer 206 surrounding the first interfacial layer 204. In some embodiments, the second gate dielectric 215 includes a second interfacial layer 214 surrounding a second semiconductor channel 212, and a second high-K dielectric layer 216 surrounding the second interfacial layer 214. As used herein, the term "surrounding" means that a layer envelops another layer. When used in reference to the cross-section view presented in FIGS. 2A through 6, a first layer is said to surroundAttorney Docket No.: 44025427WO01 PATENT a second layer when the first layer forms on the top surface, the bottom surface, and on the sidewall surfaces of the second layer. As recognized by one of skill in the art, transistors are three-dimensional structures. Thus, while the figures depict a first layer surrounding a second layer, e.g., semiconductor channel 202 is surrounded by interfacial layer 204, one of skill in the art understands that a different cross-section may illustrate a portion of the second layer not completely enveloped by the first layer.

[0049] Referring to FIGS. 2A and 2B, an interface formation process, as depicted in FIGS. 3 to 6, is performed to form an interfacial layer 204 on the surface of the semiconductor channel 202 of the n-type transistor 210, and to form an interfacial layer 214 on the surface of the semiconductor channel 212 of the p-type transistor 220. The interface formation process is described below with respect to FIGS. 3 to 6.

[0050] In one or more embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 is a thin amorphous silicon oxide (SiO2) layer, having a thickness in a range of from greater than about 0 A to about 7 A, or in a range of from greater than 0 A to less than about 5 A.

[0051] In one or more embodiments, the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 is an amorphous silicon oxide (SiO2) layer, having a thickness in a range of from greater than about 5 A to about 10 A, or in a range of from about 7 A to less than about 8 A.

[0052] In one or more embodiments, the thickness of the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 is greater than (thicker than) the thickness of the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210. Without intending to be bound by theory, it is thought that a thicker interfacial layer on the p-type transistor 220 and a corresponding thinner interfacial layer 204 formed on the n-type transistor 210 advantageously improves the performance of the n-type transistor 210 and alleviates the NBTI of the p-type transistor 220.

[0053] Referring to FIGS. 2A and 2B, in one or more embodiments, a high-K dielectric layer 206 is formed on the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210. The high-K dielectric layer 206 may be formed of high-K dielectric material, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), ytterbium oxide (Y2O3), or aluminum oxide (AI2O3).Attorney Docket No.: 44025427WO01 PATENT

[0054] In one or more embodiments, a high-K dielectric layer 216 is formed on the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p- type transistor 220. The high-K dielectric layer 216 may be formed of high-K dielectric material, such as hafnium dioxide (HfC ), zirconium dioxide (ZrC ), ytterbium oxide (Y2O3), or aluminum oxide (AI2O3).

[0055] Still referring to FIGS. 2A and 2B, in one or more embodiments an n-type metal gate 208 is then formed on the high-K dielectric layer 206 on the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210.

[0056] In one or more embodiments a p-type metal gate 218 is then formed on the high-K dielectric layer 216 on the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220.

[0057] With reference to FIG. 3, a thin interfacial layer 204 is formed on the n-type transistor 210 and a thicker interfacial layer 214 is formed on the p-type transistor 220 according to a sequential process flow 230. The method 230 may include one or more operations prior to the initiation of the stated method operations, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method 230 may include a number of optional operations, which may or may not specifically be associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation process, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below.

[0058] As illustrated in FIG. 3, the semiconductor structure may represent a device after certain processing has been completed. For example, semiconductor channel 202,212 may be a planar material, or may be a structured device, which may include one or more materials configured as or defining posts, trenches, or other structures as would be understood are similarly encompassed by the present technology. Semiconductor channel 202,212 may include any number of materials including silicon or silicon-containing materials such as oxides, nitrides, and carbides of silicon, as well as any other materials that may be incorporated within a structure.Attorney Docket No.: 44025427WO01 PATENT

[0059] One or more material layers may be formed over some or all of semiconductor channel 202,212, as well as formed at least partially within the substrate, to produce a structure that may be a planarized or structured material in embodiments. As non-limiting examples, semiconductor channel 202,212 may be or include silicon, or may include a surface amount of silicon formed over an additional material, such as silicon oxide, and which may be a reduced portion of the silicon oxide leaving a silicon exposed surface. Semiconductor channel 202,212 may include a native oxide. The exposed material at a surface of semiconductor channel 202,212 may be etched, planarized, or otherwise processed to produce an intermittent pattern in some embodiments. Although illustrated as a single instance, it is to be understood that device may include a small section of a larger process integration that may include any number of additional sections that may be similar or different to the objects shown. Semiconductor channel 202,212 may be housed or positioned in a processing region of a semiconductor processing chamber, and method 230 may be performed to produce a semiconductor material on the substrate, such as a high-k dielectric material.

[0060] In one or more embodiments, a semiconductor channel 202 is provided for the n-type transistor 210, and a semiconductor channel 212 is provided for the p-type transistor 220. As used in this specification and the appended claims, the term "provided" means that the semiconductor channel 202,212 is made available for processing (e.g., positioned in a processing chamber).

[0061] In one or more embodiments, the method 230 may optionally include delivering a pre-treatment precursor to the substrate. The pre-treatment precursor may be or include a nitrogen-containing precursor or an oxygen-containing precursor. The precursor may contact the substrate and may form or introduce reactive ligands on an exposed surface of the substrate. Unlike conventional technologies, the present technology may utilize a pre-treatment configured to produce an orderly growth of high- k dielectric material in subsequent operations.

[0062] In one or more embodiments, the substrate may be or include an exposed surface of silicon. The semiconductor channel 202,212 may itself be silicon, or may be some other silicon-containing material that is reduced or modified to exhibit a silicon surface. As one non-limiting example, where semiconductor channel 202,212 may include silicon oxide, an initial pre-treatment may include removing oxygen from aAttorney Docket No.: 44025427WO01 PATENT surface of the structure, such as with a hydrogen-containing precursor, for example. A thin, surface layer of silicon may then be exposed. Without intending to be bound by theory, silicon may provide improved base characteristics for receiving nitrogencontaining precursors relative to silicon oxide in some embodiments. This may afford a superior formation of certain high-k dielectric materials.

[0063] The pre-treatment precursor may be or include any nitrogen-containing or oxygen-containing precursor. Oxygen-containing precursors may be characterized by a hydroxyl group [-OH], which may be incorporated on the surface of semiconductor channel 202,212. Nitrogen-containing precursors may be characterized by an amine group [-NH2], or other nitrogen-containing group. For example, nitrogen-containing precursors may be or include nitrogen-and-hydrogen-containing precursors, such as ammonia as one non-limiting example, or nitrogen-and-oxygen-containing precursors, or any other precursor including nitrogen.

[0064] The surface terminations in some embodiments may be or include a hydroxyl group or an amine-group-terminated surface. The methods of one or more embodiments may then include forming a high-k dielectric material overlying the substrate. The present technology may encompass any formation or deposition of the high-k material, although in some embodiments, formation may be or include an atomic layer deposition, or any other atomic layer deposition chamber. The formation may be performed directly after pretreating the substrate surface and may be performed in the same chamber as the pre-treatment or in an additional chamber, such as an additional chamber incorporated on the same system, such as system 100. In some embodiments, vacuum conditions may be maintained while the substrate is transferred from the pretreatment chamber to the deposition or formation chamber, which may limit exposure of the substrate to air.

[0065] At operation 230A, a mask layer 203 is formed on a top surface of the semiconductor channel 202 of the n-type transistor 210, while the top surface of the semiconductor channel 212 of the p-type transistor 220 is left unmasked and exposed. The mask layer 203 may comprise any suitable hard mask material known to the skilled artisan. In one or more embodiments, the mask layer 203 comprises, for example, one or more of titanium nitride (TiN), aluminum nitride (AIN), and the like. In one or moreAttorney Docket No.: 44025427WO01 PATENT embodiments, the mask layer 203 may have any suitable thickness. In one or more embodiments, the mask layer 203 has a thickness in a range of from 50 nm to 200 nm.

[0066] In one or more embodiments, the exposed surface of the semiconductor channel 212 of the p-type transistor is subjected to an optional pre-clean process to preclean the surface. In one or more embodiments, pre-cleaning the semiconductor channel 212 may comprise removing a native oxide from the semiconductor channel 212. The removing of native oxide may be or include flowing a fluorine-containing precursor and a hydrogen-containing precursor. Fluorine-containing precursors may be or include nitrogen trifluoride as well as any other fluorine-containing precursor. Hydrogen-containing precursors may be characterized by an amine group (-NH2), or other nitrogen-containing or hydrogen-containing group. For example, hydrogencontaining precursors may be or include nitrogen-and-hydrogen-containing precursors, such as ammonia as one non-limiting example. The flowing may include flowing the fluorine-containing precursor and the hydrogen-containing precursor into a remote plasma region. The remote plasma region may be fluidly coupled to the substrate processing region. A plasma may be formed to produce plasma effluents. A flow-rate of the fluorine-containing precursor and a flow rate of the hydrogen-containing precursor may be characterized by a hydrogen-to-fluorine atomic flow ratio of less than 1 :2. The native oxide may be removed by flowing the plasma effluents into the substrate processing region while forming solid by-products on the surface of the substrate. Without being bound to any particular theory, the flow may leave of a layer of fluorine on the substrate surface that promotes interface formation at operation 230A with the fluorine termination serving to enhance reliability. The solid by-products are sublimated by increasing the temperature of the substrate above a sublimation temperature of the solid by-products. After sublimation, the semiconductor channel 212 is free or substantially free of native oxide.

[0067] With reference to FIG. 3, in one or more embodiments, method 230 may include delivering an oxidizing atmosphere and thermally annealing the surface of semiconductor channel 212 to form an oxide-containing interface in operation 230B. In one or more embodiments, an interfacial layer 214 is formed on the exposed surface of the semiconductor channel 212 of the p-type transistor 220. In some embodiments, the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-Attorney Docket No.: 44025427WO01 PATENT type transistor 220 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas.

[0068] In one or more embodiments, the oxidizing atmosphere of operation 230B comprises one or more of nitrous oxide, oxygen, or radical oxygen containing chemistries. The oxidizing atmosphere, e.g., nitrous oxide, delivered to the semiconductor channel 212 as in FIG. 3 may help to control how much of the semiconductor channel 212, having a surface free of native oxide, may be oxidized to form the oxide-containing interface 214 as in FIG. 3. Operation 230B may include a thermal based reaction using steam, such as an in situ steam generation (ISSG) process whereby oxidation takes place at a lower rate as compared with conventional thermal techniques utilizing hydrogen and / or oxygen. The oxidizing atmosphere, e.g., specifically, the nitrogen of the nitrous oxide, may serve as a carrier for oxygen and may not become part of the interface or substrate. The oxide-containing interface formed may be high quality and highly ordered, meaning a crystallographic structure free of or substantially free of defects. The resultant oxide-containing interfacial layer 214 may include silicon oxide (SiOx).

[0069] In one or more embodiments, the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor has a thickness in a range of from greater than 5 A to about 10 A, or in a range of from 7 A to less than 8 A.

[0070] In one or more embodiments, the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may act as a nucleation layer of a high-K dielectric material layer to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 212 and the high-K dielectric material layer 216. The interface formation process may be performed in a processing chamber, such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG 1 .

[0071] In some embodiments, the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gases. The interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may act as a nucleation layerAttorney Docket No.: 44025427WO01 PATENT of a high-K dielectric material layer 216 to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 212 and the high-K dielectric material layer 216. The interface formation process may be performed in a processing chamber, such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG 1 .

[0072] Still referring to FIG. 3, at operation 230C, in one or more embodiments, the mask layer 203 is then removed from the surface of the semiconductor channel 202 of the n-transistor210. The mask layer 203 may be removed by any suitable means known to the skilled artisan, including, but not limited to etching and planarization. In one or more embodiments, a second mask layer 215 is formed on the surface of the interfacial layer 214 on the semiconductor channel 212 of the p-type transistor 220. In one or more embodiments, the second mask layer 215 comprises, for example, one or more of titanium nitride (TiN), aluminum nitride (AIN), and the like. In one or more embodiments, the second mask layer 215 may have any suitable thickness. In one or more embodiments, the second mask layer 215 has a thickness in a range of from 50 nm to 200 nm.

[0073] In one or more embodiments, the exposed surface of the semiconductor channel 202 of the n-type transistor 210 is subjected to an optional pre-clean process to pre-clean the surface. In one or more embodiments, pre-cleaning the semiconductor channel 202 may comprise removing a native oxide from the semiconductor channel 202. The removing of native oxide may be or include flowing a fluorine-containing precursor and a hydrogen-containing precursor. Fluorine-containing precursors may be or include nitrogen trifluoride as well as any other fluorine-containing precursor. Hydrogen-containing precursors may be characterized by an amine group (-NH2), or other nitrogen-containing or hydrogen-containing group. For example, hydrogencontaining precursors may be or include nitrogen-and-hydrogen-containing precursors, such as ammonia as one non-limiting example. The flowing may include flowing the fluorine-containing precursor and the hydrogen-containing precursor into a remote plasma region. The remote plasma region may be fluidly coupled to the substrate processing region. A plasma may be formed to produce plasma effluents. A flow-rate of the fluorine-containing precursor and a flow rate of the hydrogen-containing precursorAttorney Docket No.: 44025427WO01 PATENT may be characterized by a hydrogen-to-fluorine atomic flow ratio of less than 1 :2. The native oxide may be removed by flowing the plasma effluents into the substrate processing region while forming solid by-products on the surface of the substrate. Without being bound to any particular theory, the flow may leave of a layer of fluorine on the substrate surface that promotes interface formation at operation 230D with the fluorine termination serving to enhance reliability. The solid by-products are sublimated by increasing the temperature of the substrate above a sublimation temperature of the solid by-products. After sublimation, the semiconductor channel 202 of the n-type transistor 210 is free or substantially free of native oxide.

[0074] With reference to FIG. 3, in one or more embodiments, method 230 may include delivering an oxidizing atmosphere and thermally annealing the substrate surface 202 to form an oxide-containing interface in operation 230D. In one or more embodiments, an interfacial layer 204 is formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210. In some embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n- type transistor 210 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas.

[0075] In one or more embodiments, the oxidizing atmosphere of operation 230D comprises one or more of nitrous oxide, oxygen, or radical oxygen containing chemistries. The oxidizing atmosphere, e.g., nitrous oxide, delivered to the semiconductor channel 202 as in FIG. 3 may help to control how much of the semiconductor channel 202, having a surface free of native oxide, may be oxidized to form the oxide-containing interface 204 as in FIG. 3. Operation 230B may include a thermal based reaction using steam, such as an in situ steam generation (ISSG) process or an enhanced in-situ steam generation (elSSG) process whereby oxidation takes place at a lower rate as compared with conventional thermal techniques utilizing hydrogen and / or oxygen. The oxidizing atmosphere, e.g., specifically, the nitrogen of the nitrous oxide, may serve as a carrier for oxygen and may not become part of the interface or substrate. The oxide-containing interface formed may be high quality and highly ordered, meaning a crystallographic structure free of or substantially free of defects. The resultant oxide-containing interfacial layer 204 may include silicon oxide (SiOx).Attorney Docket No.: 44025427WO01 PATENT

[0076] In one or more embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 is, e.g., a thin amorphous silicon oxide (SiC ) layer, having a thickness in a range of from greater than 0 A to about 7 A, or in a range of from greater than 0 A to less than about 5 A.

[0077] In one or more embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 may act as a nucleation layer of a high-K dielectric material layer to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 202 and the high-K dielectric material layer 206. The interface formation process may be performed in a processing chamber, such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG 1 .

[0078] In some embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas. The interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 may act as a nucleation layer of a high-K dielectric material layer 206 to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 202 and the high-K dielectric material layer 206. The interface formation process may be performed in a processing chamber, such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG 1 .

[0079] After the formation of the interfacial layer 204 on the surface of the channel 202 of the n-type transistor 210, in one or more embodiments, the second mask layer 215 is removed from the interfacial layer 214 on the semiconductor channel 212 of the p-type transistor. The second mask layer 215 may be removed by any suitable means known to the skilled artisan, including, but not limited to etching and planarization.

[0080] In one or more embodiments, as illustrated in FIG. 3, a device is advantageously provided that has a thicker interfacial layer on the p-type transistor 220 and a corresponding thinner interfacial layer 204 formed on the n-type transistor 210,Attorney Docket No.: 44025427WO01 PATENT improving the performance of the n-type transistor 210 and alleviating the NBTI of the p-type transistor 220.

[0081] With reference to FIG. 4, a thin interfacial layer 204 is formed on the n-type transistor 210 and a thicker interfacial layer 214 is formed on the p-type transistor 220 according to an additive process flow 240. Th method 240 may include one or more operations prior to the initiation of the stated method operations, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method 240 may include a number of optional operations, which may or may not specifically be associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation process, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below.

[0082] As illustrated in FIG. 4, the semiconductor structure may represent a device after certain processing has been completed. For example, semiconductor channel 202,212 may be a planar material, or may be a structured device, which may include one or more materials configured as or defining posts, trenches, or other structures as would be understood are similarly encompassed by the present technology. Semiconductor channel 202,212 may include any number of materials including silicon or silicon-containing materials such as oxides, nitrides, and carbides of silicon, as well as any other materials that may be incorporated within a structure.

[0083] One or more material layers may be formed over some or all of semiconductor channel 202,212, as well as formed at least partially within the substrate, to produce a structure that may be a planarized or structured material in embodiments. As non-limiting examples, semiconductor channel 202,212 may be or include silicon, or may include a surface amount of silicon formed over an additional material, such as silicon oxide, and which may be a reduced portion of the silicon oxide leaving a silicon exposed surface. Semiconductor channel 202,212 may include a native oxide. The exposed material at a surface of semiconductor channel 202,212 may be etched, planarized, or otherwise processed to produce an intermittent pattern in some embodiments. Although illustrated as a single instance, it is to be understood that device may include a small section of a larger process integration that may include any numberAttorney Docket No.: 44025427WO01 PATENT of additional sections that may be similar or different to the objects shown. Semiconductor channel 202,212 may be housed or positioned in a processing region of a semiconductor processing chamber, and method 240 may be performed to produce a semiconductor material on the substrate, such as a high-k dielectric material.

[0084] In one or more embodiments, a semiconductor channel 202 is provided for the n-type transistor 210, and a semiconductor channel 212 is provided for the p-type transistor 220. As used in this specification and the appended claims, the term "provided" means that the semiconductor channel 202,212 is made available for processing (e.g., positioned in a processing chamber).

[0085] At operation 240A, a mask layer 203 is formed on a top surface of the semiconductor channel 202 of the n-type transistor 210, while the top surface of the semiconductor channel 212 of the p-type transistor 220 is left unmasked and exposed. The mask layer 203 may comprise any suitable hard mask material known to the skilled artisan. In one or more embodiments, the mask layer 203 comprises, for example, one or more of titanium nitride (TiN), aluminum nitride (AIN), and the like. In one or more embodiments, the mask layer 203 may have any suitable thickness. In one or more embodiments, the mask layer 203 has a thickness in a range of from 50 nm to 200 nm.

[0086] In one or more embodiments, the exposed surface of the semiconductor channel 212 of the p-type transistor 220 is subjected to an optional pre-clean process to pre-clean the surface. In one or more embodiments, pre-cleaning the semiconductor channel 212 may comprise removing a native oxide from the semiconductor channel 212. The removing of native oxide may be or include flowing a fluorine-containing precursor and a hydrogen-containing precursor. Fluorine-containing precursors may be or include nitrogen trifluoride as well as any other fluorine-containing precursor. Hydrogen-containing precursors may be characterized by an amine group (-NH2), or other nitrogen-containing or hydrogen-containing group. For example, hydrogencontaining precursors may be or include nitrogen-and-hydrogen-containing precursors, such as ammonia as one non-limiting example. The flowing may include flowing the fluorine-containing precursor and the hydrogen-containing precursor into a remote plasma region. The remote plasma region may be fluidly coupled to the substrate processing region. A plasma may be formed to produce plasma effluents. A flow-rate of the fluorine-containing precursor and a flow rate of the hydrogen-containing precursorAttorney Docket No.: 44025427WO01 PATENT may be characterized by a hydrogen-to-fluorine atomic flow ratio of less than 1 :2. The native oxide may be removed by flowing the plasma effluents into the substrate processing region while forming solid by-products on the surface of the substrate. Without being bound to any particular theory, the flow may leave of a layer of fluorine on the substrate surface that promotes interface formation at operation 240A with the fluorine termination serving to enhance reliability. The solid by-products are sublimated by increasing the temperature of the substrate above a sublimation temperature of the solid by-products. After sublimation, the semiconductor channel 212 is free or substantially free of native oxide.

[0087] With reference to FIG. 4, in one or more embodiments, method 240 may include delivering an oxidizing atmosphere and thermally annealing the surface of the semiconductor channel 212 to form an oxide-containing interface in operation 240B. In one or more embodiments, a thin interfacial layer 222 is formed on the exposed surface of the semiconductor channel 212 of the p-type transistor 220. In some embodiments, the thin interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas.

[0088] In one or more embodiments, the oxidizing atmosphere of operation 240B comprises one or more of nitrous oxide, oxygen, or radical oxygen containing chemistries. The oxidizing atmosphere, e.g., nitrous oxide, delivered to the semiconductor channel 212 as in FIG. 4 may help to control how much of the semiconductor channel 212, having a surface free of native oxide, may be oxidized to form the oxide-containing interface 222 as in FIG. 4. Operation 240B may include a thermal based reaction using steam, such as an in situ steam generation (ISSG) process whereby oxidation takes place at a lower rate as compared with conventional thermal techniques utilizing hydrogen and / or oxygen. The oxidizing atmosphere, e.g., specifically, the nitrogen of the nitrous oxide, may serve as a carrier for oxygen and may not become part of the interface or substrate. The oxide-containing interface formed may be high quality and highly ordered, meaning a crystallographic structure free of or substantially free of defects. The resultant oxide-containing interfacial layer 222 may include silicon oxide (SiOx).Attorney Docket No.: 44025427WO01 PATENT

[0089] In one or more embodiments, the interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p-type transistor has a thickness in a range of from greater than about 0 A to about 7 A, or in a range of from greater than 0 A to less than about 5 A.

[0090] In one or more embodiments, the interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may act as a nucleation layer of a high-K dielectric material layer 216 to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 212 and the high-K dielectric material layer 216.

[0091] In some embodiments, the interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas. The interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may act as a nucleation layer of a high-K dielectric material layer 216 to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 212 and the high-K dielectric material layer 216. The interface formation process may be performed in a processing chamber, such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG 1 .

[0092] Still referring to FIG. 4, at operation 240C, in one or more embodiments, the mask layer 203 is then removed from the surface of the semiconductor channel 202 of the n-transistor210. The mask layer 203 may be removed by any suitable means known to the skilled artisan, including, but not limited to etching and planarization.

[0093] With reference to FIG. 4, in one or more embodiments, at operation 240D a re-oxidation process is performed to thermally oxidize the semiconductor channel 202 of the n-type transistor 210. The reoxidation process may include a thermal anneal process in an oxygen (O2), nitrous oxide (N2O), and H2 ambient, performed in a rapid thermal processing (RTP) chamber. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The re-oxidation process in operation 240D may thermally oxidize the underlying layer semiconductor channelAttorney Docket No.: 44025427WO01 PATENT202 and the interfacial layer 222 on the substrate 214, and thus thicken the interfacial layer 222 to a thickness in a range of from greater than about 5 A to about 10 A, or in a range of from about 7 A to less than about 8 A, and form an interfacial layer 214 on the semiconductor channel 212 of the p-type transistor near the interface with the high-K dielectric layer 216. The re-oxidation process may be performed for between about 1 second and about 30 seconds, at a temperature of between about 400 °C and about 900 °C, and at a pressure of between about 0.01 Torr and 100 Torr.

[0094] In one or more embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 is, e.g., a thin amorphous silicon oxide (SiC ) layer, having a thickness in a range of from greater than 0 A to about 7 A, or in a range of from greater than 0 A to less than about 5 A.

[0095] In one or more embodiments, the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 is an amorphous silicon oxide (SiO2) layer, having a thickness in a range of from greater than about 5 A to about 10 A, or in a range of from about 7 A to less than about 8 A. It is noted that the interfacial layer 214 increases in thickness from the interfacial layer 222 formed in operation 240B.

[0096] In one or more embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 and the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may act as a nucleation layer of a high-K dielectric material layer to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 202,212 and the high-K dielectric material layer 206,216. The interface formation process may be performed in a processing chamber, such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG 1.

[0097] In some embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 and the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas. The interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 and the interfacial layer 214 formed on the surface of the semiconductor channel 212Attorney Docket No.: 44025427WO01 PATENT of the p-type transistor 220 may act as a nucleation layer of a high-K dielectric material layer 206,216 to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 202,212 and the high-K dielectric material layer 206,216. The interface formation process may be performed in a processing chamber, such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG 1.

[0098] In one or more embodiments, as illustrated in FIG. 4, a device is advantageously provided that has a thicker interfacial layer on the p-type transistor 220 and a corresponding thinner interfacial layer 204 formed on the n-type transistor 210, improving the performance of the n-type transistor 210 and alleviating the NBTI of the p-type transistor 220.

[0099] With reference to FIG. 5, a thin interfacial layer 204 is formed on the n-type transistor 210 and a thicker interfacial layer 214 is formed on the p-type transistor 220 according to an additive process flow 250. Th method 250 may include one or more operations prior to the initiation of the stated method operations, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method 250 may include a number of optional operations, which may or may not specifically be associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation process, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below.

[0100] As illustrated in FIG. 5, the semiconductor structure may represent a device after certain processing has been completed. For example, semiconductor channel 202,212 may be a planar material, or may be a structured device, which may include one or more materials configured as or defining posts, trenches, or other structures as would be understood are similarly encompassed by the present technology. Semiconductor channel 202,212 may include any number of materials including silicon or silicon-containing materials such as oxides, nitrides, and carbides of silicon, as well as any other materials that may be incorporated within a structure.Attorney Docket No.: 44025427WO01 PATENT

[0101] One or more material layers may be formed over some or all of semiconductor channel 202,212, as well as formed at least partially within the substrate, to produce a structure that may be a planarized or structured material in embodiments. As non-limiting examples, semiconductor channel 202,212 may be or include silicon, or may include a surface amount of silicon formed over an additional material, such as silicon oxide, and which may be a reduced portion of the silicon oxide leaving a silicon exposed surface. Semiconductor channel 202,212 may include a native oxide. The exposed material at a surface of semiconductor channel 202,212 may be etched, planarized, or otherwise processed to produce an intermittent pattern in some embodiments. Although illustrated as a single instance, it is to be understood that device may include a small section of a larger process integration that may include any number of additional sections that may be similar or different to the objects shown. Semiconductor channel 202,212 may be housed or positioned in a processing region of a semiconductor processing chamber, and method 250 may be performed to produce a semiconductor material on the substrate, such as a high-k dielectric material.

[0102] In one or more embodiments, a semiconductor channel 202 is provided for the n-type transistor 210, and a semiconductor channel 212 is provided for the p-type transistor 220. As used in this specification and the appended claims, the term "provided" means that the semiconductor channel 202,212 is made available for processing (e.g., positioned in a processing chamber).

[0103] At operation 250A, in one or more embodiments, the exposed surface of the semiconductor channel 202 of the n-type transistor and the exposed surface of the semiconductor channel 212 of the p-type transistor 220 are subjected to an optional pre-clean process to pre-clean the surface. In one or more embodiments, pre-cleaning the semiconductor channel 202,212 may comprise removing a native oxide from the semiconductor channel 202,212. The removing of native oxide may be or include flowing a fluorine-containing precursor and a hydrogen-containing precursor. Fluorine- containing precursors may be or include nitrogen trifluoride as well as any other fluorine- containing precursor. Hydrogen-containing precursors may be characterized by an amine group (-NH2), or other nitrogen-containing or hydrogen-containing group. For example, hydrogen-containing precursors may be or include nitrogen-and-hydrogen- containing precursors, such as ammonia as one non-limiting example. The flowing mayAttorney Docket No.: 44025427WO01 PATENT include flowing the fluorine-containing precursor and the hydrogen-containing precursor into a remote plasma region. The remote plasma region may be fluidly coupled to the substrate processing region. A plasma may be formed to produce plasma effluents. A flow-rate of the fluorine-containing precursor and a flow rate of the hydrogen-containing precursor may be characterized by a hydrogen-to-fluorine atomic flow ratio of less than 1 :2. The native oxide may be removed by flowing the plasma effluents into the substrate processing region while forming solid by-products on the surface of the substrate. Without being bound to any particular theory, the flow may leave of a layer of fluorine on the substrate surface that promotes interface formation at operation 250A with the fluorine termination serving to enhance reliability. The solid by-products are sublimated by increasing the temperature of the substrate above a sublimation temperature of the solid by-products. After sublimation, the semiconductor channel 202,212 is free or substantially free of native oxide.

[0104] With reference to FIG. 5, in one or more embodiments, method 250 may include delivering an oxidizing atmosphere and thermally annealing the surface of the semiconductor channel 202,212 to form an oxide-containing interface in operation 250A. In one or more embodiments, a thin interfacial layer 204 is formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and a thin interfacial layer 222 is formed on the exposed surface of the semiconductor channel 212 of the p-type transistor 220. In some embodiments, the thin interfacial layer 204 is formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and the thin interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas.

[0105] In one or more embodiments, the oxidizing atmosphere of operation 250A comprises one or more of nitrous oxide, oxygen, or radical oxygen containing chemistries. The oxidizing atmosphere, e.g., nitrous oxide, delivered to the semiconductor channel 202,212 as in FIG. 5 may help to control how much of the semiconductor channel 202,212, having a surface free of native oxide, may be oxidized to form the oxide-containing interface 204,222 as in FIG. 5. Operation 250A may include a thermal based reaction using steam, such as an in situ steam generation (ISSG)Attorney Docket No.: 44025427WO01 PATENT process whereby oxidation takes place at a lower rate as compared with conventional thermal techniques utilizing hydrogen and / or oxygen. The oxidizing atmosphere, e.g., specifically, the nitrogen of the nitrous oxide, may serve as a carrier for oxygen and may not become part of the interface or substrate. The oxide-containing interface formed may be high quality and highly ordered, meaning a crystallographic structure free of or substantially free of defects. The resultant oxide-containing interfacial layer 204,222 may include silicon oxide (SiOx).

[0106] In one or more embodiments, the thin interfacial layer 204 formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and the thin interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p-type transistor have a thickness in a range of from greater than about 0 A to about 7 A, or in a range of from greater than 0 A to less than about 5 A.

[0107] In one or more embodiments, the thin interfacial layer 204 formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and the interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p- type transistor 220 may act as a nucleation layer of a high-K dielectric material layer 206, 216 to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 202,212 and the high-K dielectric material layer 206,216.

[0108] In some embodiments, the thin interfacial layer 204 formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and the thin interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p- type transistor 220 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas. The thin interfacial layer 204 formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and the interfacial layer 222 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may act as a nucleation layer of a high-K dielectric material layer 206,216 to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 202,212 and the high-K dielectric material layer 206,216. The interfaceAttorney Docket No.: 44025427WO01 PATENT formation process may be performed in a processing chamber, such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG 1.

[0109] In one or more embodiments, the method 250 may then include forming a high-k dielectric material overlying the semiconductor channel 202,212 at operation 250B. The present technology may encompass any formation or deposition of the high- k material, although in some embodiments, formation operation 250B may be or include an atomic layer deposition, or any other atomic layer deposition chamber. The formation may be performed directly after forming the interfacial layer 204, 222 and may be performed in the same chamber as the interfacial layer formation or in an additional chamber, such as an additional chamber incorporated on the same system, such as system 100. In some embodiments, vacuum conditions may be maintained while the substrate is transferred from the interface formation chamber to the deposition chamber, which may limit exposure of the substrate to air.

[0110] Where an atomic layer deposition process is performed to form the high-k dielectric material 206,216, a metal-containing precursor may be delivered to the substrate to react with the pretreated surface. For example, a transition-metal- containing precursor, a poor-metal-containing precursor, or a lanthanide-metal- containing precursor may be delivered to the processing chamber to interact with the reactive ligands exposed on the substrate from the pre-treatment. An oxygen-containing precursor may then be delivered in a second operation, such as subsequent a purge of the metal-containing precursor. The metal containing precursor may be any suitable metal-containing precursor known to the skilled artisan. In one or more embodiments, the metal-containing precursor comprises a metal halide. In some embodiments, high- K dielectric layer comprises a metal selected from one or more of hafnium (Hf), zirconium (Zr), silicon (Si), lanthanum (La), aluminum (Al), titanium (Ti), and strontium (Sr). This may produce an oxide layer by atomic layer deposition, such as high-k layer 206,216 as illustrated in FIG. 5. In one non-limiting example, a hafnium-containing precursor may be delivered in a first operation and an oxidant may be delivered in a second operation for producing a hafnium oxide (HfOx) film. Additional metal-containing precursors may include zirconium-containing precursors for producing zirconium- containing materials, as well as any other number of metal-containing precursors for producing additional metal oxide structures. For hafnium-containing precursors, andAttorney Docket No.: 44025427WO01 PATENT similarly for any alternative metals, the precursors may be or include halogen-containing precursors, oxygen-containing precursors, hydrogen-containing precursors, or carbon- containing precursors in any of which hafnium is incorporated.

[0111] For the oxidant, any oxygen-containing precursor may be used that may react with the metal-containing materials. For example, the oxygen-containing precursor may be or include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, nitrogen-and oxygen-containing precursors, plasma-enhanced oxygen including locally or remotely enhanced oxygen, or any other material including oxygen that may be incorporated with the metal, such as hafnium, to produce a metal oxide material layer overlying the substrate. Again, any of the metal-containing materials noted above may be used in embodiments of the present technology, and may include any of the grouped metals, which may include, and may not be limited to, hafnium, zirconium, silicon, lanthanum, aluminum, titanium, strontium, or combinations of these materials, such as, for example, hafnium silicate.

[0112] In one or more embodiments, the high-k dielectric material layer 206,216 formed has a thickness in a range of from 3 A to 50 A.

[0113] Still referring to FIG. 5, in one or more embodiments, a mask layer 207 is formed on a top surface of the high-k layer 216 on the interfacial layer 224 on the semiconductor channel 212 of the p-type transistor 220, while the top surface of the high-k layer 206 on the interfacial layer 204 on the semiconductor channel 202 of the n-type transistor 210 is left unmasked and exposed. The mask layer 207 may comprise any suitable hard mask material known to the skilled artisan. In one or more embodiments, the mask layer 207 comprises, for example, one or more of titanium nitride (TiN), aluminum nitride (AIN), and the like. In one or more embodiments, the mask layer 207 may have any suitable thickness. In one or more embodiments, the mask layer 207 has a thickness in a range of from 1 nm to 50 nm.

[0114] In one or more embodiments, the exposed surface of the mask layer 207 and the exposed surface of the high-K dielectric layer 206 are subjected to an optional preclean process to pre-clean the surface(s). In one or more embodiments, pre-cleaning the mask layer 207 and the exposed surface of the high-K dielectric layer 206 may comprise removing a native oxide from the surface(s). The removing of native oxide may be or include flowing a fluorine-containing precursor and a hydrogen-containingAttorney Docket No.: 44025427WO01 PATENT precursor. Fluorine-containing precursors may be or include nitrogen trifluoride as well as any other fluorine-containing precursor. Hydrogen-containing precursors may be characterized by an amine group (-NH2), or other nitrogen-containing or hydrogencontaining group. For example, hydrogen-containing precursors may be or include nitrogen-and-hydrogen-containing precursors, such as ammonia as one non-limiting example. The flowing may include flowing the fluorine-containing precursor and the hydrogen-containing precursor into a remote plasma region. The remote plasma region may be fluidly coupled to the substrate processing region. A plasma may be formed to produce plasma effluents. A flow-rate of the fluorine-containing precursor and a flow rate of the hydrogen-containing precursor may be characterized by a hydrogen-to- fluorine atomic flow ratio of less than 1 :2. The native oxide may be removed by flowing the plasma effluents into the substrate processing region while forming solid byproducts on the surface of the substrate. Without being bound to any particular theory, the flow may leave of a layer of fluorine on the substrate surface that promotes interface formation at operation 250D with the fluorine termination serving to enhance reliability. The solid by-products are sublimated by increasing the temperature of the substrate above a sublimation temperature of the solid by-products. After sublimation, the mask layer 207 and the exposed surface of the high-K dielectric layer 206 are free or substantially free of native oxide.

[0115] With reference to FIG. 5, in one or more embodiments, at operation 250D a re-oxidation process is performed to thermally oxidize the semiconductor channel 212 of the p-type transistor 220. The reoxidation process may include a thermal anneal process in an oxygen (O2), nitrous oxide (N2O), and H2 ambient, performed in a rapid thermal processing (RTP) chamber. The RTP chamber may be any of the processing chambers 120, 122, 124, 126, 128, and 130 shown in FIG. 1. The re-oxidation process in operation 250E may thermally oxidize the underlying layer through the high-K dielectric layer 216, and thus thicken the interfacial layer 222 to a thickness in a range of from greater than about 5 A to about 10 A, or in a range of from about 7 A to less than about 8 A, and form an interfacial layer 214 in the semiconductor channel 212 of the p-type transistor 220 near the interface with the high-K dielectric layer 216. The reoxidation process may be performed for between about 1 second and about 30Attorney Docket No.: 44025427WO01 PATENT seconds, at a temperature of between about 400 °C and about 900 °C, and at a pressure of between about 0.01 Torr and 100 Torr.

[0116] Still referring to FIG. 5, at operation 250E, in one or more embodiments, the mask layer 207 is then removed from the surface of the high-K dielectric layer 216 on the interfacial layer 214 on the semiconductor channel 212 of the p-transistor 220. The mask layer 207 may be removed by any suitable means known to the skilled artisan, including, but not limited to etching and planarization.

[0117] In one or more embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 is, e.g., a thin amorphous silicon oxide (SiC ) layer, having a thickness in a range of from greater than 0 A to about 7 A, or in a range of from greater than 0 A to less than about 5 A.

[0118] In one or more embodiments, the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 is an amorphous silicon oxide (SiO2) layer, having a thickness in a range of from greater than about 5 A to about 10 A, or in a range of from about 7 A to less than about 8 A. It is noted that the interfacial layer 214 increases in thickness from the interfacial layer 222 formed in operation 240C.

[0119] In one or more embodiments, as illustrated in FIG. 4, a device is advantageously provided that has a thicker interfacial layer on the p-type transistor 220 and a corresponding thinner interfacial layer 204 formed on the n-type transistor 210, improving the performance of the n-type transistor 210 and alleviating the NBTI of the p-type transistor 220.

[0120] With reference to FIG. 6, a thin interfacial layer 204 is formed on the n-type transistor 210 and a thicker interfacial layer 214 is formed on the p-type transistor 220 according to subtractive process flow 260. Th method 260 may include one or more operations prior to the initiation of the stated method operations, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method 260 may include a number of optional operations, which may or may not specifically be associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation process, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below.Attorney Docket No.: 44025427WO01 PATENT

[0121] As illustrated in FIG. 6, the semiconductor structure may represent a device after certain processing has been completed. For example, semiconductor channel 202,212 may be a planar material, or may be a structured device, which may include one or more materials configured as or defining posts, trenches, or other structures as would be understood are similarly encompassed by the present technology. Semiconductor channel 202,212 may include any number of materials including silicon or silicon-containing materials such as oxides, nitrides, and carbides of silicon, as well as any other materials that may be incorporated within a structure.

[0122] One or more material layers may be formed over some or all of semiconductor channel 202,212, as well as formed at least partially within the substrate, to produce a structure that may be a planarized or structured material in embodiments. As non-limiting examples, semiconductor channel 202,212 may be or include silicon, or may include a surface amount of silicon formed over an additional material, such as silicon oxide, and which may be a reduced portion of the silicon oxide leaving a silicon exposed surface. Semiconductor channel 202,212 may include a native oxide. The exposed material at a surface of semiconductor channel 202,212 may be etched, planarized, or otherwise processed to produce an intermittent pattern in some embodiments. Although illustrated as a single instance, it is to be understood that device may include a small section of a larger process integration that may include any number of additional sections that may be similar or different to the objects shown. Semiconductor channel 202,212 may be housed or positioned in a processing region of a semiconductor processing chamber, and method 260 may be performed to produce a semiconductor material on the substrate, such as a high-k dielectric material.

[0123] In one or more embodiments, a semiconductor channel 202 is provided for the n-type transistor 210, and a semiconductor channel 212 is provided for the p-type transistor 220. As used in this specification and the appended claims, the term "provided" means that the semiconductor channel 202,212, or semiconductor channel, is made available for processing (e.g., positioned in a processing chamber).

[0124] At operation 260A, in one or more embodiments, the exposed surface of the semiconductor channel 202 of the n-type transistor and the exposed surface of the semiconductor channel 212 of the p-type transistor 220 are subjected to an optional pre-clean process to pre-clean the surface. In one or more embodiments, pre-cleaningAttorney Docket No.: 44025427WO01 PATENT the semiconductor channel 202,212 may comprise removing a native oxide from the semiconductor channel 202,212. The removing of native oxide may be or include flowing a fluorine-containing precursor and a hydrogen-containing precursor. Fluorine- containing precursors may be or include nitrogen trifluoride as well as any other fluorine- containing precursor. Hydrogen-containing precursors may be characterized by an amine group (-NH2), or other nitrogen-containing or hydrogen-containing group. For example, hydrogen-containing precursors may be or include nitrogen-and-hydrogen- containing precursors, such as ammonia as one non-limiting example. The flowing may include flowing the fluorine-containing precursor and the hydrogen-containing precursor into a remote plasma region. The remote plasma region may be fluidly coupled to the substrate processing region. A plasma may be formed to produce plasma effluents. A flow-rate of the fluorine-containing precursor and a flow rate of the hydrogen-containing precursor may be characterized by a hydrogen-to-fluorine atomic flow ratio of less than 1 :2. The native oxide may be removed by flowing the plasma effluents into the substrate processing region while forming solid by-products on the surface of the substrate. Without being bound to any particular theory, the flow may leave of a layer of fluorine on the substrate surface that promotes interface formation at operation 260A with the fluorine termination serving to enhance reliability. The solid by-products are sublimated by increasing the temperature of the substrate above a sublimation temperature of the solid by-products. After sublimation, the semiconductor channel 202,212 is free or substantially free of native oxide.

[0125] With reference to FIG. 6, in one or more embodiments, method 260 may include delivering an oxidizing atmosphere and thermally annealing the surface of the semiconductor channel 202,212 to form an oxide-containing interface in operation 260A. In one or more embodiments, a thick interfacial layer 224 is formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and a thick interfacial layer 214 is formed on the exposed surface of the semiconductor channel 212 of the p-type transistor 220. In some embodiments, the thick interfacial layer 224 formed on the exposed surface of the semiconductor channel 202 of the n- type transistor 210 and the thick interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may be formed by an in-situAttorney Docket No.: 44025427WO01 PATENT steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas.

[0126] In one or more embodiments, the oxidizing atmosphere of operation 260A comprises one or more of nitrous oxide, oxygen, or radical oxygen containing chemistries. The oxidizing atmosphere, e.g., nitrous oxide, delivered to the semiconductor channel 202,212 as in FIG. 6 may help to control how much of the semiconductor channel 202,212, having a surface free of native oxide, may be oxidized to form the oxide-containing interface 204,222 as in FIG. 6. Operation 260A may include a thermal based reaction using steam, such as an in situ steam generation (ISSG) process whereby oxidation takes place at a lower rate as compared with conventional thermal techniques utilizing hydrogen and / or oxygen. The oxidizing atmosphere, e.g., specifically, the nitrogen of the nitrous oxide, may serve as a carrier for oxygen and may not become part of the interface or substrate. The oxide-containing interface formed may be high quality and highly ordered, meaning a crystallographic structure free of or substantially free of defects. The resultant oxide-containing interfacial layer 224,214 may include silicon oxide (SiOx).

[0127] In one or more embodiments, the thick interfacial layer 224 formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and the thick interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor have a thickness in a range of from greater than about 5 A to about 10 A, or in a range of from about 7 A to less than about 8 A.

[0128] In one or more embodiments, the thick interfacial layer 224 formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p- type transistor 220 may act as a nucleation layer of a high-K dielectric material layer 206, 216 to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 202,212 and the high-K dielectric material layer 206,216.

[0129] In some embodiments, the thick interfacial layer 224 formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and the thick interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-Attorney Docket No.: 44025427WO01 PATENT type transistor 220 may be formed by an in-situ steam generation (ISSG) process utilizing H2 and O2 gases, or a rapid thermal oxidation (RTO) process utilizing O2 gas. The thick interfacial layer 224 formed on the exposed surface of the semiconductor channel 202 of the n-type transistor 210 and the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 may act as a nucleation layer of a high-K dielectric material layer 206,216 to be deposited thereon and improve quality (e.g., such as interface state density, accumulation capacitance, frequency dispersion, and leakage current) of the interface between the semiconductor channel 202,212 and the high-K dielectric material layer 206,216. The interface formation process may be performed in a processing chamber, such as the processing chamber 120, 122, 124, 126, 128, or 130 shown in FIG 1.

[0130] In one or more embodiments, the method 260 may then include forming a high-k dielectric material overlying the semiconductor channel 202,212 at operation 260B. The present technology may encompass any formation or deposition of the high- k material, although in some embodiments, formation operation 260B may be or include an atomic layer deposition, or any other atomic layer deposition chamber. The formation may be performed directly after forming the interfacial layer 224, 214 and may be performed in the same chamber as the interfacial layer formation or in an additional chamber, such as an additional chamber incorporated on the same system, such as system 100. In some embodiments, vacuum conditions may be maintained while the substrate is transferred from the interface formation chamber to the deposition chamber, which may limit exposure of the substrate to air.

[0131] Where an atomic layer deposition process is performed to form the high-k dielectric material 206,216, a metal-containing precursor may be delivered to the substrate to react with the pretreated surface. For example, a transition-metal- containing precursor, a poor-metal-containing precursor, or a lanthanide-metal- containing precursor may be delivered to the processing chamber to interact with the reactive ligands exposed on the substrate from the pre-treatment. An oxygen-containing precursor may then be delivered in a second operation, such as subsequent a purge of the metal-containing precursor. The metal containing precursor may be any suitable metal-containing precursor known to the skilled artisan. In one or more embodiments, the metal-containing precursor comprises a metal halide. In some embodiments, high-Attorney Docket No.: 44025427WO01 PATENTK dielectric layer comprises a metal selected from one or more of hafnium (Hf), zirconium (Zr), silicon (Si), lanthanum (La), aluminum (Al), titanium (Ti), and strontium (Sr). This may produce an oxide layer by atomic layer deposition, such as high-k layer 206,216 as illustrated in FIG. 6. In one non-limiting example, a hafnium-containing precursor may be delivered in a first operation and an oxidant may be delivered in a second operation for producing a hafnium oxide (HfOx) film. Additional metal-containing precursors may include zirconium-containing precursors for producing zirconium- containing materials, as well as any other number of metal-containing precursors for producing additional metal oxide structures. For hafnium-containing precursors, and similarly for any alternative metals, the precursors may be or include halogen-containing precursors, oxygen-containing precursors, hydrogen-containing precursors, or carbon- containing precursors in any of which hafnium is incorporated.

[0132] For the oxidant, any oxygen-containing precursor may be used that may react with the metal-containing materials. For example, the oxygen-containing precursor may be or include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, nitrogen-and oxygen-containing precursors, plasma-enhanced oxygen including locally or remotely enhanced oxygen, or any other material including oxygen that may be incorporated with the metal, such as hafnium, to produce a metal oxide material layer overlying the substrate. Again, any of the metal-containing materials noted above may be used in embodiments of the present technology, and may include any of the grouped metals, which may include, and may not be limited to, hafnium, zirconium, silicon, lanthanum, aluminum, titanium, strontium, or combinations of these materials, such as, for example, hafnium silicate.

[0133] In one or more embodiments, the high-k dielectric material layer 206,216 formed has a thickness in a range of from 3 A to 50 A.

[0134] Still referring to FIG. 6, in one or more embodiments, a mask layer 217 is formed on a top surface of the high-k layer 216 on the interfacial layer 214 on the substrate 21 of the p-type transistor 220, while the top surface of the high-k layer 206 on the interfacial layer 224 on the substrate 20 of the n-type transistor 210 is left unmasked and exposed. The mask layer 217 may comprise any suitable hard mask material known to the skilled artisan. In one or more embodiments, the mask layer 217 comprises, for example, one or more of titanium nitride (TiN), aluminum nitride (AIN),Attorney Docket No.: 44025427WO01 PATENT and the like. In one or more embodiments, the mask layer 217 may have any suitable thickness. In one or more embodiments, the mask layer 217 has a thickness in a range of from 1 nm to 50 nm.

[0135] In one or more embodiments, at operation 260D of method 260, the exposed surface of the mask layer 217 and the exposed surface of the high-K dielectric layer 206 are subjected to scavenging to decrease the thickness of the interfacial layer 224 on the semiconductor channel 202 of the n-type transistor 210. Any suitable scavenging process known to the skilled artisan may be used. In one or more embodiments, scavenging includes, for example, exposing the exposed surface of the mask layer 217 and the exposed surface of the high-K dielectric layer 206 to DPNH3. During the process of one or more embodiments, the hydrogen radicals can penetrate the high-K dielectric layer 206 and chemically interact with the interfacial layer beneath. The interaction chemically reduces the bonding between silicon and oxygen atoms of the interfacial layers, and, as a result, the oxygen atoms of the interfacial layer are liberated and cause the thickness of the interfacial layer to decrease. In one or more embodiments, the thickness of the interfacial layer 224 is decreased to form a thin interfacial layer 204 on the semiconductor channel 202 of the n-type transistor 210, while leaving a thick interfacial layer 214 on the semiconductor channel 212 of the p-type transistor 212.

[0136] Still referring to FIG. 6, at operation 260E, in one or more embodiments, the mask layer 217 is then removed from the surface of the high-K dielectric layer 216 on the interfacial layer 214 on the semiconductor channel 212 of the p-transistor 220. The mask layer 217 may be removed by any suitable means known to the skilled artisan, including, but not limited to etching and planarization.

[0137] In one or more embodiments, the interfacial layer 204 formed on the surface of the semiconductor channel 202 of the n-type transistor 210 is, e.g., a thin amorphous silicon oxide (SiC ) layer, having a thickness in a range of from greater than 0 A to about 7 A, or in a range of from greater than 0 A to less than about 5 A.

[0138] In one or more embodiments, the interfacial layer 214 formed on the surface of the semiconductor channel 212 of the p-type transistor 220 is an amorphous silicon oxide (SiO2) layer, having a thickness in a range of from greater than about 5 A to about 10 A, or in a range of from about 7 A to less than about 8 A.Attorney Docket No.: 44025427WO01 PATENT

[0139] In one or more embodiments, as illustrated in FIG. 6, a device is advantageously provided that has a thicker interfacial layer on the p-type transistor 220 and a corresponding thinner interfacial layer 204 formed on the n-type transistor 210, improving the performance of the n-type transistor 210 and alleviating the NBTI of the p-type transistor 220.

[0140] In one or more embodiments, the formation, including atomic layer deposition may be performed at any temperature, regardless of whether the operations are performed in the same or different chambers. For example, the atomic layer deposition may be performed at a temperature less than or about 500° C in embodiments, and may be less than or about 450° C, less than or about 400° C, less than or about 350° C, less than or about 300° C, less than or about 250° C, or less.

[0141] After the layer of high-k material has been formed or deposited, one or more posttreatments may be performed. In some embodiments, the semiconductor channel 202,212 may be transferred from the deposition chamber to another chamber or set of chambers for post-treating the materials. Similar to that explained above, the transfer may occur on a single processing system having multiple chambers, and thus the transfer from or between any of these chambers may be performed while maintaining vacuum conditions. In one or more embodiments, the methods may then include one or more additional post-treatment operations. The post-treatment operations may include one or more operations performed in one or more chambers, including multiple chambers on the same cluster tool. Post-treatment operations may include an oxidation, a nitridation, and / or a thermal anneal.

[0142] The deposition or formation of the high-k film may produce a porous film, or a film including vacancies in the structure. By performing an oxidation operation, oxygen species may permeate the film filling vacancies, as well as producing an oxide material at the interface of the high-k material, such as interfacial layer 204, 214 if not formed in previous operations described above. This may improve the underlying interface from the amine terminal groups, which may increase the mobility performance of the device. To limit an excessive increase in an underlying oxide layer, the oxidation operation may be performed for a limited time period and may be performed within any of the previously noted time ranges.Attorney Docket No.: 44025427WO01 PATENT

[0143] Post-treatment operations may additionally include further contacting the substrate with a nitrogen-containing precursor. The nitrogen-containing precursor may include any nitrogen-containing precursor, and may include nitrogen gas, as well as any nitrogen-containing precursor noted elsewhere. The nitrogen-containing precursor may include a plasma-activated or enhanced nitrogen-containing precursor, a thermally activated nitrogen, or some other nitrogen precursor, which may allow nitrogen radicals or nitrogen atoms to be incorporated within the high-k structure, which may stabilize the film or settle the film towards an equilibrium state. Unlike an oxidation operation, the nitridation may not increase the thickness of an underlying layer, such as silicon oxide, and may also slightly increase the k-value of the produced film.

[0144] Nitrogen incorporation may be controlled to limit the incorporation in the film, in order to maintain the structural and electrical properties. In some embodiments, a post-treatment nitridation may incorporate less than or about 20 atomic% nitrogen at a surface region of the high-k film, and may incorporate less than or about 15 atomic% nitrogen, less than or about 10 atomic% nitrogen, less than or about 8 atomic% nitrogen, less than or about 6 atomic% nitrogen, less than or about 4 atomic% nitrogen, less than or about 2 atomic% nitrogen, or less. In some embodiments, an incorporation between about 3 atomic% and about 7 atomic% may maintain a higher k-value than higher nitrogen incorporation and may better stabilize the film than lower nitrogen incorporation. By surface region may be meant an exposed surface of the material, although the nitrogen incorporation may extend to any distance within the film, and may be consistent, or form a reducing gradient through the material.

[0145] A post-treatment oxidation or nitridation may be performed at any of the temperatures noted previously, although in some embodiments the post-treatment oxidation and / or nitridation may be performed at a temperature range below or about 500° C and may be performed at a temperature range below or about 400° C, below or about 300° C, below or about 200° C, below or about 100° C, or less depending on the operation being performed.

[0146] A post-treatment anneal may be performed subsequent to any of the operations, including any of the noted post-treatment operations. The post-treatment anneal may be performed in any chamber in which a previous operation is performed, or may involve transfer to a different chamber, such as one configured to perform aAttorney Docket No.: 44025427WO01 PATENT rapid thermal anneal process, for example. Again, the chamber may be incorporated on the same platform as other chambers, which may allow a transfer between chambers while maintaining vacuum conditions. The post-treatment anneal may further align the film bonding and further stabilize the film. In embodiments the post-treatment anneal may be performed at a third temperature relative to the first temperature, where the third temperature may be above or about the first temperature. For example, the posttreatment anneal may be performed at a temperature above or about 400° C, and in embodiments may be performed at a temperature above or about 500° C, above or about 600° C, above or about 700° C, above or about 800° C, above or about 900° C, or higher.

[0147] By performing a pre-treatment and / or post-treatments according to embodiments of the present technology, improved high-k materials may be produced. The layer of high-k material may be produced to any thickness including up to or about several nanometers. In one or more embodiments, the high-k dielectric layer may have a thickness in a range of from about 3 A to about 50 A. However, due to the preferred grain structure produced by the present technology, thinner effective oxide thickness may be produced without loss to gate leakage performance. High-k materials produced according to the present technology may be characterized by k-values greater than or about 10, and may be characterized by k-values greater than or about 15, greater than or about 20, greater 20 than or about 21 , greater than or about 22, greater than or about 23, greater than or about 24, greater than or about 25, or greater.

[0148] As noted above, the present technology further allows improved dielectric constants compared to conventional technologies. Additionally, because of the produced grain structure, gate leakage currents associated with the film may be less than or about one tenth of the gate leakage current of a similar thickness film of silicon oxide, and the gate leakage currents may be less than or about one hundredth of the gate leakage current of a similar thickness film of silicon oxide, less than or about one thousandth of a similar thickness film of silicon oxide, less than or about 1 / 5,000 of a similar thickness film of silicon oxide, less than or about 1 / 10,000 of a similar thickness film of silicon oxide, less than or about 1 / 20,000 of a similar thickness film of silicon oxide, less than or about 1 / 50,000 of a similar thickness film of silicon oxide, less than or about 1 / 100,000 of a similar thickness film of silicon oxide, or less. By producing filmsAttorney Docket No.: 44025427WO01 PATENT according to embodiments of the present technology, formed films having a beneficial morphology may be produced, which may enhance the electrical characteristics of the film compared to conventional technologies.

[0149] Spatially relative terms, such as "beneath," "below," "lower," "above," "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below,” or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0150] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0151] Reference throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments" or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, theAttorney Docket No.: 44025427WO01 PATENT appearances of the phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0152] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will understand that the embodiments described are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, the present disclosure can include modifications and variations that are within the scope of the appended claims and their equivalents.

Claims

Attorney Docket No.: 44025427WO01 PATENTWhat is claimed is:1 . A method of forming a semiconductor device, the method comprising: forming a first interfacial layer of a first gate dielectric on a first semiconductor channel of a first transistor of the semiconductor device, the first interfacial layer having a first thickness; and forming a second interfacial layer of a second gate dielectric on a second semiconductor channel of a second transistor of the semiconductor device, the second interfacial layer having a second thickness greater than the first thickness.

2. The method of claim 1 , wherein the first transistor is an n-type transistor, and the second transistor is a p-type transistor.

3. The method of claim 1 , wherein the first interfacial layer surrounds the first semiconductor channel, and the second interfacial layer surrounds the second semiconductor channel.

4. The method of claim 1 , wherein the first thickness is in a range of from greater than about 0 A to about 7 A.

5. The method of claim 1 , wherein the second thickness is in a range of from greater than about 5 A to about 10 A.

6. The method of claim 1 , wherein the first thickness is in a range of from greater than 0 A to less than about 5 A and the second thickness is in a range of from about 7 A to less than about 8 A.

7. The method of claim 1 , wherein forming the first interfacial layer and forming the second interfacial layer comprises: forming a first mask layer on the first semiconductor channel; pre-cleaning a top surface of the second semiconductor channel to remove native oxide and form a pre-cleaned second semiconductor channel;Attorney Docket No.: 44025427WO01 PATENT exposing the pre-cleaned second semiconductor channel to an oxidizing atmosphere and thermally annealing to form the second interfacial layer on the pre-cleaned second semiconductor channel; removing the first mask layer to expose the first semiconductor channel; forming a second mask layer on the second interfacial layer; pre-cleaning the first semiconductor channel to remove native oxide and form a pre-cleaned first semiconductor channel; and exposing the pre-cleaned first semiconductor channel to an oxidizing atmosphere and thermally annealing to form the first interfacial layer on the precleaned first semiconductor channel.

8. The method of claim 1 , wherein forming the first interfacial layer and forming the second interfacial layer comprises: forming a first mask layer on the first semiconductor channel; pre-cleaning a top surface of the second semiconductor channel to remove native oxide and form a pre-cleaned second semiconductor channel; exposing the pre-cleaned second semiconductor channel to an oxidizing atmosphere and thermally annealing to form a third interfacial layer on the precleaned second semiconductor channel; removing the first mask layer to expose the first semiconductor channel; and performing a re-oxidation process to thermally oxidize the first semiconductor channel and the third interfacial layer to form the first interfacial layer on the first semiconductor channel and the second interfacial layer on the second semiconductor channel.

9. The method of claim 8, wherein the re-oxidation process comprises annealing the first semiconductor channel and the third interfacial layer in an oxygen (O2), nitrous oxide (N2O), and hydrogen (H2) ambient at a temperature in a range of from 400 °C to 900 °C.Attorney Docket No.: 44025427WO01 PATENT10. The method of claim 1 , wherein forming the first interfacial layer and forming the second interfacial layer comprises: pre-cleaning a top surface of the first semiconductor channel and a top surface of the second semiconductor channel to remove native oxide and form a pre-cleaned first semiconductor channel and a pre-cleaned second semiconductor channel; exposing the pre-cleaned first substrate and the pre-cleaned second semiconductor channel to an oxidizing atmosphere and thermally annealing to form the first interfacial layer on the first semiconductor channel and a third interfacial layer on the pre-cleaned second semiconductor channel; depositing a first high-k dielectric layer on the first interfacial layer and a second high-k dielectric layer on the third interfacial layer; forming a mask layer on the first high-k dielectric layer; performing a re-oxidation process to thermally oxidize the third interfacial layer to form the second interfacial layer on the second semiconductor channel; and removing the mask layer.

11. The method of claim 1 , wherein forming the first interfacial layer and forming the second interfacial layer comprises: pre-cleaning a top surface of the first semiconductor channel and a top surface of the second semiconductor channel to remove native oxide and form a pre-cleaned first semiconductor channel and a pre-cleaned second semiconductor channel; exposing the pre-cleaned first semiconductor channel and the precleaned second semiconductor channel to an oxidizing atmosphere and thermally annealing to form a fourth interfacial layer on the first semiconductor channel and the second interfacial layer on the pre-cleaned second semiconductor channel; depositing a first high-k dielectric layer on the fourth interfacial layer and a second high-k dielectric layer on the second interfacial layer; forming a mask layer on the second high-k dielectric layer;Attorney Docket No.: 44025427WO01 PATENT performing a scavenging process to form the first interfacial layer on the first semiconductor channel; and removing the mask layer.

12. The method of claim 1, further comprising depositing a first high-K dielectric layer on the first interfacial layer and a second high-K dielectric layer on the second interfacial layer.

13. The method of claim 12, further comprising depositing a first gate electrode on the first high-K dielectric layer on the first interfacial layer and second gate electrode on the second high-K dielectric layer on the second interfacial layer.

14. The method of claim 1, wherein the oxidizing atmosphere comprises one or more of nitrous oxide, oxygen, or radical oxygen containing chemistries.

15. The method of claim 12, wherein the first high-K dielectric layer and the second high-K dielectric layer independently comprise one or more of hafnium, zirconium, silicon, lanthanum, aluminum, titanium, and strontium.

16. A method of forming a semiconductor structure, the method comprising: forming a first interfacial layer of a first gate dielectric on a first semiconductor channel of an n-type transistor, the first interfacial layer having a first thickness; forming a second interfacial layer of a second gate dielectric on a second semiconductor channel of a p-type transistor, the second interfacial layer having a second thickness greater than the first thickness; and forming a first high-K dielectric layer on the first interfacial layer and a second high-K dielectric layer on the second interfacial layer.

17. The method of claim 16, wherein forming the first interfacial layer, the second interfacial layer, the first high-K dielectric layer, and the second high-K dielectric layer comprises:Attorney Docket No.: 44025427WO01 PATENT forming a first mask layer on the first semiconductor channel of the n-type transistor; pre-cleaning a top surface of the second semiconductor channel to remove native oxide and form a pre-cleaned second semiconductor channel; exposing the pre-cleaned second semiconductor channel to an oxidizing atmosphere and thermally annealing to form the second interfacial layer on the pre-cleaned second semiconductor channel; removing the first mask layer to expose the first semiconductor channel; forming a second mask layer on the second interfacial layer; pre-cleaning the first semiconductor channel to remove native oxide and form a pre-cleaned first semiconductor channel; exposing the pre-cleaned first semiconductor channel to an oxidizing atmosphere and thermally annealing to form the first interfacial layer on the precleaned first semiconductor channel; and depositing the first high-K dielectric layer on the first interfacial layer and the second high-K dielectric layer on the second interfacial layer.

18. The method of claim 16, wherein forming the first interfacial layer, the second interfacial layer, the first high-K dielectric layer, and the second high-K dielectric layer comprises: forming a first mask layer on the first semiconductor channel of the n-type transistor; pre-cleaning a top surface of the second semiconductor channel to remove native oxide and form a pre-cleaned second semiconductor channel on the p-type transistor; exposing the pre-cleaned second semiconductor channel to an oxidizing atmosphere and thermally annealing to form a third interfacial layer on the precleaned second semiconductor channel; removing the first mask layer to expose the first semiconductor channel; performing a re-oxidation process to thermally oxidize the first semiconductor channel and the third interfacial layer to form the first interfacialAttorney Docket No.: 44025427WO01 PATENT layer on the first semiconductor channel and the second interfacial layer on the second semiconductor channel; and depositing the first high-K dielectric layer on the first interfacial layer and the second high-K dielectric layer on the second interfacial layer.

19. The method of claim 16, wherein forming the first interfacial layer, the second interfacial layer, the first high-K dielectric layer, and the second high-K dielectric layer comprises: pre-cleaning a top surface of the first semiconductor channel and a top surface of the second semiconductor channel to remove native oxide and form a pre-cleaned first semiconductor channel of the n-type transistor and a precleaned second semiconductor channel on the p-type transistor; exposing the pre-cleaned first semiconductor channel and the precleaned second semiconductor channel to an oxidizing atmosphere and thermally annealing to form the first interfacial layer on the first semiconductor channel and a third interfacial layer on the pre-cleaned second semiconductor channel; depositing the first high-k dielectric layer on the first interfacial layer and the second high-k dielectric layer on the third interfacial layer; forming a mask layer on the first high-k dielectric layer; performing a re-oxidation process to thermally oxidize the third interfacial layer to form the second interfacial layer on the second semiconductor channel; and removing the mask layer.

20. The method of claim 16, wherein forming the first interfacial layer, the second interfacial layer, the first high-K dielectric layer, and the second high-K dielectric layer comprises: pre-cleaning a top surface of the first semiconductor channel and a top surface of the second substrate to remove native oxide and form a pre-cleaned first semiconductor channel and a pre-cleaned second semiconductor channel;Attorney Docket No.: 44025427WO01 PATENT exposing the pre-cleaned first semiconductor channel and the precleaned second semiconductor channel to an oxidizing atmosphere and thermally annealing to form a fourth interfacial layer on the first semiconductor channel and the second interfacial layer on the pre-cleaned second semiconductor channel; depositing the first high-k dielectric layer on the fourth interfacial layer and the second high-k dielectric layer on the second interfacial layer; forming a mask layer on the second high-k dielectric layer; performing a scavenging process to form the first interfacial layer on the first semiconductor channel; and removing the mask layer.21 . A semiconductor device comprising: a first transistor having a first semiconductor channel and a first gate dielectric layer, wherein the first gate dielectric layer comprises a first interfacial layer and a first high-k dielectric layer; and a second transistor having a second semiconductor channel and a second gate dielectric layer, wherein the second gate dielectric layer comprises a second interfacial layer and a second high-k dielectric layer, wherein the second interfacial layer is thicker than the first interfacial layer.

22. The semiconductor device of claim 21 , wherein the first transistor is a n-type transistor and the second transistor is a p-type transistor.

23. The semiconductor device of claim 21 , wherein the first interfacial layer surrounds the first semiconductor channel, and the second interfacial layer surrounds the second semiconductor channel.

24. The semiconductor device of claim 21 , wherein the first interfacial layer has a first thickness and the second interfacial layer has a second thickness.Attorney Docket No.: 44025427WO01 PATENT25. The semiconductor device of claim 24, wherein the first thickness is in a range of from greater than about 0 A to about 7 A.

26. The semiconductor device of claim 24, wherein the second thickness is in a range of from greater than about 5 A to about 10 A.

27. The semiconductor device of claim 24, wherein the first thickness is in a range of from greater than 0 A to less than about 5 A and the second thickness is in a range of from about 7 A to less than about 8 A.

28. The semiconductor device of claim 21 , wherein the first semiconductor channel and the second semiconductor channel comprise silicon.

29. The semiconductor device of claim 21 , wherein the first interfacial layer and the second interfacial layer comprise silicon oxide (SiOx).

30. The semiconductor device of claim 21 , wherein the first high-K dielectric layer and the second high-K dielectric layer independently comprise one or more of hafnium, zirconium, silicon, lanthanum, aluminum, titanium, and strontium.

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