Method for improving stability of measurement of passivation layer overlay accuracy
By etching supplementary feature structure patterns in the top metal layer of a semiconductor structure and then exposing and developing them with photoresist, the problem of anchor point identification failure in passivation layer overlay accuracy measurement is solved, thus improving the stability and accuracy of the measurement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2026-02-04
- Publication Date
- 2026-06-09
AI Technical Summary
The passivation layer is affected by the random grain distribution of the preceding metal layer, causing the OVL measurement equipment to fail to identify the anchor point, resulting in the failure of overlay accuracy measurement.
A supplementary feature structure pattern is formed by etching in the top metal layer of the semiconductor structure, and a photoresist layer is coated on the surface of the combined passivation layer for exposure and development. The feature structure pattern is used as an anchor point for overlay accuracy measurement.
It improves the stability of passivation layer overlay accuracy measurement, solves the problem of anchor point identification failure, and improves measurement accuracy.
Smart Images
Figure CN122180389A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit manufacturing technology, specifically to a method for improving the measurement stability of passivation layer overlay accuracy. Background Technology
[0002] During overlay accuracy measurement (OVL measurement), the feature image of the anchor point is usually acquired first, and then matched with the anchor point image stored in the RCP (Rule of Processes Library). Only when the match is successful will the system move to the alignment mark position to perform the measurement. If the match fails, the system will prompt an error indicating measurement failure.
[0003] In the back-end manufacturing process of semiconductor devices, the front metal layer is usually deposited on a substrate with alignment mark patterns. The front metal layer is usually not etched with additional alignment marks. However, due to the random distribution of the grains in the front metal layer (such as aluminum film), the passivation layer (back layer) is affected by the microstructure density, surface morphology and stress uniformity. This substrate defect is coupled through the process, causing the size / morphology distortion of the OVL measurement anchor point pattern lithographically formed on the passivation layer (back layer) to be unable to match the standard pattern in RCP. As a result, the OVL measurement equipment cannot identify the anchor point, causing the overlay accuracy measurement to fail completely. Summary of the Invention
[0004] This application provides a method to improve the stability of passivation layer overlay accuracy measurement, which can solve the problem that the OVL measurement equipment cannot identify the OVL measurement anchor point due to the influence of the random distribution of the grains of the previous metal layer on the passivation layer, thus causing the passivation layer overlay accuracy measurement failure.
[0005] This application provides a method for improving the measurement stability of passivation layer overlay accuracy, including: A semiconductor structure is provided, the semiconductor structure is processed in a back-end process, the semiconductor structure includes at least: a barrier layer and an interlayer dielectric layer stacked in sequence and interleaved, and a metal interconnect layer located in the barrier layer and the interlayer dielectric layer, the metal interconnect layer being covered by the top layer of the barrier layer and the interlayer dielectric layer. The interlayer dielectric layer and the barrier layer stacked on the top layer of the semiconductor structure are etched to form a via, the via exposing the metal interconnect layer; A top metal layer is formed, which covers the interlayer dielectric layer and fills the vias, and the top metal layer is connected to the metal interconnect layer; The top metal layer on the surface of the interlayer dielectric layer of the top layer of the semiconductor structure is etched and stopped on the surface of the interlayer dielectric layer of the top layer in the semiconductor structure to form at least one opening for defining a supplementary feature structure pattern. A combined passivation layer is formed, which covers the sidewalls and bottom wall of the opening and the top metal layer; A photoresist layer is coated on the surface of the combined passivation layer; Using the feature structure pattern as the anchor point for measuring the overlay accuracy of the combined passivation layer, the photoresist layer is exposed and developed to open the photoresist layer in the target area and expose the combined passivation layer at the bottom.
[0006] Optionally, in the method for improving the measurement stability of passivation layer overlay accuracy, the supplementary feature structure pattern is a rectangular pattern.
[0007] Optionally, in the method for improving the measurement stability of passivation layer overlay accuracy, the size of the supplementary feature structure pattern along the X direction is 4.5μm~8.5μm; the size of the supplementary feature structure pattern along the Y direction is 4.5μm~8.5μm.
[0008] Optionally, in the method for improving the measurement stability of passivation layer overlay accuracy, the photoresist layer in the target area is the photoresist layer directly above the via.
[0009] Optionally, in the method for improving the measurement stability of passivation layer overlay accuracy, the combined passivation layer includes at least a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer covers the sidewalls, bottom walls, and top metal layer of the opening, and the silicon nitride layer covers the silicon oxide layer.
[0010] Optionally, in the method for improving the measurement stability of passivation layer overlay accuracy, the material of the top metal layer is aluminum.
[0011] Optionally, in the method for improving the measurement stability of passivation layer overlay accuracy, the material of the metal interconnect layer is copper.
[0012] Optionally, in the method for improving the measurement stability of passivation layer overlay accuracy, the material of the interlayer dielectric layer is silicon dioxide.
[0013] Optionally, in the method for improving the measurement stability of passivation layer overlay accuracy, the barrier layer is made of silicon nitride.
[0014] The technical solution of this application has at least the following advantages: In the method for improving the stability of passivation layer overlay accuracy measurement provided in this application, after forming a top metal layer on the surface of a semiconductor structure, the top metal layer is etched and the etching stops at the surface of the interlayer dielectric layer at the top of the semiconductor structure, forming at least one opening. This creates at least one new feature structure pattern in the top metal layer as an OVL measurement anchor point pattern required for the overlay accuracy measurement of the subsequent combined passivation layer. A combined passivation layer is then formed on the top metal layer. Finally, using this feature structure pattern as the anchor point for the overlay accuracy measurement of the combined passivation layer, the photoresist layer is exposed and developed to open the photoresist layer in the target area and expose the underlying combined passivation layer. This method, by creating at least one new feature structure pattern in the top metal layer as an OVL measurement anchor point feature pattern required for the overlay accuracy measurement of the subsequent combined passivation layer, solves the problem that the OVL measurement equipment cannot identify the OVL measurement anchor point due to the random grain distribution of the previous top metal layer, thus causing overlay accuracy measurement failure. This improves the stability of passivation layer overlay accuracy measurement. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0016] Figure 1 This is a flowchart of a method for improving the measurement stability of passivation layer overlay accuracy according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the semiconductor structure after the formation of a through-hole in an embodiment of the present invention; Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the top metal layer in an embodiment of the present invention; Figure 4 This is a schematic diagram of the semiconductor structure after etching to form supplementary feature structure patterns in the top metal layer according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the combined passivation layer according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the semiconductor structure after a photoresist layer is coated on the surface of the combined passivation layer according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the semiconductor structure formed after the photoresist layer has been exposed and developed according to an embodiment of the present invention; The reference numerals in the attached figures are explained as follows: 10-Metal interconnect layer, 11-First barrier layer, 12-Second barrier layer, 13-Third barrier layer, 21-First interlayer dielectric layer, 22-Second interlayer dielectric layer, 23-Third interlayer dielectric layer, 41-Through hole, 42-Opening, 50-Top metal layer, 60-Combined passivation layer, 70-Photoresist layer. Detailed Implementation
[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0021] This application provides a method for improving the measurement stability of passivation layer overlay accuracy, referring to... Figure 1 , Figure 1 This is a flowchart of a method for improving the measurement stability of passivation layer overlay accuracy according to an embodiment of the present invention. The method for improving the measurement stability of passivation layer overlay accuracy includes: First, perform step S1: Refer to Figure 2 , Figure 2This is a schematic diagram of a semiconductor structure after the formation of a via according to an embodiment of the present invention. A semiconductor structure is provided, which enters a back-end process. The semiconductor structure includes at least: a barrier layer and an interlayer dielectric layer stacked alternately in sequence, and a metal interconnect layer located in the barrier layer and the interlayer dielectric layer. The metal interconnect layer is covered by the top layer of the barrier layer and the interlayer dielectric layer.
[0022] This embodiment uses a semiconductor structure comprising three sets of sequentially stacked barrier layers and interlayer dielectric layers as an example, namely, a first barrier layer 11, a first interlayer dielectric layer 21, a second barrier layer 12, a second interlayer dielectric layer 22, a third barrier layer 13, and a third interlayer dielectric layer 23. A metal interconnect layer 10 is located among the second interlayer dielectric layer 22, the second barrier layer 12, the first interlayer dielectric layer 21, and the first barrier layer 11, and the metal interconnect layer 10 is covered by the third barrier layer 13 and the third interlayer dielectric layer 23.
[0023] In this embodiment, the metal interconnect layer 10 is made of copper.
[0024] Preferably, the material of the first interlayer dielectric layer 21 to the third interlayer dielectric layer 23 is silicon dioxide.
[0025] Furthermore, the first barrier layer 11 to the third barrier layer 13 are all made of silicon nitride.
[0026] Then, proceed to step S2: Continue to refer to Figure 2 The third interlayer dielectric layer 23 and the third barrier layer 13 in the semiconductor structure are etched to form a via 41, which exposes the metal interconnect layer 10.
[0027] Next, proceed to step S3: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the top metal layer in an embodiment of the present invention. The top metal layer 50 is formed, which covers the third interlayer dielectric layer 23 and fills part of the via 41. The top metal layer 50 is connected to the metal interconnect layer 11 at the bottom of the via 41.
[0028] In this embodiment, the top metal layer 50 is made of aluminum.
[0029] Further, proceed to step S4: (Refer to...) Figure 4 , Figure 4This is a schematic diagram of a semiconductor structure after etching a supplementary feature structure pattern in the top metal layer according to an embodiment of the present invention. The top metal layer 50 on the surface of the third interlayer dielectric layer 23 of the semiconductor structure is etched and stopped on the surface of the third interlayer dielectric layer 23 in the semiconductor structure to form at least one opening 42 for defining the supplementary feature structure pattern, that is, the opening 42 is the supplementary feature structure pattern.
[0030] In this embodiment, the etching location of the supplementary feature structure pattern is the peripheral region of the semiconductor structure.
[0031] Preferably, when viewed from a top-down angle (top view of the semiconductor structure), the supplementary feature structure pattern is a rectangular shape.
[0032] Preferably, when viewed from a top-down angle, the size of the supplementary feature structure pattern along the X direction is 4.5μm to 8.5μm; the size of the supplementary feature structure pattern along the Y direction is 4.5μm to 8.5μm.
[0033] Next, proceed to step S5: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the combined passivation layer according to an embodiment of the present invention. The combined passivation layer 60 covers the sidewalls and bottom wall of the opening 42 and the top metal layer 50.
[0034] Preferably, the combined passivation layer 60 includes at least: a stacked silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer covers the sidewalls and bottom wall of the opening 42 and the top metal layer 50, and the silicon nitride layer covers the silicon oxide layer.
[0035] Further, proceed to step S6: Refer to Figure 6 , Figure 6 This is a schematic diagram of a semiconductor structure after a photoresist layer is coated on the surface of the combined passivation layer 60, according to an embodiment of the present invention. A photoresist layer 70 is coated on the surface of the combined passivation layer 60.
[0036] Finally, proceed to step S7: (Refer to...) Figure 7 , Figure 7 The present invention forms a combined passivation layer by exposing and developing a semiconductor structure after the photoresist layer is exposed and developed. The feature structure pattern is used as the anchor point for measuring the overlay accuracy of the combined passivation layer. The photoresist layer 70 is exposed and developed to open the photoresist layer 70 in the target area and expose the combined passivation layer 60 at the bottom.
[0037] Preferably, the photoresist layer 70 in the target area is the photoresist layer 70 directly above the via 41.
[0038] In this application, after the top metal layer is formed, at least one feature structure pattern (opening) is added to the top metal layer through an etching process as an OVL measurement anchor point feature pattern required for the overlay accuracy measurement of the subsequent passivation layer. This can solve the problem that the OVL measurement equipment cannot identify the OVL measurement anchor point due to the random distribution of the grains of the previous top metal layer, thus causing the overlay accuracy measurement to fail, and improve the stability of the passivation layer overlay accuracy measurement.
[0039] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for improving the measurement stability of passivation layer overlay accuracy, characterized in that, include: A semiconductor structure is provided, the semiconductor structure is processed in a back-end process, the semiconductor structure includes at least: a barrier layer and an interlayer dielectric layer stacked in sequence and interleaved, and a metal interconnect layer located in the barrier layer and the interlayer dielectric layer, the metal interconnect layer being covered by the top layer of the barrier layer and the interlayer dielectric layer. The interlayer dielectric layer and the barrier layer stacked on the top layer of the semiconductor structure are etched to form a via, the via exposing the metal interconnect layer; A top metal layer is formed, which covers the interlayer dielectric layer and fills the vias, and the top metal layer is connected to the metal interconnect layer; The top metal layer on the surface of the interlayer dielectric layer of the top layer of the semiconductor structure is etched and stopped on the surface of the interlayer dielectric layer of the top layer in the semiconductor structure to form at least one opening for defining a supplementary feature structure pattern. A combined passivation layer is formed, which covers the sidewalls and bottom wall of the opening and the top metal layer; A photoresist layer is coated on the surface of the combined passivation layer; Using the feature structure pattern as the anchor point for measuring the overlay accuracy of the combined passivation layer, the photoresist layer is exposed and developed to open the photoresist layer in the target area and expose the combined passivation layer at the bottom.
2. The method for improving the measurement stability of passivation layer overlay accuracy according to claim 1, characterized in that, The supplementary feature structure graphic is a rectangular graphic.
3. The method for improving the measurement stability of passivation layer overlay accuracy according to claim 2, characterized in that, The dimensions of the supplementary feature structure pattern along the X direction are 4.5μm to 8.5μm; the dimensions of the supplementary feature structure pattern along the Y direction are 4.5μm to 8.5μm.
4. The method for improving the measurement stability of passivation layer overlay accuracy according to claim 1, characterized in that, The photoresist layer in the target area is the photoresist layer directly above the via.
5. The method for improving the measurement stability of passivation layer overlay accuracy according to claim 1, characterized in that, The combined passivation layer includes at least a silicon oxide layer and a silicon nitride layer, wherein the silicon oxide layer covers the sidewalls and bottom wall of the opening and the top metal layer, and the silicon nitride layer covers the silicon oxide layer.
6. The method for improving the measurement stability of passivation layer overlay accuracy according to claim 1, characterized in that, The top metal layer is made of aluminum.
7. The method for improving the measurement stability of passivation layer overlay accuracy according to claim 1, characterized in that, The metal interconnect layer is made of copper.
8. The method for improving the measurement stability of passivation layer overlay accuracy according to claim 1, characterized in that, The interlayer dielectric layer is made of silicon dioxide.
9. The method for improving the measurement stability of passivation layer overlay accuracy according to claim 1, characterized in that, The barrier layer is made of silicon nitride.