Asymmetric co-fab for optoelectronic devices

Abstract

This application discloses an asymmetric in-layer shielding structure, an interposer, and a semiconductor package for optoelectronic co-packaging, belonging to the field of semiconductor device technology. The asymmetric in-layer shielding structure for optoelectronic co-packaging of this application forms an asymmetric shielding layout by setting a first grounding structure and a second grounding structure with different widths and gaps on both sides of the transmission structure. This significantly enhances the shielding effectiveness on the side closer to the electromagnetic interference source, achieving targeted suppression of strong electromagnetic interference on one side. Simultaneously, the size of the grounding structure on the side farther from the interference source is relatively weakened to free up wiring space, balancing shielding effectiveness and signal channel density. The dimensional parameters of each shielding unit are adapted to the preset target value of the characteristic impedance of the transmission structure, ensuring that the characteristic impedance of the transmission structure remains constant at 100Ω±10% during differential signal transmission, effectively avoiding impedance mismatch and signal reflection caused by improper shielding structure dimensions.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to asymmetric co-layer shielding structures, interposers, and semiconductor packages for optoelectronic co-packaging. Background Technology

[0002] As semiconductor technology evolves towards ultra-high speed, high density, and multi-channel, 224G PAM4 / 6 has become the core signal transmission standard for co-packaged optoelectronics (CPO). Its high baud rate of 86.66 / 112 GBaud results in signal rise / fall times of less than 15 ps, placing micron-level requirements on electromagnetic interference suppression and impedance matching accuracy. In the redistribution layer wiring of the interposer in existing CPO optoelectronic co-packages, the same-layer shielding structure generally adopts a symmetrical layout, that is, the width of the ground gap on both sides of the signal line is exactly the same as the width of the ground metal. However, this symmetrical structure has significant drawbacks: On the one hand, in the CPO scenario, the bare core side is adjacent to the optical engine, and the electro-optical conversion unit of the optical engine generates strong unilateral electromagnetic radiation. The symmetrical shielding cannot differentiate and suppress this strong unilateral interference. Even weak electromagnetic coupling can cause inter-symbol interference, eye diagram closure, and excessive bit error rate in the 224G PAM4 / 6 signal, severely degrading signal integrity. On the other hand, the symmetrical shielding still uses a narrow gap and wide grounding structure on the interference-free side away from the interference source, excessively occupying valuable micron-level wiring space, reducing the signal channel density of the interposer, and making it difficult to meet the requirements of high-density multi-signal interconnection. In addition, the existing shielding structure design does not correlate and optimize the dimensional parameters such as grounding gap and grounding width with the impedance matching requirements of the 224G PAM4 / 6 signal. Some solutions blindly reduce the grounding gap in pursuit of shielding effectiveness, causing the characteristic impedance of the signal line to deviate from the standard value of 100Ω (differential) or 50Ω (single-ended), causing impedance mismatch and signal reflection, further exacerbating the deterioration of ultra-high-speed signal transmission performance. Therefore, there is an urgent need to propose a same-layer shielding scheme that can adapt to unilateral electromagnetic interference environments, balance shielding effectiveness and wiring density, and achieve precise impedance matching. Summary of the Invention

[0003] To address the issues of existing CPO optoelectronic co-packaging interposers' inability to adapt to strong electromagnetic interference on one side, difficulty in balancing shielding effectiveness and wiring density, and insufficient impedance matching accuracy, this paper provides an asymmetric co-packaging shielding structure, optoelectronic co-packaging interposer, and semiconductor package. This structure aims to achieve targeted enhanced shielding on one side through an asymmetric co-packaging layout, freeing up wiring space on the interference-free side, and ensuring that the characteristic impedance of the signal transmission structure meets the preset target value through matching design of dimensional parameters.

[0004] This application provides an asymmetric in-layer shielding structure for optoelectronic co-packaging, applied in the redistribution layer of the optoelectronic co-packaging interposer, comprising:

[0005] A transmission structure used to transmit signals;

[0006] A shielding unit is disposed coplanarly with the transmission structure in the same redistribution layer. The shielding unit includes a first grounding structure located on a first side of the transmission structure and a second grounding structure located on a second side of the transmission structure.

[0007] The first grounding structure and the second grounding structure are asymmetrical structures so that the shielding effectiveness of the first side against electromagnetic interference is stronger than that of the second side.

[0008] The size parameters of the shielding unit meet the preset target value condition of the characteristic impedance of the transmission structure.

[0009] Optionally, a first gap is provided between the first grounding structure and the transmission structure, and a second gap is provided between the second grounding structure and the transmission structure. The width of the first gap is smaller than the width of the second gap, and the width of the first grounding structure is larger than the width of the second grounding structure.

[0010] Optionally, the sum of the width of the first gap and the width of the first grounding structure is equal to the sum of the width of the second gap and the width of the second grounding structure.

[0011] Optionally, the optoelectronic co-encapsulation interposer layer includes multiple redistribution layers spaced apart along the thickness direction, with the shielding unit disposed in at least two redistribution layers respectively, and at least one of the following dimensional parameters—the width of the first gap between the first grounding structure and the transmission structure, the width of the second gap between the second grounding structure and the transmission structure, the width of the first grounding structure, and the width of the second grounding structure—gradually changing along the thickness direction.

[0012] Optionally, from the first redistribution layer near the chip connection side to the second redistribution layer near the substrate connection side, the width of the first gap increases layer by layer, the width of the first ground structure decreases layer by layer, the width of the second gap decreases layer by layer, and the width of the second ground structure increases layer by layer.

[0013] This application provides an optoelectronic co-encapsulation interlayer, including multiple redistribution layers spaced apart along the thickness direction, with an insulating layer between adjacent redistribution layers;

[0014] At least two of the redistribution layers are respectively provided with asymmetric co-layer shielding structures, the asymmetric co-layer shielding structures comprising:

[0015] A transmission structure used to transmit signals;

[0016] A shielding unit is disposed on the same redistribution layer as the transmission structure. The shielding unit includes a first grounding structure located on a first side of the transmission structure and a second grounding structure located on a second side of the transmission structure. The first grounding structure and the second grounding structure are asymmetrical structures so that the shielding effectiveness of the first side against electromagnetic interference is stronger than that of the second side.

[0017] Along the thickness direction, the dimensional parameters of the asymmetric co-layer shielding structure in different redistribution layers show a gradual trend.

[0018] This application provides an optoelectronic co-packaging interposer, comprising:

[0019] Matrix;

[0020] A multi-layer redistribution layer is disposed within the matrix, and an insulating layer is provided between adjacent redistribution layers;

[0021] Among them, at least one of the redistribution layers includes the aforementioned asymmetric in-layer shielding structure for optoelectronic co-packaging.

[0022] Optionally, it further includes a grounding vertical interconnect structure that extends along the thickness direction and is electrically connected to the first grounding structure and / or the second grounding structure in at least two redistribution layers.

[0023] This application provides a semiconductor package, including:

[0024] The aforementioned optoelectronic co-packaging interposer layer;

[0025] At least one optical engine is electrically connected to the first surface of the optoelectronic co-encapsulation interlayer;

[0026] At least one integrated circuit chip is electrically connected to the first surface of the opto-co-encapsulation interposer layer;

[0027] The packaging substrate is electrically connected to the second surface of the optoelectronic co-encapsulation interposer, and the second surface is opposite to the first surface.

[0028] Optionally, the connection between the optical engine and the optoelectronic co-encapsulation interlayer is located on the side where the first grounding structure is located.

[0029] The beneficial effects of the above technical solution are as follows:

[0030] The asymmetric in-layer shielding structure for optoelectronic co-packaging in this application forms an asymmetric shielding layout by setting a first grounding structure and a second grounding structure with different widths and gaps on both sides of the transmission structure. This significantly enhances the shielding effectiveness on the side closer to the electromagnetic interference source, achieving targeted suppression of strong electromagnetic interference on one side. At the same time, the size of the grounding structure on the side farther from the interference source is relatively weakened to free up wiring space, balancing shielding effectiveness and signal channel density. The dimensional parameters of each shielding unit are adapted to the preset target value of the characteristic impedance of the transmission structure, ensuring that the characteristic impedance of the transmission structure is constant at 100Ω±10% during differential signal transmission or constant at 50Ω±5% during single-ended signal transmission. This effectively avoids impedance mismatch and signal reflection caused by improper shielding structure dimensions, ensuring the integrity and continuity of 224G PAM4 / 6 ultra-high-speed signal transmission in the optoelectronic co-packaging interposer. Attached Figure Description

[0031] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0032] Figure 1 This is a three-dimensional schematic diagram of an embodiment of the asymmetric in-layer shielding structure for optoelectronic co-packaging described in Embodiment 1 of this application;

[0033] Figure 2 This is a schematic diagram of one embodiment of the multi-layer asymmetric same-layer shielding structure of this application;

[0034] Figure 3 This is a schematic diagram of one embodiment of the semiconductor package described in this application. Detailed Implementation

[0035] The advantages of this application are further illustrated below with reference to the accompanying drawings and specific embodiments.

[0036] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0037] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The singular forms “a,” “the,” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0038] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0039] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0040] The following terms are used in this document:

[0041] CPO (Co-Packaged Optics): Co-packaging of optoelectronics is an advanced optoelectronic integration technology that tightly integrates optical engines with switching / computing chips (ASIC / GPU) on the same packaging substrate / intermediate layer. It is a core solution for next-generation data centers and AI computing power interconnection.

[0042] PAM4 (4-level Pulse Amplitude Modulation): This method uses four different signal amplitudes to represent data on the same differential line / wavelength. Under the same bandwidth, the data rate is twice that of the traditional NRZ (2-level, 1 bit / symbol).

[0043] 224G PAM4 / 6: refers to a single-channel raw data rate of 224 Gbps, which is achieved by using two high-order pulse amplitude modulation methods, PAM4 (four-level) and PAM6 (six-level), respectively. It is the core physical layer solution for the next generation of ultra-high-speed 1.6T / 3.2Tbps CPO.

[0044] Intermediate layer: In advanced packaging, the intermediate layer is a multi-layer interconnection layer located between the bare die, optical engine (OE), and packaging substrate. It is used to realize high-density, short-distance, low-loss electrical interconnection between multiple chips (such as computing chips, optical engines, HBM, ASICs, etc.) and is a core structural component of 2.5D / 3D packaging and CPO optoelectronic co-packaging.

[0045] RDL (Redistribution Layer): A redistribution layer is a finely wired network of multilayer metal conductors built on the surface of the interposer (silicon / organic / glass) through processes such as photolithography and electroplating. It enables signal / power redistribution and interconnection between bare chips and between bare chips and the substrate. The horizontal and vertical metal conductors are isolated by insulating materials.

[0046] Bare chip: refers to a chiplet (die) that has been manufactured and diced but has not undergone any encapsulation, wire bonding, or mounting. It is the most primitive and unencapsulated form in the chiplet system.

[0047] Bare die microbumps are tiny metal bumps fabricated on the surface of a die or chiplet for vertical electrical interconnection between chips and between a chip and an interposer. They are a key structure for 2.5D / 3D packaging and heterogeneous chiplet integration.

[0048] C4 solder bumps (Controlled Collapse Chip Connection) are a type of solder bump technology arranged in an array. They are used for the electrical and mechanical connection of flip-chip between the active surface of a chip and the substrate / carrier, and are one of the basic bump forms in modern advanced packaging.

[0049] Example 1

[0050] like Figure 1 As shown, this embodiment provides an asymmetric in-layer shielding structure for optoelectronic co-packaging, applied in the redistribution layer of the optoelectronic co-packaging interposer, comprising:

[0051] A transmission structure for transmitting signals; wherein the transmission structure includes multiple transmission units (S2, S1, S3) arranged in parallel.

[0052] The shielding unit is disposed coplanarly with the transmission structure in the same redistribution layer (RDL). The shielding unit includes a first grounding structure Gn located on the first side of the transmission structure (i.e., transmission unit S3) and a second grounding structure Gf located on the second side of the transmission structure (i.e., transmission unit S2).

[0053] The first grounding structure Gn and the second grounding structure Gf are asymmetrical structures so that the shielding effectiveness of the first side against electromagnetic interference is stronger than that of the second side.

[0054] The size parameters of the shielding unit meet the preset target value condition of the characteristic impedance of the transmission structure.

[0055] In this embodiment, the transmission structure is a signal metal line. The asymmetric co-layer shielding structure for optoelectronic co-packaging forms an asymmetric shielding layout by setting a first grounding structure Gn and a second grounding structure Gf with different widths and gaps on both sides of the transmission structure. This significantly enhances the shielding effectiveness on the side closer to the electromagnetic interference source, achieving targeted suppression of strong electromagnetic interference on one side. At the same time, the size of the grounding structure on the side farther from the interference source is relatively weakened to free up wiring space, balancing shielding effect and signal channel density. The first side corresponds to the near-interference side adjacent to the optical engine OE in the CPO scenario, and the second side corresponds to the far-interference side farther from the optical engine OE. The bare ASIC chip, as the far-interference source, is located on the second side. The dimensions of the shielding unit are matched with the preset target values ​​of the characteristic impedance of the transmission structure, so that the characteristic impedance of the transmission structure is constant at 100Ω±10% during differential signal transmission or at 50Ω±5% during single-ended signal transmission. This effectively avoids impedance mismatch and signal reflection caused by improper shielding structure dimensions, and ensures the integrity and continuity of 224G PAM4 / 6 ultra-high-speed signal transmission in the optoelectronic co-packaged interposer.

[0056] In an optional embodiment, a first gap is provided between the first grounding structure Gn and the transmission structure (i.e., transmission unit S3), and a second gap is provided between the second grounding structure Gf and the transmission structure (i.e., transmission unit S2). The width of the first gap is smaller than the width of the second gap, and the width of the first grounding structure Gn is larger than the width of the second grounding structure Gf.

[0057] The width of the first gap is equal to the width of the second grounding structure Gf, and the width of the second gap is equal to the width of the first grounding structure Gn.

[0058] In this embodiment, the first grounding structure Gn is a near-interference-side grounding metal located on the near-interference side of the signal metal line; the second grounding structure Gf is a far-interference-side grounding metal located on the far-interference side of the signal metal line. A near-side gap exists between the near-interference-side grounding metal and the signal metal line, and a far-side gap exists between the far-interference-side grounding metal and the signal metal line. The width of the near-side gap is smaller than the width of the far-side gap, and the width of the near-interference-side grounding metal is greater than the width of the far-interference-side grounding metal, thus forming an asymmetric co-layer shielding structure against strong electromagnetic interference on the near-interference side.

[0059] In this embodiment, by combining a narrow gap with a wide grounding on the first side, the coupling path of electromagnetic interference from the interference source to the transmission structure is shortened, and the charge discharge area of ​​the grounding structure is increased, thereby effectively suppressing strong electromagnetic radiation from the first side. The second side adopts a relatively wide second gap and a narrow second grounding structure Gf, which reduces the area occupied by the grounding metal on the wiring while meeting the basic shielding requirements. This is beneficial for arranging more signal channels in the limited redistribution layer space and improving the overall wiring density.

[0060] The differentiated configuration of the gap width and the grounding structure width is coordinated with the preset target value of the characteristic impedance of the transmission structure. While achieving the asymmetric shielding layout, it maintains the stability of the characteristic impedance of the transmission structure within the target range, and avoids impedance deviation due to unilateral compression of the gap or change of the grounding size.

[0061] In an optional embodiment, the sum of the width of the first gap and the width of the first grounding structure Gn is equal to the sum of the width of the second gap and the width of the second grounding structure Gf.

[0062] In this embodiment, the sum of the width of the first gap and the width of the first grounding structure Gn is equal to the sum of the width of the second gap and the width of the second grounding structure Gf. This equality ensures that the lateral distance from the edges of the grounding structures on both sides of the transmission structure to their respective outermost reference planes remains equal. Even with an asymmetrical configuration of local gaps and grounding widths, a symmetrical global reference ground boundary is still provided for the transmission structure. Thus, although the first side uses a narrow gap and wide grounding to enhance the suppression of strong electromagnetic interference, and the second side uses a wide gap and narrow grounding to free up wiring space, the consistency of the total lateral dimensions on both sides effectively suppresses common-mode noise and mode conversion introduced by boundary asymmetry. At the same time, it makes the equivalent dielectric environment of the transmission structure relative to the reference ground planes on both sides tend to be balanced, which helps to stabilize the characteristic impedance of the transmission structure near the preset target value and reduces the risk of impedance fluctuations induced by asymmetrical layout.

[0063] In an alternative embodiment, such as Figure 2 As shown, the optoelectronic co-encapsulation interposer 1 includes multiple redistribution layers spaced apart along the thickness direction. The shielding unit is respectively disposed in at least two redistribution layers. Along the thickness direction, at least one of the following dimensional parameters in different redistribution layers—the width of the first gap between the first grounding structure Gn and the transmission structure, the width of the second gap between the second grounding structure Gf and the transmission structure, the width of the first grounding structure Gn, and the width of the second grounding structure Gf—shows a gradual change trend.

[0064] In this embodiment, the multi-layered gradient configuration allows the asymmetry of the shielding structure to adapt to the changes in electromagnetic interference field strength distribution in the vertical direction: in the top redistribution layer near the bare core and optical engine, the first side uses a narrower gap and a wider grounding to concentrate on dealing with strong near-field interference. As the redistribution layers move down and away from the interference source, the first gap gradually widens and the first grounding structure Gn gradually narrows, while the second gap and the second grounding structure Gf show an inverse gradient. This parameter gradient trend along the thickness direction makes each shielding unit more compatible with the actual electromagnetic environment of the corresponding layer, forming a differentiated shielding strength distribution in the vertical dimension. This avoids excessive use of wiring resources in the far-field region and maintains the continuity of the overall shielding effectiveness from the top to the bottom layer. At the same time, the layer-by-layer gradient of the size parameters avoids abrupt changes in interlayer impedance, making the characteristic impedance transition smoother when the signal is transmitted along the vertical path. This effectively suppresses reflections and mode conversions caused by abrupt changes in interlayer structure, further ensuring the transmission integrity of ultra-high-speed signals in a multi-layered redistribution layer environment.

[0065] In an optional embodiment, from the first redistribution layer near the chip connection side to the second redistribution layer near the substrate connection side, the width of the first gap increases layer by layer, the width of the first ground structure Gn decreases layer by layer, the width of the second gap decreases layer by layer, and the width of the second ground structure Gf increases layer by layer.

[0066] In this embodiment, from the RDL layer near the bare core microbump to the RDL layer near the C4 solder bump, the width of the near-side gap in each RDL layer gradually increases from narrow to wide, the width of the near-interference side ground metal gradually decreases from wide to narrow, the width of the far-side gap gradually decreases from wide to narrow, and the width of the far-interference side ground metal gradually increases from narrow to wide. In the RDL layer near the C4 solder bump, the width of the near-side gap is equal to the width of the far-side gap, and the width of the near-interference side ground metal is equal to the width of the far-interference side ground metal.

[0067] In this embodiment, the gradient configuration causes the strength of the asymmetric shielding structure to exhibit a trend change along the thickness direction: in the top redistribution layer adjacent to the optical engine and the bare core, the first side provides the highest shielding effectiveness with the narrowest gap and widest grounding to cope with strong near-field interference. As the redistribution layer extends downwards and away from the interference source, the gap on the first side gradually widens and the grounding width gradually decreases, while the second side adjusts in the opposite direction. In this way, the shielding resource configuration of each redistribution layer matches the electromagnetic environment of its vertical position. The upper layer prioritizes effective suppression of strong interference on one side, while the lower layer gradually releases wiring area to optimize the overall signal channel density. At the same time, the smooth gradient of each dimensional parameter along the thickness direction makes the characteristic impedance change of the transmission structure on the vertical transition path more gradual, reducing impedance discontinuities and signal reflections caused by interlayer structural differences, which is beneficial to maintaining the transmission consistency and eye diagram opening of ultra-high-speed signals in multi-layer redistribution layers.

[0068] Example 2

[0069] like Figure 2 As shown, this embodiment provides an optoelectronic co-encapsulation intermediary layer 1, including multiple redistribution layers 12 arranged at intervals along the thickness direction, and an insulating layer 11 is provided between adjacent redistribution layers 12;

[0070] At least two of the redistribution layers 12 are respectively provided with asymmetric co-layer shielding structures, the asymmetric co-layer shielding structures including:

[0071] A transmission structure for transmitting signals; wherein the transmission structure includes multiple transmission units (S2, S1, S3) arranged in parallel.

[0072] The shielding unit is disposed on the same redistribution layer 12 as the transmission structure. The shielding unit includes a first grounding structure Gn located on the first side of the transmission structure (i.e., the transmission unit S3) and a second grounding structure Gf located on the second side of the transmission structure (i.e., the transmission unit S2). The first grounding structure Gn and the second grounding structure Gf are asymmetrical structures so that the shielding effectiveness of the first side against electromagnetic interference is stronger than that of the second side.

[0073] Along the thickness direction, the dimensional parameters of the asymmetric co-layer shielding structure in different redistribution layers 12 exhibit a gradual change. The insulating layer 11 includes grounded vertical interconnecting metal pillars v.

[0074] In this embodiment, in the asymmetric co-layer shielding structure, the first grounding structure Gn and the second grounding structure Gf on both sides of the transmission structure are asymmetrically configured, which makes the first side closer to the electromagnetic interference source obtain stronger shielding effectiveness, while the grounding structure on the second side is relatively reduced to save wiring area. Along the thickness direction, the size parameters of this asymmetric co-layer shielding structure in different redistribution layers 12 show a gradual trend, making the shielding strength of each layer more matched with the actual electromagnetic environment of the corresponding layer: in the upper layer near the chip connection side, the degree of asymmetry is more significant to concentrate on dealing with strong near-field interference; in the lower layer near the substrate connection side, the degree of asymmetry gradually weakens until the grounding structures on both sides tend to be symmetrical. This gradual shielding layout along the vertical direction not only suppresses strong electromagnetic interference on one side, but also effectively releases wiring space on the side away from the interference source, improves the overall signal channel density, and avoids impedance discontinuity introduced by abrupt changes in the inter-layer shielding structure, which is conducive to ensuring the transmission consistency and eye diagram quality of ultra-high-speed signals in the multi-layer redistribution layers 12.

[0075] In an optional embodiment, in the redistribution layer 12 near the C4 solder bump, the width of the first gap is equal to the width of the second gap, and the width of the first grounding structure Gn is equal to the width of the second grounding structure Gf, forming a symmetrical in-layer shielding structure. That is, the width of the near-side gap is equal to the width of the far-side gap, and the width of the near-interference-side grounding metal is equal to the width of the far-interference-side grounding metal.

[0076] By way of example and not limitation, the number of redistribution layers 12 is 1 to 6, the spacing between adjacent redistribution layers 12 is 1 μm to 20 μm, and the thickness of the insulating layer 11 is 1 μm to 10 μm. For example, Figure 2 This example demonstrates a 3-layer redistribution layer 12.

[0077] Specifically, the width of the first gap is 1 μm to 3 μm, the width of the second gap is 3 μm to 5 μm, the width of the first grounding structure Gn is 3 μm to 5 μm, and the width of the second grounding structure Gf is 1 μm to 3 μm. Preferably, the width of the first gap is 2 μm, the width of the second gap is 4 μm, the width of the first grounding structure Gn is 4 μm, and the width of the second grounding structure Gf is 2 μm.

[0078] In an optional embodiment, the metal material of the redistribution layer 12 is copper or copper-titanium alloy, and the thickness of the metal layer of the redistribution layer 12 is 1 μm to 5 μm.

[0079] In an optional embodiment, a grounding vertical interconnect structure is further included. This grounding vertical interconnect structure extends along the thickness direction and is electrically connected to a first grounding structure Gn and / or a second grounding structure Gf in at least two redistribution layers 12. The arrangement density of the grounding vertical interconnect structure is 2 to 3 times that of the signal vertical interconnect structure V, and the diameter of the grounding vertical interconnect structure is 2 μm to 4 μm. By setting the grounding vertical interconnect structure, the first grounding structure Gn and the second grounding structure Gf distributed in different redistribution layers 12 are connected vertically, constructing a three-dimensional grounding network that runs through multiple redistribution layers 12. This effectively enhances the interlayer electromagnetic isolation effect, suppresses vertical electromagnetic leakage and interlayer crosstalk, and provides a more continuous and low-impedance reference ground loop for the transmission structure.

[0080] Example 3

[0081] This embodiment provides an optoelectronic co-packaging intermediary layer 1, including:

[0082] Matrix;

[0083] A multilayer redistribution layer 12 is disposed in the matrix, and an insulating layer 11 is provided between adjacent redistribution layers 12;

[0084] Among them, at least one of the redistribution layers 12 includes the asymmetric in-layer shielding structure for optoelectronic co-packaging described in Embodiment 1.

[0085] In this embodiment, from the RDL layer near the bare core microbump to the RDL layer near the C4 solder bump, the width of the near-side gap in each RDL layer gradually increases from narrow to wide, the width of the near-interference side ground metal gradually decreases from wide to narrow, the width of the far-side gap gradually decreases from wide to narrow, and the width of the far-interference side ground metal gradually increases from narrow to wide. In the RDL layer near the C4 solder bump, the width of the near-side gap is equal to the width of the far-side gap, and the width of the near-interference side ground metal is equal to the width of the far-interference side ground metal.

[0086] In this embodiment, by configuring the asymmetric co-layer shielding structure within the redistribution layer 12 of the interposer, the first grounding structure Gn on the side of the transmission structure closest to the electromagnetic interference source provides enhanced shielding effectiveness with a narrower gap and a wider grounding width. This effectively suppresses strong unilateral electromagnetic interference generated by devices such as optical engines, reducing the risk of inter-symbol interference and eye diagram closure after interference with ultra-high-speed signals. Simultaneously, the second grounding structure Gf on the side of the transmission structure furthest from the interference source employs a relatively wider gap and a narrower grounding width, reducing the grounding metal's occupation of the limited wiring area. This allows for the arrangement of more signal channels within the same redistribution layer 12 space, increasing the overall interconnect density of the optoelectronic co-package interposer 1. Furthermore, the dimensional parameters of the shielding unit are adapted to the preset target value of the characteristic impedance of the transmission structure, ensuring that the characteristic impedance of the transmission structure remains stable near the target value even under the asymmetric shielding layout. This avoids impedance fluctuations and signal reflections caused by improper grounding structure size configuration, providing reliable assurance for the transmission integrity of 224G PAM4 / 6 ultra-high-speed signals in the optoelectronic co-package interposer 1.

[0087] In an optional embodiment, a grounded vertical interconnect structure is further included, which extends along the thickness direction and is electrically connected to the first grounded structure Gn and / or the second grounded structure Gf in at least two redistribution layers 12.

[0088] In this embodiment, by setting a vertical grounding interconnection structure, the first grounding structure Gn and the second grounding structure Gf, which are distributed in different redistribution layers 12, are connected in the vertical direction, constructing a three-dimensional grounding network that runs through the multi-layer redistribution layers 12. This three-dimensional grounding network makes each layer of shielding unit no longer an isolated planar shielding structure, but an interconnected overall shielding system, effectively enhancing the interlayer electromagnetic isolation effect and suppressing electromagnetic leakage and interlayer crosstalk in the vertical direction. At the same time, the vertical grounding interconnection structure provides a more continuous and low-impedance reference ground loop for the transmission structure, making the reference ground potential more stable when the signal is transmitted along the vertical path, reducing common-mode noise and mode conversion caused by discontinuity in the grounding loop, and further improving the signal integrity and anti-interference capability of ultra-high-speed signals when transmitted in the multi-layer redistribution layer 12 environment.

[0089] Example 4

[0090] like Figure 3 As shown, this embodiment provides a semiconductor package, including:

[0091] The optoelectronic co-packaging interposer layer 1 described in Example 2;

[0092] At least one optical engine (OE) 5 is electrically connected to the first surface of the optoelectronic co-encapsulation interlayer 1;

[0093] At least one integrated circuit chip 4 is electrically connected to the first surface of the optoelectronic co-encapsulation interposer layer 1;

[0094] The packaging substrate is electrically connected to the second surface of the optoelectronic co-encapsulation interposer 1, and the second surface is opposite to the first surface.

[0095] A PCB substrate 2 is disposed below the optoelectronic co-packaging interposer layer 1.

[0096] In this embodiment, the semiconductor package integrates the optical engine 5 and the integrated circuit chip 4 onto the same optoelectronic co-package interposer 1. The asymmetric co-layer shielding structure within the interposer's multi-layer redistribution layers 12 specifically suppresses the strong electromagnetic interference generated by the optical engine 5. The shielding dimensions, gradually varying along the thickness of the interposer, match the shielding strength between different layers to the electromagnetic environment. The upper redistribution layer 12, closer to the optical engine 5, provides stronger shielding to protect the adjacent integrated circuit chip 4 from interference, while the lower redistribution layer 12, closer to the package substrate, gradually releases wiring resources to support high-density interconnects. Thus, the ultra-high-speed signal within the package achieves a stable electromagnetic environment and continuous impedance control along its transmission path from the integrated circuit chip 4 through the interposer to the package substrate, effectively reducing inter-symbol interference and signal reflection. This ensures the eye diagram quality and bit error rate of the 224G PAM4 / 6 signal, while also meeting the overall wiring density and miniaturization requirements of the optoelectronic co-package.

[0097] In this embodiment, from the RDL layer near the bare die microbump to the RDL layer near the C4 solder bump 3, the width of the near-side gap in each RDL layer gradually increases from narrow to wide, the width of the near-interference side ground metal gradually decreases from wide to narrow, the width of the far-side gap gradually decreases from wide to narrow, and the width of the far-interference side ground metal gradually increases from narrow to wide. In the RDL layer near the C4 solder bump 3, the width of the near-side gap is equal to the width of the far-side gap, and the width of the near-interference side ground metal is equal to the width of the far-interference side ground metal. The C4 solder bump 3 is disposed on the second surface of the optoelectronic co-packaging interposer and is connected to the packaging substrate through the C4 solder bump 3.

[0098] In an optional embodiment, the connection position between the optical engine 5 and the optoelectronic co-packaged interposer 1 is adjacent to the side where the first ground structure Gn is located. The connection position between the integrated circuit chip 4 and the optoelectronic co-packaged interposer 1 is adjacent to the side where the second ground structure Gf is located. The integrated circuit chip 4 may be an ASIC bare chip.

[0099] In this embodiment, the connection between the optical engine 5 and the optoelectronic co-packaged interposer 1 is located adjacent to the side where the first grounding structure Gn is located. This layout significantly shortens the spatial distance between the optical engine 5, the main single-sided electromagnetic interference source, and the first grounding structure Gn. Before reaching the transmission structure, the electromagnetic radiation generated by the optical engine 5 is first received by the adjacent first grounding structure Gn through a more direct path and discharged to the grounding network. Due to the asymmetrical configuration of the first grounding structure Gn with a narrower gap and a wider grounding width, its shielding effectiveness against strong near-field interference is more prominent. Therefore, the adjacent arrangement of the optical engine 5 and the first grounding structure Gn further enhances the physical proximity effect of the shielding structure on the interference source, reducing the chance of electromagnetic radiation laterally coupling to the transmission structure. At the same time, noise-sensitive devices such as the integrated circuit chip 4 can be arranged in the second side region away from the optical engine 5. The relatively wide gap and narrow grounding layout of the second grounding structure Gf provides more wiring space, and due to the enhanced shielding effect of the first side, the electromagnetic environment in the second side region is cleaner, which is beneficial to ensuring the accuracy and stability of the integrated circuit chip 4 in transmitting and receiving signals. In this way, the packaging layout of the optical engine 5 adjacent to the first grounding structure Gn and the shielding characteristics of the asymmetric co-layer shielding structure in the interposer layer work together to suppress unilateral electromagnetic interference from both the packaging level and the interconnection level, further improving the overall anti-interference performance and signal integrity of the optoelectronic co-package in the 224G PAM4 / 6 ultra-high-speed signal transmission scenario.

[0100] Performance Comparison

[0101] The following comparative implementation further illustrates the beneficial effects of the technical solution of this application. In the comparative experiment, the control group used an existing symmetrical shielding structure, while the example group used the asymmetrical same-layer shielding structure of this application with 3 redistribution layers and 4 same-layer conductors. The test results are shown in Table 1 below: Table 1

[0102]

[0103] As can be seen from Table 1 above, the asymmetric co-layer shielding structure of this application is significantly superior to the existing symmetric shielding structure in terms of shielding efficiency, impedance stability, crosstalk suppression and electromagnetic loss, and is especially suitable for scenarios where the 224G PAM4 / 6 CPO optoelectronic co-package has extremely high requirements for signal integrity.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An asymmetric in-layer shielding structure for optoelectronic co-packaging, applied in the redistribution layer of the optoelectronic co-packaging interposer, characterized in that, include: A transmission structure used to transmit signals; A shielding unit is disposed coplanarly with the transmission structure in the same redistribution layer. The shielding unit includes a first grounding structure located on a first side of the transmission structure and a second grounding structure located on a second side of the transmission structure. The first grounding structure and the second grounding structure are asymmetrical structures so that the shielding effectiveness of the first side against electromagnetic interference is stronger than that of the second side. The size parameters of the shielding unit meet the preset target value condition of the characteristic impedance of the transmission structure.

2. The asymmetric in-layer shielding structure for optoelectronic co-packaging according to claim 1, characterized in that, A first gap is provided between the first grounding structure and the transmission structure, and a second gap is provided between the second grounding structure and the transmission structure. The width of the first gap is smaller than the width of the second gap, and the width of the first grounding structure is larger than the width of the second grounding structure.

3. The asymmetric in-layer shielding structure for optoelectronic co-packaging according to claim 2, characterized in that, The sum of the width of the first gap and the width of the first grounding structure is equal to the sum of the width of the second gap and the width of the second grounding structure.

4. The asymmetric in-layer shielding structure for optoelectronic co-packaging according to claim 1, characterized in that, The optoelectronic co-encapsulation interposer includes multiple redistribution layers spaced apart along the thickness direction. The shielding unit is disposed in at least two redistribution layers. Along the thickness direction, at least one of the following dimensional parameters in different redistribution layers—the width of the first gap between the first grounding structure and the transmission structure, the width of the second gap between the second grounding structure and the transmission structure, the width of the first grounding structure, and the width of the second grounding structure—shows a gradual change.

5. The asymmetric in-layer shielding structure for optoelectronic co-packaging according to claim 4, characterized in that, From the first redistribution layer near the chip connection side to the second redistribution layer near the substrate connection side, the width of the first gap increases layer by layer, the width of the first ground structure decreases layer by layer, the width of the second gap decreases layer by layer, and the width of the second ground structure increases layer by layer.

6. A photoelectric co-encapsulation interposer layer, comprising multiple redistribution layers spaced apart along the thickness direction, wherein an insulating layer is provided between adjacent redistribution layers; characterized in that, At least two of the redistribution layers are respectively provided with asymmetric co-layer shielding structures, the asymmetric co-layer shielding structures comprising: A transmission structure used to transmit signals; A shielding unit is disposed on the same redistribution layer as the transmission structure. The shielding unit includes a first grounding structure located on a first side of the transmission structure and a second grounding structure located on a second side of the transmission structure. The first grounding structure and the second grounding structure are asymmetrical structures so that the shielding effectiveness of the first side against electromagnetic interference is stronger than that of the second side. Along the thickness direction, the dimensional parameters of the asymmetric co-layer shielding structure in different redistribution layers show a gradual trend.

7. An optoelectronic co-packaging interposer, comprising: Matrix; A multi-layer redistribution layer is disposed within the matrix, and an insulating layer is provided between adjacent redistribution layers; Wherein, at least one of the redistribution layers includes an asymmetric in-layer shielding structure for optoelectronic co-packaging as described in any one of claims 1 to 5.

8. The optoelectronic co-packaging interposer layer according to claim 6 or 7, characterized in that, It also includes a grounding vertical interconnect structure that extends along the thickness direction and is electrically connected to the first grounding structure and / or the second grounding structure in at least two redistribution layers.

9. A semiconductor package, comprising: Optoelectronic co-encapsulation intermediary layer as described in any one of claims 6 to 8; At least one optical engine is electrically connected to the first surface of the optoelectronic co-encapsulation interlayer; At least one integrated circuit chip is electrically connected to the first surface of the opto-co-encapsulation interposer layer; The packaging substrate is electrically connected to the second surface of the optoelectronic co-encapsulation interposer, and the second surface is opposite to the first surface.

10. The semiconductor package according to claim 9, characterized in that, The connection between the optical engine and the optoelectronic co-encapsulation interlayer is located on the side where the first grounding structure is located.

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