A silicon carbide mosfet layout structure having a stepped source doping region

Abstract

This invention discloses a silicon carbide MOSFET layout structure with a stepped source doped region, comprising multiple planar gate MOSFET cells. Each planar gate MOSFET cell includes a source doped region, a body contact doped region, a gate structure, and a source ohmic contact hole. The source doped regions are arranged in a stepped manner along the cell width direction and form at least one groove structure. The body contact doped regions are spaced apart within the grooves formed by the source doped regions. The length direction of the gate structure is consistent with the length direction of the cell and is periodically spaced along the width direction of the cell. The source ohmic contact holes are located within the grooves and distributed along the length direction of the cell. This invention aims to reduce the on-resistance of the device by effectively reducing the cell width, thereby increasing the channel density and reducing the on-resistance.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, specifically to a layout structure design of a silicon carbide power MOSFET, and more particularly to a planar gate silicon carbide MOSFET layout structure that reduces the size of the source ohmic contact hole, lowers the cell width, and increases the channel density through a stepped source doped region layout. Background Technology

[0002] Silicon carbide, as a third-generation semiconductor material, has excellent properties such as wide bandgap, high breakdown electric field, high thermal conductivity and high electron saturation drift velocity. As a result, power MOSFET devices based on silicon carbide materials have shown significant advantages over traditional silicon-based power devices in high-voltage, high-temperature and high-frequency applications. They have been widely used in new energy vehicles, power electronic converters, photovoltaic grid connection and rail transportation.

[0003] Currently, silicon carbide MOSFETs mainly include planar gate structures and trench gate structures. Among them, planar gate silicon carbide MOSFETs still occupy an important position in engineering applications due to their mature process and high gate oxide reliability. However, due to their cell structure, the channel density of planar gate silicon carbide MOSFETs is relatively limited, and there is still room for further reduction in their on-resistance.

[0004] See Figure 1 Traditional planar gate silicon carbide MOSFETs have a strip-shaped cell structure consisting of a source n+ doped region 1, a p+ body contact doped region 2, a source ohmic contact 3, and a gate structure 4. The source n+ doped region 1 and the p+ body contact doped region 2 are typically arranged side-by-side along the cell width direction (wcell). The source ohmic contact 3 needs to simultaneously cover the side-by-side "n+ source doped region – p+ body contact doped region – n+ source doped region" structure. To ensure reliable ohmic contact even with lithographic alignment errors, the source ohmic contact 3 needs to be designed with a large lateral dimension, resulting in an increased cell width and a reduced number of cells that can be arranged per unit chip area, ultimately limiting further reductions in the device's on-resistance. If the cell width is reduced simply by shrinking the size of the ohmic contact 3, the lithographic alignment accuracy needs to be significantly improved, increasing manufacturing costs and process complexity.

[0005] Therefore, how to reduce the cell width and increase the channel density of planar gate silicon carbide MOSFETs by optimizing the layout structure of the source doping region and the bulk contact doping region without significantly increasing the process complexity and photolithography precision requirements is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] To address the aforementioned shortcomings of existing technologies, the present invention aims to provide a silicon carbide MOSFET layout structure with a stepped source doped region, which aims to reduce the on-resistance of the device. Without changing the existing device process flow and photolithography alignment accuracy requirements, it effectively reduces the cell width, thereby increasing the channel density and reducing the on-resistance.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: a silicon carbide MOSFET layout structure with a stepped source doped region, comprising a silicon carbide substrate, and a plurality of planar gate MOSFET cells on the silicon carbide substrate, wherein the planar gate MOSFET cells include a source doped region, a body contact doped region, a drift region, a gate structure, and a source ohmic contact hole; characterized in that:

[0008] The source doped region is an n+ type doped region, and it is arranged in a stepped manner along the cell width direction, and has at least one groove structure.

[0009] The bulk contact doped region is a p+ type doped region, which is distributed at intervals within the groove formed by the source doped region;

[0010] The gate structure is a polysilicon gate strip region. The length direction of the polysilicon gate strip region is consistent with the length direction of the cell, and it is periodically distributed along the width direction of the cell and located between the source doped regions of adjacent cells.

[0011] The source ohmic contact hole is located in the groove and distributed along the cell length direction. Its lateral dimension meets the ohmic contact requirements with the n+ source doped region and enables electrical connection to the p+ bulk contact doped region to be realized simultaneously within the same ohmic contact hole.

[0012] Furthermore, the stepped source doped region is composed of multiple n+ source doped sub-regions that are staggered along the cell length direction.

[0013] Furthermore, the source ohmic contact hole has a continuous strip-shaped hole structure.

[0014] Furthermore, the source doped region and the bulk contact doped region are alternately distributed along the length direction of the source ohmic contact hole.

[0015] Furthermore, the polysilicon gate region is disposed above the gate oxide layer on the surface of the P-type body region, and is used to form a channel between the source doped region and the drift region.

[0016] Compared with the prior art, the present invention has the following advantages:

[0017] 1. This solution redesigns the arrangement of the n+ source doped region and the p+ body contact doped region in the planar direction. The n+ source doped region is designed as a stepped layout, and the p+ body contact doped region is set in the stepped groove. This changes the spatial relationship between the n+ source doped region and the p+ body contact doped region and the source metal ohmic contact hole, thereby reducing the lateral dimension required for the source ohmic contact hole and reducing the cell width.

[0018] 2. Through the above structural design, the lateral dimension of the source ohmic contact hole only needs to meet the requirement of forming a reliable ohmic contact with the n+ source doped region, so as to simultaneously realize the electrical connection to the p+ body contact doped region. Under the premise of ensuring a reliable short circuit between the source and the body region, the lateral dimension of the source ohmic contact hole is significantly reduced.

[0019] 3. The reduction in the lateral dimension of the source ohmic contact hole further reduces the cell width Wcell, increases the channel density per unit chip area, thereby effectively reducing the on-resistance of the planar gate silicon carbide MOSFET and improving the current carrying capacity of the device.

[0020] 4. The present invention achieves the above-mentioned technical effects only through planar layout optimization, without introducing new process steps or improving photolithography alignment accuracy. It is compatible with existing planar gate silicon carbide MOSFET manufacturing processes and has good engineering feasibility and application value. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the planar structure of the existing technology layout.

[0022] Figure 2 This is a schematic diagram of the planar structure of the present invention.

[0023] Figure 2 In the middle: 1—n+ source doped region, 2—p+ bulk contact doped region, 3—source ohmic contact hole, 4—polysilicon gate strip region. Detailed Implementation

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0026] It should be noted that similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the figures, or the orientation or positional relationship commonly used when the product is in use. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance. In addition, the terms "horizontal," "vertical," etc., do not indicate that the component is required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted. In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0027] Regarding some of the technical terms used in this solution:

[0028] Source doped region (n+ source doped region): refers to the n-type heavily doped region located in the source region with a doping concentration higher than that in the channel region. It is used to form a low-resistance ohmic contact with the source metal to realize the injection and collection of charge carriers.

[0029] Bulk contact doped region (p+ doped region): refers to the heavily p-type doped region set on the surface of the p-type bulk region, used to form an ohmic contact with the source metal, thereby realizing a reliable short circuit between the bulk region and the source, and suppressing the bulk potential drift and parasitic effects.

[0030] Stepped source doped region: This refers to a layout structure in which the source n+ doped regions are no longer arranged side by side along the cell width direction in the planar direction, but instead form a stepped profile through multiple staggered n+ doped sub-regions, thereby forming at least one stepped groove or "staircase hole" in the plane.

[0031] The drift region is a lightly doped epitaxial layer (usually n⁻ region) located between the channel region and the drain in a silicon carbide MOSFET. Its main function is to bear most of the drain-source voltage and determine the voltage withstand capability of the device when the device is off, and to serve as part of the current transport path when the device is on.

[0032] Stepped groove (staircase hole): refers to a localized recessed area formed by a stepped source doped region in a planar layout. This area is used to accommodate the body contact doped region, so that the source doped region and the body contact doped region are arranged sequentially in the planar direction along the extension direction of the ohmic contact hole.

[0033] A source ohmic contact hole (or simply ohmic hole) is an opening structure formed in an insulating dielectric layer (such as an interlayer dielectric or oxide layer) between the source metal layer and the semiconductor surface. This opening structure is formed by etching, allowing the source metal to pass through the dielectric layer and form an electrical connection with the underlying source doped region and / or body contact doped region, thereby constituting an ohmic contact.

[0034] The parallel “nplus–pplus–nplus” structure refers to the layout structure in the prior art where the source n+ doped region and the p+ body contact doped region are arranged side by side along the cell width direction, and multiple doped regions need to be covered by the same ohmic contact hole in the lateral direction.

[0035] Channel density refers to the number of effective channels that can be formed per unit chip area, and its size is inversely proportional to the cell width. Increasing channel density helps reduce the on-resistance of devices.

[0036] Example: See Figure 2 A silicon carbide MOSFET layout structure with a stepped source doped region includes a silicon carbide substrate and multiple planar gate MOSFET cells on the silicon carbide substrate, the multiple planar gate MOSFET cells being periodically arranged in a planar direction. Each planar gate MOSFET cell includes a source doped region, a body contact doped region, a drift region, a gate structure, and a source ohmic contact hole 3.

[0037] The source doped region is an n+ type doped region (n+ source doped region 1), and it is arranged in a stepped manner along the cell width direction, forming at least one groove structure or "staircase hole". In practice, the stepped source doped region is composed of multiple n+ source doped sub-regions that are staggered along the cell length direction.

[0038] The bulk contact doped region is a p+ type doped region (p+ bulk contact doped region 2), which is spaced apart within the groove formed by the source doped region; it is used to achieve a reliable short circuit between the p-type bulk region and the source. In implementation, the p+ bulk contact doped region 2 is disposed within the stepped groove formed by the stepped n+ source doped region 1, so that the p+ bulk contact doped region 2 is embedded in the n+ source doped region 1 in the planar direction. With the above arrangement, the n+ source doped region 1 and the p+ bulk contact doped region 2 are no longer distributed side by side along the cell width direction, but are arranged sequentially along the strip extension direction of the source ohmic contact hole 3.

[0039] The gate structure is a polysilicon gate strip region 4. The length direction of the polysilicon gate strip region 4 is consistent with the length direction of the cell, and it is periodically spaced along the width direction of the cell, located between the source doped regions of adjacent cells. The polysilicon gate strip region 4 is disposed above the gate oxide layer on the surface of the P-type body region, and is used to form a channel between the source doped region and the drift region.

[0040] The source ohmic contact hole 3 is located within the groove of the n+ source doped region 1 and distributed along the cell length direction. The source ohmic contact hole 3 is disposed in the dielectric layer and is used to achieve electrical connection between the source metal and the underlying doped region. The source ohmic contact hole 3 is a continuous strip-shaped hole structure; its lateral dimension meets the ohmic contact requirements with the n+ source doped region 1 and allows simultaneous electrical connection to the p+ body contact doped region 2 within the same ohmic contact hole. In this embodiment, body contact doped regions (p+) are arranged at intervals within the groove region of the n+ source doped region 1, while source doped regions (n+) are located on both sides of the groove. Therefore, by placing the ohmic contact hole within the groove, the same contact hole can simultaneously form electrical connections with both the source n+ doped region and the body contact p+ doped region, thereby achieving a reliable short circuit between the source metal and the body region. Specifically, the ohmic contact hole has a strip-shaped opening structure in the plan view, extending along the cell length direction and having a finite dimension in the cell width direction. The lateral dimension refers to the size of the strip-shaped opening in the cell width direction.

[0041] In practice, the source doped region and the body contact doped region are alternately distributed along the length of the source ohmic contact hole 3. Since the n+ source doped region 1 and the p+ body contact doped region 2 are arranged sequentially along the extension direction of the ohmic contact hole, the size of the source ohmic contact hole 3 in the lateral direction only needs to meet the requirement of forming a reliable ohmic contact with the n+ source doped region 1, so that the electrical connection to the p+ body contact doped region 2 can be achieved simultaneously within the same ohmic contact hole.

[0042] Through the above structural design, while ensuring a reliable short circuit between the source and the body region, the size of the source ohmic contact hole 3 in the cell width direction is significantly reduced, thereby reducing the width Wcell of a single cell. The reduction in cell width allows for the arrangement of more planar gate MOSFET cells within the same chip area, increasing channel density and thus reducing the on-resistance of the device.

[0043] This implementation method only involves the optimization of the source region layout in the planar direction. It is achieved by setting up a stepped source doped region and a bulk contact doped region without changing the existing planar gate silicon carbide MOSFET process flow or increasing the photolithography alignment accuracy requirements. It has good process compatibility and engineering feasibility.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A silicon carbide MOSFET layout structure with a stepped source doped region, comprising a silicon carbide substrate, a plurality of planar gate MOSFET cells on the silicon carbide substrate, wherein the planar gate MOSFET cells include a source doped region, a body contact doped region, a drift region, a gate structure, and a source ohmic contact hole; characterized in that: The source doped region is an n+ type doped region, and it is arranged in a stepped manner along the cell width direction, and has at least one groove structure. The bulk contact doped region is a p+ type doped region, which is distributed at intervals within the groove formed by the source doped region; The gate structure is a polysilicon gate strip region. The length direction of the polysilicon gate strip region is consistent with the length direction of the cell, and it is periodically distributed along the width direction of the cell and located between the source doped regions of adjacent cells. The source ohmic contact hole is located in the groove and distributed along the cell length direction. Its lateral dimension meets the ohmic contact requirements with the n+ source doped region and enables electrical connection to the p+ bulk contact doped region to be realized simultaneously within the same ohmic contact hole.

2. The silicon carbide MOSFET layout structure with a stepped source doped region according to claim 1, characterized in that: The stepped source doped region is composed of multiple n+ source doped sub-regions that are staggered along the length of the cell.

3. The silicon carbide MOSFET layout structure with a stepped source doped region according to claim 1, characterized in that: The source ohmic contact hole has a continuous strip-shaped hole structure.

4. The silicon carbide MOSFET layout structure with a stepped source doped region according to claim 1, characterized in that: The source doped region and the bulk contact doped region are alternately distributed along the length of the source ohmic contact hole.

5. A silicon carbide MOSFET layout structure with a stepped source doped region according to claim 1, characterized in that: The polysilicon gate region is disposed above the gate oxide layer on the surface of the P-type body region and is used to form a channel between the source doped region and the drift region.

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