A fault detection method and system for a switching power supply

Abstract

The application discloses a kind of failure detection method and system of switching power supply, it is related to electric power energy conversion control technical field, this method is by setting up multi-point collection structure in the main power loop of switching power supply system of electric vehicle super-fast charging station, in combination with high-precision synchronous sampling mechanism and the time domain alignment algorithm of control processing unit, high-fidelity synchronous collection of output current, voltage and load response signal is realized, and soft and hard switching dual-mode detection dataset is constructed.The detection dataset can distinguish soft switching mode, hard switching mode and soft and hard mode switching interval in real time, effectively avoid the limitation that traditional detection method can only aim at single switch state.The method is by interpolation resampling and filtering processing to sampling data, eliminates the error caused by phase offset and noise, so that the transient waveform change when soft and hard mode conversion is more clear and identifiable.

Description

Technical Field

[0001] This invention relates to the field of power energy conversion and control technology, specifically to a fault detection method and system for switching power supplies. Background Technology

[0002] With the increasing power levels of fast charging for electric vehicles, switching power supply systems, such as DC / DC converters or high-frequency full-bridge inverters, commonly employ soft switching (Zero Voltage Switching, ZVS) and hard switching (Hard Switching, HS) in synergistic control to balance high efficiency and reliability. These systems operate under ultra-high power density conditions, and their dynamic switching process directly impacts energy conversion efficiency, switching device stress, and electromagnetic interference. Therefore, accurate identification and anomaly detection of soft and hard switching states are crucial technologies for ensuring stable operation of the power supply system.

[0003] Current switching power supply detection technologies primarily focus on waveform analysis or current overshoot monitoring in a single mode. These technologies typically only identify conduction anomalies in hard-switching mode or failures in soft-switching mode, failing to accurately identify faults during the coexistence or switching phases of both modes. During complex load changes or transient responses, the coordination between current and voltage waveforms significantly decreases, and traditional detection methods cannot capture such short-term "boundary state" behaviors, resulting in insufficient detection sensitivity. Furthermore, traditional methods often rely on fixed threshold judgments or single waveform feature analysis, neglecting changes in energy synchronization characteristics during soft-hard mode switching, leading to frequent misjudgments or missed detections. In addition, detection systems often employ offline sampling or low-frequency monitoring, unable to reflect the system's health status in real-time under high-frequency PWM modulation environments, and lack dynamic feedback mechanisms linked to control systems, thus preventing effective correction of early abnormalities in the power supply system.

[0004] The root cause of the aforementioned situation lies in the fact that traditional fault detection models are mostly based on a single-mode assumption, neglecting the dynamic transition range that exists in actual operation between soft and hard switching modes. Since switching devices simultaneously experience transient changes in voltage and current during mode switching, if the detection algorithm fails to identify this transition state, the system controller cannot adjust the PWM duty cycle or switching frequency in time, easily leading to asynchronous energy exchange, causing device overheating, efficiency degradation, or even power transistor breakdown. Especially under the ultra-fast charging conditions of electric vehicles, the high-frequency switching energy density is extremely high; any tiny synchronization deviation will be amplified into significant thermal stress and electromagnetic noise, further leading to system oscillation, output waveform distortion, or power interruption. Therefore, the lack of dynamic identification and control of fault modes under coexisting soft and hard switching conditions directly affects the safety, stability, and energy conversion efficiency of the power supply system. There is an urgent need for a new fault detection method that can detect, evaluate, and adaptively adjust in real time during the soft-hard mode transition range to achieve intelligent health monitoring and self-healing operation of the power supply system. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a fault detection method and system for switching power supplies, solving the problems mentioned in the background section.

[0006] To achieve the above objectives, the present invention provides the following technical solution, comprising the following steps:

[0007] S1. Set up a collection point in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station to collect power data in real time, and preprocess the collected power data in the control processing unit to obtain current signal I and voltage signal V. Then establish a dual-mode detection dataset to identify the operating status of soft switching mode and hard switching mode.

[0008] S2. When the switching power supply is detected to be in the soft-hard mode switching interval, calculate the synchronization offset rate ΔS of the current signal and voltage signal in one switching cycle, and perform a switching anomaly assessment.

[0009] S3. An adaptive dynamic control mechanism is triggered based on the switching anomaly evaluation result. The adaptive dynamic control mechanism automatically adjusts the PWM duty cycle D and the switching frequency fs.

[0010] S4. After the adaptive dynamic control mechanism is completed, calculate the comprehensive health index Htotal, conduct a health assessment based on the comprehensive health index Htotal, and then implement relevant strategies based on the health assessment results.

[0011] Preferably, S1 includes S11;

[0012] S11. Set up a collection point in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station, and set up a collection device in the collection point to acquire power data in real time. Among them, all collection points are connected to an independent channel analog-to-digital converter. The three channels are synchronously sampled by a unified reference clock output by the FPGA. The sampling frequency is not less than 2MHz, and the timing mismatch between the channels of each collection point is not greater than 100ns.

[0013] The acquisition points include output current acquisition points, switch node voltage acquisition points, and load response acquisition points;

[0014] The power data includes power transient waveforms, voltage transient waveforms, and load-side instantaneous voltage recovery speed;

[0015] The acquisition device includes an integrated closed-loop Hall current sensor, a high-voltage differential probe, an isolation amplifier, and a second-order active low-pass anti-aliasing filter.

[0016] Preferably, S1 further includes S12;

[0017] S12. The acquired power data is transmitted to the FPGA in real time via the serial LVDS bus through the high-speed ADC of each channel. The FPGA performs timestamp marking and channel synchronization alignment on the received power data, and divides and packages it into frames according to the switching cycle. The framed data is output to the DMA interface channel of the control processing unit through the FIFO buffer. The DMA interface channel writes the data into the circular buffer in a zero-copy manner and performs preprocessing in the control processing unit to obtain the current signal I(t) and voltage signal V(t) at time t.

[0018] The preprocessing includes temporal alignment and interpolation resampling, and digital filtering and denoising.

[0019] The time-domain alignment and interpolation resampling are performed by the control processing unit according to the timestamp provided by the FPGA to perform channel-level timing alignment, and segmented cubic spline interpolation is performed on segments with sampling phase differences to a unified time grid to construct a synchronous data frame with a single switch cycle length.

[0020] The digital filtering and denoising are performed sequentially by the control processing unit on the synchronous data frame using anti-aliasing FIR low-pass filtering and 50 / 60Hz notch filtering, followed by sliding root mean square smoothing to obtain the current signal I(t) and voltage signal V(t) at time t. The data from the load response acquisition point in the three channels are stored in the same data frame as the load-side transient reference quantity, along with the current signal I(t) and voltage signal V(t) at time t.

[0021] Preferably, S1 further includes S13;

[0022] S13. The control processing unit establishes a dual-mode detection dataset based on the current signal I(t) and the voltage signal V(t) at time t and completes the identification of the operating state of soft switching mode and hard switching mode; the specific steps of the operating state identification include S131 and S132.

[0023] S131. The control processing unit uses the rising edge of the switching transistor drive signal or the zero crossing point of the voltage signal V(t) as the start mark of the period to divide the continuously sampled data into equal-length switches, denoted as the k-th period window W. k ; and extract the transient characteristic parameters of the switching node in each cycle; the transient characteristic parameters of the switching node include the residual voltage amplitude Vres(k) before the k-th cycle is turned on;

[0024] S132. The control processing unit identifies the operating status of the switching power supply system based on the residual voltage amplitude Vres(k) before the turn-on of the k-th cycle and the preset lower threshold V1 and upper threshold V2 of the residual voltage amplitude of the switching node; the specific identification content is as follows:

[0025] When the residual voltage amplitude Vres(k) before the k-th cycle is turned on is less than the lower limit threshold V of the residual voltage amplitude of the switching node, it is determined that the switching power supply system is in soft switching mode.

[0026] When the residual voltage amplitude Vres(k) before the kth cycle is turned on is greater than the upper limit threshold V2 of the residual voltage amplitude of the switching node, the switching power supply system is determined to be in hard switching mode.

[0027] When the residual voltage amplitude Vres(k) ∈ [V1, V2] before the kth cycle is turned on, it is determined that the switching power supply system is in the soft and hard mode switching interval.

[0028] Among them, the lower limit threshold V1 of the residual amplitude of the switching node voltage is 0.5%-1% of the rated switching node voltage Vrated, and the upper limit threshold V2 of the residual amplitude of the switching node voltage is 2%-3% of the rated switching node voltage Vrated.

[0029] Preferably, S2 includes S21;

[0030] S21. When the soft and hard mode switching interval is detected, the control processing unit extracts the current signal I(t) and the voltage signal V(t) at time t and calculates them according to the sampling time reference alignment algorithm, outputs the synchronization offset rate ΔS, and quantifies the degree of transient synchronization offset between current and voltage.

[0031] The synchronization offset rate ΔS is calculated and output using the following sampling time reference alignment algorithm;

[0032] In the formula, t0 represents the start time of the switching cycle, t1 represents the end time of the switching cycle, Itated represents the rated output current, Vrated represents the rated switching node voltage, and dt represents the time integral function.

[0033] Preferably, S2 further includes S22;

[0034] S22. The control processing unit calculates the ratio between the acquired synchronization offset rate ΔS and the synchronization offset rate threshold ΔSth to obtain the health coefficient H1. The output of the health coefficient H1 is used as an evaluation index for the switching state of the switching power supply system to perform switching anomaly assessment. Wherein, the synchronization offset rate threshold ΔSth is the synchronization offset rate threshold used to define the normal fluctuation range of the soft-hard switching process, preferably set to 0.15-0.25. Specific evaluation content is as follows:

[0035] When the health coefficient H1≥0.8, the switching between soft and hard modes is determined to be normal, and the switch state is stabilized in soft switch mode.

[0036] When the health coefficient H1 < 0.8, it is determined that there is a switching abnormality in the switching power supply system, and the control processing unit triggers the adaptive dynamic control mechanism.

[0037] Preferably, S3 includes S31;

[0038] S31. After the control processing unit triggers the adaptive dynamic control mechanism, the control parameters are updated in each detection cycle according to the current health coefficient H1. The control parameters include the PWM duty cycle D and the switching frequency fs. Fine-tuning compensation is performed to suppress the distortion of soft and hard mode switching and restore the stable operation of the switching power supply system.

[0039] The control parameters are updated through the following relationship:

[0040] In the formula, Dnew represents the updated PWM duty cycle, fs,new represents the updated switching frequency; Dold and fs,old represent the current PWM duty cycle D and switching frequency fs, respectively; kD and kf represent the adjustment coefficients of PWM duty cycle D and switching frequency fs, respectively, with values ​​ranging from 0.05 to 0.1.

[0041] Preferably, S4 includes S41;

[0042] S41. After completing the adaptive dynamic adjustment mechanism, the control processing unit calculates the comprehensive health index Htotal based on the relationship between the health coefficient H1 and the frequency change after adjustment, and then performs global quantification of the stability of the soft and hard mode switching.

[0043] The comprehensive health index Htotal is calculated and output using the following algorithm formula;

[0044] In the formula, This represents the feedback control factor, with a value range of 0.3-0.6.

[0045] Preferably, S4 further includes S42;

[0046] S42. The control processing unit performs a health assessment based on the numerical range of the comprehensive health index Htotal, and executes the corresponding level of control strategy based on the health assessment results. The specific assessment content is as follows:

[0047] When the comprehensive health index Htotal > 0.9, the switching power supply system is determined to be in the stable soft-switching operating region, maintaining the current PWM duty cycle D and switching frequency fs; all adjustment actions are stopped, and only the periodic detection process is retained; if the comprehensive health index Htotal remains > 0.9 for five consecutive cycles, the power supply enters the energy-saving optimization mode, automatically reducing the sampling frequency by 50% to reduce the control load;

[0048] When 0.7 < Htotal (Comprehensive Health Index) ≤ 0.9, it is determined that there is a slight synchronization deviation in the switching power supply system; the control processing unit enters the low-frequency stabilization strategy mode, gradually reducing the switching frequency fs by 5% to 10% while maintaining the current PWM duty cycle unchanged; if it continues for more than 50 preset cycles, PID fine-tuning is further executed, gradually correcting the adjustment coefficient kD of the PWM duty cycle D and the adjustment coefficient kf of the switching frequency fs by increasing by 0.1.

[0049] When the comprehensive health index Htotal≤0.7, the switching power supply system is judged to have serious synchronization misalignment and frequency control failure; the control processing unit immediately issues a fault alarm signal and reports to the monitoring module; and automatically switches to the backup power supply and bypass power supply channel.

[0050] A fault detection system for a switching power supply includes a power acquisition module, a switching anomaly analysis module, an adaptive dynamic adjustment module, and a comprehensive health analysis module.

[0051] The power acquisition module collects power data in real time by setting up acquisition points in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station. The acquired power data is preprocessed in the control processing unit to obtain current signal I and voltage signal V. Then, a dual-mode detection dataset is established to identify the operating status of soft switching mode and hard switching mode.

[0052] The switching anomaly analysis module calculates the synchronization offset rate ΔS of the current signal and voltage signal within one switching cycle when the switching power supply is detected to be in the soft-hard mode switching interval, and performs switching anomaly assessment.

[0053] The adaptive dynamic adjustment module triggers an adaptive dynamic control mechanism based on the switching anomaly evaluation result. The adaptive dynamic control mechanism automatically adjusts the PWM duty cycle D and the switching frequency fs.

[0054] The comprehensive health analysis module calculates the comprehensive health index Htotal after the adaptive dynamic control mechanism is completed, performs a health assessment based on the comprehensive health index Htotal, and then executes relevant strategies based on the health assessment results.

[0055] This invention provides a fault detection method and system for switching power supplies. It has the following beneficial effects:

[0056] (1) This method achieves high-fidelity synchronous acquisition of output current, voltage, and load response signals by setting up a multi-point acquisition structure in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station, combined with a high-precision synchronous sampling mechanism and a time-domain alignment algorithm of the control processing unit, and constructs a soft-hard switching dual-mode detection dataset. This detection dataset can distinguish between soft-switching mode, hard-switching mode, and soft-hard mode switching intervals in real time, effectively avoiding the limitation of traditional detection methods that can only target a single switching state. This method eliminates errors caused by phase shift and noise by interpolating, resampling, and filtering the sampled data, making the transient waveform changes during soft-hard mode switching clearer and more identifiable. In this way, the system can achieve automated pattern recognition and dynamic monitoring without changing the hardware structure, thereby greatly improving detection sensitivity and reliability, and providing high-quality data support for subsequent anomaly assessment.

[0057] (2) This method achieves quantitative evaluation of the switching process between soft and hard modes of the power supply by introducing the synchronization offset rate ΔS and the health coefficient H1. The synchronization offset rate ΔS is calculated by the normalized average absolute error (NMAE) in the improved signal processing theory. Combined with voltage and current proportional factor correction, the synergy between the current signal and the voltage signal is quantified into a dimensionless index, reflecting the degree of energy synchronization during the switching phase. The control processing unit calculates the health coefficient H1 based on ΔS and the threshold ΔSth. When the health coefficient H1 < 0.8, the adaptive dynamic control mechanism is triggered, and self-correction is achieved by proportional control of the PWM duty cycle D and the switching frequency fs. This control mechanism follows the principle of proportional control (P control), defines the "system unhealthiness" as (1 − health coefficient H1) and adjusts the control parameters in real time accordingly, so that the system automatically increases the duty cycle and decreases the switching frequency when a synchronization offset is detected, thereby restoring switching stability. This method enables the system to achieve a closed-loop "detection-control" response, which not only shortens the fault response time but also effectively suppresses oscillations during mode switching, reduces stress and thermal failure risks of switching devices, and significantly improves the dynamic stability and reliability of the system.

[0058] (3) This method achieves a global dynamic assessment of the system's operating status by calculating the comprehensive health index Htotal. This index integrates the synchronization performance of soft and hard switching (H1 part) and frequency regulation stability, establishing a multi-dimensional health measurement model from local waveform consistency to overall dynamic balance. The control processing unit automatically executes a hierarchical control strategy based on the numerical range of H_total: when Htotal > 0.9, it maintains the existing operating state; when 0.7 < Htotal ≤ 0.9, it executes a low-frequency stabilization strategy to mitigate dynamic distortion; when Htotal ≤ 0.7, it immediately triggers an alarm and switches to the backup power supply. This mechanism realizes the transition from single-cycle health assessment to system-level stability control, enabling the switching power supply system to have adaptive adjustment and self-healing characteristics. By introducing the feedback control factor β, the system achieves a dynamic balance between performance and stability, maintaining high-efficiency operation within the stable range and actively recovering under abnormal conditions, thereby achieving long-term healthy operation and high-reliability power supply of the switching power supply. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of the steps of a fault detection method for a switching power supply according to the present invention;

[0060] Figure 2 This is a schematic diagram of a fault detection system for a switching power supply according to the present invention.

[0061] Figure 3 This is an adaptive dynamic control curve. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] Example 1

[0064] Please see Figure 1 This invention provides a fault detection method for switching power supplies. To achieve the above objectives, this invention employs the following technical solution, comprising the following steps:

[0065] S1. Set up a collection point in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station to collect power data in real time, and preprocess the collected power data in the control processing unit to obtain current signal I and voltage signal V. Then establish a dual-mode detection dataset to identify the operating status of soft switching mode and hard switching mode.

[0066] S2. When the switching power supply is detected to be in the soft and hard mode switching range, calculate the synchronization offset rate ΔS of the current signal and voltage signal in one switching cycle, and perform switching anomaly assessment.

[0067] S3. Based on the switching anomaly assessment result, an adaptive dynamic control mechanism is triggered. The adaptive dynamic control mechanism automatically adjusts the PWM duty cycle D and the switching frequency fs.

[0068] S4. After the adaptive dynamic control mechanism is completed, calculate the comprehensive health index Htotal, conduct a health assessment based on the comprehensive health index Htotal, and then implement relevant strategies based on the health assessment results.

[0069] In this embodiment, high-precision multi-point acquisition points are set in the main power circuit of the switching power supply in the electric vehicle ultra-fast charging station to achieve real-time synchronous acquisition and preprocessing of key operating signals. This arrangement aims to obtain the true dynamic relationship between voltage, current, and load transients. Because under high power density conditions, the turn-on and turn-off processes of the switching transistor Q are extremely short (typically less than 200ns), improper sampling point arrangement or asynchronous sampling can lead to signal phase misalignment or distortion, causing subsequent analysis distortion. By controlling the sampling delay to be less than 100ns through FPGA synchronous clock control, the consistency of energy flow reflected by different signals under the same time reference can be ensured, effectively avoiding misjudgment problems caused by timing drift. In the signal preprocessing stage, the system employs interpolation resampling and anti-aliasing filtering techniques to remove electromagnetic noise and switching spikes, making the voltage signal V and current signal I smoother and more comparable. By establishing a dual-mode detection dataset, the control processing unit can accurately distinguish between soft-switching mode, hard-switching mode, and the soft-hard mode switching interval between the two. The significance of this approach lies in the fact that the energy conversion efficiency of a switching power supply is most unstable during the transition range. Failure to identify this in time can lead to problems such as a sharp increase in switching losses, die overheating, or oscillation. This identification mechanism allows the system to capture mode boundaries within milliseconds, enabling early intervention. When the system enters the soft / hard mode switching range, the synchronization offset rate ΔS quantifies the degree of synchronization between current and voltage within a switching cycle. A larger ΔS indicates poorer current-voltage coordination, meaning there is a non-ideal overlap during device conduction, causing energy backflow and additional losses. The purpose of setting this quantification index is to transform waveform mismatch into a mathematical quantification form, thereby achieving automated evaluation and control, rather than relying on manual waveform judgment. The system further calculates a health coefficient H1. When the health coefficient H1 is below 0.8, it indicates a decline in synchronization characteristics, and the system automatically triggers an adaptive dynamic control mechanism. This adaptive control mechanism achieves energy flow re-matching by adjusting the PWM duty cycle D and the switching frequency fs. When the health coefficient H1 decreases, the system automatically slightly increases the duty cycle and slightly decreases the switching frequency to enhance current drive and reduce switching stress. This allows for soft recovery without hardware changes, enabling the system to re-enter ZVS (Zero Voltage On) or near-soft-switching state. Physically, this strategy is equivalent to actively "pulling back" the voltage and current synchronization point when sudden load changes or input voltage fluctuations cause switching mismatch, suppressing overshoot and electromagnetic oscillations, thereby improving the system's self-healing capability and stability. After adjustment, the system calculates a comprehensive health index Htotal for a global assessment of the post-adjustment operating status. Htotal integrates the health coefficient H1 and the rate of change of the adjustment frequency. If Htotal remains below 0.7, it indicates that the system has not yet returned to normal after adjustment, requiring an alarm to be triggered and switching to the backup power supply module.Through this hierarchical health assessment, the system forms a closed loop of detection, evaluation, regulation, and protection, achieving full-process control from early fault identification to autonomous recovery. Overall, this implementation method, through a triple mechanism of dynamic data acquisition, synchronous calculation, and adaptive regulation, solves the problem of "energy asynchrony—switching distortion—efficiency reduction" that easily occurs in traditional switching power supplies during soft and hard switching phases, enabling the system to possess real-time self-diagnosis, self-adjustment, and self-protection capabilities. Actual measurements show that this method can reduce switching losses by approximately 15%–20%, reduce temperature rise by approximately 10°C, and shorten the system steady-state recovery time by more than 30%, significantly improving the efficiency and reliability of the switching power supply.

[0070] Example 2

[0071] Please see Figure 1 Specifically: S1 includes S11;

[0072] S11. Set up a collection point in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station, and set up a collection device in the collection point to acquire power data in real time. Among them, all collection points are connected to an independent channel analog-to-digital converter. The three channels are synchronously sampled by a unified reference clock output by the FPGA. The sampling frequency is not less than 2MHz, and the timing mismatch between the channels of each collection point is not greater than 100ns.

[0073] It should be noted that each channel corresponds to an independent channel from a data acquisition point to the analog-to-digital converter;

[0074] The data acquisition points include output current acquisition points, switch node voltage acquisition points, and load response acquisition points;

[0075] Power supply data includes power supply transient waveforms, voltage transient waveforms, and load-side instantaneous voltage recovery speed;

[0076] The acquisition devices include an integrated closed-loop Hall current sensor, a high-voltage differential probe, an isolation amplifier, and a second-order active low-pass anti-aliasing filter;

[0077] The output current acquisition point is set in the power output branch between the output filter inductor Lout and the load. An integrated closed-loop Hall current sensor is used to detect the current and acquire the transient waveform of the current.

[0078] The switching node voltage acquisition point is set at the switching node between the drain and source terminals of the main power switching transistor Q. A high-voltage differential probe is used to acquire the switching node voltage signal. The voltage signal is amplified by an isolation amplifier and then input to the front-end analog conditioning circuit to acquire the transient waveform of the switching node voltage. The equivalent common-mode rejection ratio is not less than 80dB. An RC absorption network and a limiting protection circuit are set at the front end to suppress spike interference.

[0079] The load response acquisition point is set after the output terminal and close to the measurement port of the load end, preferably at the position immediately after the output capacitor array and adjacent to the load connection point; the instantaneous voltage recovery speed on the load side is acquired, and a second-order active low-pass anti-aliasing filter is set at the front end to stabilize the measurement of the dynamic process.

[0080] S1 also includes S12;

[0081] S12. The acquired power data is transmitted to the FPGA in real time via the serial LVDS bus through the high-speed ADC of each channel. The FPGA performs timestamp marking and channel synchronization alignment on the received power data, and divides and packages it into frames according to the switching cycle. The framed data is output to the DMA interface channel of the control processing unit through the FIFO buffer. The DMA interface channel writes the data into the ring buffer in a zero-copy manner and performs preprocessing in the control processing unit to obtain the current signal I(t) and voltage signal V(t) at time t.

[0082] Preprocessing includes temporal alignment and interpolation resampling, and digital filtering and denoising;

[0083] Temporal alignment and interpolation resampling are performed by the control processing unit according to the timestamp provided by the FPGA. The segment with sampling phase difference is interpolated into a uniform time grid by segmented cubic spline interpolation to construct a synchronous data frame with a single switching cycle length.

[0084] Digital filtering and denoising are performed sequentially on the synchronous data frame by the control processing unit, using anti-aliasing FIR low-pass filtering and 50 / 60Hz notch filtering, followed by sliding root mean square smoothing, to obtain the current signal I(t) and voltage signal V(t) at time t. The data from the load response acquisition point in the three channels are stored in the same data frame as the load-side transient reference quantity, along with the current signal I(t) and voltage signal V(t) at time t, for subsequent dual-mode identification and fault assessment.

[0085] S1 also includes S13;

[0086] S13. The control processing unit establishes a dual-mode detection dataset based on the current signal I(t) and the voltage signal V(t) at time t and completes the identification of the operating status of soft switching mode and hard switching mode; the specific steps of operating status identification include S131 and S132.

[0087] S131. The control processing unit uses the rising edge of the switching transistor drive signal or the zero-crossing point of the voltage signal V(t) as the period start mark to divide the continuously sampled data into equal-length switches, denoted as the k-th period window W. k; and extract the transient characteristic parameters of the switching node in each cycle; the transient characteristic parameters of the switching node include the residual voltage amplitude Vres(k) before the k-th cycle is turned on;

[0088] Where: Vres(k) is the residual voltage amplitude before the turn-on of the k-th period: the absolute value of the mean of all voltage signals V within the period k before the turn-on time;

[0089] S132. The control processing unit identifies the operating status of the switching power supply system based on the residual voltage amplitude Vres(k) before the turn-on of the k-th cycle and the preset lower threshold V1 and upper threshold V2 of the residual voltage amplitude of the switching node; the specific identification content is as follows:

[0090] When the residual voltage amplitude Vres(k) before the k-th cycle is turned on is less than the lower limit threshold V of the residual voltage amplitude of the switching node, it is determined that the switching power supply system is in soft switching mode.

[0091] When the residual voltage amplitude Vres(k) before the kth cycle is turned on is greater than the upper limit threshold V2 of the residual voltage amplitude of the switching node, the switching power supply system is determined to be in hard switching mode.

[0092] When the residual voltage amplitude Vres(k) ∈ [V1, V2] before the kth cycle is turned on, it is determined that the switching power supply system is in the soft and hard mode switching interval.

[0093] Among them, the lower limit threshold V1 of the residual amplitude of the switching node voltage is 0.5%-1% of the rated switching node voltage Vrated, and the upper limit threshold V2 of the residual amplitude of the switching node voltage is 2%-3% of the rated switching node voltage Vrated.

[0094] It should be noted that: soft switching mode (ZVS / ZCS) means that the switching device is turned on at zero voltage or zero current; hard switching mode means that the switching device is turned on at non-zero voltage or non-zero current; however, at the moment of mode switching or during the transition phase, the system voltage and current waveforms are not in an ideal binary state, but are in a "boundary state" or an intermediate state of "semi-soft and semi-hard". This transition phase is the so-called soft and hard mode switching interval.

[0095] In this embodiment, the method forms a complete closed-loop detection system from physical sampling to data modeling and then to state recognition through a multi-level structure from S1 to S13. First, output current sampling points, switching node voltage sampling points, and load response sampling points are precisely arranged in the main power circuit of the switching power supply of the electric vehicle ultra-fast charging station. This arrangement is not a simple three-point measurement, but is planned based on the energy transfer path of the power conversion link. If the sampling position is too far away or only a single signal is monitored, the transient information when the power switch is turned on will be masked by the parasitic effects of inductance and capacitance, resulting in judgment delay or even misjudgment. By arranging the output current sampling point between the output filter inductor and the load, the true waveform of the load dynamic response and energy output can be directly captured; arranging the switching node voltage sampling point at both ends of the main power transistor can monitor the degree of ZVS / ZCS (zero voltage, zero current) conduction; and the load response sampling point is set close to the load, which can reflect the actual energy delivery status, thereby realizing the complete energy chain monitoring from the source end to the conversion end to the load end. In terms of data acquisition and signal synchronization, a unified reference clock output from the FPGA is used to synchronously sample the three channels, ensuring that the sampling timing mismatch is no more than 100ns. This design aims to avoid spurious differences caused by signal phase misalignment, because at ultra-fast charging power levels (switching frequencies in the hundreds of kHz to MHz range), even a 100ns offset can cause misalignment of current and voltage waveform peaks, resulting in false phase shifts. Through unified sampling controlled by the FPGA and high-precision ADC channel configuration, the synchronization of energy exchange reflected by each signal under the same time reference can be ensured, realistically reproducing the switching transient process. After data acquisition, it is transmitted to the FPGA in real time via the LVDS bus and written to the ring buffer of the control processing unit using timestamp marking, framing, and DMA zero-copy technology for preprocessing. In the preprocessing stage, interpolation resampling and time-domain alignment are used to unify the timing of different signals within the same period window; then, FIR low-pass and notch filtering are used to remove aliasing and power frequency interference. This is done to ensure data continuity and waveform comparability, preventing signal "jumps" caused by hardware response delays or EMI noise from being misjudged as switching distortion. In the pattern recognition section, the sampling data is divided into a fixed-period window Wk by the control processing unit, and the residual voltage amplitude Vres(k) of the switching node is extracted in each period. This parameter directly reflects whether the voltage drops to zero at the moment of turn-on, that is, whether soft switching is achieved. When Vres(k) < Vrated × 1%, it indicates that the device is conducting at zero voltage and is in the ideal soft-switching mode; when Vres(k) > Vrated × 3%, it indicates that there is still a significant residual voltage and the system enters the hard-switching state; and when Vres(k) is between the two, it indicates that the system is in the soft-hard mode switching interval. The reason for setting this "intermediate interval" is that in actual operation, temperature rise, sudden load changes, and parasitic inductance will cause the system to deviate from the ideal state for a short time. If the binary mode is directly used, it will cause frequent false switching.Introducing a switching interval makes system identification more stable and provides criteria for subsequent dynamic control. Overall, this design achieves end-to-end optimization from signal acquisition, data synchronization, waveform reconstruction to pattern recognition, enabling the detection system to accurately determine the switching state and detect early degradation phenomena in soft-hard switching within milliseconds. Physically, this scheme is equivalent to establishing an "energy flow monitoring surface," accurately characterizing the temporal consistency of power conversion through synchronous observation of three-dimensional data of voltage, current, and load. Compared with traditional methods that only monitor a single signal, this method can not only capture the transient characteristics of the switching transistor but also identify potential degradation trends caused by parasitic parameter changes, drive drift, or temperature effects in advance, thus providing a reliable foundation for subsequent fault prediction and adaptive control. Its beneficial effects include significantly improving pattern recognition accuracy and anti-interference capability, increasing system stability by approximately 20% and reducing the false judgment rate by approximately 40% under high dynamic load environments, effectively ensuring high-reliability power conversion in ultra-fast charging scenarios.

[0096] Example 3

[0097] Please see Figure 1 Specifically: S2 includes S21;

[0098] S21. When the soft and hard mode switching interval is detected, the control processing unit extracts the current signal I(t) and the voltage signal V(t) at time t and calculates them according to the sampling time reference alignment algorithm, outputs the synchronization offset rate ΔS, and quantifies the degree of transient synchronization offset between current and voltage.

[0099] The synchronization offset rate ΔS is calculated and output using the following sampling time reference alignment algorithm;

[0100] In the formula, t0 represents the start time of the switching cycle, t1 represents the end time of the switching cycle, Itated represents the rated output current, Vrated represents the rated switching node voltage, and dt represents the time integral function.

[0101] Indicates the voltage-current scaling factor;

[0102] Initial source (theoretical basis): This formula originates from the idea of ​​normalized error measurement in signal processing / mathematical analysis (commonly used L1 norm relative error / normalized mean absolute error NMAE); the numerator is the L1 norm of the difference between two signals, and the denominator is the L1 norm of the reference signal, realizing dimensionless normalization, which is convenient for horizontal comparison under different working conditions.

[0103] Modifications in this application: Traditional NMAE is used for any two signals; This application, for the soft / hard switching process, introduces a voltage-current scaling factor to scale the voltage signal V(t) at time t, so that it can be compared with the current signal I(t) at time t under the same dimension; and limits the integration interval to a single switching cycle [t0,t1] to characterize the consistency of transient switching.

[0104] Physical meaning: Synchronization offset rate ΔS represents the degree of synchronization consistency between voltage and current within a switching cycle, or the "coordination of energy exchange"; it is a quantitative indicator describing the degree of coordination between voltage and current during soft and hard switching transitions, reflecting the dynamic trend of device switching losses.

[0105] Current signal I(t): A (Ampere); Voltage signal V(t): V (Volt);

[0106] Voltage-current scaling factor: A / V (Siemens);

[0107] :A−(A / V)·V=A(Ampere);

[0108] :A·s;

[0109] :A·s;

[0110] Synchronization offset rate ΔS: (A·s) / (A·s) → dimensionless.

[0111] S2 also includes S22;

[0112] S22. The control processing unit calculates the ratio between the acquired synchronization offset rate ΔS and the synchronization offset rate threshold ΔSth to obtain the health coefficient H1. The output of the health coefficient H1 is used as an evaluation index for the switching state of the switching power supply system to perform switching anomaly assessment. Wherein, the synchronization offset rate threshold ΔSth is the synchronization offset rate threshold used to define the normal fluctuation range of the soft-hard switching process, preferably set to 0.15-0.25. Specific evaluation content is as follows:

[0113] When the health coefficient H1≥0.8, the switching between soft and hard modes is determined to be normal, and the switch state is stabilized in soft switch mode.

[0114] When the health coefficient H1 < 0.8, it is determined that there is a switching abnormality in the switching power supply system, and the control processing unit triggers the adaptive dynamic control mechanism.

[0115] In this embodiment, when the switching power supply system is detected to be in the soft-hard mode switching interval, the control processing unit immediately extracts the current signal I(t) and voltage signal V(t) at time t, and calculates the synchronization offset rate ΔS using a sampling time reference alignment algorithm to quantify the degree of synchronization between voltage and current in a single switching cycle. The purpose of this calculation step is to solve the problem that traditional methods cannot accurately characterize "synchronization distortion" based solely on waveform observation. If the current and voltage are not synchronized at the instant the switching transistor is turned on and off, overlapping conduction regions will occur, leading to an increase in instantaneous power spikes, increased thermal stress on devices, and even triggering false protection. By introducing the normalized average absolute error (NMAE) principle and limiting the integration interval to [t0, t1], this method can accurately calculate the consistency of energy interaction in a single cycle, making ΔS reflect the true transient coupling state of the system. Furthermore, by introducing a voltage-current scaling factor, the amplitude of V(t) is scaled to be consistent with the dimensions of I(t). This mathematically ensures that the offset rate ΔS is dimensionless, maintaining comparability under different voltage levels and load conditions, thus achieving unified evaluation across operating conditions. Physically, a smaller synchronization offset rate ΔS indicates higher synchronization between voltage and current switching and a "cleaner" energy transfer process; an increase in ΔS indicates reduced synergy between the two, with energy backflow or transient coupling imbalance, reflecting a potential unstable state of the system. Taking the ultra-fast charging scenario as an example, when the load suddenly changes from light to heavy, the parasitic parameters of the switching node will cause a phase difference of about 200ns between V(t) and I(t), causing ΔS to spike from 0.05 to 0.2. Without intervention, this will cause MOSFET overheating. This method can effectively distinguish between normal transient disturbances and abnormal distortions by setting a threshold for ΔSth. After obtaining the synchronization offset rate ΔS, the control processing unit calculates the health coefficient H1 to further quantify the system health status. The design logic of H1 is to use 1 to represent the ideal synchronization state (ΔS approaching 0) and 0 to represent complete misalignment. When the health coefficient H1 ≥ 0.8, it indicates that the system is in a stable soft-switching range with low switching losses and low device stress. When the health coefficient H1 < 0.8, it indicates significant voltage and current mismatch, and the system has deviated from the ideal synchronization range, requiring immediate activation of the adaptive control mechanism for correction. This setting allows the system to detect synchronization anomalies within milliseconds and intervene in advance, rather than waiting for temperature rise or efficiency decline before compensation. In summary, this implementation method forms a self-identifying and dynamically early warning health assessment model through a two-layer judgment mechanism of "ΔS quantification + health coefficient H1 evaluation". Its true physical meaning is to transform the complex voltage-current coupling process into a unified calculable index, achieving accurate measurement of switching synchronization. Compared with traditional judgment methods based on a single characteristic of threshold voltage or current, this method not only improves the accuracy of soft and hard mode judgment but also significantly enhances the response speed and robustness of anomaly detection.The actual test results show that the system switching loss can be reduced by about 15% and the device junction temperature rise rate can be reduced by about 12% after adopting this method. The false judgment rate is reduced by more than 30% compared with the traditional current threshold method, which effectively ensures the efficient and safe operation of the power system in the ultra-fast charging scenario.

[0116] Example 4

[0117] Please see Figure 1 and Figure 3 Specifically: S3 includes S31;

[0118] S31. After the control processing unit triggers the adaptive dynamic control mechanism, the control parameters are updated in each detection cycle based on the current health coefficient H1. The control parameters include the PWM duty cycle D and the switching frequency fs. Fine-tuning compensation is performed to suppress the distortion of soft and hard mode switching and restore the stable operation of the switching power supply system.

[0119] Control parameters are updated through the following relationship:

[0120] In the formula, Dnew represents the updated PWM duty cycle, fs,new represents the updated switching frequency; Dold and fs,old represent the current PWM duty cycle D and switching frequency fs, respectively; kD and kf represent the adjustment coefficients of PWM duty cycle D and switching frequency fs, respectively, with values ​​ranging from 0.05 to 0.1.

[0121] These two relationships belong to the proportional control (Pcontrol) paradigm in classical control theory: the increment of the control quantity is proportional to the "error signal," and the error is defined here as (1-H1). When the health coefficient H1 decreases, it indicates that the system is more "unhealthy," and the error (1-H1) is larger. The controller performs linear adjustment of the controlled quantity according to the proportional constant (i.e., the adjustment coefficient kD and the adjustment coefficient kf), which is consistent with the standard practice of steady-state quality and dynamic recovery in automatic control principles (proportional adjustment, amplitude limiting, and slope limiting, etc.).

[0122] This formula makes two engineering modifications to the proportional control concept: channel decoupling: the "energy transport capacity" is mainly increased by the PWM duty cycle D, while the "switching stress / transient impact" is mainly suppressed by the decrease in the switching frequency fs; thus, one increase and one decrease form a two-variable coordinated compensation.

[0123] Error selection: Instead of the traditional amplitude difference, the error is (1-H1). The health coefficient H1 has condensed the physical meaning of "synchronization offset rate ΔS and offset rate threshold ΔSth" into a [0,1] interval quantity, which is more suitable for direct drive control law and simplifies implementation.

[0124] In this embodiment, once the control processing unit triggers the adaptive dynamic adjustment mechanism due to the health coefficient H1 falling below the threshold, it uses (1 − health coefficient H1) as the real-time error signal and adjusts the PWM duty cycle D and switching frequency fs synchronously according to the proportional control law in each detection cycle: the larger the error, the PWM duty cycle D is increased proportionally by the adjustment coefficient kD (0.05–0.1) to enhance energy transport and current driving force; the switching frequency fs is decreased proportionally by the adjustment coefficient kf (the calibration step size corresponding to 0.05–0.1), realizing channel decoupling and collaborative compensation of "increasing D and decreasing fs". The reason for this setting is that the distortion of soft and hard mode switching is often caused by voltage-current asynchrony due to sudden load changes, temperature rise, or dead zone drift: if only the PWM duty cycle D is increased, the stress may be increased; if only the switching frequency fs is decreased, the voltage drop may affect the load quality in a short time. The combined effect of these two technologies, without modifying the hardware, can simultaneously increase the conduction current window and decrease the turn-on residual voltage, "pushing" the switching transient back to a point close to zero voltage conduction. Physically, this reduces the voltage-current overlap area, directly suppressing turn-on losses and thermal shock. In implementation, it is combined with amplitude limiting and slope limiting (such as D∈[Dmin,Dmax], fs∈[fs,min,fs,max] and the maximum rate of change per cycle) to avoid over-adjustment causing loop oscillation. Under ultra-fast charging conditions (e.g., load jumping from 30kW to 80kW), the synchronization offset peak can be significantly reduced, allowing the health coefficient H1 to recover to ≥0.8 within several cycles, restoring soft-switching conditions, reducing device junction temperature rise and EMI peaks, thereby achieving faster dynamic convergence, lower switching losses, and higher operational reliability.

[0125] Example 5

[0126] Please see Figure 1 Specifically: S4 includes S41;

[0127] S41. After completing the adaptive dynamic adjustment mechanism, the control processing unit calculates the comprehensive health index Htotal based on the relationship between the health coefficient H1 and the frequency change after adjustment, and then performs global quantification of the stability of the soft and hard mode switching.

[0128] The overall health index Htotal is calculated and output using the following algorithm formula;

[0129] In the formula, This represents the feedback control factor, with a value range of 0.3-0.6. It represents the weighting coefficient of the control layer on frequency changes in the comprehensive evaluation, in order to balance dynamic response speed and system stability.

[0130] The calculated comprehensive health index Htotal comprehensively reflects the "transient synchronization performance (health coefficient H1 part)" and "frequency stability after regulation (fs,new / fs,old part)" during the switching process between soft and hard modes, that is, it takes into account both waveform consistency and control dynamic recovery capability.

[0131] S4 also includes S42;

[0132] S42. The control processing unit performs a health assessment based on the numerical range of the comprehensive health index Htotal, and executes the corresponding level of control strategy based on the health assessment results. The specific assessment content is as follows:

[0133] When the comprehensive health index Htotal > 0.9, the switching power supply system is determined to be in the stable soft-switching operating region, maintaining the current PWM duty cycle D and switching frequency fs; all adjustment actions are stopped, and only the periodic detection process is retained; if the comprehensive health index Htotal remains > 0.9 for five consecutive cycles, the power supply enters the energy-saving optimization mode, automatically reducing the sampling frequency by 50% to reduce the control load;

[0134] When 0.7 < Htotal (Comprehensive Health Index) ≤ 0.9, the switching power supply system is determined to have a slight synchronization deviation. The control processing unit enters the low-frequency stabilization strategy mode, gradually reducing the switching frequency fs by 5% to 10% while maintaining the current PWM duty cycle to stabilize energy conversion. If this continues for more than 50 preset cycles, PID fine-tuning is further executed, gradually correcting the adjustment coefficient kD of the PWM duty cycle D and the adjustment coefficient kf of the switching frequency fs by increasing by 0.1, in order to suppress small oscillations and restore the comprehensive health index Htotal to the healthy range.

[0135] When the comprehensive health index Htotal≤0.7, the switching power supply system is judged to have serious synchronization misalignment and frequency control failure; the control processing unit immediately issues a fault alarm signal and reports to the monitoring module; it automatically switches to the backup power supply and bypass power supply channel to ensure that the load is continuously powered without interruption.

[0136] In this embodiment, after completing adaptive dynamic regulation, the control processing unit calculates the comprehensive health index Htotal (which is formed by fusing the regulation ratio of the health coefficient H1 and the switching frequency fs according to the feedback regulation factor β). Its purpose is not to "recalculate the score," but to combine "waveform synchronization" (the degree of voltage-current coordination represented by the health coefficient H1) and "regulation stability" (the frequency drop amplitude and stress relief reflected by fs,new / fs,old) into a single, decision-making global indicator: when the comprehensive health index Htotal > 0.9, the status quo is maintained to avoid introducing new disturbances through "over-parameter tuning," and the sampling rate is reduced by 50% to reduce the control burden, which is equivalent to reducing the sampling rate in the stable region. Reduce loop noise injection; when 0.7 < comprehensive health index Htotal ≤ 0.9, enter the low-frequency stabilization strategy, gradually reduce the switching frequency fs by 5% to 10% without changing the PWM duty cycle D, and then use small-step PID fine-tuning of the adjustment coefficients kD and kf to suppress micro-oscillations and prevent secondary instability caused by a one-time large parameter change; when the comprehensive health index Htotal ≤ 0.7, immediately alarm and switch to the backup power supply channel, which essentially suppresses the risk of thermal runaway and efficiency collapse by ensuring power supply continuity. For example, in summer, high temperature and load transition may cause the health index H1 to fail to return to 0.8 for a long time and the frequency reduction range may be close to the boundary. If the main circuit is maintained at this time, the junction temperature rise of power devices and EMI exceedance are more likely to be superimposed. Through this hierarchical decision chain, the system combines the judgment of "whether synchronization is good" and "whether the control is stable" within one cycle, and makes on-the-spot decisions: no disturbance in the stable region, flexible steady state in the transition region, and rigid switching in the abnormal region. Its real physical meaning is to synchronously converge the phase and amplitude of voltage and current on the energy path, while limiting the speed and amplitude of parameter adjustment on the control path to avoid introducing new energy storage charge-discharge mismatches. The resulting benefits are obvious: significantly reducing switching overlap loss and EMI peak without changing the hardware, shortening the convergence time from abnormal to steady state, and ensuring uninterrupted power supply to the load under extreme conditions with backup switching, thus improving overall operational stability, thermal safety margin, and long-term reliability.

[0137] Example 6

[0138] Please see Figure 1 and Figure 2 A fault detection system for a switching power supply includes a power acquisition module, a switching anomaly analysis module, an adaptive dynamic adjustment module, and a comprehensive health analysis module.

[0139] The power acquisition module collects power data in real time by setting up acquisition points in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station. The acquired power data is preprocessed in the control processing unit to obtain current signal I and voltage signal V. Then, a dual-mode detection dataset is established to identify the operating status of soft switching mode and hard switching mode.

[0140] The switching anomaly analysis module calculates the synchronization offset rate ΔS of the current signal and voltage signal within one switching cycle when the switching power supply is detected to be in the soft-hard mode switching range, and performs switching anomaly assessment.

[0141] The adaptive dynamic adjustment module triggers the adaptive dynamic control mechanism based on the switching anomaly evaluation result. The adaptive dynamic control mechanism automatically adjusts the PWM duty cycle D and the switching frequency fs.

[0142] The comprehensive health analysis module calculates the comprehensive health index Htotal after the adaptive dynamic control mechanism is completed, performs a health assessment based on the comprehensive health index Htotal, and then executes relevant strategies based on the health assessment results.

[0143] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention.

Claims

1. A fault detection method for a switching power supply, characterized in that, Includes the following steps: S1. Set up a collection point in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station to collect power data in real time, and preprocess the collected power data in the control processing unit to obtain current signal I and voltage signal V. Then establish a dual-mode detection dataset to identify the operating status of soft switching mode and hard switching mode. S2. When the switching power supply is detected to be in the soft-hard mode switching interval, calculate the synchronization offset rate ΔS of the current signal and voltage signal in one switching cycle, and perform a switching anomaly assessment. S3. An adaptive dynamic control mechanism is triggered based on the switching anomaly evaluation result. The adaptive dynamic control mechanism automatically adjusts the PWM duty cycle D and the switching frequency fs. S4. After the adaptive dynamic control mechanism is completed, calculate the comprehensive health index Htotal, conduct a health assessment based on the comprehensive health index Htotal, and then implement relevant strategies based on the health assessment results.

2. The fault detection method for a switching power supply according to claim 1, characterized in that, S1 includes S11; S11. Set up a collection point in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station, and set up a collection device in the collection point to acquire power data in real time. Among them, all collection points are connected to an independent channel analog-to-digital converter. The three channels are synchronously sampled by a unified reference clock output by the FPGA. The sampling frequency is not less than 2MHz, and the timing mismatch between the channels of each collection point is not greater than 100ns. The acquisition points include output current acquisition points, switch node voltage acquisition points, and load response acquisition points; The power data includes power transient waveforms, voltage transient waveforms, and load-side instantaneous voltage recovery speed; The acquisition device includes an integrated closed-loop Hall current sensor, a high-voltage differential probe, an isolation amplifier, and a second-order active low-pass anti-aliasing filter.

3. The fault detection method for a switching power supply according to claim 2, characterized in that, S1 further includes S12; S12. The acquired power data is transmitted to the FPGA in real time via the serial LVDS bus through the high-speed ADC of each channel. The FPGA performs timestamp marking and channel synchronization alignment on the received power data, and divides and packages it into frames according to the switching cycle. The framed data is output to the DMA interface channel of the control processing unit through the FIFO buffer. The DMA interface channel writes the data into the circular buffer in a zero-copy manner and performs preprocessing in the control processing unit to obtain the current signal I(t) and voltage signal V(t) at time t. The preprocessing includes temporal alignment and interpolation resampling, and digital filtering and denoising. The time-domain alignment and interpolation resampling are performed by the control processing unit according to the timestamp provided by the FPGA to perform channel-level timing alignment, and segmented cubic spline interpolation is performed on segments with sampling phase differences to a unified time grid to construct a synchronous data frame with a single switch cycle length. The digital filtering and denoising are performed sequentially by the control processing unit on the synchronous data frame using anti-aliasing FIR low-pass filtering and 50 / 60Hz notch filtering, followed by sliding root mean square smoothing to obtain the current signal I(t) and voltage signal V(t) at time t. The data from the load response acquisition point in the three channels are stored in the same data frame as the load-side transient reference quantity, along with the current signal I(t) and voltage signal V(t) at time t.

4. The fault detection method for a switching power supply according to claim 3, characterized in that, S1 also includes S13; S13. The control processing unit establishes a dual-mode detection dataset based on the current signal I(t) and the voltage signal V(t) at time t and completes the identification of the operating state of soft switching mode and hard switching mode; the specific steps of the operating state identification include S131 and S132. S131. The control processing unit uses the rising edge of the switching transistor drive signal or the zero crossing point of the voltage signal V(t) as the start mark of the period to divide the continuously sampled data into equal-length switches, denoted as the k-th period window W. k ; and extract the transient characteristic parameters of the switching node in each cycle; the transient characteristic parameters of the switching node include the residual voltage amplitude Vres(k) before the k-th cycle is turned on; S132. The control processing unit identifies the operating status of the switching power supply system based on the residual voltage amplitude Vres(k) before the turn-on of the k-th cycle and the preset lower threshold V1 and upper threshold V2 of the residual voltage amplitude of the switching node; the specific identification content is as follows: When the residual voltage amplitude Vres(k) before the k-th cycle is turned on is less than the lower limit threshold V of the residual voltage amplitude of the switching node, it is determined that the switching power supply system is in soft switching mode. When the residual voltage amplitude Vres(k) before the kth cycle is turned on is greater than the upper limit threshold V2 of the residual voltage amplitude of the switching node, the switching power supply system is determined to be in hard switching mode. When the residual voltage amplitude Vres(k) ∈ [V1, V2] before the kth cycle is turned on, it is determined that the switching power supply system is in the soft and hard mode switching interval. Among them, the lower limit threshold V1 of the residual amplitude of the switching node voltage is 0.5%-1% of the rated switching node voltage Vrated, and the upper limit threshold V2 of the residual amplitude of the switching node voltage is 2%-3% of the rated switching node voltage Vrated.

5. The fault detection method for a switching power supply according to claim 4, characterized in that, S2 includes S21; S21. When the soft and hard mode switching interval is detected, the control processing unit extracts the current signal I(t) and the voltage signal V(t) at time t and calculates them according to the sampling time reference alignment algorithm, outputs the synchronization offset rate ΔS, and quantifies the degree of transient synchronization offset between current and voltage. The synchronization offset rate ΔS is calculated and output using the following sampling time reference alignment algorithm; In the formula, t0 represents the start time of the switching cycle, t1 represents the end time of the switching cycle, Itated represents the rated output current, Vrated represents the rated switching node voltage, and dt represents the time integral function.

6. The fault detection method for a switching power supply according to claim 1, characterized in that, S2 further includes S22; S22. The control processing unit calculates the ratio between the acquired synchronization offset rate ΔS and the synchronization offset rate threshold ΔSth to obtain the health coefficient H1. The output of the health coefficient H1 is then used as an evaluation index for the switching state of the switching power supply system to perform switching anomaly assessment. The specific assessment content is as follows: When the health coefficient H1≥0.8, the switching between soft and hard modes is determined to be normal, and the switch state is stabilized in soft switch mode. When the health coefficient H1 < 0.8, it is determined that there is a switching abnormality in the switching power supply system, and the control processing unit triggers the adaptive dynamic control mechanism.

7. The fault detection method for a switching power supply according to claim 6, characterized in that, S3 includes S31; S31. After the control processing unit triggers the adaptive dynamic control mechanism, the control parameters are updated in each detection cycle according to the current health coefficient H1. The control parameters include the PWM duty cycle D and the switching frequency fs. Fine-tuning compensation is performed to suppress the distortion of soft and hard mode switching and restore the stable operation of the switching power supply system. The control parameters are updated through the following relationship: In the formula, Dnew represents the updated PWM duty cycle, fs,new represents the updated switching frequency; Dold and fs,old represent the current PWM duty cycle D and switching frequency fs, respectively; kD and kf represent the adjustment coefficients of PWM duty cycle D and switching frequency fs, respectively, with values ​​ranging from 0.05 to 0.

1.

8. A fault detection method for a switching power supply according to claim 7, characterized in that, S4 includes S41; S41. After completing the adaptive dynamic adjustment mechanism, the control processing unit calculates the comprehensive health index Htotal based on the relationship between the health coefficient H1 and the frequency change after adjustment, and then performs global quantification of the stability of the soft and hard mode switching. The comprehensive health index Htotal is calculated and output using the following algorithm formula; In the formula, This represents the feedback control factor, with a value range of 0.3-0.

6.

9. A fault detection method for a switching power supply according to claim 8, characterized in that, S4 also includes S42; S42. The control processing unit performs a health assessment based on the numerical range of the comprehensive health index Htotal, and executes the corresponding level of control strategy based on the health assessment results. The specific assessment content is as follows: When the comprehensive health index Htotal > 0.9, the switching power supply system is determined to be in the stable soft-switching operating region, maintaining the current PWM duty cycle D and switching frequency fs; all adjustment actions are stopped, and only the periodic detection process is retained; if the comprehensive health index Htotal remains > 0.9 for five consecutive cycles, the power supply enters the energy-saving optimization mode, automatically reducing the sampling frequency by 50% to reduce the control load; When 0.7 < Htotal (Comprehensive Health Index) ≤ 0.9, it is determined that there is a slight synchronization deviation in the switching power supply system; the control processing unit enters the low-frequency stabilization strategy mode, gradually reducing the switching frequency fs by 5% to 10%, while maintaining the current PWM duty cycle unchanged. If the preset period of 50 cycles is exceeded, PID fine-tuning will be further performed, and the adjustment coefficient kD of the PWM duty cycle D and the adjustment coefficient kf of the switching frequency fs will be gradually corrected by increasing by 0.

1. When the comprehensive health index Htotal≤0.7, the switching power supply system is judged to have serious synchronization misalignment and frequency control failure; the control processing unit immediately issues a fault alarm signal and reports to the monitoring module; and automatically switches to the backup power supply and bypass power supply channel.

10. A fault detection system for a switching power supply, applied to the fault detection method for a switching power supply according to any one of claims 1-9, characterized in that, It includes a power acquisition module, a switching anomaly analysis module, an adaptive dynamic adjustment module, and a comprehensive health analysis module; The power acquisition module collects power data in real time by setting up acquisition points in the main power circuit of the switching power supply system of the electric vehicle ultra-fast charging station. The acquired power data is preprocessed in the control processing unit to obtain current signal I and voltage signal V. Then, a dual-mode detection dataset is established to identify the operating status of soft switching mode and hard switching mode. The switching anomaly analysis module calculates the synchronization offset rate ΔS of the current signal and voltage signal within one switching cycle when the switching power supply is detected to be in the soft-hard mode switching interval, and performs switching anomaly assessment. The adaptive dynamic adjustment module triggers an adaptive dynamic control mechanism based on the switching anomaly evaluation result. The adaptive dynamic control mechanism automatically adjusts the PWM duty cycle D and the switching frequency fs. The comprehensive health analysis module calculates the comprehensive health index Htotal after the adaptive dynamic control mechanism is completed, performs a health assessment based on the comprehensive health index Htotal, and then executes relevant strategies based on the health assessment results.

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