A high-precision time measurement system and method

Abstract

The application provides a high-precision time measurement system and method, wherein the time measurement method comprises a signal conditioning circuit, a PLL frequency division, a coarse measurement module, a fine measurement module, a temperature compensation module, data processing and a network interface for external communication. The high-precision time measurement system comprises a reference clock source, a signal conditioning circuit, a core FPGA and a communication interface. The application adopts an adaptive interpolation type TDC and a temperature compensation technology to realize high-precision time measurement. The time frequency measurement technology can be applied to laser radar, intelligent driving and the like, has high precision and low non-linear error, the system maintains extremely high long-term stability in a wide temperature range, greatly reduces a measurement dead zone, is suitable for high-speed continuous event measurement, and reduces cost. And the high programmability of the FPGA makes the system easy to integrate with other digital systems and expand functions.

Description

Technical Field

[0001] This invention relates to the field of time and frequency measurement technology, specifically to a high-precision time measurement system and method. Background Technology

[0002] High-precision time interval measurement plays a crucial role in fields such as satellite navigation, communication synchronization, physical experiments, financial transactions, and industrial control. Existing high-precision timing technologies, such as time-to-digital converters (TDCs), while offering high accuracy, still have some inherent limitations:

[0003] 1. Nonlinear Error: Traditional time-delay converters (TDCs), especially those based on delay chains, experience time drift in their delay units due to variations in process technology, voltage, and temperature (PVT), resulting in significant nonlinearity in the measurement results and requiring complex background calibration. 2. Temperature Sensitivity: The frequency output of crystal oscillators (CIOs) is highly sensitive to temperature changes. Frequency drift of the CIO is a major factor limiting the long-term stability of timing systems over a wide temperature range. 3. Measurement Dead Zone: Many high-precision TDCs require a processing time after completing a measurement, during which new measurements cannot be performed, creating a measurement dead zone that limits their application in high-speed continuous events. 4. Cost and Integration: Dedicated TDC chips or high-end measurement instruments are expensive and difficult to integrate with other digital logic systems. Therefore, this invention provides a high-precision timing system and method. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a high-precision timing system and method to solve the problems mentioned in the background. This invention features high precision and low nonlinear error, maintains extremely high long-term stability over a wide temperature range, significantly reduces measurement dead zones, is suitable for measuring high-speed continuous events, and lowers costs. Furthermore, the high programmability of FPGAs makes this system easy to integrate with other digital systems and expand its functionality.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution: a high-precision time measurement system, including a reference clock source, a signal conditioning circuit, a core FPGA, and a communication interface; the core FPGA integrates a coarse measurement module, a fine measurement module, a temperature sensing and compensation module, and a data fusion and processing module; the fine measurement module is an adaptive interpolation TDC, and the fine measurement module dynamically controls a measurement window through the signal under test, and uses a high-frequency vernier clock to count within the window, combined with a digital time interpolation algorithm to achieve high-resolution fine time measurement.

[0006] Furthermore, the temperature sensing and compensation module includes a temperature sensor and a lookup table (LUT) pre-stored with the temperature-frequency error relationship. The temperature sensing and compensation module is used to dynamically and digitally compensate for the frequency error of the reference clock source based on the real-time monitored temperature.

[0007] Furthermore, the temperature sensor is an XADC module integrated within the FPGA.

[0008] Furthermore, the temperature sensor also includes an external, independent, high-precision digital temperature sensor.

[0009] Furthermore, the data fusion and processing module performs the following calculations:

[0010]

[0011] in:

[0012] These are high-precision time interval measurements;

[0013] This is a coarse time value;

[0014] , These are the time values ​​for the start and stop signals, respectively.

[0015] K is the temperature compensation coefficient obtained from the lookup table.

[0016] A timing method using the above-mentioned timing system includes the following steps:

[0017] S1. Receive and process the start and stop signals to be measured through the signal conditioning circuit;

[0018] S2. Use the coarse measurement module to count the reference clock to obtain a coarse time value. ;

[0019] S3. Using the fine measurement module, through a dynamic interpolation window and a high-frequency vernier clock, combined with a digital interpolation algorithm, the fine time value is obtained. , ;

[0020] S4. Obtain the current temperature and the corresponding frequency compensation coefficient K through the temperature sensing and compensation module;

[0021] S5. By fusing the coarse and fine values ​​and applying the compensation coefficient K, the final high-precision time interval measurement value is calculated. .

[0022] Furthermore, the operation of the fine measurement module and the operation of the coarse measurement module are executed in parallel.

[0023] Furthermore, in step S3, after the start signal is triggered, an interpolation measurement window is dynamically opened, and the vernier clock counts within this window.

[0024] Furthermore, when the stop signal is triggered, the interpolation measurement window is dynamically closed, the count value of the vernier clock within the window is recorded, and the fine time value corresponding to the phase difference between the start and stop signals within the coarse value period is calculated using a digital interpolation algorithm.

[0025] The beneficial effects of this invention are:

[0026] 1. This high-precision timing system and method replaces the traditional fixed delay chain with "adaptive interpolation TDC" and avoids the nonlinear distortion of analog circuits by using digital interpolation algorithms, thus achieving higher measurement linearity and accuracy (up to the picosecond level).

[0027] 2. This high-precision timing system and method effectively suppresses crystal oscillator frequency drift caused by changes in ambient temperature through innovative real-time temperature sensing and dynamic frequency compensation mechanism, enabling the system to maintain extremely high long-term stability over a wide temperature range.

[0028] 3. This high-precision timing system and method uses coarse and fine measurement modules to process data in parallel within the FPGA, and the data processing flow is highly pipelined. The system can immediately prepare for the next measurement after one measurement is completed, which greatly reduces the measurement dead zone and is suitable for the measurement of high-speed continuous events.

[0029] 4. The core of the system of this invention is implemented based on a general-purpose FPGA, eliminating the need for expensive dedicated TDC chips and greatly reducing costs. At the same time, the high programmability of the FPGA makes the system easy to integrate with other digital systems and expand its functionality. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of a high-precision timing system according to the present invention. Detailed Implementation

[0031] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0032] Please see Figure 1 The present invention provides the following technical solution: a high-precision timing system, comprising:

[0033] • Reference clock source: Used to generate a stable reference clock signal.

[0034] • Signal conditioning circuit: Connected to the input terminal of the signal under test, it is used to shape, amplify and level-convert the input pulse signal under test.

[0035] • Core FPGA: As the core of the system's control and computation, it integrates:

[0036] • Coarse measurement module: Uses a counter to count the entire cycles of the reference clock to achieve coarse measurement of the time interval.

[0037] • Fine Measurement Module: Employs an adaptive interpolation TDC (Time Difference Module), which, instead of using a fixed delay chain, dynamically generates a measurement window using configurable logic blocks (CLBs) within the FPGA. The start and stop of this window are triggered by the signal under test, and the window is filled with a high-frequency "vernier" clock. By measuring the number of cycles of the "vernier" clock within the window and combining this with a digital time interpolation algorithm, a high-resolution fine time value within the coarse value is calculated. This method effectively avoids the nonlinearity problems of traditional delay chains.

[0038] By replacing the traditional fixed delay chain with "adaptive interpolation TDC", the nonlinear distortion of analog circuits is avoided by using digital interpolation algorithms, and higher measurement linearity and accuracy (up to the picosecond level) are achieved.

[0039] By using coarse and fine measurement modules to process data in parallel within the FPGA, and with a highly pipelined data processing flow, the system can immediately prepare for the next measurement after one measurement is completed, greatly reducing the measurement dead zone and making it suitable for high-speed continuous event measurements.

[0040] • Temperature Sensing and Compensation Module: A high-precision temperature sensor is integrated internally or externally into the FPGA to monitor the FPGA chip's temperature in real time. This module incorporates a temperature-frequency error lookup table (LUT), obtained through prior calibration. The system dynamically compensates for the actual frequency of the reference clock source by consulting the LUT in real time based on the current temperature, significantly improving the system's stability across the entire temperature range.

[0041] Through innovative real-time temperature sensing and dynamic frequency compensation mechanisms, the crystal oscillator frequency drift caused by changes in ambient temperature is effectively suppressed, enabling the system to maintain extremely high long-term stability over a wide temperature range.

[0042] The system is implemented using a general-purpose FPGA, eliminating the need for expensive dedicated TDC chips and significantly reducing costs. Furthermore, the high programmability of FPGAs makes the system easy to integrate with other digital systems and expand its functionality.

[0043] • Data fusion and processing module: used to seamlessly stitch together coarse and fine measurement results, apply temperature compensation algorithms, and finally output high-precision absolute time interval measurement results.

[0044] • Communication interface: Used to output measurement results to a host computer or other devices.

[0045] In this embodiment, the system includes a crystal oscillator (TCXO) as a reference clock source, outputting a 100MHz clock signal. The signal conditioning circuit uses a high-speed comparator to convert the input LVDS or ECL level test signal into the LVCMOS level of the FPGA.

[0046] The core FPGA is a Xilinx Artix-7 series chip. Its internal coarse measurement module is a 32-bit counter. The fine measurement module uses a 500MHz "vernier" clock generated by the FPGA's PLL. The temperature sensor uses an XADC module integrated within the FPGA.

[0047] After the system is powered on, it is first calibrated in a constant temperature chamber: within a temperature range of -40°C to +85°C, the error of the reference clock relative to the standard frequency source is measured every 5°C, a temperature-frequency error lookup table (LUT) is generated and stored in the FPGA's Block RAM.

[0048] During measurement, it is assumed that a coarse value is obtained. The fine measurement module measured 15 clock cycles (i.e., 150 ns). It is 1.234 ns. The value is 0.567 ns. Simultaneously, the XADC reads the current chip temperature as 45°C and queries the LUT to obtain the compensation coefficient K = 1.000012.

[0049] The final measurement result is:

[0050] = (150ns + 1.234ns - 0.567ns) * 1.000012 = 150.667ns *1.000012 ≈ 150.6688ns.

[0051] Through this invention, the system achieves a single measurement accuracy better than ±10ps, and the accuracy variation is less than ±50ps over the entire temperature range from -40°C to +85°C.

[0052] This embodiment also provides a high-precision time measurement method based on the above system, including the following steps:

[0053] S1: System power-on initialization, loading temperature-frequency error lookup table (LUT);

[0054] S2: The signal conditioning circuit receives the start and stop pulse signals to be tested and converts them into standard logic levels that the FPGA can recognize;

[0055] S3: When the start signal arrives, the counter of the coarse measurement module starts counting the reference clock; when the stop signal arrives, the counter stops counting, obtaining a coarse value of the time interval. ;

[0056] S4: (Core Innovation Point 3) The fine testing module is activated simultaneously with the coarse testing:

[0057] S4.1: The start signal triggers and dynamically opens an interpolation measurement window;

[0058] S4.2: A "vernier" clock with a frequency much higher than the reference clock counts within this window;

[0059] S4.3: Stop signal triggering, dynamically close the interpolation measurement window;

[0060] S4.4: Record the count value of the "cursor" clock within the window. The fine time value corresponding to the phase difference between the start and stop signals within the coarse period is calculated using a digital interpolation algorithm. , ;

[0061] S5: The temperature sensing and compensation module reads the current temperature in real time and queries the LUT to obtain the frequency compensation coefficient K under the current temperature;

[0062] S6: The data fusion and processing module synthesizes the coarse and fine values, and uses a compensation coefficient K to correct the result. The calculation formula is as follows:

[0063]

[0064] in, This is the final high-precision time interval measurement value.

[0065] S7: Outputs the final measurement results via the communication interface.

[0066] In summary, this invention provides an innovative high-precision timing solution that effectively combines accuracy, stability, speed, and cost, and has high practical value and market prospects.

[0067] The foregoing has shown and described the basic principles and main features of the present invention and its advantages. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0068] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A high-precision timing system, characterized in that: It includes a reference clock source, signal conditioning circuit, core FPGA, and communication interface; the core FPGA integrates a coarse measurement module, a fine measurement module, a temperature sensing and compensation module, and a data fusion and processing module; the fine measurement module is an adaptive interpolation TDC, and the fine measurement module dynamically controls a measurement window through the signal under test, and uses a high-frequency vernier clock to count within the window, combined with a digital time interpolation algorithm to achieve high-resolution fine time measurement.

2. The high-precision timing system according to claim 1, characterized in that: The temperature sensing and compensation module includes a temperature sensor and a lookup table (LUT) pre-stored with the temperature-frequency error relationship. The temperature sensing and compensation module is used to dynamically and digitally compensate the frequency error of the reference clock source based on the real-time monitored temperature.

3. The high-precision timing system according to claim 2, characterized in that: The temperature sensor is an XADC module integrated within the FPGA.

4. A high-precision timing system according to claim 2, characterized in that: The temperature sensor also includes an external, independent, high-precision digital temperature sensor.

5. A high-precision timing system according to claim 1, characterized in that: The data fusion and processing module performs the following calculations: ； in: These are high-precision time interval measurements; This is a coarse time value; , These are the time values ​​for the start and stop signals, respectively. K is the temperature compensation coefficient obtained from the lookup table.

6. A timing method using the timing system as described in claim 1, characterized in that: Includes the following steps: S1. Receive and process the start and stop signals to be measured through the signal conditioning circuit; S2. Use the coarse measurement module to count the reference clock to obtain a coarse time value. ; S3. Using the fine measurement module, through a dynamic interpolation window and a high-frequency vernier clock, combined with a digital interpolation algorithm, the fine time value is obtained. , ; S4. Obtain the current temperature and the corresponding frequency compensation coefficient K through the temperature sensing and compensation module; S5. By fusing the coarse and fine values ​​and applying the compensation coefficient K, the final high-precision time interval measurement value is calculated. .

7. The timing method according to claim 6, characterized in that: The fine measurement module operates in parallel with the coarse measurement module.

8. The timing method according to claim 6, characterized in that: In step S3, after the start signal is triggered, an interpolation measurement window is dynamically opened, and the vernier clock counts within this window.

9. The timing method according to claim 8, characterized in that: When the stop signal is triggered, the interpolation measurement window is dynamically closed, the count value of the vernier clock within the window is recorded, and the fine time value corresponding to the phase difference between the start and stop signals within the coarse value period is calculated by a digital interpolation algorithm.

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