Statistical eye diagram determination method and apparatus

Abstract

This invention discloses a method and apparatus for determining a statistical eye diagram. The method involves acquiring a simulated statistical eye diagram of the parallel interface under test up to the receiving end, and obtaining the characteristics of the clock comparator. Based on an offset voltage detection circuit, the offset voltage of the target clock comparator under various preset operating parameters is detected to determine an offset voltage lookup table. Then, the 2D shmoo statistical eye diagram of the parallel interface under test is determined according to the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The preset operating parameters include a preset clock phase and a preset reference voltage. The 2D shmoo statistical eye diagram is used to characterize the impact of the clock phase and reference voltage on the performance of the parallel interface under test. Therefore, this invention can model the comparator characteristics to generate an accurate 2D shmoo statistical eye diagram during the simulation phase and ensure that the 2D shmoo statistical eye diagram corresponds to the 2D shmoo eye diagram in the actual measurement phase.

Description

Technical Field

[0001] This invention relates to the field of parallel interface testing, and more specifically to a method and apparatus for determining statistical eye diagrams. Background Technology

[0002] 2D Shmoo statistical eye diagrams are commonly used to analyze the response distribution of a link under a specific code pattern, based on known link responses. This allows for rapid acquisition of eye diagram results at low bit error rates, avoiding the problems of insufficient code complexity and excessive simulation time associated with traditional time-domain eye diagram simulation methods. In the current design phase of high-speed interfaces, statistical eye diagram calculation methods are generally used to evaluate system capabilities.

[0003] However, current statistical eye diagram calculation methods typically do not model comparator characteristics but instead use rectangular or rhomboid masks for representation. This results in poor accuracy and fails to truly correspond to the 2D Shmoo eye diagrams measured in the field. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a statistical eye diagram determination method and apparatus to generate an accurate 2D shmoo statistical eye diagram during the simulation stage and to ensure that the 2D shmoo statistical eye diagram corresponds to the 2D shmoo eye diagram in the actual measurement stage.

[0005] In a first aspect, embodiments of the present invention aim to provide a method for determining statistical eye diagrams, the method comprising: Obtain the simulation statistical eye diagram of the parallel interface under test before the receiving end; The characteristics of the clock comparator are obtained, and the offset voltage of the target clock comparator under various preset operating parameters is determined based on the offset voltage detection circuit to obtain an offset voltage lookup table. The preset operating parameters include a preset clock phase and a preset reference voltage. The 2D shmoo statistical eye diagram of the parallel interface under test is determined based on the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The 2D shmoo statistical eye diagram is used to characterize the impact of clock phase and reference voltage on the performance of the parallel interface under test.

[0006] Secondly, embodiments of the present invention aim to provide a statistical eye diagram determination device, the device comprising: The simulation statistical eye diagram acquisition unit is used to acquire the simulation statistical eye diagram of the parallel interface under test before the receiving end; Offset voltage lookup table determination unit is used to obtain the characteristics of the clock comparator, determine the offset voltage of the target clock comparator under various preset operating parameters based on the offset voltage detection circuit, and obtain the offset voltage lookup table. The preset operating parameters include preset clock phase and preset reference voltage. The statistical eye diagram generation unit is used to determine the 2D shmoo statistical eye diagram of the parallel interface under test based on the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The 2D shmoo statistical eye diagram is used to characterize the impact of clock phase and reference voltage on the performance of the parallel interface under test.

[0007] Thirdly, embodiments of the present invention aim to provide a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, implement the method described in the first aspect.

[0008] Fourthly, embodiments of the present invention aim to provide an electronic device, the device comprising: Memory is used to store one or more computer program instructions; A processor, wherein the one or more computer program instructions are executed by the processor to implement the method as described in the first aspect.

[0009] Fifthly, embodiments of the present invention aim to provide a computer program product that, when run on a computer, causes the computer to perform the method described in the first aspect.

[0010] This invention discloses a method and apparatus for determining a statistical eye diagram. The method involves acquiring a simulated statistical eye diagram of the parallel interface under test up to the receiving end, and obtaining the characteristics of the clock comparator. Based on an offset voltage detection circuit, the offset voltage of the target clock comparator under various preset operating parameters is detected to determine an offset voltage lookup table. Then, the 2D shmoo statistical eye diagram of the parallel interface under test is determined according to the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The preset operating parameters include a preset clock phase and a preset reference voltage. The 2D shmoo statistical eye diagram is used to characterize the impact of the clock phase and reference voltage on the performance of the parallel interface under test. Therefore, this invention can model the comparator characteristics to generate an accurate 2D shmoo statistical eye diagram during the simulation phase and ensure that the 2D shmoo statistical eye diagram corresponds to the 2D shmoo eye diagram in the actual measurement phase. Attached Figure Description

[0011] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of a 2D shmoo statistical eye diagram according to an embodiment of the present invention; Figure 2 This is a flowchart of the statistical eye diagram determination method according to an embodiment of the present invention; Figure 3This is a schematic diagram of the offset voltage lookup table according to an embodiment of the present invention; Figure 4 This is a flowchart of the method for determining the offset voltage lookup table according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the offset voltage detection circuit according to an embodiment of the present invention; Figure 6 This is a flowchart of the method for determining the offset voltage lookup table according to an embodiment of the present invention; Figure 7 This is a flowchart of the 2D shmoo statistical eye diagram determination method according to an embodiment of the present invention; Figure 8 This is a flowchart of the comparator discrimination result determination method according to an embodiment of the present invention; Figure 9 This is a schematic diagram of a simulated statistical eye diagram according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the corresponding offset voltage in an embodiment of the present invention; Figure 11 This is a schematic diagram of a 2D shmoo statistical eye diagram according to an embodiment of the present invention; Figure 12 This is a schematic diagram of the statistical eye diagram determination device according to an embodiment of the present invention; Figure 13 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0012] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0013] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0014] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0015] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0016] The solutions described in this specification and embodiments, if involving the processing of personal information, will be processed only on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0017] It is important to note that the embodiments of the present invention generate accurate 2D shmoo statistical eye diagrams during the simulation phase and ensure that the 2D shmoo statistical eye diagrams correspond to the 2D shmoo eye diagrams obtained during the actual measurement phase. Furthermore, the simulated statistical eye diagram can be obtained by simulation at the input of the comparator (without introducing the non-ideal characteristics of the clock comparator), and is a graph composed of superimposed level signals of different states (i.e., high-level signals and low-level signals). In the embodiments of the present invention, the simulated statistical eye diagram of the parallel interface under test before the receiving end is the data required to determine the 2D shmoo statistical eye diagram.

[0018] Figure 1 This is a schematic diagram of a 2D shmoo statistical eye diagram according to an embodiment of the present invention. Figure 1 As shown, the horizontal and vertical axes of the 2D Shmoo statistical eye diagram can be used to characterize the clock phase and reference voltage, respectively. The 2D Shmoo statistical eye diagram can include multiple cells defined by the horizontal and vertical axes. Each cell in the 2D Shmoo statistical eye diagram can be used to characterize whether the signal transmitted by the parallel interface can be correctly identified by the clock comparator under a corresponding preset clock phase and a corresponding preset reference voltage. It is worth noting that in this embodiment of the invention, when the parallel interface transmits signals, the clock comparator compares the transmitted signal with the reference voltage to recover the corresponding digital signal. Furthermore, as a representation method, Figure 1 The cells with the binary character "1 (pass)" inside can be used to indicate that the signals transmitted by the parallel interface can be correctly identified by the clock comparator under the corresponding preset clock phase and the corresponding preset reference voltage. Figure 1 Cells marked with the binary character "0 (fail)" within the 2D Shmoo statistical eye diagram can be used to characterize the signal transmitted by the parallel interface that cannot be correctly identified by the clock comparator under the corresponding preset clock phase and preset reference voltage. Therefore, the 2D Shmoo statistical eye diagram can characterize the impact of clock phase and reference voltage on the performance of the parallel interface under test.

[0019] Figure 2 This is a flowchart of a statistical eye diagram determination method according to an embodiment of the present invention. It is intended to be noted that... Figure 2 The statistical eye diagram determination method shown can be executed by a general-purpose data processing device. By executing, as... Figure 2The statistical eye diagram determination method shown herein allows the data processing device to generate accurate 2D shmoo statistical eye diagrams during the simulation phase and ensure that the 2D shmoo statistical eye diagrams correspond to the 2D shmoo eye diagrams obtained in the experimental phase. For example... Figure 2 As shown, the statistical eye diagram determination method may specifically include the following steps: Step S100: Obtain the simulation statistical eye diagram of the parallel interface to be tested before the receiving end.

[0020] Specifically, this embodiment can obtain a simulated statistical eye diagram of the parallel interface under test before the receiving end. The simulated statistical eye diagram can be a graph composed of superimposed level signals of different states (i.e., high-level signals and low-level signals) without the introduction of a clock comparator and exhibiting non-ideal characteristics. Furthermore, the simulated statistical eye diagram can be a statistical eye diagram of the parallel interface under test at a corresponding bit error rate; this application does not impose any limitations on this.

[0021] Step S200: Obtain the characteristics of the clock comparator, determine the offset voltage of the target clock comparator under each preset operating parameter based on the offset voltage detection circuit, and obtain the offset voltage lookup table.

[0022] Specifically, this embodiment can acquire the characteristics of a clock comparator, determine the offset voltage of the target clock comparator under various preset operating parameters based on the offset voltage detection circuit, and obtain an offset voltage lookup table. The preset operating parameters may include a preset clock phase and a preset reference voltage. The offset voltage lookup table can be used to record the offset voltage of the target clock comparator under different clock phases and reference voltages.

[0023] Figure 3 This is a schematic diagram of the offset voltage lookup table according to an embodiment of the present invention. Figure 3 As shown, by determining the offset voltage of the target clock comparator under various preset operating parameters based on the offset voltage detection circuit, this embodiment can obtain an offset voltage lookup table 31. The offset voltage lookup table 31 can be used to record the offset voltage Offset of the target clock comparator under each clock phase τ and each reference voltage Vref.

[0024] It should be noted that the clock comparator can be a comparator carrying a clock (i.e., a sampling clock). The clock comparator can perform a comparison operation based on the edge trigger of the clock signal; that is, the comparison operation is performed when an edge of the clock signal is detected. In this embodiment of the invention, the clock phase can refer to the clock signal phase of the target clock comparator. Optionally, the target clock comparator can specifically be a Strong-ARM type comparator. The Strong-ARM type comparator is a high-speed, low-power voltage comparator based on the StrongARM cross-coupled inverter latch structure, which is widely used in high-speed digital and mixed-signal circuits. The reference voltage can be the signal referenced by the parallel interface under test when converting the original signal into a differential signal pair. When converting the original signal into a differential signal pair, the parallel interface under test can use the reference voltage as a common-mode voltage to convert the original signal into a complementary differential signal pair. However, in practical applications, due to the influence of non-ideal characteristics, clock comparators can only correctly restore the signal when they detect that the input voltage at the first input terminal exceeds the input voltage at the second input terminal by a certain degree (that is, the voltage difference between the differential signal and the center signal transmitted by the parallel interface is greater than the corresponding threshold). Offset voltage can be the equivalent input error voltage caused by the non-ideal characteristics of the clock comparator.

[0025] Figure 4 This is a flowchart illustrating the method for determining the offset voltage lookup table according to an embodiment of the present invention. It is intended to illustrate that by executing... Figure 4 The offset voltage lookup table determination method shown in this embodiment can determine the offset voltage of the target clock comparator under various preset operating parameters based on the offset voltage detection circuit, so as to obtain the offset voltage lookup table, that is, to realize the above step S200. Figure 4 As shown, the method for determining the offset voltage lookup table may specifically include the following steps: Step S210: Determine the clock phase pacing parameters and the reference voltage pacing parameters.

[0026] Specifically, in this embodiment, the clock phase pacing parameter and the reference voltage pacing parameter can be determined first. The clock phase pacing parameter determines the interval between preset clock phases, and the reference voltage pacing parameter determines the interval between preset reference voltages. The clock phase pacing parameter and the reference voltage pacing parameter together affect the test accuracy that the final determined 2D shmoo statistical eye diagram can exhibit.

[0027] Optionally, in step S210, as one implementation, this embodiment can determine the corresponding clock phase stepping parameters and reference voltage stepping parameters based on the effective clock phase adjustment range, the effective reference voltage adjustment range, and the test accuracy setting information. Furthermore, as a numerical setting method, the effective clock phase adjustment range can be a unit interval (UnitInterval, UI), that is, the duration of a single bit signal. The effective reference voltage adjustment range can be the voltage range covered by the supply voltage (VDDQ) of the I / O pin. And, the test accuracy setting information can be specifically preset by relevant personnel; this application does not limit its value. (Illustrative, for the purpose of obtaining...) Figure 3 The offset voltage lookup table 31 shown in this embodiment allows the test accuracy setting information to be set to 1 / 128.

[0028] Step S220: Based on the clock phase pacing parameters and the reference voltage pacing parameters, determine the offset voltage of the target clock comparator under each preset operating parameter using the offset voltage detection circuit, so as to obtain an offset voltage lookup table.

[0029] Specifically, after determining the clock phase step parameters and the reference voltage step parameters, this embodiment can determine the offset voltage of the target clock comparator under each preset operating parameter based on the offset voltage detection circuit according to the clock phase step parameters and the reference voltage step parameters, so as to obtain an offset voltage lookup table.

[0030] Optionally, as one implementation, the offset voltage detection circuit can be configured to include a reference voltage generation unit, an offset voltage generation unit, and a target clock comparator. The target clock comparator may include a first input terminal and a second input terminal. The first and second input terminals of the target clock comparator can be connected to the reference voltage generation unit, respectively. The reference voltage generation unit can be used to provide the same output voltage to the first and second input terminals. The offset voltage generation unit can be located between the first input terminal and the reference voltage generation unit, or alternatively, the offset voltage generation unit can be located between the second input terminal and the reference voltage generation unit.

[0031] Figure 5 This is a schematic diagram of the offset voltage detection circuit according to an embodiment of the present invention. Figure 5 As shown, Figure 5As shown, the offset voltage detection circuit may include a reference voltage generation unit 51, an offset voltage generation unit 52, and a target clock comparator 53. The target clock comparator may include a first input terminal and a second input terminal. The first and second input terminals of the target clock comparator 53 may be connected to the reference voltage generation unit 51, respectively. The reference voltage generation unit 51 may be used to provide the same output voltage to both the first and second input terminals. The offset voltage generation unit 52 may be positioned between the first input terminal and the reference voltage generation unit 51.

[0032] Alternatively, as an implementation, this embodiment can continuously adjust the relevant operating parameters in the offset voltage detection circuit according to the clock phase step parameters and the reference voltage step parameters, and determine the offset voltage of the target clock comparator under each preset operating parameter, thereby obtaining an offset voltage lookup table.

[0033] Figure 6 This is a flowchart illustrating the method for determining the offset voltage lookup table according to an embodiment of the present invention. It is intended to illustrate that by executing... Figure 6 The method for determining the offset voltage lookup table shown in this embodiment involves continuously adjusting the relevant operating parameters in the offset voltage detection circuit based on the clock phase step parameters and the reference voltage step parameters, and determining the offset voltage of the target clock comparator under each preset operating parameter, thereby obtaining the offset voltage lookup table, which achieves step S220 above. Figure 6 As shown, the method for determining the offset voltage lookup table may specifically include the following steps: Step S210: Control the reference voltage generation unit to output an initial preset reference voltage.

[0034] Specifically, this embodiment can control the reference voltage generation unit to output an initial preset reference voltage. The specific setting of this initial preset reference voltage can be determined by relevant personnel, and this application does not impose any specific limitations on it.

[0035] Step S220: Adjust the clock phase of the target clock comparator sequentially according to the clock phase pacing parameters, and determine the offset voltage of the target clock comparator under each preset clock phase.

[0036] Specifically, while keeping the output voltage of the reference voltage generation unit constant, this embodiment can sequentially adjust the clock phase of the target clock comparator according to the clock phase stepping parameter (that is, adjust the clock phase of the target clock comparator to each preset clock phase), and determine the offset voltage of the target clock comparator at each preset clock phase. The offset voltage of the target clock comparator at each preset clock phase can be determined by iteratively adjusting the output voltage of the offset voltage generation unit. The offset voltage can specifically be the critical voltage value that enables the target clock comparator to switch its output. It should be noted that when iteratively adjusting the output voltage of the offset voltage generation unit to determine the offset voltage, if no corresponding offset voltage is found after a complete iteration, this embodiment can determine that the target clock comparator does not have a corresponding offset voltage at the current preset clock phase. In this case, the offset voltage can be recorded as "NA" in the offset voltage lookup table.

[0037] Step S230: Detect whether there is an undetermined offset voltage under the corresponding preset operating parameters.

[0038] Specifically, after determining the offset voltage of the target clock comparator under each preset clock phase, this embodiment can detect whether there is an offset voltage under the corresponding preset operating parameters that has not been determined. If so, this embodiment can continue to execute step S240 to continue the iterative process. If not, this embodiment can end the iterative process.

[0039] Step S240: Adjust the output voltage of the reference voltage generation unit according to the reference voltage stepping parameters.

[0040] Specifically, when it is detected that the offset voltage under the corresponding preset operating parameters has not been determined, this embodiment can adjust the output voltage of the reference voltage generation unit according to the reference voltage stepping parameters, that is, control the reference voltage generation unit to output the next preset reference voltage.

[0041] Step S300: Determine the 2D shmoo statistical eye diagram of the parallel interface under test based on the relationship between the offset voltage lookup table and the simulation statistical eye diagram.

[0042] Specifically, after obtaining the offset voltage lookup table, this embodiment can determine the 2D shmoo statistical eye diagram of the parallel interface under test based on the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The 2D shmoo statistical eye diagram can be used to characterize the impact of clock phase and reference voltage on the performance of the parallel interface under test.

[0043] Figure 7 This is a flowchart of a 2D shmoo statistical eye diagram determination method according to an embodiment of the present invention. It is intended to illustrate that by executing... Figure 7 The 2D shmoo statistical eye diagram determination method shown in this embodiment can determine the 2D shmoo statistical eye diagram of the parallel interface under test based on the relationship between the offset voltage lookup table and the simulated statistical eye diagram, that is, to implement the above step S300. Figure 7 As shown, the 2D shmoo statistical eye map determination method may specifically include the following steps: Step S310: Determine the comparator discrimination result of the parallel interface under test under each of the preset operating parameters based on the offset voltage lookup table and the simulation statistical eye diagram.

[0044] Specifically, this embodiment can determine the comparator discrimination result of the parallel interface under test under various preset operating parameters based on the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The comparator discrimination result can be used to characterize whether the signal transmitted by the parallel interface can be correctly discriminated by the clock comparator under the corresponding preset operating parameters.

[0045] Figure 8 This is a flowchart of a comparator discrimination result determination method according to an embodiment of the present invention. It is intended to illustrate that by executing... Figure 8 The comparator discrimination result determination method shown in this embodiment can determine the comparator discrimination result of the parallel interface under test under various preset operating parameters based on the relationship between the offset voltage lookup table and the simulation statistical eye diagram, that is, to realize the above step S310. Figure 8 As shown, the method for determining the comparator discrimination result may specifically include the following steps: Step S311: Determine the corresponding eye height of the simulated statistical eye diagram under each preset clock phase.

[0046] Specifically, this embodiment can determine the corresponding eye height of the simulated statistical eye diagram at each preset clock phase. The corresponding eye height of the simulated statistical eye diagram at each preset clock phase can be considered as the voltage difference between the differential signal pairs transmitted by the parallel interface under test at each preset clock phase. It should be noted that, in this embodiment, the simulated statistical eye diagram can be viewed as a graph formed by the superposition of the differential signal pairs transmitted by the parallel interface. Furthermore, since changes in the preset reference voltage do not affect the voltage difference between the differential signal pairs, this embodiment only needs to determine the corresponding eye height of the simulated statistical eye diagram at each preset clock phase.

[0047] Figure 9 This is a schematic diagram of a simulated statistical eye diagram according to an embodiment of the present invention. Figure 9 As shown, assuming the preset reference voltage includes a preset clock phase τ1, this embodiment can determine the corresponding eye height EH1 of the simulated statistical eye diagram under the preset clock phase τ1 for the preset clock phase τ1.

[0048] Step S312: For each preset clock phase, determine the comparator discrimination result of the parallel interface under test at each preset reference voltage according to the corresponding eye height and the offset voltage lookup table.

[0049] Specifically, for each preset clock phase, this embodiment can determine the comparator discrimination result of the parallel interface under test at each preset reference voltage based on the corresponding eye height and offset voltage lookup table.

[0050] Optionally, in step S312, in order to determine the comparator discrimination result of the parallel interface under test under each preset reference voltage, this embodiment can first look up the corresponding offset voltage of the target clock comparator under each preset reference voltage in the offset voltage lookup table, and then compare each corresponding offset voltage with the corresponding eye height to determine the comparator discrimination result of the parallel interface under test under each preset reference voltage.

[0051] Figure 10 This is a schematic diagram of the corresponding offset voltage in an embodiment of the present invention. Figure 10 As shown, assuming the preset reference voltage includes a preset clock phase τ1, then for the preset clock phase τ1, this embodiment can determine the corresponding offset voltages V1-Vn of the target clock comparator under each preset reference voltage by looking up the offset voltage lookup table. Furthermore, after determining the corresponding offset voltages V1-Vn of the target clock comparator under each preset reference voltage, this embodiment can compare the corresponding offset voltages V1-Vn with the corresponding eye height (e.g., eye height). Figure 9 The comparison is performed using EH1 (as shown in the diagram) to determine the comparator's discrimination result for the parallel interface under test at each preset reference voltage. It is worth noting that when comparing each corresponding offset voltage with its corresponding eye height, if the corresponding eye height is greater than or equal to the corresponding offset voltage, this embodiment confirms that the comparator's discrimination result indicates the signal transmitted by the parallel interface can be correctly discerned by the clock comparator. If the corresponding eye height is less than the corresponding offset voltage, this embodiment confirms that the comparator's discrimination result indicates the signal transmitted by the parallel interface cannot be correctly discerned by the clock comparator. Furthermore, for offset voltages recorded as "NA", this embodiment consistently confirms that the comparator's discrimination result indicates the signal transmitted by the parallel interface cannot be correctly discerned by the clock comparator.

[0052] Step S320: Determine the 2D shmoo statistical eye diagram of the parallel interface under test based on the comparator discrimination results of the parallel interface under test under each preset operating parameter.

[0053] Specifically, after determining the comparator discrimination results of the parallel interface under test under each preset operating parameter, this embodiment can determine the 2D shmoo statistical eye diagram of the parallel interface under test based on the comparator discrimination results of the parallel interface under test under each preset operating parameter.

[0054] Figure 11 This is a schematic diagram of a 2D shmoo statistical eye diagram according to an embodiment of the present invention. Figure 11 As shown, assuming the preset reference voltage includes a preset clock phase τ1, then for the preset clock phase τ1, after determining the corresponding offset voltages V1-Vn of the target clock comparator under each preset reference voltage, this embodiment can obtain the comparator discrimination result 1111. The comparator discrimination result 1111 can be used as part of the finally determined 2D shmoo statistical eye diagram.

[0055] This invention discloses a method and apparatus for determining a statistical eye diagram. The method involves acquiring a simulated statistical eye diagram of the parallel interface under test up to the receiving end, and obtaining the characteristics of the clock comparator. Based on an offset voltage detection circuit, the offset voltage of the target clock comparator under various preset operating parameters is detected to determine an offset voltage lookup table. Then, the 2D shmoo statistical eye diagram of the parallel interface under test is determined according to the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The preset operating parameters include a preset clock phase and a preset reference voltage. The 2D shmoo statistical eye diagram is used to characterize the impact of the clock phase and reference voltage on the performance of the parallel interface under test. Therefore, this invention can model the comparator characteristics to generate an accurate 2D shmoo statistical eye diagram during the simulation phase and ensure that the 2D shmoo statistical eye diagram corresponds to the 2D shmoo eye diagram in the actual measurement phase.

[0056] Figure 12 This is a schematic diagram of a statistical eye diagram determination device according to an embodiment of the present invention. Figure 12 As shown, the statistical eye diagram determination device of this embodiment includes a simulation statistical eye diagram acquisition unit 121, an offset voltage lookup table determination unit 122, and a statistical eye diagram generation unit 123.

[0057] Specifically, the simulation statistical eye diagram acquisition unit 121 is used to acquire the simulation statistical eye diagram of the parallel interface under test before the receiving end.

[0058] The offset voltage lookup table determination unit 122 is used to obtain the characteristics of the clock comparator and determine the offset voltage of the target clock comparator under various preset operating parameters based on the offset voltage detection circuit, so as to obtain the offset voltage lookup table. The preset operating parameters include preset clock phase and preset reference voltage.

[0059] The statistical eye diagram generation unit 123 is used to determine the 2D shmoo statistical eye diagram of the parallel interface under test according to the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The 2D shmoo statistical eye diagram is used to characterize the influence of clock phase and reference voltage on the performance of the parallel interface under test.

[0060] This invention discloses a method and apparatus for determining a statistical eye diagram. The method involves acquiring a simulated statistical eye diagram of the parallel interface under test up to the receiving end, and obtaining the characteristics of the clock comparator. Based on an offset voltage detection circuit, the offset voltage of the target clock comparator under various preset operating parameters is detected to determine an offset voltage lookup table. Then, the 2D shmoo statistical eye diagram of the parallel interface under test is determined according to the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The preset operating parameters include a preset clock phase and a preset reference voltage. The 2D shmoo statistical eye diagram is used to characterize the impact of the clock phase and reference voltage on the performance of the parallel interface under test. Therefore, this invention can model the comparator characteristics to generate an accurate 2D shmoo statistical eye diagram during the simulation phase and ensure that the 2D shmoo statistical eye diagram corresponds to the 2D shmoo eye diagram in the actual measurement phase.

[0061] Figure 13 This is a schematic diagram of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 13 includes a server, a terminal, etc. Figure 13 As shown, the electronic device 13 includes at least one processor 131; a memory 132 communicatively connected to at least one processor 131; and a communication component 133 communicatively connected to a scanning device, wherein the communication component 133 receives and transmits data under the control of the processor 131; wherein the memory 132 stores instructions executable by at least one processor 131, the instructions being executed by at least one processor 131 to implement the above-described statistical eye diagram determination method.

[0062] Specifically, the electronic device includes: one or more processors 131 and a memory 132. Figure 13 Taking a processor 131 as an example, the processor 131 and the memory 132 can be connected via a bus or other means. Figure 13 Taking a bus connection as an example, memory 132, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Processor 131 executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in memory 132, thereby implementing the above-mentioned statistical eye diagram determination method.

[0063] Memory 132 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store an option list, etc. Furthermore, memory 132 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 132 may optionally include memory remotely located relative to processor 131, and these remote memories may be connected to external devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0064] One or more modules are stored in memory 132 and, when executed by one or more processors 131, perform the statistical eye diagram determination method in any of the above method embodiments.

[0065] The above-mentioned products can perform the methods provided in the embodiments of this application, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of this application.

[0066] This invention discloses a method and apparatus for determining statistical eye diagrams. The method involves acquiring the simulated statistical eye diagram of the parallel interface under test before the receiving end, and obtaining the characteristics of the clock comparator. Based on an offset voltage detection circuit, the offset voltage of the target clock comparator under various preset operating parameters is detected to determine an offset voltage lookup table. Then, the 2D shmoo statistical eye diagram of the parallel interface under test is determined according to the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The preset operating parameters include a preset clock phase and a preset reference voltage. The 2D shmoo statistical eye diagram is used to characterize the impact of the clock phase and reference voltage on the performance of the parallel interface under test. Therefore, this invention can model the comparator characteristics to generate an accurate 2D shmoo statistical eye diagram during the simulation phase and ensure that the 2D shmoo statistical eye diagram corresponds to the 2D shmoo eye diagram in the actual measurement phase. (Statistical eye diagram determination) Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.

[0067] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0068] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for determining statistical eye diagrams, characterized in that, The method includes: Obtain the simulation statistical eye diagram of the parallel interface under test before the receiving end; The characteristics of the clock comparator are obtained, and the offset voltage of the target clock comparator under various preset operating parameters is determined based on the offset voltage detection circuit to obtain an offset voltage lookup table. The preset operating parameters include a preset clock phase and a preset reference voltage. The 2D shmoo statistical eye diagram of the parallel interface under test is determined based on the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The 2D shmoo statistical eye diagram is used to characterize the impact of clock phase and reference voltage on the performance of the parallel interface under test.

2. The method according to claim 1, characterized in that, The process of acquiring the characteristics of the clock comparator and determining the offset voltage of the target clock comparator under various preset operating parameters based on the offset voltage detection circuit to obtain an offset voltage lookup table includes: Determine the clock phase pacing parameters and the reference voltage pacing parameters; Based on the clock phase pacing parameters and the reference voltage pacing parameters, the offset voltage of the target clock comparator under each preset operating parameter is determined by the offset voltage detection circuit to obtain an offset voltage lookup table.

3. The method according to claim 2, characterized in that, The offset voltage detection circuit includes a reference voltage generation unit, an offset voltage generation unit, and a target clock comparator. The target clock comparator includes a first input terminal and a second input terminal. The first and second input terminals of the target clock comparator are respectively connected to the reference voltage generation unit. The reference voltage generation unit is used to provide the same output voltage to the first input terminal and the second input terminal. The offset voltage generation unit is disposed between the first input terminal and the reference voltage generation unit, or the offset voltage generation unit is disposed between the second input terminal and the reference voltage generation unit.

4. The method according to claim 3, characterized in that, The step of determining the offset voltage of the target clock comparator under various preset operating parameters based on the clock phase pacing parameters and the reference voltage pacing parameters, and obtaining the offset voltage lookup table, includes: The reference voltage generation unit is controlled to output an initial preset reference voltage, and the following steps are executed iteratively until the offset voltage of the target clock comparator under each preset operating parameter is determined, so as to obtain the offset voltage lookup table: The clock phase of the target clock comparator is adjusted sequentially according to the clock phase pacing parameters, and the offset voltage of the target clock comparator under each preset clock phase is determined respectively. The output voltage of the reference voltage generation unit is adjusted according to the reference voltage stepping parameters.

5. The method according to claim 4, characterized in that, The offset voltage of the target clock comparator at each preset clock phase is determined by iteratively adjusting the output voltage of the offset voltage generation unit.

6. The method according to claim 1, characterized in that, The step of determining the 2D Shmoo statistical eye diagram of the parallel interface under test based on the relationship between the offset voltage lookup table and the simulated statistical eye diagram includes: The comparator discrimination result of the parallel interface under test under each preset operating parameter is determined based on the offset voltage lookup table and the simulation statistical eye diagram. The 2D shmoo statistical eye diagram of the parallel interface under test is determined based on the comparator discrimination results under each preset operating parameter.

7. The method according to claim 6, characterized in that, The step of determining the comparator discrimination result of the parallel interface under test under each preset operating parameter based on the offset voltage lookup table and the simulation statistical eye diagram includes: Determine the corresponding eye height of the simulated statistical eye diagram under each of the preset clock phases; For each preset clock phase, the comparator discrimination result of the parallel interface under test at each preset reference voltage is determined according to the corresponding eye height and the offset voltage lookup table.

8. The method according to claim 7, characterized in that, The step of determining the comparator discrimination result of the parallel interface under test at each preset reference voltage based on the corresponding eye height and the offset voltage lookup table includes: The offset voltage of the target clock comparator under each preset reference voltage is determined by querying the offset voltage lookup table. Each of the corresponding offset voltages is compared with the corresponding eye height to determine the comparator discrimination result of the parallel interface under test at each of the preset reference voltages.

9. A statistical eye diagram determination device, characterized in that, The device includes: The simulation statistical eye diagram acquisition unit is used to acquire the simulation statistical eye diagram of the parallel interface under test before the receiving end; Offset voltage lookup table determination unit is used to obtain the characteristics of the clock comparator, determine the offset voltage of the target clock comparator under various preset operating parameters based on the offset voltage detection circuit, and obtain the offset voltage lookup table. The preset operating parameters include preset clock phase and preset reference voltage. The statistical eye diagram generation unit is used to determine the 2D shmoo statistical eye diagram of the parallel interface under test based on the relationship between the offset voltage lookup table and the simulated statistical eye diagram. The 2D shmoo statistical eye diagram is used to characterize the impact of clock phase and reference voltage on the performance of the parallel interface under test.

10. A computer-readable storage medium storing computer program instructions thereon, characterized in that, The computer program instructions, when executed by a processor, implement the method as described in any one of claims 1-8.

11. An electronic device, characterized in that, The device includes: Memory is used to store one or more computer program instructions; A processor, wherein the one or more computer program instructions are executed by the processor to implement the method as described in any one of claims 1-8.

12. A computer program product, characterized in that, When the computer program product is run on a computer, it causes the computer to perform the method as described in any one of claims 1-8.

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