A cable riser assembly and design method

Abstract

The application relates to a cable riser cable assembly and a design method, and belongs to the technical field of PCB assembly design and manufacturing. The design method comprises the following steps: selecting a shielding wire suitable for PCIe signal transmission of an adaptive server; connecting a connector with a PCIe expansion card pad, connecting a high-speed signal transmission wire with a high-speed signal pad of a UBC high-speed connector and a PCIe expansion card, connecting a low-speed communication transmission wire with a low-speed plastic shell connector and a communication pad and an idle pad of the PCIe expansion card, and electrically connecting a power connector with a power supply pad of the PCIe expansion card; short-circuiting the PCIe expansion card pad; building a management communication channel, and constructing a management communication channel independent of a high-speed PCIe link; performing PCIe protocol simulation and link configuration, and reporting PCIe link topology information to a server mainboard according to a new architecture protocol specification, and completing PCIe link configuration. The application is used for solving the technical problem that an old architecture design riser card cannot be recognized by a new architecture server and is directly used without compatibility.

Description

Technical Field

[0001] This invention belongs to the field of PCB component design and manufacturing technology, and specifically relates to a cable riser assembly and its design method. Background Technology

[0002] With the rapid iteration of server technology, processor platforms and peripheral I / O architectures are undergoing frequent upgrades. As a core component for CPU PCIe channel expansion, the compatibility of server PCIe Riser cards with new architecture servers has become a key technical issue. New architecture servers have placed new demands on the management of PCIe resources, requiring PCIe Riser cards to integrate microcontroller units (MCUs) and actively send port topology information to the host through specific protocols in order to be correctly identified and initialized.

[0003] Existing Riser cards designed for the old architecture lack MCU and corresponding protocol support, making them unrecognizable by new architecture servers and completely incompatible for direct use. Redesigning and producing Riser cards that conform to the new architecture specifications would result in high R&D, material, and manufacturing costs, while also wasting resources on existing inventory of old architecture Riser cards. Furthermore, the long design and mass production cycle would prevent a rapid response to deployment needs during architecture switching. Summary of the Invention

[0004] This invention provides a cable riser assembly and design method to solve the problem that older architecture riser cards cannot be recognized by new architecture servers, and directly using completely incompatible technologies is problematic.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution: A design method for a cable riser assembly includes the following steps: Step 1, cable selection: Select shielded cables suitable for server PCIe signal transmission, using them as high-speed signal transmission cables and low-speed communication transmission cables respectively, to ensure signal transmission integrity and reduce electromagnetic interference; Step 2, connector and PCIe expansion card pad connection: Connect the high-speed signal transmission cable to the UBC high-speed connector and the high-speed signal pad of the PCIe expansion card; connect the low-speed communication transmission cable to the low-speed plastic shell connector and the communication pad and unused pad of the PCIe expansion card; simultaneously, electrically connect the power connector to the power supply pad of the PCIe expansion card; Step 3, short-circuit the PCIe expansion card pads to conduct electricity. The topology information transmission pads and idle topology pads on the Ie expansion card are shorted with solder to achieve signal pin conduction between the UBC high-speed connector and the low-speed plastic shell connector, and the ground pins of both are connected to the ground pad of the PCIe expansion card; Step 4: Management communication channel construction. A low-speed cable adapter is connected to the low-speed plastic shell connector to adapt the adapter to the signal adapter unit, thus constructing a management communication channel independent of the high-speed PCIe link; Step 5: PCIe protocol simulation and link establishment configuration. The protocol communication behavior of the microcontroller unit under the new architecture is simulated through the signal adapter unit, and the PCIe link topology information is reported to the server motherboard according to the new architecture protocol specification to complete the PCIe link establishment.

[0006] Furthermore, in step one, the high-speed signal transmission line is a 1-core shielded cable with aluminum foil Mylar, and the low-speed communication transmission line is a 2-core shielded cable. The shielding coverage of the aluminum foil Mylar is not less than 95%, and the core wires are all made of tin-plated copper wire to improve conductivity.

[0007] Further, in step two, the signal pin of the UBC high-speed connector is pin B30, and the ground pin is pin B31. Pin B30 is connected to the TP14 topology information transmission pad of the PCIe expansion card, and pin B31 is connected to the TP158 ground pad of the PCIe expansion card. The low-speed plastic shell connector is a PH2.0mm²X8P specification, with pin 16 connected to the TP15 unused topology pad of the PCIe expansion card, and pin 11 connected to the TP122 ground pad of the PCIe expansion card. The power connector is a PH3.0mm²x2P specification, with its power supply pin forming a reverse connection protection electrical connection with the 3.3V power supply pad of the PCIe expansion card.

[0008] Furthermore, in step three, since the TP14 pad of the PCIe expansion card can only accommodate one electronic line, the TP14 pad and the TP15 pad are connected by a short-circuiting process with solder bridging. The short-circuit point is covered with UV glue for protection, so as to achieve stable conduction between the B30 pin of the UBC high-speed connector and the 16 pin of the low-speed plastic shell connector. In addition, the grounding pins of both the UBC high-speed connector and the low-speed plastic shell connector are reliably grounded to the grounding pad of the PCIe expansion card.

[0009] Furthermore, in step four, the signal conversion unit is provided with a first connection interface and a second connection interface. The first connection interface is a low-speed connector interface adapted to the existing V2 architecture Riser card, and is precisely adapted to the low-speed plastic shell connector through a low-speed cable adapter. The second connection interface is a standard communication interface adapted to the new architecture server motherboard, and is connected to the corresponding interface of the server motherboard.

[0010] Furthermore, in step five, the signal transfer unit has a HISPORT protocol program embedded inside, which simulates the behavior of the microcontroller unit on the new architecture Riser card. After power-on, it actively sends TX TOPOLOGY port topology information to the server motherboard, so that the server motherboard recognizes the combination of the existing V2 Riser card and this cable assembly as a device that conforms to the new architecture specification.

[0011] Furthermore, the cable riser assembly manufactured by the aforementioned design method includes a PCIe expansion card, a UBC high-speed connector, a power connector, a low-speed plastic shell connector, wires, and a signal conversion unit. The topology information transmission pads of the PCIe expansion card are shorted and connected to the idle topology pads. The wires are divided into high-speed and low-speed types to realize signal transmission between the corresponding connectors and pads. The signal conversion unit adapts to the low-speed plastic shell connector and simulates the new architecture protocol.

[0012] Furthermore, the PCIe expansion card is equipped with at least one PCIe slot, the slot layout of which matches the slot layout of the existing V2 architecture Riser card, allowing the installation of standard PCIe device cards and realizing flexible expansion of the CPU PCIe channel; the signal conversion unit also includes a signal processing module, which is based on a low-cost microcontroller and has a new architecture communication protocol embedded in it, enabling it to actively send topology information requesting resources to the server motherboard.

[0013] This invention provides a cable riser assembly and its design method, with the following advantages: By using the design method as the core technical solution, the standardized design of the cable assembly is achieved step by step without modifying the existing V2 Riser card hardware, achieving near-zero R&D cost and solving the compatibility problem between old cards and new architecture servers; through precise cable selection and corresponding connector pad connection design, stable transmission of PCIe high-speed signals and low-speed topology information is ensured, and the use of aluminum foil Mylar shielding significantly reduces the impact of electromagnetic interference on signals; the soldering shorting process achieves signal pin conduction for different connectors, cleverly solving the problem of limited soldering space on PCIe expansion card pads, and UV adhesive protection improves connection stability and lifespan; by solidifying the HISPORT protocol and simulating MCU behavior in the signal conversion unit, the server motherboard can correctly identify existing old cards, achieving architecture compatibility at the protocol level, with a near 100% connection success rate; the cable assembly made based on this design method is a plug-and-play upgrade kit, reusing existing V2... The idle interfaces and pads of the Riser card make use of existing inventory and avoid waste of hardware resources. Each step of this design method adopts standardized electronic processing technology, which can achieve mass production in ordinary processing plants. The development and verification cycle is short, which can quickly respond to the urgent deployment needs of server architecture switching. At the same time, the component deployment is flexible and does not require modification of the server chassis. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a cable riser assembly provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the design flow of a cable riser assembly design method provided in an embodiment of the present invention; Figure 3 A schematic diagram showing the connection between a PCIe expansion card and a UBC high-speed connector in the cable assembly process implementation scheme provided in this embodiment of the invention. Figure 4 A schematic diagram of the connection between the PCIe expansion card and the UBC high-speed connector in the cable assembly process implementation scheme provided in this embodiment of the invention (continued) Figure 3 ); Figure 5A schematic diagram of the connection between the PCIe expansion card and the power connector for the cable assembly process implementation scheme provided in the embodiments of the present invention; Figure 6 A schematic diagram showing the connection between a PCIe expansion card and a low-speed plastic shell connector in the cable assembly process implementation scheme provided in this embodiment of the invention.

[0016] In the diagram: P1 - PCIe expansion card; P3 - power connector; P2 - UBC high-speed connector; P4 - low-speed plastic shell connector; 1 - wire. Detailed Implementation

[0017] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0018] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0019] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to welding, bolting, or riveting; they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0021] Example: like Figures 1 to 6As shown, this embodiment provides a design method for a cable riser assembly, including the following steps: Step 1: Cable selection. Select shielded cable 1 adapted to server PCIe signal transmission, serving as both high-speed signal transmission cable 1 and low-speed communication transmission cable 1, ensuring signal transmission integrity and reducing electromagnetic interference; Step 2: Connect the connectors to the corresponding pads of the PCIe expansion card P1. Connect the high-speed signal transmission cable 1 to the UBC high-speed connector P2 and the high-speed signal pad of the PCIe expansion card P1. Connect the low-speed communication transmission cable 1 to the low-speed plastic shell connector P4 and the communication pad and unused pad of the PCIe expansion card P1. Simultaneously, electrically connect the power connector P3 to the power supply pad of the PCIe expansion card P1; Step 3: Short-circuit the pads of the PCIe expansion card P1. Step 1: Connect the topology information transmission pads and idle topology pads on PCIe expansion card P1 by soldering them together to achieve signal pin connectivity between UBC high-speed connector P2 and low-speed plastic shell connector P4. Also, connect the ground pins of both connectors to the ground pad of PCIe expansion card P1. Step 4: Establish the management communication channel by connecting a low-speed cable adapter to the low-speed plastic shell connector P4, ensuring the adapter is compatible with the signal adapter unit, and constructing a management communication channel independent of the high-speed PCIe link. Step 5: Simulate and configure the PCIe protocol by simulating the protocol communication behavior of the microcontroller unit under the new architecture through the signal adapter unit. Report the PCIe link topology information to the server motherboard according to the new architecture protocol specifications to complete the PCIe link establishment.

[0022] In this embodiment, the design method is specifically designed for Huawei Kunpeng V3 architecture servers. The entire process revolves around adapting to the hardware resources of existing V2 architecture Riser cards. All steps do not involve hardware modifications to the V2 Riser cards. The overall development cycle is controlled within 15 working days, significantly shorter than the development cycle of redesigning a V3 Riser card, and the development cost is less than 5% of that of a new card design. The specific steps are as follows: Step S100: Cable selection. Select shielded cables that are compatible with the server's PCIe signal transmission. Step S200: Connect the connector to the corresponding pads of the PCIe expansion card; Step S300: Short-circuit the PCIe expansion card pads to make them conductive, and perform solder short-circuit treatment on the topology information transmission pads and idle topology pads on the PCIe expansion card. Step S400: Establish a management communication channel, building a management communication channel independent of the high-speed PCIe link; Step S500: PCIe protocol simulation and chain configuration to complete PCIe chain establishment.

[0023] Furthermore, in step one, the high-speed signal transmission line 1 is a shielded wire with a single core and a layer of aluminum foil Mylar, and the low-speed communication transmission line 1 is a shielded cable with two cores. The shielding coverage of the aluminum foil Mylar is not less than 95%, and the core wires are all made of tin-plated copper wire to improve conductivity.

[0024] In this embodiment, the high-speed signal transmission line 1 has a 28AWG tinned copper wire core and a ground wire tightly connected to an aluminum foil Mylar shielding layer, forming a double-layer anti-interference protection to meet the high-speed signal transmission requirements of PCIe 4.0, with a transmission rate of up to 32Gbps. The low-speed communication transmission line 1 has a 30AWG tinned copper wire core and a braided mesh + aluminum foil composite shielding layer to ensure a low bit error rate for topology information reporting, with the bit error rate controlled at 10⁻⁻⁶. 9 the following.

[0025] Further, in step two, the signal pin of the UBC high-speed connector P2 is pin B30, and the ground pin is pin B31. Pin B30 is connected to the TP14 topology information transmission pad of the PCIe expansion card P1, and pin B31 is connected to the TP158 ground pad of the PCIe expansion card P1. The low-speed plastic shell connector P4 is a PH2.0mm2x8P specification, with pin 16 connected to the TP15 unused topology pad of the PCIe expansion card P1, and pin 11 connected to the TP122 ground pad of the PCIe expansion card P1. The power connector P3 is a PH3.0mm2x2P specification, with its power supply pin forming a reverse connection protection electrical connection with the 3.3V power supply pad of the PCIe expansion card P1.

[0026] In this embodiment, all connectors and pads are connected using wave soldering, with the soldering temperature controlled at 260±5℃ and the soldering time at 3-5 seconds, to avoid high-temperature damage to the pads and connectors. The pin definitions of the UBC high-speed connector P2 are fully matched with the UBC interface of the V3 architecture server motherboard. Pins 2 and 4 of the low-speed plastic shell connector P4 are standard I2C communication pins, which are connected to the SMDAT and SMCLK pads of the PCIe expansion card P1, respectively. The remaining unused pins are left open and combined with the cable bundle 1 to increase the strength of the cable bundle 1. The power supply pins of the power connector P3 adopt a staggered reverse connection protection design, outputting a stable 3.3V standby voltage and having a 5A overcurrent protection function.

[0027] Furthermore, in step three, since the TP14 pad of the PCIe expansion card P1 can only accommodate one electronic line, the TP14 pad and the TP15 pad are connected by a shorting process with solder bridging. The shorting point is covered and protected with UV glue to achieve stable connection between the B30 pin of the UBC high-speed connector P2 and the 16 pin of the low-speed plastic shell connector P4. The grounding pins of both the UBC high-speed connector P2 and the low-speed plastic shell connector P4 are reliably grounded to the grounding pad of the PCIe expansion card P1.

[0028] In this embodiment, the solder shorting is performed using a manual precision soldering process with φ0.3mm lead-free solder wire. After soldering, the conductivity is tested with a multimeter, and the conductivity resistance is controlled within 50mΩ. Photosensitive UV adhesive is applied to the shorting point, and after curing under UV light, a protective layer is formed, which can effectively prevent oxidation and short circuit problems, improve the long-term stability of the connection, and achieve a fault-free working time of more than 50,000 hours in the high temperature and vibration working environment of the server.

[0029] Furthermore, in step four, the signal conversion unit is provided with a first connection interface and a second connection interface. The first connection interface is a low-speed connector interface adapted to the existing V2 architecture Riser card, and is precisely adapted to the low-speed plastic shell connector P4 through a low-speed cable adapter. The second connection interface is a standard communication interface adapted to the new architecture server motherboard, and is connected to the corresponding interface of the server motherboard.

[0030] In this embodiment, the signal conversion unit is a miniaturized PCB board measuring 50mm×30mm×5mm, which can be directly installed in an unused space in the server chassis. It connects to the low-speed plastic shell connector P4 via DuPont wires as a low-speed cable adapter. The first connection interface is a PH2.0mm 2X8P female connector, which is perfectly compatible with the male connector of the low-speed plastic shell connector P4, reusing the idle pin resources of the V2 Riser card. The second connection interface is a HISPORT protocol pin header interface, which is a standard feature of V3 architecture server motherboards and adopts a foolproof design to avoid damage to the device caused by reverse connection.

[0031] Furthermore, in step five, the signal transfer unit has a HISPORT protocol program embedded inside, which simulates the behavior of the microcontroller unit on the new architecture Riser card. After power-on, it actively sends TX TOPOLOGY port topology information to the server motherboard, so that the server motherboard recognizes the combination of "existing V2 Riser card + this cable assembly" as a device that conforms to the new architecture specification.

[0032] In this embodiment, the core of the signal switching unit is the STM32F030 low-cost microcontroller. The on-chip Flash has the HISPORT protocol program embedded in it. After power-on, it completes initialization within 500ms and sends TX TOPOLOGY port topology information to the server BMC. The information includes key parameters such as the number of PCIe slots, channel bandwidth, and link speed, which are completely consistent with the information reported by the V3 architecture Riser card, enabling the server motherboard to complete normal device identification and initialization.

[0033] Furthermore, the cable riser assembly manufactured by the aforementioned design method includes: a PCIe expansion card (corresponding to P1, i.e., PCIe expansion card), which has functional pads and idle pads. The functional pads include high-speed signal pads, ground pads, and power supply pads. The idle pads include idle topology pads, and the topology information transmission pads and idle topology pads are connected by a solder bridge; a UBC high-speed connector P2, which is electrically connected to the high-speed signal pads of the PCIe expansion card P1, serving as the CPU. The PCIe high-speed signal physical transmission interface; power connector P3, electrically connected to the power supply pads of the PCIe expansion card P1, providing a stable power supply for the PCIe expansion card P1; low-speed plastic shell connector P4, electrically connected to the communication pads and idle pads of the PCIe expansion card P1, used to construct a management communication channel; cable 1, including high-speed signal transmission cable 1 and low-speed communication transmission cable 1, respectively realizing signal transmission between the UBC high-speed connector P2, the low-speed plastic shell connector P4 and the corresponding pads of the PCIe expansion card P1; signal conversion unit, adapted to the low-speed plastic shell connector P4 through a low-speed cable conversion cable, used to simulate the new architecture protocol and report PCIe link topology information.

[0034] In this embodiment, all components of the cable assembly are industrial-grade components with an operating temperature range of -40℃ to 85℃, which is fully compatible with the industrial-grade working environment of the server. The PCIe expansion card P1 is made of FR-4 fiberglass board with immersion gold plating on the pads, which has strong oxidation resistance. Its overall size is fully compatible with the existing V2 Riser card and can be directly embedded in the V2 Riser card's mounting structure.

[0035] Furthermore, the PCIe expansion card P1 is equipped with at least one PCIe slot, the slot layout of which matches the slot layout of the existing V2 architecture Riser card, and can install standard PCIe device cards such as GPUs, NVMe SSDs, and network cards, realizing flexible expansion of the CPU PCIe channel; the signal conversion unit also includes a signal processing module, which is based on a low-cost microcontroller and has a new architecture communication protocol embedded in it, and can actively send topology information of resource requests to the server motherboard.

[0036] In this embodiment, the PCIe expansion card P1 has two PCIe 4.0 x16 slots, with a slot layout completely consistent with the V2 architecture Riser card, compatible with mainstream PCIe device cards on the market, and the maximum power supply per slot can reach 75W; in addition to the microcontroller, the signal processing module also includes a power management chip and a level conversion chip. The power management chip converts the server's 12V voltage to 3.3V to power the microcontroller, and the level conversion chip realizes the level matching between the microcontroller and the server motherboard, ensuring the compatibility of protocol communication.

[0037] In summary, this invention patent achieves cable implementation step by step by using a design method as its core. The standardized design of the riser cable assembly cleverly reuses the idle hardware resources of existing V2 architecture riser cards, fundamentally solving the compatibility issue between older cards and V3 architecture servers. Precise cable selection and connector pad design ensure stable transmission of high-speed PCIe signals and topology information, with significant electromagnetic interference protection. The solder bridging process overcomes the technical challenge of limited pad soldering space, while UV adhesive protection enhances long-term connection stability. By embedding the HISPORT protocol in the signal transfer unit and simulating MCU behavior, protocol-level architecture compatibility is achieved, resulting in fast connection establishment response and a high success rate. The cable assembly produced based on this design method is a plug-and-play upgrade kit, requiring no server or existing older cards modification, resulting in extremely low R&D and manufacturing costs, revitalizing existing inventory, and avoiding resource waste. Furthermore, each step of the design method employs standardized electronic processing technology, making mass production easy and quick, enabling rapid response to urgent deployment needs during server architecture switching. This solution has extremely high commercial application and market promotion value in the field of server PCIe expansion architecture upgrades, significantly reducing the architecture upgrade costs for server manufacturers.

Claims

1. A design method for a cable riser assembly, characterized in that, Includes the following steps: Step 1: Cable selection. Select shielded cables that are compatible with server PCIe signal transmission, and use them as high-speed signal transmission cables and low-speed communication transmission cables respectively. Step 2: Connect the connectors to the corresponding pads of the PCIe expansion card. Connect the UBC high-speed connector to the high-speed signal pads of the PCIe expansion card using a high-speed signal transmission cable. Connect the low-speed plastic shell connector to the communication pads and unused pads of the PCIe expansion card using a low-speed communication transmission cable. At the same time, electrically connect the power connector to the power supply pads of the PCIe expansion card. Step 3: Short-circuit the PCIe expansion card pads. Short-circuit the topology information transmission pads and idle topology pads on the PCIe expansion card with solder. Connect the signal pins of the UBC high-speed connector and the low-speed plastic shell connector to each other, and connect the ground pins of both to the ground pad of the PCIe expansion card. Step 4: Establish a management communication channel. Connect a low-speed cable adapter to the low-speed plastic shell connector to make the adapter compatible with the signal conversion unit and build a management communication channel independent of the high-speed PCIe link. Step 5: PCIe Protocol Simulation and Link Establishment Configuration. The signal switching unit simulates the protocol communication behavior of the microcontroller unit under the new architecture, and reports the PCIe link topology information to the server motherboard according to the new architecture protocol specification to complete the PCIe link establishment.

2. The design method of a cable riser assembly according to claim 1, characterized in that, In step one, the high-speed signal transmission line is a shielded cable with a single core and a bare ground wire combined with aluminum foil Mylar, and the low-speed communication transmission line is a two-core shielded cable with an aluminum foil Mylar shielding coverage of not less than 95%, and all core wires are made of tin-plated copper wire.

3. The design method of a cable riser assembly according to claim 2, characterized in that, In step two, the signal pin of the UBC high-speed connector is pin B30, and the ground pin is pin B31. Pin B30 is connected to the TP14 topology information transmission pad of the PCIe expansion card, and pin B31 is connected to the TP158 ground pad of the PCIe expansion card. The low-speed plastic shell connector is a PH2.0mm²X8P specification, with pin 16 connected to the TP15 unused topology pad of the PCIe expansion card, and pin 11 connected to the TP122 ground pad of the PCIe expansion card. The power connector is a PH3.0mm²x2P specification, with its power supply pin forming a reverse-connection-proof electrical connection with the 3.3V power supply pad of the PCIe expansion card.

4. The design method of a cable riser assembly according to claim 3, characterized in that, In step three, the TP14 pad of the PCIe expansion card can only be soldered with one electronic line. The TP14 pad and the TP15 pad are connected by a short circuit process. The short circuit is covered and protected with UV glue. The B30 pin of the UBC high-speed connector is connected to the 16 pin of the low-speed plastic shell connector. The ground pins of both the UBC high-speed connector and the low-speed plastic shell connector are grounded to the ground pad of the PCIe expansion card.

5. The design method of a cable riser assembly according to claim 4, characterized in that, In step four, the signal conversion unit is provided with a first connection interface and a second connection interface. The first connection interface is a low-speed connector interface adapted to the existing V2 architecture Riser card, and is connected to the low-speed plastic shell connector through a low-speed cable adapter. The second connection interface is a standard communication interface adapted to the new architecture server motherboard, and is connected to the corresponding interface of the server motherboard.

6. The design method of a cable riser assembly according to claim 5, characterized in that, In step five, the signal transfer unit has a HISPORT protocol program embedded inside, which simulates the behavior of the microcontroller unit on the new architecture Riser card. After power-on, it actively sends TX TOPOLOGY port topology information to the server motherboard, so that the server motherboard recognizes the combination of "existing V2 Riser card + this cable assembly" as a device that conforms to the new architecture specification.

7. A cable riser assembly, characterized in that, The cable riser assembly, manufactured according to the design method of claim 6, comprises: a PCIe expansion card with functional pads and idle pads, wherein the functional pads include high-speed signal pads, ground pads, and power supply pads, and the idle pads include idle topology pads, with the topology information transmission pads and the idle topology pads connected by a solder bridge; and a UBC high-speed connector electrically connected to the high-speed signal pads of the PCIe expansion card, serving as a CPU. The system includes: a physical transmission interface for high-speed PCIe signals; a power connector electrically connected to the power supply pads of the PCIe expansion card to provide operating power; a low-speed plastic shell connector electrically connected to the communication pads and idle pads of the PCIe expansion card to construct a management communication channel; cables, including high-speed signal transmission cables and low-speed communication transmission cables, respectively connecting the UBC high-speed connector, the low-speed plastic shell connector, and the corresponding pads of the PCIe expansion card for signal transmission; and a signal conversion unit adapted to the low-speed plastic shell connector via a low-speed cable conversion cable to simulate new architecture protocols and report PCIe link topology information.

8. A cable riser assembly according to claim 7, characterized in that, The PCIe expansion card has at least one PCIe slot, the slot layout of which matches the slot layout of the existing V2 architecture Riser card, for installing standard PCIe device cards and expanding the CPU PCIe channel; the signal conversion unit also includes a signal processing module, which is based on a low-cost microcontroller and has a new architecture communication protocol embedded in it, and can actively send topology information of resource requests to the server motherboard.

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