Graphical semiconductor device layout method and apparatus

Abstract

The application provides a graphical semiconductor device layout method and device, the method comprising: displaying node layouts of a plurality of first nodes and node connection relationships between the plurality of first nodes in a visual operation interface based on layout rendering data; in the case of detecting a target user operation instruction, responding to the target user operation instruction to display edited node layouts and edited node connection relationships on the visual operation interface; determining all device nodes as at least one to-be-verified device node, and determining device ports of each to-be-verified device node and device port connection edges of each to-be-verified device node; verifying each to-be-verified device node based on the device port connection edges and the group identifiers corresponding to each device port; and in the case of failing to pass the device connection rule verification, outputting alarm indication information of an abnormal device layout. The method can realize visual device layout with high layout efficiency and high layout accuracy.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method and apparatus for layout of patterned semiconductor devices. Background Technology

[0002] In the field of advanced semiconductor packaging, through-hole boards are miniature devices or miniature metal contact components that enable connectivity and communication. A semiconductor packaging system can contain multiple through-hole boards. With the continuous increase in the demand for highly integrated systems in intelligent applications, the design complexity of semiconductor packaging systems has risen sharply. It is necessary to accurately manage the interconnection relationships between a massive number of device ports and through-hole boards, and the difficulty of device layout and coordination far exceeds that of traditional designs.

[0003] Existing technical solutions typically rely on tables (e.g., Excel) for data management, using tables to manage large amounts of device data, PCB data, and interconnection relationships. However, in these existing solutions, the layout results of device ports and PCBs are maintained using tables, and the amount of data and interconnection relationships within these tables are extremely complex, often requiring storage in multiple tables. When verifying the accuracy of the layout results for multiple ports of a particular device, it is necessary to look up the PCB that each device port should connect to in the port-PCB mapping table, and then verify whether the PCB currently connected to that device port is the correct PCB. This significantly increases the difficulty and time cost of verification, limiting the efficiency of device layout. Summary of the Invention

[0004] This application provides a graphical semiconductor device layout method and apparatus, which can improve the accuracy and efficiency of device layout.

[0005] In a first aspect, this application provides a graphical semiconductor device layout method, comprising: displaying the node layout of multiple first nodes and the node connection relationships between the multiple first nodes in a visual operation interface based on the layout rendering data of the semiconductor device; the visual operation interface being used for semiconductor device layout editing; the multiple first nodes including at least one board index node, at least one device node, and at least one device placeholder node; upon detecting a target user operation instruction on the visual operation interface, responding to the target user operation instruction to display the edited node layout and the edited node connection relationships on the visual operation interface; the target user operation instruction including a first operation of editing any one of the board index nodes, a second operation of editing any one of the device nodes, or a third operation of adding a single device node to any one of the device placeholder nodes and the connection relationship between the single device node and a specified board index node; and displaying the edited node layout and node connection relationships in a visual operation interface based on the layout rendering data of the semiconductor device. The edited node connection relationship determines all device nodes as at least one device node to be verified, and identifies the device ports and connection edges of each device node to be verified, wherein each device port has a corresponding group identifier. Based on the device port connection edges and the corresponding group identifiers of each device port, the system verifies whether device ports in the same group of each device node are connected to the same board index node, or whether device ports in different groups of each device node are connected to different board index nodes. If any device port in the same group of any device node is connected to different board index nodes and / or if device ports in different groups of any device node are connected to the same board index node, the device connection rule verification fails. If the device connection rule verification fails, an alarm indication message for device layout abnormality is output.

[0006] In this application, the node layout of multiple first nodes and the node connection relationships between multiple first nodes can be displayed on a visual operation interface based on the layout rendering data of semiconductor devices. When a target user operation command is detected in the visual operation interface, the interface can respond to the target user operation command to display the edited node layout and node connection relationships. After determining all device nodes as at least one device node to be verified based on the edited node layout and node connection relationships, the device connection rules are verified based on the device port connection edges of each device node to be verified and the grouping identifier corresponding to each device port. The method provided in this application enables node layout based on user operation commands on a visual interface, achieving a visual layout of devices and board indexes. The interface displays device nodes, board index nodes, and device placeholder nodes before and after editing, improving device layout efficiency. The device connection rule verification mechanism uses the group identifier corresponding to the device port as a reliable basis to perform static checks on the connection edges of the device port, improving the correctness of the connection between the device port and the board index node, thus contributing to the accuracy of device layout. Furthermore, grouping multiple device ports of the same device node to be verified (i.e., grouping multiple device ports that need to connect to the same board) allows for grouped verification to determine whether device ports within any group are connected to the same board index node, eliminating the need for multiple port board mapping tables to determine this, thus reducing verification pressure and improving verification and device layout efficiency. Simultaneously, in cases where device connection rule verification fails, alarm information for potential layout problems is provided, facilitating timely correction of device layout and further improving device layout efficiency.

[0007] In one possible implementation of the first aspect, before displaying the node layout of multiple first nodes and the node connection relationship between the multiple first nodes in the visualization operation interface based on the above-mentioned semiconductor device layout rendering data, the method further includes: obtaining a two-dimensional matrix for describing the position distribution of the board index and the device, wherein the zero-value elements in the two-dimensional matrix are used to indicate free points, and the non-zero elements in the two-dimensional matrix are used to indicate board indexes or devices; obtaining the attribute data corresponding to the board index or device indicated by each of the above-mentioned non-zero elements and the attribute data of the above-mentioned free points, and converting the attribute data corresponding to the board index or device indicated by each of the above-mentioned non-zero elements and the attribute data of the above-mentioned free points into the layout rendering data of the semiconductor device; wherein the layout rendering data of the semiconductor device includes node attribute data and connection edge attribute data for rendering the nodes corresponding to the board index, device or free point indicated by each element in the above-mentioned two-dimensional matrix, and the connection edge attribute data includes the attribute data of the connection edge between the device port of the device and the port of the board index.

[0008] In this application, a two-dimensional matrix describing the positional distribution of PCB indices and devices can be obtained. Then, attribute data corresponding to the PCB indices or devices indicated by each non-zero element in the two-dimensional matrix, as well as attribute data of the free points, can be obtained. This attribute data, along with the attribute data of the free points, is converted into layout rendering data for semiconductor devices. Here, the layout rendering data can include node attribute data and connection edge attribute data for the nodes (i.e., PCB index nodes, device nodes, or device placeholder nodes) corresponding to the PCB indices, devices, or free points indicated by each element in the aforementioned two-dimensional matrix. This enables the parsing of data that lacks readability, such as two-dimensional matrices. By calling the attribute data corresponding to the PCB indices or devices and the attribute data of the free points based on the two-dimensional matrix to obtain visualization rendering data, efficient data visualization processing and data parsing can be achieved. The layout rendering data can accurately render and present the initial device layout and node connection relationships, improving the efficiency and accuracy of subsequent data arrangement.

[0009] In one possible implementation of the first aspect, the above-mentioned layout rendering data based on semiconductor devices, displaying the node layout of multiple first nodes and the node connection relationships between the multiple first nodes in a visual operation interface, includes: rendering the node attribute data corresponding to the board index and / or device included in the layout rendering data of the semiconductor device, so as to render the board index as a board index node and / or render the device as a device node; and rendering the node attribute data corresponding to the free points included in the layout rendering data of the semiconductor device, so as to render the free points as device placeholder nodes, to obtain the node layout of the multiple first nodes; wherein, the board index node... The node shape and layout position of the points, the aforementioned device nodes and the aforementioned device placeholder nodes are defined by the aforementioned board index, the aforementioned device and the aforementioned free point corresponding to the aforementioned node attribute data in the aforementioned layout rendering data; the aforementioned connection edge attribute data included in the aforementioned semiconductor device layout rendering data are rendered to render the connection relationship between the device port of the aforementioned device and the port of the aforementioned board index as the connection edge between the device port and the board index node on the device node, so as to obtain the node layout of the aforementioned plurality of first nodes and the node connection relationship between the aforementioned plurality of first nodes, wherein the device port or board index node connected at both ends of the aforementioned connection edge is defined by the aforementioned connection edge attribute data in the aforementioned semiconductor device layout rendering data.

[0010] In this application, the node attribute data corresponding to the board index and / or device included in the layout rendering data can be rendered to render the board index as a board index node and / or the device as a device node. The node attribute data corresponding to the idle points included in the layout rendering data can also be rendered to render the idle points as device placeholder nodes. The node shape and layout position of each first node are defined by the corresponding node attribute data in the layout rendering data. The connection edge attribute data included in the layout rendering data can also be rendered to render the connection relationship between the device port of the device and the port of the board index as a connection edge between the device port and the board index node on the device node, thus obtaining the node layout of multiple first nodes. It can be understood that the node layout and node connection relationship of multiple first nodes can be rendered based on the layout rendering data, thereby improving the readability of the node attribute data and connection edge attribute data included in the layout rendering data. The layout rendering data can accurately render and present the node layout and node connection relationship of each first node in the visualization interface, which helps to improve the efficiency and accuracy of subsequent node layout implementation on the visualization operation interface.

[0011] In one possible implementation of the first aspect, the above-mentioned verification of whether device ports of the same group in each device node to be verified are connected to the same board index node, or whether device ports of different groups in each device node to be verified are connected to different board index nodes, based on the device port connection edge of each device port to be verified and the group identifier corresponding to each device port, includes: determining the group corresponding to each device port through the group identifier corresponding to each device port; searching for the board index node connected to the device port connection edge of each device node to be verified, so as to obtain the board index node to which each device port is connected; and determining whether device ports of the same group in each device node to be verified are connected to the same board index node, or whether device ports of different groups in each device node to be verified are connected to different board index nodes.

[0012] In this application, the group corresponding to each device port can be determined by the group identifier corresponding to each device port. The board index node to which each device port is connected can be found to obtain the board index node to which each device port is connected. Then, it can be determined whether the device ports of the same group in each device node to be verified are connected to the same board index node, or whether the device ports of different groups in each device node to be verified are connected to different board index nodes (i.e., device connection rule verification is realized). The group of the device port can be quickly determined by the group identifier of the device port, and then the grouped device connection rule verification can be quickly entered, which helps to improve the verification efficiency and device layout efficiency.

[0013] In one possible implementation of the first aspect, when device ports in different groups of each of the aforementioned device nodes to be verified are connected to different board index nodes, and each device port in the same group is connected to the same board index node, the device connection rule verification passes. The method further includes: when the device connection rule verification passes, updating the layout rendering data to obtain updated layout rendering data. The updated layout rendering data includes node attribute data of a plurality of second nodes and connection edge attribute data between the plurality of second nodes. The plurality of second nodes includes at least one board index node that has undergone the first operation and the device connection rule verification has passed, at least one device node that has undergone the second operation and the device connection rule verification has passed, or at least one device placeholder node that has undergone the third operation and the device connection rule verification has passed.

[0014] In this application, the layout rendering data can be updated after the device connection rule verification is passed (i.e., the device ports of different groups in each of the above-mentioned device nodes to be verified are connected to different board index nodes, and each device port in the same group is connected to the same board index node). That is, the node attribute data and connection edge attribute data of the nodes in the updated layout rendering data are the node attribute data and connection edge attribute data of the nodes after verification, thereby improving the accuracy of the node attribute data and connection edge attribute data in the layout rendering data, thus improving the accuracy of the layout rendering data and helping to improve the accuracy of device layout.

[0015] In one possible implementation of the first aspect, updating the layout rendering data to obtain updated layout rendering data includes: adding node attribute data corresponding to the node layout of the first device node and connection edge attribute data corresponding to the connection relationship between the first device node and at least one first board index node to the layout rendering data, wherein the first device node is a device node added in response to the third operation, and any one of the first board index nodes is a board index node specified by the third operation; and clearing the node attribute data corresponding to the node layout of the second device node and the connection edge attribute data corresponding to the connection relationship between the second device node and at least one second board index node from the layout rendering data, so as to remove the aforementioned first... Two device nodes are changed to device placeholder nodes. The second device node is the device node deleted in response to the second operation. Any of the second board index nodes is a board index node connected to the second device node. The node layout of the third device node is updated to the node attribute data corresponding to the third device node in the layout rendering data. The third device node is the device node whose node layout is adjusted in response to the second operation. At least one of the start point and the end point of the target operation connection edge is updated to the connection edge attribute data corresponding to the target operation connection edge in the layout rendering data. The target operation connection edge is a connection edge whose start point and end point are changed in response to at least one of the first operation and the second operation.

[0016] In this application, after the device connection rules pass verification, the layout rendering data can be updated based on the edited node layout and node connection relationships. The node attribute data corresponding to the node layout of the first device node and the connection edge attribute data corresponding to the connection relationship between the first device node and at least one specified board index node can be added to the layout rendering data. The first device node is the device node added in response to the third operation. The node attribute data corresponding to the node layout of the second device node and the connection edge attribute data corresponding to the connection relationship between the second device node and all board index nodes can be removed from the layout rendering data. The second device node is the device node deleted in response to the second operation. The node layout of the third device node can be updated to the node attribute data corresponding to the third device node in the layout rendering data. The third node is the device node whose node layout is adjusted in response to the second operation. At least one of the start point and end point of the target operation connection edge can be updated to the connection edge attribute data corresponding to the target operation connection edge in the layout rendering data. The target operation connection edge is the connection edge whose start point and end point are changed in response to at least one of the first and second operations. Through the above data updates, updated layout rendering data can be obtained, thus realizing the update of the layout rendering data. Updating the layout rendering data after the device connection rules have been verified improves the accuracy of the layout rendering data and helps to further improve the accuracy of device layout.

[0017] In one possible implementation of the first aspect, the node layout of the plurality of first nodes and the node connection relationship between the plurality of first nodes are first version data of semiconductor device layout stored in local storage space; when the device connection rule verification passes, the method further includes: when receiving a data storage instruction, storing the edited node layout and the edited node connection relationship in the local storage space as second version data of semiconductor device layout; when receiving a version rollback instruction, updating and displaying the node layout and node connection relationship corresponding to the first version data in the visualization operation interface.

[0018] In this application, the node layout of the aforementioned plurality of first nodes and the node connection relationships between the aforementioned plurality of first nodes can be the first version data of the semiconductor device layout stored in the local storage space. When the device connection rule verification passes, upon receiving a data storage instruction, the edited node layout and the edited node connection relationships can be stored in the aforementioned local storage space as the second version data of the semiconductor device layout. Upon receiving a version rollback instruction, the node layout and node connection relationships corresponding to the first version data can be updated and displayed in the visual operation interface. This method allows for the storage of two versions of data—before and after editing—in the local storage space, eliminating the need for external software and enabling localized data version management. This reduces the possibility of data loss or overwriting during the editing process, improving data security and accuracy. Simultaneously, version rollback is supported; upon receiving a version rollback instruction, the node layout and node connection relationships corresponding to the first version data before editing can be updated and displayed.

[0019] In one possible implementation of the first aspect, determining all device nodes as at least one device node to be verified based on the edited node layout and the edited node connection relationship, and determining the device port of each device node to be verified and the device port connection edge of each device node to be verified, includes: taking all device nodes included in the edited node layout as at least one device node to be verified; and determining the device port of each device node to be verified and the device port connection edge of each device node to be verified from the edited node layout and the edited node connection relationship.

[0020] In this application, all device nodes included in the edited node layout can be used as device nodes to be verified. The device ports and their connection edges are obtained from the edited node layout and node connection relationships. This allows for the rapid identification of all device nodes to be verified, their device ports, and their connection edges, improving verification and device layout efficiency. Furthermore, using all device nodes in the edited node layout as verification nodes allows for subsequent verification of device connection rules on their ports and connection edges, enhancing the accuracy of the device layout.

[0021] In one possible implementation of the first aspect, the second operation includes a device movement operation that adjusts the layout position of a target device node, wherein the target device node is any one of the device nodes displayed on the visualization operation interface; the step of responding to the target user operation instruction to display the edited node layout and the edited node connection relationship on the visualization operation interface includes: responding to the device movement operation, changing the layout position of the target device node on the visualization operation interface to the target layout position indicated by the device movement operation, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface.

[0022] In this application, in response to the aforementioned device movement operation, the node layout position of the target device node can be changed on the visual operation interface to the target node layout position indicated by the device movement operation, thereby displaying the edited node layout and node connection relationships. This enables visual device layout adjustment, is highly readable, and is easy to operate. While maintaining the integrity of the layout rendering data, the edited node layout and node connection relationships are displayed, supporting flexible layout adjustment and optimization, and facilitating subsequent device connection rule verification and visual location of potential layout problems.

[0023] In one possible implementation of the first aspect, the third operation includes adding a device and adding a device connection edge; responding to the target user operation instruction to display the edited node layout and the edited node connection relationship on the visualization operation interface includes: responding to the device adding and device connection edge adding operations, adding a target device at the layout position of the target device placeholder node in the visualization operation interface, updating the target device placeholder node to a target device node, and generating a connection edge between the target device port on the target device node and the target board index node on the visualization operation interface, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface, wherein the target device placeholder node is any one of the device placeholder nodes displayed on the visualization operation interface, the target device port is any one of the device ports on the target device node, and the target board index node is the board index node indicated by the device connection edge adding operation.

[0024] In this application, the system can respond to device addition and device connection edge addition operations to add a target device to the node layout position of the target device placeholder node in the aforementioned visual operation interface, and update the target device placeholder node to the target device node. This generates connection edges between the target device port and the target board index node on the target device node in the aforementioned visual operation interface, displaying the edited node layout and node connection relationships. This allows for visualized device layout adjustments, is highly readable, and easy to operate. While maintaining the integrity of the layout rendering data, it displays the edited node layout and node connection relationships, supporting flexible layout adjustments and optimizations, facilitating subsequent device connection rule verification and visual location of potential layout problems. Furthermore, it enriches the types of responsive target user operation commands.

[0025] In one possible implementation of the first aspect, the second operation includes a device deletion operation; the response to the target user operation instruction to display the edited node layout and the edited node connection relationship on the visualization operation interface includes: in response to the device deletion operation, deleting the connection edge connected to the target device node indicated by the device deletion operation on the visualization operation interface, and updating the target device node as the device placeholder node, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface, wherein the target device node is any one of the device nodes displayed on the visualization operation interface.

[0026] In this application, in response to a device deletion operation, the connection edges connected to the target device node indicated by the device deletion operation can be deleted in the aforementioned visual operation interface, and the target device node can be updated as a device placeholder node to display the edited node layout and node connection relationships. This enables visual device layout adjustments, is highly readable, and is easy to operate. While maintaining the integrity of the layout rendering data, the edited node layout and node connection relationships are displayed, supporting flexible layout adjustments and optimizations, and facilitating subsequent device connection rule verification and visual location of potential layout problems.

[0027] In one possible implementation of the first aspect, the second operation includes a first connection edge modification operation that adjusts the starting point of the target connection edge, and the first operation includes a second connection edge modification operation that adjusts the ending point of the target connection edge, wherein the target connection edge is any of the node connection relationships displayed on the visualization operation interface; the step of responding to the target user operation instruction to display the edited node layout and the edited node connection relationship on the visualization operation interface includes: responding to the first connection edge modification operation, changing the starting point of the target connection edge to the target device port indicated by the first connection edge modification operation on the visualization operation interface, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface; or responding to the second connection edge modification operation, changing the ending point of the target connection edge to the target board index node indicated by the second connection edge modification operation on the visualization operation interface, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface.

[0028] In this application, in response to the aforementioned first connection edge modification operation and / or second connection edge modification operation, the starting point of the aforementioned target connection edge can be changed to the target device port indicated by the aforementioned first connection edge modification operation, and / or the ending point of the aforementioned target connection edge can be changed to the target board index node indicated by the aforementioned second connection edge modification operation on the aforementioned visualization operation interface, so as to display the edited node layout and node connection relationship. It can realize the visualization of device layout adjustment, with strong visualization and simple operation. It can display the edited node layout and node connection relationship while maintaining the integrity of the layout rendering data, and provide the positioning of the visualization of node layout and node connection relationship.

[0029] In a second aspect, this application provides a patterned semiconductor device layout apparatus, which includes modules or units for performing the patterned semiconductor device layout method provided in the first aspect or any possible implementation thereof.

[0030] For example, the above-described patterned semiconductor device layout apparatus includes: The rendering module is used to render layout data based on semiconductor devices. It displays the node layout of multiple first nodes and the node connection relationship between the multiple first nodes in the visualization operation interface. The visualization operation interface is used for semiconductor device layout editing. The multiple first nodes include at least one board index node, at least one device node and at least one device placeholder node. The response module is used to respond to the target user operation instruction on the above-mentioned visual operation interface when the target user operation instruction is detected, so as to display the edited node layout and the edited node connection relationship on the above-mentioned visual operation interface. The target user operation instruction includes a first operation to edit any one of the above-mentioned board index nodes, a second operation to edit any one of the above-mentioned device nodes, or a third operation to add a single device node to any one of the above-mentioned device placeholder nodes and the connection relationship between the single device node and the specified board index node. The determination module is used to determine all device nodes as at least one device node to be verified based on the above-edited node layout and the above-edited node connection relationship, and to determine the device port of each device node to be verified and the device port connection edge of each device node to be verified, wherein each device port has a corresponding group identifier. The verification module is used to verify, based on the device port connection edge of each of the above-mentioned device nodes to be verified and the group identifier corresponding to each of the above-mentioned device ports, whether the device ports of the same group in each of the above-mentioned device nodes to be verified are connected to the same board index node, or whether the device ports of different groups in each of the above-mentioned device nodes to be verified are connected to different board index nodes. In the case that there are device ports of the same group in any of the above-mentioned device nodes to be verified connected to different board index nodes and / or device ports of different groups in any of the above-mentioned device nodes to be verified connected to the same board index node, the device connection rule verification fails. The output module is used to output alarm indication information for abnormal device layout when the above device connection rule verification fails.

[0031] Thirdly, this application provides a computer device, which includes a display, a processor, and a memory; the display, the memory, and the processor are connected together, wherein the display is used to display a visual view, the memory is used to store program code, and the processor is used to call the program code to execute the graphical semiconductor device layout method provided in the first aspect or any possible embodiment of the first aspect.

[0032] Fourthly, this application provides a computer-readable storage medium storing a computer program adapted to be loaded by a processor and executed by the graphical semiconductor device layout method provided in the first aspect or any possible implementation thereof.

[0033] Fifthly, this application provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the graphical semiconductor device layout method provided in the first aspect or any possible implementation of the first aspect.

[0034] The technical effects of the second, third, fourth, and fifth aspects can be referred to the technical effects of the first aspect and any possible implementation thereof, and will not be repeated here. Attached Figure Description

[0035] Figure 1 This is a system architecture diagram of the graphical semiconductor device layout method provided in the embodiments of this application; Figure 2 This is a schematic diagram illustrating an application scenario of the graphical semiconductor device layout method provided in this application embodiment; Figure 3 This is a schematic flowchart of the graphical semiconductor device layout method provided in the embodiments of this application; Figure 4 This is an application diagram illustrating the target user operation instructions provided in an embodiment of this application; Figure 5 This is another application diagram of the target user operation instructions provided in the embodiments of this application; Figure 6 This is another application diagram of the target user operation instructions provided in the embodiments of this application; Figure 7 This is another application diagram of the target user operation instructions provided in the embodiments of this application; Figure 8 This is a schematic diagram of a semiconductor device layout on a visual operating interface provided in an embodiment of this application; Figure 9 This is a schematic diagram of another semiconductor device layout on the visual operation interface provided in the embodiments of this application; Figure 10 This is a schematic diagram of the structure of the graphical semiconductor device layout apparatus provided in the embodiments of this application; Figure 11 This is a schematic diagram of the structure of the computer device provided in the embodiments of this application.

[0036] Explanation of reference numerals in the attached figures: 10-Server; 20-Computer equipment; 201 - Processor; 202 - Communication bus; 203 - User interface; 204 - Network interface; 205 - Memory; 30 - Graphical semiconductor device layout apparatus; 310 - Rendering Module; 320 - Response Module; 330 - Determine Module; 340 - Rule Validation Module; 350 - Output Module; 360 - Version Management Module; 41 - Device node; 42 - Device node; 43 - Device node; 44 - Device node; 51 - Device port; 52 - Device port; 53 - Device port; 54 - Device port; 55 - Device port; 56 - Device port; 57 - Device port; 58 - Device port; 59 - Device port; 60 - Device port; 61 - Device port. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0038] In the field of advanced semiconductor packaging, through-hole boards, as miniature devices or miniature metal contact components that enable connectivity and communication, have become the mainstream carrier for realizing key technologies such as 2.5D / 3D integration. A semiconductor packaging system can integrate one or more through-hole boards, each carrying multiple functional devices. Multiple through-hole boards can be joined and communicate with each other through high-density interconnect technologies such as packaging substrates or silicon bridges, forming a complete integrated system. Here, the through-hole board can be a programmable analog device (PAD), silicon interposer, glass interposer, organic laminate, ceramic interposer, or redistribution interposer, etc., which enable connectivity and communication. Devices that can be inserted into the through-hole board include central processing unit / graphics processing unit (CPU / GPU) dies, high-bandwidth memory stacks, field-programmable gate arrays (FPGAs), etc., depending on the actual application scenario, and are not limited here. In the embodiments of this application, the board index can be used to mark (or point to) a board, that is, one board index can mark (or point to) one board, which will not be elaborated further below. For ease of description, PAD will be used as the board and PADIndex as the board index in the following description, which will not be elaborated further below.

[0039] The graphical semiconductor device layout method provided in this application can display the node layout of multiple first nodes and the node connection relationships between multiple first nodes on a visual operation interface based on the layout rendering data of semiconductor devices. Here, the multiple first nodes may include board index nodes, device nodes, and device placeholder nodes. When a target user operation command is detected in the visual operation interface, the method can respond to the target user operation command to display the edited node layout and node connection relationships on the visual operation interface. Further, based on the edited node layout and edited node connection relationships, all device nodes can be determined as at least one device node to be verified. Based on the device port connection edge of each device node to be verified and the group identifier corresponding to each device port, the method verifies whether the device ports of the same group in each device node to be verified are connected to the same board index node, or whether the device ports of different groups in each device node to be verified are connected to different board index nodes. If in any device node to be verified, there are device ports of the same group connected to different board index nodes and / or in any of the above-mentioned device nodes to be verified, device connection rule verification fails. If the device connection rule verification fails, an alarm message indicating abnormal device layout can be output.

[0040] The graphical semiconductor device layout method provided in this application can realize node layout based on the target user operation commands on the visual operation interface, achieving a visual layout of devices and board indexes. The visual operation interface displays device nodes, board index nodes, and device placeholder nodes before and after editing, improving device layout efficiency. The device connection rule verification mechanism uses the group identifier corresponding to the device port as a reliable basis to perform static checks on the device port connection edges, improving the correctness of the connection between the device port and the board index node, thus contributing to improved device layout accuracy. Furthermore, group-based verification reduces verification pressure and improves verification efficiency, thereby enhancing device layout efficiency. Simultaneously, in the event of a device connection rule verification failure, alarm information for potential layout problems is provided, facilitating timely correction of the device layout and further improving device layout efficiency.

[0041] Please see Figure 1 , Figure 1 This is a system architecture diagram of the graphical semiconductor device placement method provided in the embodiments of this application. The graphical semiconductor device placement method provided in the embodiments of this application can be applied to, for example... Figure 1The system architecture shown may include connected servers 10 and computer devices 20. Server 10 may be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud databases, cloud services, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, and big data and artificial intelligence platforms. Computer device 20 may be a PDA, smartphone, laptop, desktop computer, tablet, mobile internet device (MID), wearable device (e.g., smartwatch, smart bracelet), smart computer, or other smart terminal, but is not limited to these. Computer device 20 may include an operating system, hardware, and application software. The hardware may include, but is not limited to, a central processing unit (CPU), memory (e.g., RAM, hard disk), and peripherals, providing core capabilities for computing, storage, and input / output. An operating system can serve as the hardware management and abstraction layer. Through its kernel and drivers, it can schedule CPU resources, manage memory space, and control peripheral operations. It also encapsulates complex hardware details into unified system calls and service interfaces, thereby providing a stable, efficient, and secure operating environment for upper-layer application software. Application software, built on the operating system, can use hardware resources through the interfaces provided by the operating system. For example, it can read code stored in memory to provide users with usable services. In this embodiment, the application software may include, but is not limited to, graphical semiconductor device layout software. The computer device 20 can run this graphical semiconductor device layout software to execute the graphical semiconductor device layout method provided in this embodiment.

[0042] The server 10 and the computer device 20 can establish a communication connection. The communication connection method is not limited; it can be established directly or indirectly via wired communication or wireless communication, etc., depending on the actual application scenario, and is not restricted here.

[0043] The method provided in the embodiments of this application can be derived from, for example... Figure 1 The computer device 20 shown can execute the command, or it can be executed by the server 10, or it can be executed by both the server 10 and the computer device 20. The specific execution method can be determined according to the actual application scenario, and there are no restrictions here.

[0044] It should be understood that, such as Figure 1The computer device 20 shown can be equipped with an application client (not shown) for graphical semiconductor device layout software. This application client can be used to implement graphical semiconductor device layout, such as visually displaying the layout position and connection status of semiconductor devices, and receiving user operation commands. When this application client runs on the computer device 20, it can interact with the aforementioned... Figure 1 The servers 10 shown interact with each other, enabling the servers 10 to obtain business data from the computer device 20 through interfaces and other paths. The business data may be generated during the user's use of the application client, including but not limited to layout rendering data stored in the local storage space of the computer device 20, and new version layout data edited by the user. This business data can be shared with the server 10, or it can be shared with other business devices (not shown in the figure) connected to the server 10 through the server 10. The specific method can be determined according to the actual application scenario, and no restrictions are imposed here.

[0045] The application client can be an application program, a webpage, or a website, depending on the specific application scenario, and is not limited here. The application client can be a standalone client or an embedded sub-client integrated into another client (such as an instant messaging client, social networking client, etc.), depending on the specific application scenario, and is not limited here.

[0046] For ease of subsequent understanding and explanation, in the embodiments of this application, the following will be used as... Figure 1 The computer device 20 shown serves as the execution entity of the graphical semiconductor device layout method (which can be simply referred to as the method for ease of description) provided in the embodiments of this application, combined with Figure 2 The application scenarios of the graphical semiconductor device layout method provided in the embodiments of this application are illustrated with examples.

[0047] To facilitate understanding of the data interaction within the system during the implementation of the graphical semiconductor device layout method provided in this application, please also refer to... Figure 2 , Figure 2 This is a schematic diagram illustrating an application scenario of the graphical semiconductor device layout method provided in this application embodiment.

[0048] See Figure 2 , Figure 2 This is a schematic diagram illustrating an application scenario of the graphical semiconductor device layout method provided in this application embodiment. For example... Figure 2As shown, assuming the target user (hereinafter referred to as the user for convenience) wants to place components within a target layout area (hereinafter referred to as the layout area for convenience), the computer device can provide a visual operation interface (such as user interface 1) to visually display the component layout within the layout area and receive the user's component layout operation commands. Here, the visual operation interface can include board index nodes, component nodes, and component placeholder nodes with different node forms. The number and positional distribution of the board index nodes, component nodes, and component placeholder nodes can be determined based on the component layout within the layout area and are not limited here. It can be understood that the component layout within the layout area can be an initial component layout (e.g., containing only board indexes, with no components inserted) or a historical component layout (e.g., components already inserted), which can be determined based on the actual application scenario and is not limited here.

[0049] It is understood that the above-mentioned board index node can be used to indicate the board index that has been inserted in the layout area, the above-mentioned device node can be used to indicate the device that has been inserted in the layout area, and the above-mentioned device placeholder node can be used to indicate the free space in the layout area where a device can be inserted (i.e., a new device).

[0050] like Figure 2 As shown, the cross-shaped node can be the placeholder node for the aforementioned device, the right-angled square node can be the index node for the aforementioned board, and the rounded rectangle node (containing multiple device ports) can be the device node for the aforementioned device. The specific node shape corresponding to each node can be determined according to the actual application scenario, and is not limited here. It can be understood that, as Figure 2As shown, the layout area indicated by user interface 1 includes at least 12 board indices, 1 device (with 4 device ports), and multiple free slots. User interface 1 may also include components such as a "Verify" button, a "Save" button (here, saving can be understood as passing the check and entering the data, which can be abbreviated as check-in), and a "Back" button. When a user clicks the "Verify" button, the device connection rules of the currently displayed device layout can be verified (or checked) to verify the validity of the current device layout. For example, it can check whether there are any floating device ports. The specific verification rules can be determined according to the actual application scenario and are not limited here. When the device connection rule verification fails, the computer device can issue an alarm. The alarm method can include, but is not limited to, pop-up displays, highlighting, etc., which can be determined according to the actual application scenario and are not limited here. For example, suppose the device connection rules mentioned above include the prohibition of floating device ports. Since a device port 51 on the device in user interface 1 (hereinafter referred to as the target device for ease of description) is not connected to the board index, the device layout corresponding to the current user interface 1 cannot pass the device connection rule verification. A pop-up window can be generated in user interface 1 to warn "Device port 51 is not connected." Suppose the user wants to connect device port 51 to board index node c4. The user can click on device port 51 and board index node c4 sequentially within user interface 1 to input the target user operation command into the computer device. When the computer device receives the target user operation command, it can generate a connection edge between device port 51 and board index node c4 (as in user interface 2) to display the user-edited node layout and node connection relationship on user interface 2. The computer device can detect user clicks on the "Verify" button in real time or periodically. Figure 2As shown, when the computer device detects a user click on the "Verify" button in user interface 2, it can perform rule verification on the currently displayed device layout. If the device connection rule verification passes, the user can be notified that the current device layout is valid through methods including but not limited to pop-ups and color changes. If the device connection rule verification passes, when the computer device detects a user click on the "Save" button, it can update the layout rendering data stored in the background based on the currently displayed device layout, or update the layout rendering data stored in the background after a preset waiting time following the above verification. The specific method can be determined according to the actual application scenario and is not limited here. When the computer device detects a user click on the "Undo" button, it can revert to the device layout before the user edited it. That is, after the user arbitrarily edits the device layout through the target user operation command, they can revert to the device layout corresponding to the version before editing. It can be understood that the above target user operation command can be used for, but is not limited to, adding devices, deleting devices, changing connection edges, etc. For details, please refer to the subsequent embodiments, which will not be elaborated here. The graphical semiconductor device layout method provided in this application can realize visual node layout based on the target user operation instructions on the visual operation interface. The device nodes before and after editing, the board index nodes, and the device placeholder nodes are displayed on the visual operation interface, which can improve the accuracy and efficiency of device layout.

[0051] It is understood that in the specific implementation of this application, data related to object information is involved. When the embodiments of this application are applied to specific products or technologies, permission or consent from the object is required, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0052] The following will combine Figures 3 to 10 The graphical device layout method and apparatus provided in the embodiments of this application will be described in detail.

[0053] See Figure 3 , Figure 3 This is a schematic flowchart of the graphical semiconductor device layout method provided in the embodiments of this application. For ease of understanding, the embodiments of this application use a computer device as an example for illustration. Figure 1 The following description will be based on computer device 20. Figure 3 In the patterned semiconductor device placement method shown, each step of the patterned device placement method can be derived from the above. Figure 1 The computer device 20 in the middle is used to perform, such as Figure 3 As shown, the method for graphical device layout may include at least the following steps S301-S305: S301, based on the layout rendering data of semiconductor devices, the node layout of multiple first nodes and the node connection relationship between the multiple first nodes are displayed in the visualization operation interface. The visualization operation interface is used for semiconductor device layout editing. The multiple first nodes include at least one board index node, at least one device node and at least one device placeholder node.

[0054] In some feasible implementations, the computer device can acquire the layout rendering data of the semiconductor device. Here, the layout rendering data can be, but is not limited to, JSON format data, YAML format data, JavaScript object literals, XML format data, etc., depending on the actual application scenario, and is not limited here. It can be understood that the layout rendering data of the semiconductor device can be initial layout rendering data or historical layout rendering data, and the computer device can use local storage space (e.g., Figure 1 The layout rendering data can be obtained from the memory (shown in the diagram) or server, or initial layout rendering data can be generated. The specific method can be determined based on the actual application scenario and is not limited here. The computer device can render the node layout and node connection relationships of multiple first nodes based on the layout rendering data, and output the node layout and node connection relationships of the multiple first nodes to the visualization operation interface for device layout editing, so as to display the node layout and node connection relationships of the multiple first nodes in the visualization operation interface. Here, the multiple first nodes may include board index nodes, device nodes, and device placeholder nodes. The number of board index nodes, device nodes, and device placeholder nodes, their node layout positions, node shapes, and connection status can all be obtained from the layout rendering data. Here, the visualization operation interface can be used to display the node layout and node connection relationships of multiple first nodes, and can also be used to receive user operation commands to execute device layout editing. For details, please refer to the following embodiments, which will not be elaborated here. It is understandable that the node layout and connection relationships of multiple first nodes in the visual operation interface can be used to reflect the actual layout of multiple board indexes, devices, and idle points within the layout area, as well as the connection relationships between board indexes and devices. Specifically, board index nodes can be used to indicate board indexes, device nodes can be used to indicate devices, and device nodes can be used to indicate idle points. It is also understood that different types of board indexes can correspond to different node shapes or node identifiers for board index nodes, and different types of devices can correspond to different node shapes or node identifiers for device nodes. The specifics can be determined based on the actual application scenario and are not limited.

[0055] In some feasible implementations, before displaying the node layout of multiple first nodes and the node connection relationships between these first nodes in the visualization interface based on the aforementioned semiconductor device layout rendering data, the computer device can acquire a two-dimensional matrix describing the positional distribution of the board index and the device. Zero-value elements in the two-dimensional matrix indicate free points, and non-zero elements indicate board indexes or devices. Here, the non-zero elements can be preset board indexes or device identifiers, which can be determined according to the actual application scenario and are not limited here. It can be understood that if it is an initialized device layout, i.e., a device layout without any inserted devices (only including board indexes and free points), the two-dimensional matrix may only include non-zero elements indicating board indexes and zero-value elements indicating free points. Here, the free point indicator can be used to indicate the points where devices can be inserted. Specific device addition and device connection edge addition operations can be found in subsequent embodiments and will not be elaborated here. Optionally, the two-dimensional matrix can be generated based on upstream data received by the computer device. This two-dimensional matrix can be a matrix generated after the user fills in data indicating the positional distribution of devices into the two-dimensional matrix template. Here, the template described above can be used to indicate the location distribution of the board indexes to the user and prompt the user to fill in the initial location distribution of the devices. The template can be in the form of, but is not limited to, matrices, etc., and the specific form can be determined according to the actual application scenario. For example, assuming the template is in the form of a matrix, and the matrix is ​​[(0,0,0,0),(1,0,2,0),(0,0,0,0)], this template can be provided to the user to obtain the location distribution of the initial devices. For example, the user can fill in a non-zero value element at any zero value element position in the template to indicate that an initial device has been inserted at that position. The specific form can be determined according to the actual application scenario. The computer device can obtain the attribute data corresponding to the board indexes or devices indicated by each of the non-zero elements in the above two-dimensional matrix, and convert the attribute data corresponding to the board indexes or devices indicated by each of the non-zero elements and the attribute data of the free points into the layout rendering data of the semiconductor devices. The layout rendering data for the aforementioned semiconductor devices includes node attribute data and connection edge attribute data for the nodes (i.e., board index nodes, device nodes, or device placeholder nodes) corresponding to the board indexes, devices, or free points indicated by each element in the aforementioned two-dimensional matrix. The connection edge attribute data includes the attribute data of the connection edges between the device ports and the ports of the board indexes. Here, the attribute data for the free points can be preset initial data, which can be determined according to the actual application scenario and is not limited here.It is understood that the aforementioned node attribute data may include, but is not limited to, node identifiers (such as device identification numbers), node shapes (such as cross shapes), node layout positions (such as node coordinates, the number of rows and columns where the node is located), and node data volume. The aforementioned connection edge attribute data may include, but is not limited to, connection edge shapes, connection edge start points, and connection edge end points. The specific details can be determined based on the actual application scenario and are not limited here. Here, the attribute data corresponding to the board index or device, and the attribute data of the free points, can be stored in the local storage space of the computer device, or can be downloaded from the connected server. The specific details can be determined based on the actual application scenario and are not limited here. It is understood that the readability of the aforementioned two-dimensional matrix, the aforementioned board index or device attribute data, and the aforementioned free point attribute data is generally poor. The computer device can convert the aforementioned two-dimensional matrix, the aforementioned board index or device attribute data, and the aforementioned free point attribute data into readable layout rendering data. For example, suppose a computer device obtains a two-dimensional matrix to describe an initial device layout. In this case, the layout area includes only multiple board indices and multiple empty slots (i.e., no devices are inserted), and the two-dimensional matrix is ​​[(0,0,0,...,0,0),(1,0,2,...,12,0),(0,0,0,...,0,0)]. The computer device can determine from this two-dimensional matrix that the layout area includes 12 board indices, and determine the layout position of the nodes corresponding to each board index. Here, the non-zero elements in the two-dimensional matrix (such as 1, 2, ..., 12) can be the board index identifiers corresponding to the 12 board indices, and the zero-value elements in the two-dimensional matrix can be used to indicate empty slots where devices can be inserted. The computer device can parse the aforementioned two-dimensional matrix to obtain the positional distribution of each board index and the corresponding nodes for each free position. For example, board index node c1 is located in the second row and first column. It can then obtain the attribute data corresponding to each board index and the attribute data corresponding to each free position, converting this data into layout rendering data. This layout rendering data can be understood to include the node layout of the 12 board index nodes corresponding to the 12 board indices and the multiple device placeholder nodes corresponding to the multiple free positions. Since no devices have been inserted into the layout area at this time, the layout rendering data does not contain device nodes or node connection relationships.

[0056] In this embodiment, a two-dimensional matrix describing the positional distribution of PCB indices and devices can be obtained. Then, attribute data corresponding to the PCB indices or devices indicated by each non-zero element in the two-dimensional matrix, as well as attribute data of the free points, can be obtained. This attribute data, along with the attribute data of the free points, is converted into layout rendering data for semiconductor devices. Here, the layout rendering data can include node attribute data and connection edge attribute data for the nodes (i.e., PCB index nodes, device nodes, or device placeholder nodes) corresponding to the PCB indices, devices, or free points indicated by each element in the aforementioned two-dimensional matrix. This enables the parsing of data that lacks readability, such as two-dimensional matrices. By converting the attribute data of the PCB indices or devices and the attribute data of the free points into visual rendering data based on the two-dimensional matrix, efficient data visualization and parsing can be achieved. The layout rendering data can accurately render and present the initial device layout and node connection relationships, improving the efficiency and accuracy of subsequent data arrangement.

[0057] In some feasible implementations, the computer device can render the node layout and connection relationships of the aforementioned plurality of first nodes based on the layout rendering data of semiconductor devices, and then output the node layout and connection relationships of the aforementioned plurality of first nodes to the aforementioned visual operation interface. It is understood that the computer device can parse the aforementioned layout rendering data to obtain layout information such as the node layout positions, node shapes, and connection status of the aforementioned plurality of first nodes. For example, the computer device can integrate the aforementioned layout information into an operable rendering tree, and then traverse this operable rendering tree through a renderer (such as Blink / WebKit in a browser or a native platform UI framework), and call the underlying graphics application programming interface (API), such as Skia, DirectX, Metal, or Core Graphics, to execute actual pixel drawing commands, rasterizing text, shapes, and effects to the frame buffer. Furthermore, the computer device can output as a visual operation interface, such as a webpage or application on the computer device screen, the specifics of which can be determined according to the actual application scenario and are not limited here. In this embodiment, based on the layout rendering data of semiconductor devices, the node layout of multiple first nodes and the node connection relationship of multiple first nodes can be rendered. Then, the node layout of the first nodes and the node connection relationship between the first nodes can be output to the visualization operation interface. The abstract and complex data (i.e., the layout rendering data mentioned above) can be converted into intuitive graphics (i.e., the multiple first nodes mentioned above) and lines (i.e., the node connection relationship between the multiple first nodes mentioned above) on the visualization interface, which improves the readability of the node layout, makes it easier for users to quickly understand the current node layout, and provides an intuitive interactive entry point for subsequent editing.

[0058] In some feasible implementations, the computer device can render the PCB index and / or the node attribute data corresponding to the device included in the layout rendering data of the semiconductor device, to render the PCB index as a PCB index node and / or the device as a device node, and render the node attribute data corresponding to the free points included in the layout rendering data of the semiconductor device, to render the free points as device placeholder nodes, so as to obtain the node layout of the plurality of first nodes. The node shape and layout position of the PCB index node, the device node, and the device placeholder node are defined by the node attribute data corresponding to the PCB index, the device, and the free points in the layout rendering data. The computer device can render the connection edge attribute data included in the layout rendering data of the semiconductor device, to render the connection relationship between the device port of the device and the port of the PCB index as a connection edge between the device port and the PCB index node on the device node, so as to obtain the node layout of the plurality of first nodes and the node connection relationship between the plurality of first nodes. The device ports or board index nodes connected at both ends of the aforementioned connecting edge are defined by the connecting edge attribute data in the layout rendering data of the aforementioned semiconductor device. It is understood that the layout rendering data may include, but is not limited to, the node attribute data corresponding to each board index, each device, and each free point within the current layout area. Node attribute data may include, but is not limited to, node shape, node layout position, etc. The node attribute data of the device node may also include the grouping identifier of each device port of the device node, etc. The specific details can be determined according to the actual application scenario and are not limited here. Here, the node shape may include, but is not limited to, rectangles, crosses, etc. For example, the node shape of a device node can be rectangular, and the node shape of a device placeholder node can be cross-shaped, the specific details can be determined according to the actual application scenario and are not limited here. It is understood that a device may include multiple device ports. Connecting each device port on a device to one or more board indices can enable the device to have different device functions. The connecting edge attribute data may include, but is not limited to, the start point, end point, the grouping identifier of the starting device port, and the edge shape (e.g., a solid straight line) of each connecting edge. Here, the start point of the connecting edge can usually be any device port on the device (e.g., a solid straight line). Figure 2 The device port 51 shown in the diagram usually corresponds to the board index (e.g., ...). Figure 2The edge shape of the insert index node c4 shown can include, but is not limited to, edge color and thickness (e.g., a thin, solid black edge), which can be determined according to the actual application scenario and is not limited here. It can be understood that computer devices can use renderers (such as Blink / WebKit in a browser or native platform UI frameworks) to call underlying graphics APIs (such as Skia, DirectX, Metal, or Core Graphics) to draw the node layout and node connection relationships of multiple first nodes, and can output them to a visual operation interface to display the node layout and node connection relationships of the aforementioned multiple nodes. The specific rendering and presentation method can be determined according to the actual application scenario and is not limited here.

[0059] In this embodiment, the node attribute data corresponding to the board index and / or device included in the layout rendering data can be rendered to render the board index as a board index node and / or the device as a device node. The node attribute data corresponding to the idle points included in the layout rendering data can also be rendered to render the idle points as device placeholder nodes. The node shape and layout position of each first node are defined by the corresponding node attribute data in the layout rendering data. The connection edge attribute data included in the layout rendering data can also be rendered to render the connection relationship between the device port of the device and the port of the board index as a connection edge between the device port and the board index node on the device node, thus obtaining the node layout of multiple first nodes. It can be understood that the node layout and node connection relationship of multiple first nodes can be rendered based on the layout rendering data, thereby improving the readability of the node attribute data and connection edge attribute data included in the layout rendering data. The layout rendering data can accurately render and present the node layout and node connection relationship of each first node in the visualization interface, which helps to improve the efficiency and accuracy of subsequent node layout implementation on the visualization operation interface.

[0060] S302, upon detecting a target user operation instruction on the aforementioned visual operation interface, responding to the target user operation instruction to display the edited node layout and the edited node connection relationship on the aforementioned visual operation interface, wherein the target user operation instruction includes a first operation of editing any of the aforementioned board index nodes, a second operation of editing any of the aforementioned device nodes, or a third operation of adding a single device node to any of the aforementioned device placeholder nodes and the connection relationship between the single device node and the specified board index node.

[0061] In some feasible implementations, when a target user operation command is detected on the visual operation interface, the computer device can respond to the target user operation command to display the edited node layout and node connection relationships on the visual operation interface. Here, the target user operation command can be a first operation that edits any board index node in the visual operation interface (such as modifying the connection edge at the endpoint of the target connection edge), a second operation that edits any device node in the visual operation interface (such as moving or deleting a device), or a third operation that edits any device placeholder node in the visual operation interface (such as adding a device or adding a device connection edge). The specific operation can be determined according to the actual application scenario and is not limited here. The computer device can detect various user interaction behaviors on the visual operation interface in real time or periodically to detect target user operation commands. Here, the aforementioned various user interaction behaviors can include, but are not limited to, touchscreen clicks or swipes, mouse movements or clicks, touchpad input, keyboard input, etc., and the specific operation can be determined according to the actual application scenario and the type of computer device, and is not limited here. It is understood that computer devices can transform user interaction behaviors (i.e., user operation intentions) into processable digital commands to respond to the target user's operation instructions. For details, please refer to the following embodiments, which will not be elaborated here.

[0062] In some feasible implementations, the second operation described above can be a device movement operation that adjusts the layout position of a target device node. Here, the target device node can be any device node displayed on the visual operation interface. The computer device can respond to the device movement operation by changing the layout position of the target device node on the visual operation interface to the target layout position indicated by the device movement operation, thereby displaying the edited node layout and the edited node connection relationships on the visual operation interface. It is understood that the computer device can detect various user interaction behaviors on the visual operation interface in real time or periodically. When a device movement operation that adjusts the node layout position of a target device node is detected, the device device can change the node layout position of the target device node on the visual operation interface to the target node layout position indicated by the device movement operation. Here, the device movement operation can be a user interaction behavior of dragging the target device node to the target node layout position, or it can be a user interaction behavior of selecting the target node layout position by clicking on the target device node. The specific behavior can be determined according to the actual application scenario and is not limited here. For ease of understanding, dragging the target device node to the target node layout position is used as an example. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is an application diagram illustrating the target user operation instructions provided in an embodiment of this application. In such... Figure 4The visual interface shown can display multiple board index nodes (such as board index node c1, board index node c2, ..., board index node c12), multiple device placeholder nodes, and one device node (i.e., the target device node). This target device node has four device ports, which are connected to board index nodes c1, c2, c3, and c4, respectively. Figure 4 As shown, if a user wishes to adjust the node layout position of the target device node, they can drag and drop the target device node to the target node layout position in the visual operation interface. This target node layout position can be any placeholder node in the visual operation interface, and the specific location can be determined according to the user's actual needs; no restrictions are imposed here. When the computer device detects the user's command to drag the target device node in the visual operation interface, it moves the target device node to the target node layout position indicated by the user's command and generates a placeholder node at the original node layout position of the target device node to display the edited node layout and node connection relationships. It can be understood that the connection edges between the ports of each device on the target device node and the ports of the board index node can remain unchanged during the movement process.

[0063] In this embodiment, the second operation can be a device movement operation that adjusts the node layout position of any device node (i.e., the target device node) on the visual operation interface. The computer device can respond to the device movement operation and change the node layout position of the target device node on the visual operation interface to the target node layout position indicated by the device movement operation, so as to display the edited node layout and node connection relationship. This can realize the visual device layout adjustment, which is highly readable and simple to operate. It can display the edited node layout and node connection relationship while maintaining the integrity of the layout rendering data. It can support flexible layout adjustment and optimization, and facilitate subsequent device connection rule verification and visualization of potential layout problems.

[0064] In some feasible implementations, the third operation described above can be a device addition and device connection edge addition operation. The computer device can respond to the device addition and device connection edge addition operations by adding a target device at the layout position of the target device placeholder node in the visualization interface, updating the target device placeholder node to a target device node, and generating a connection edge between the target device port and the target board index node on the target device node in the visualization interface, thereby displaying the edited node layout and the edited node connection relationship on the visualization interface. The target device placeholder node can be any of the device placeholder nodes displayed in the visualization interface, the target device port can be any device port on the target device node, and the target board index node can be the board index node indicated by the device connection edge addition operation. Here, the target device can be any of the various types of devices recorded in the computer device's local storage space, or any of the various types of devices obtained by the computer device from a server. The computer device can provide a user interface for the user to select the target device; the specific selection can be determined according to the actual application scenario and is not limited here. It is understandable that computer equipment can detect various user interactions on the visual operation interface in real time or periodically. When the computer equipment detects a device addition or device connection edge addition operation, it can add a target device to the node layout position of the target device placeholder node indicated by the device addition or device connection edge addition operation in the visual operation interface, and update the target device placeholder node to the target device node in response to the device addition or device connection edge addition operation. This allows for the generation of a connection edge between the target device port on the target device node and the target board index node on the visual operation interface. Here, the target device port can be any device port on the target device node. The number of ports on the target device node can be determined based on the specific device selection corresponding to the target device node, and is not limited here. The device addition or device connection edge addition operation can be a user interaction that clicks on the target device placeholder node, and the device connection edge addition operation can be a user interaction that connects the target device port to the target board index node; the specifics can be determined based on the actual application scenario, and are not limited here. For easier understanding, please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is another application illustration of the target user operation instructions provided in the embodiments of this application. In such... Figure 5 The visual interface shown can display multiple board index nodes (such as board index node c1, board index node c2, ..., board index node c12), multiple device placeholder nodes, and one device node. This device node is used to indicate the devices already inserted within the layout area. Figure 5As shown, if a user wants to add a target device to the node layout position of a target device placeholder node, the user can click the target device placeholder node in the visual operation interface to replace the placeholder node with the target device node. Here, the computer device can provide various types of devices for the user to select the target board index through pop-ups, lists, etc. (not shown in the figure), which can be determined according to the actual application scenario and is not limited here. When the computer device detects that any device placeholder node in the visual operation interface has been clicked, it can update the clicked placeholder node to the target device node and prompt the user to configure port connection edges. Suppose the user wants to connect device port 52 on the target device node to board index node c12, the user can click device port 52 and board index node c12 sequentially in the visual operation interface to input the device connection edge addition operation into the computer device. When the computer device receives the device connection edge addition operation, it can generate a connection edge between device port 52 and board index node c12 to display the user-edited node layout and node connection relationship on the visual operation interface. Figure 5 As shown, based on the user's device connection edge addition operation, the computer device can connect each device port on the target device node to the corresponding board index node. It can be understood that different device ports can be connected to the same board index node or different board index nodes, depending on the actual application scenario and device connection rules, etc., and no restrictions are imposed here.

[0065] In this embodiment, the third operation can be a device addition and device connection edge addition operation. This operation can respond to the device addition and device connection edge addition operation to add a target device to the node layout position of the target device placeholder node in the aforementioned visual operation interface, and update the target device placeholder node to the target device node. This generates a connection edge between the target device port and the target board index node on the target device node in the aforementioned visual operation interface, displaying the edited node layout and node connection relationship. This allows for visual device layout adjustment, is highly readable, and simple to operate. It can display the edited node layout and node connection relationship while maintaining the integrity of the layout rendering data. It supports flexible layout adjustment and optimization, facilitating subsequent device connection rule verification and visual location of potential layout problems. Simultaneously, it enriches the responsive target user operation commands.

[0066] In some feasible implementations, the second operation described above can be a device deletion operation. The computer device can respond to the device deletion operation by deleting the connection edges connected to the target device node indicated by the device deletion operation in the visual operation interface, and updating the target device node as a device placeholder node, so as to display the edited node layout and the edited node connection relationships on the visual operation interface. The target device node can be any of the device nodes displayed on the visual operation interface. It is understood that the computer device can detect various user interaction behaviors on the visual operation interface in real time or periodically. When a device deletion operation targeting a target device node is detected, the connection edges connected to the target device node can be deleted on the visual operation interface, and the target device node can be updated as a device placeholder node. Here, the device deletion operation can be an operation of dragging the target device node to a preset deletion area, or an operation of selecting the target device node and then checking the delete option in the menu bar. The specific operation can be determined according to the actual application scenario and is not limited here. It is understood that the connection edges connected to the target device node are all connection edges connected to the target device node before the device deletion operation. For easier understanding, please refer to [link to relevant documentation]. Figure 6 , Figure 6 This is another application illustration of the target user operation instructions provided in the embodiments of this application. In such... Figure 6 The visual operation interface shown can display multiple board index nodes (such as board index node c1, board index node c2, ..., board index node c12), multiple device placeholder nodes, device node 41, and device node 42. Figure 6 As shown, if a user wishes to delete device node 42, the user can click on device node 42 in the visual operation interface to select device node 42. When the computer device detects that the user has clicked on device node 42 in the visual operation interface, it can highlight device node 42. Figure 6 As shown, an elliptical selection box can be generated around device node 42 to highlight it. Optionally, a "Delete" button can be generated in the computer device's visual interface for the user to click and delete the currently selected device node. When the computer device detects a click on the "Delete" button, it can delete the connecting edges connected to device node 42 and update device node 42 as a device placeholder node to display the edited node layout and node connection relationships.

[0067] In this embodiment, the second operation can be a device deletion operation. The computer device can respond to this device deletion operation by deleting the connection edges connected to the target device node indicated by the device deletion operation in the visual operation interface, and updating the target device node as a device placeholder node. This displays the edited node layout and node connection relationships, enabling visual device layout adjustments. It is highly readable, easy to operate, and can display the edited node layout and node connection relationships while maintaining the integrity of the layout rendering data. It supports flexible layout adjustments and optimizations, facilitating subsequent device connection rule verification and visual location of potential layout problems. Simultaneously, it increases the diversity of responsive target user operation commands.

[0068] In some feasible implementations, the second operation described above can be a first connection edge modification operation that adjusts the starting point of the target connection edge, and the first operation can be a second connection edge modification operation that adjusts the ending point of the target connection edge. The target connection edge can be any of the node connection relationships displayed on the visualization interface. In response to the first connection edge modification operation, the computer device can change the starting point of the target connection edge to the target device port indicated by the first connection edge modification operation on the visualization interface to display the edited node layout and the edited node connection relationships on the visualization interface; or, in response to the second connection edge modification operation, change the ending point of the target connection edge to the target board index node indicated by the second connection edge modification operation on the visualization interface to display the edited node layout and the edited node connection relationships on the visualization interface. It is understood that the computer device can respond to a first connection edge modification operation and / or a second connection edge modification operation that modifies the start and / or end point of the target connection edge, and change the start point of the target connection edge to the target device port indicated by the first connection edge modification operation, and / or change the end point of the target connection edge to the target board index node indicated by the connection edge modification operation, on the aforementioned visual operation interface, so as to display the edited node layout and node connection relationship on the aforementioned visual operation interface. It is understood that the computer device can detect various user interaction behaviors on the visual operation interface in real time or periodically, and when the aforementioned first connection edge modification operation and / or the aforementioned second connection edge modification operation are detected, the start and / or end point of the target connection edge can be adjusted on the visual operation interface based on the first connection edge modification operation and / or the second connection edge modification operation. Here, the first and / or second edge modification operations can be operations such as dragging the start and / or end points of the target edge to the target start and / or target end points, or operations such as selecting the start and / or end points of the target edge and then checking the "Modify" option in the menu bar. The specific operation can be determined according to the actual application scenario and is not limited here. For ease of understanding, please refer to [link to relevant documentation]. Figure 7 , Figure 7 This is another application illustration of the target user operation instructions provided in the embodiments of this application. In such... Figure 7 The visual operation interface shown can display multiple board index nodes (such as board index node c1, board index node c2, ..., board index node c12), multiple device placeholder nodes, and one device node. The four device ports on this device node are connected to board index nodes c1, c2, c3, and c4, respectively. Device port 53 is connected to board index node c2. Figure 7As shown, if a user wants to change the board index of the device port 53 to the board index node c8, that is, to change the endpoint of the target connection edge between the device port 53 and the board index node c2 to the board index node c8, the user can drag the endpoint of the target connection edge (the initial position of the endpoint is the board index node c2) to the board index node c8 in the visual operation interface to form the connection edge between the device port 53 and the board index node c8, and display the edited node layout and node connection relationship.

[0069] In this embodiment, the second operation can be a first connection edge modification operation that adjusts the starting point of the target connection edge, and the first operation can be a second connection edge modification operation that adjusts the ending point of the target connection edge. Responding to the first and / or second connection edge modification operations, the starting point of the target connection edge can be changed to the target device port indicated by the first connection edge modification operation, and / or the ending point of the target connection edge can be changed to the target board index node indicated by the second connection edge modification operation on the visualization interface. This displays the edited node layout and node connection relationships, enabling visualization of device layout adjustments. It is highly readable, simple to operate, and can display the edited node layout and node connection relationships while maintaining the integrity of the layout rendering data, improving visualization positioning. Simultaneously, it increases the diversity of responsive target user operation commands.

[0070] S303, based on the above-edited node layout and the above-edited node connection relationship, all device nodes are determined as at least one device node to be verified, and the device port of each of the above-mentioned device nodes to be verified and the device port connection edge of each of the above-mentioned device nodes to be verified are determined, wherein each of the above-mentioned device ports has a corresponding group identifier.

[0071] In some feasible implementations, the computer device can use all device nodes included in the edited node layout as at least one device node to be verified, and determine the device port and device port connection edge of each device node to be verified from the edited node layout and the edited node connection relationship. It is understood that the computer device can determine all device nodes as device nodes to be verified based on the edited node layout and the edited node connection relationship (such as the node layout and node connection relationship on the visual operation interface edited by the target user's operation instructions), and parse each device node to be verified to determine the device port and device port connection edge of each device node to be verified. Here, the number of device nodes to be verified can be determined according to the actual application scenario and is not limited here. It is understood that the device corresponding to the device node to be verified can have one or more device ports, and each device port has a corresponding group identifier.

[0072] For example, when the output voltages of all ports of a device belong to the same voltage range, and this voltage range is within the voltage range that a certain socket can withstand, the grouping rule for the device's ports can be determined as follows: all ports of the device are connected to the same socket index node. In this case, all ports of the device belong to the same group and can be marked with the same group identifier. When the output voltages of a portion of the device ports (which can be referred to as the first portion for convenience) belong to the first voltage range, and the output voltages of another portion of the device ports (which can be referred to as the second portion for convenience) belong to the second voltage range, and the first voltage range is within the voltage range that a certain socket (which can be referred to as the first socket for convenience), and the second voltage range is within the voltage range that another socket (which can be referred to as the second socket for convenience), the grouping rule for the device's ports can be determined as follows: the ports of the first portion of the device are all connected to the same socket index node (i.e., the socket index node corresponding to the first socket), and the ports of the second portion of the device are all connected to the same socket index node (i.e., the socket index node corresponding to the second socket). At this point, the ports of the first part of the device belong to the same group and can be marked with the same group identifier (e.g., the first group identifier), the ports of the second part of the device belong to the same group and can be marked with the same group identifier (e.g., the second group identifier), and the ports of the first part and the ports of the second part of the device do not belong to the same group, and the first group identifier and the second group identifier are different.

[0073] It is understood that the above example is merely a simplified illustration based on component selection and the actual application scenario. In specific implementations, the grouping rules for component ports can be determined according to the actual component selection and application scenario, and are not limited here. Here, the grouping identifier can be in the form of a name, label, etc., and can be determined according to the actual application scenario, and is not limited here. It should be understood that computer devices can obtain the grouping identifiers of each component port from the node attribute data and / or connection edge attribute data in the layout rendering data, and can be determined according to the actual application scenario, and is not limited here. For example, please refer to [link to example]. Figure 2 Assuming Figure 2 The user interface 1 shown is the interface after user editing. The device node in user interface 1 should be the device node to be verified. The computer device can obtain the grouping identifier of the four ports of the device corresponding to the device node to be verified from the local storage space to support the subsequent device connection rule verification. This will not be elaborated on here.

[0074] In this embodiment, all device nodes included in the edited node layout can be used as device nodes to be verified. The device ports and connection edges of each device node to be verified are obtained from the edited node layout and the edited node connection relationships. This allows for the rapid identification of all device nodes to be verified, their device ports, and their connection edges, thus improving verification efficiency and device layout efficiency. Furthermore, using all device nodes included in the edited node layout as device nodes to be verified allows for subsequent verification of device connection rules on the device ports and connection edges of all device nodes included in the edited node layout, thereby improving the accuracy of device layout.

[0075] S304, based on the device port connection edge of each of the above-mentioned device nodes to be verified and the group identifier corresponding to each of the above-mentioned device ports, verify whether the device ports of the same group in each of the above-mentioned device nodes to be verified are connected to the same board index node, or whether the device ports of different groups in each of the above-mentioned device nodes to be verified are connected to different board index nodes. In any case where the device ports of the same group in any of the above-mentioned device nodes to be verified are connected to different board index nodes and / or the device ports of different groups in any of the above-mentioned device nodes to be verified are connected to the same board index node, the device connection rule verification fails.

[0076] In some feasible implementations, the computer device can determine the group corresponding to each of the aforementioned device ports through the group identifier corresponding to each device port. Here, any device may include device ports belonging to one or more groups, and ports belonging to the same group may be located on different devices. The grouping rules for device ports can be determined according to the specific selection and internal structure of the device, and are not limited here. It should be understood that ports belonging to the same group should be connected to the same board index node, and ports belonging to different groups should be connected to different board index nodes. For example, suppose device A has 4 device ports, and all 4 device ports belong to different groups, then the 4 device ports can be independent of each other, and the 4 device ports need to be connected to 4 different board index nodes, and are not allowed to share the same board index node. As another example, suppose device B has 4 device ports, and 2 of them belong to the same group, then the 2 device ports belonging to the same group need to be connected to the same board index node, and are isolated from the other 2 device ports that do not belong to the same group, that is, they cannot be connected to the same board index node with device ports that do not belong to the same group. The computer device can search / traverse the board index nodes connected to the device port connection edges of each device node to be verified, so as to obtain the board index nodes to which each device port is connected. This allows the computer device to determine whether device ports in the same group within each of the aforementioned device nodes to be verified are connected to the same board index node, or whether device ports in different groups within each of the aforementioned device nodes to be verified are connected to different board index nodes. When any of the aforementioned devices to be verified have device ports in the same group connected to different board index nodes and / or device ports in different groups connected to the same board index node, the computer device can verify that the device connection rules for the edited node layout and node connection relationships fail the verification. Alternatively, when device ports in different groups within each of the aforementioned devices to be verified are connected to different board index nodes, and each device port in the same group is connected to the same board index node, the computer device can verify that the device connection rules for the edited node layout and node connection relationships pass the verification. It is understandable that if any device under test has device ports of the same group connected to different board index nodes, or if any device under test has device ports of different groups connected to the same board index node, or if any device under test has device ports of the same group connected to different board index nodes and device ports of different groups connected to the same board index node, the device connection rule verification can be deemed to fail.

[0077] For example, please see Figure 8 , Figure 8This is a schematic diagram of a semiconductor device layout on a visual operating interface provided in an embodiment of this application. For example... Figure 8 The visual interface shown can display multiple board index nodes (such as board index node c1, board index node c2, ..., board index node c12), multiple device placeholder nodes, and two device nodes (such as device node 43 and device node 44). Device node 43 has four device ports: device port 54, device port 55, device port 56, and device port 57. Device node 44 has four device ports: device port 58, device port 59, device port 60, and device port 61. Assume that device ports 54, 55, 56, and 57 on device node 43 belong to groups J, K, L, and M respectively; device ports 58 and 61 on device node 44 belong to groups N and X respectively; and device ports 59 and 60 belong to group Y. Since device ports in different groups on any given device need to be connected to different board index nodes, and ports in the same group need to be connected to the same board index node, as... Figure 8 As shown, in the case where device ports on device node 43 are connected to different board index nodes, and device ports 59 and 60 on device node 44 belong to the same group (i.e., group Y mentioned above) but are connected to different board index nodes, the computer device can detect that the device connection rule verification of the current node layout and node connection relationship fails. When the computer device detects that the connection rule verification of device node 44 fails, it can issue an alarm to device node 44 (not shown in the figure), for example, by highlighting device ports 59 and 60, etc. For details, please refer to the subsequent embodiments, which will not be elaborated here. Please refer to the following examples. Figure 9 , Figure 9 This is a schematic diagram of another semiconductor device layout on the visual operation interface provided in this application embodiment. Assuming... Figure 9 For users Figure 8 The edited visual interface shown is compared to the previous one. Figure 8 The node connection relationship shown is as follows: Figure 9 Device port 60 on device node 44 is connected to board index node c11. It can be understood that device port 59 and device port 60 belong to the same group (i.e., group Y above) and are connected to the same board index node. The computer device... Figure 9 The device port connection edges shown are verified, and the device connection rules of the current node layout and node connection relationship are verified and passed.

[0078] In this embodiment, the group corresponding to each device port can be determined by the group identifier corresponding to each device port. The board index node to which each device port is connected can be found to obtain the board index node to which each device port is connected. This allows for determination of whether device ports in the same group within each device node to be verified are connected to the same board index node, or whether device ports in different groups within each device node to be verified are connected to different board index nodes (i.e., implementing device connection rule verification). The group identifier of the device port allows for quick determination of the device port group, enabling rapid entry into grouped device connection rule verification, which helps improve verification efficiency and device layout efficiency. When any of the above-mentioned devices to be verified have device ports in the same group connected to different board index nodes and / or device ports in different groups connected to the same board index node, the device connection rule verification of the edited node layout and node connection relationship fails. Conversely, the device connection rule verification of the edited node layout and node connection relationship passes. The device connection rule verification mechanism improves the correctness of device layout and device connections, thereby improving the accuracy of the updated layout rendering data.

[0079] In some feasible implementations, when device ports in different groups within each of the aforementioned device nodes to be verified are connected to different board index nodes, and each device port in the same group is connected to the same board index node, the device connection rule verification passes. The computer device can update the layout rendering data to obtain updated layout rendering data when the device connection rule verification passes. The updated layout rendering data includes node attribute data of multiple second nodes and connection edge attribute data between the multiple second nodes. The multiple second nodes include at least one board index node that has undergone the first operation and passed the device connection rule verification, at least one device node that has undergone the second operation and passed the device connection rule verification, or at least one device placeholder node that has undergone the third operation and passed the device connection rule verification. It can be understood that when the second operation is a device deletion operation, the device node that has undergone the second operation and passed the device connection rule verification is a device placeholder node after the board index node has been changed. It is understandable that the layout rendering data stored locally on the computer device is not updated or overwritten before the device connection rule verification, so the original version of the data can be maintained, that is, the node layout of multiple first nodes and the data corresponding to the node connection relationship between multiple first nodes are retained before editing.

[0080] In this embodiment, the layout rendering data can be updated after the device connection rule verification is passed (i.e., the device ports of different groups in each of the above-mentioned device nodes to be verified are connected to different board index nodes, and each device port in the same group is connected to the same board index node). That is, the node attribute data and connection edge attribute data of the nodes in the updated layout rendering data are the node attribute data and connection edge attribute data of the nodes that have passed the verification, thereby improving the accuracy of the node attribute data and connection edge attribute data in the layout rendering data, thus improving the accuracy of the layout rendering data and helping to improve the accuracy of device layout.

[0081] In some feasible implementations, the computer device, upon successful verification of the aforementioned device connection rules, can add the node attribute data corresponding to the node layout of the first device node, and the connection edge attribute data corresponding to the connection relationship between the first device node and at least one first board index node, to the aforementioned layout rendering data. The first device node is the device node added in response to the aforementioned third operation, and any one of the aforementioned first board index nodes is the board index node specified by the aforementioned third operation. The device then removes the node attribute data corresponding to the node layout of the second device node, and the connection edge attribute data corresponding to the connection relationship between the second device node and at least one second board index node, from the aforementioned layout rendering data, thereby removing the second device node... The point is changed to a device placeholder node, the second device node is the device node deleted in response to the second operation, and any one of the second board index nodes is a board index node connected to the second device node; the node layout of the third device node is updated to the node attribute data corresponding to the third device node in the layout rendering data, the third device node is the device node whose node layout is adjusted in response to the second operation; at least one of the start point and the end point of the target operation connection edge is updated to the connection edge attribute data corresponding to the target operation connection edge in the layout rendering data, the target operation connection edge is at least one of the connection edges whose start point and end point are changed in response to at least one of the first operation and the second operation. It is understandable that, after the device connection rules for the currently edited node layout and node connection relationships have passed verification, the computer device can add the node layout positions and node connection relationships of newly added device nodes to the layout rendering data, delete the node layout positions and node connection relationships of deleted device nodes from the layout rendering data, update the node layout positions of device nodes with changed positions to the layout rendering data, and update the start and / or end points of changed connection edges to the corresponding connection edge attribute data in the layout rendering data. It should be understood that the layout rendering data stored by the computer device will not be changed or overwritten before the device connection rules have passed verification, thus improving data reliability.

[0082] In this embodiment, if the device connection rule verification passes, the layout rendering data can be updated based on the edited node layout and node connection relationships. The node attribute data corresponding to the node layout of the first device node and the connection edge attribute data corresponding to the connection relationship between the first device node and at least one specified board index node can be added to the layout rendering data. The first device node is the one added in response to the third operation. The node attribute data corresponding to the node layout of the second device node and the connection edge attribute data corresponding to the connection relationship between the second device node and all board index nodes can be removed from the layout rendering data. The second device node is the one deleted in response to the second operation. The node layout of the third device node can be updated to the node attribute data corresponding to the third device node in the layout rendering data. The third node is the one whose node layout was adjusted in response to the second operation. At least one of the start point and end point of the target operation connection edge can be updated to the connection edge attribute data corresponding to the target operation connection edge in the layout rendering data. The target operation connection edge is the connection edge whose start point and end point are changed in response to at least one of the first and second operations. Through the above data updates, updated layout rendering data can be obtained, thus realizing the update of the layout rendering data. Updating the layout rendering data after the device connection rules have been verified improves the accuracy of the layout rendering data and helps to further improve the accuracy of device layout.

[0083] In some feasible implementations, the node layout of the aforementioned plurality of first nodes and the node connection relationships between the aforementioned plurality of first nodes can be the first version data of the semiconductor device layout stored in the local storage space. When the aforementioned device connection rule verification passes, and the computer device receives a data storage instruction, it can store the edited node layout and the edited node connection relationships in the aforementioned local storage space as the second version data of the semiconductor device layout. When the computer device receives a version rollback instruction, it can update and display the node layout and node connection relationships corresponding to the aforementioned first version data in the aforementioned visual operation interface. Here, the aforementioned first version data and the aforementioned second version data can be distinguished by version identifier number, version identifier text, etc., which can be determined according to the actual application scenario and is not limited here. When the device rule connection verification passes, the computer device can detect various user interaction behaviors on the visual operation interface in real time or periodically. When the aforementioned data storage instruction is detected, the edited node layout and the edited node connection relationships are stored in the aforementioned local storage space as the second version data of the semiconductor device layout. It can be understood that, as mentioned above, when the device rule connection verification passes, the computer device can update the layout rendering data to the updated layout rendering data; at this time, the updated layout rendering data is the second version data. If the device rule connection verification passes, the computer device can detect various user interaction behaviors on the visual operation interface in real time or at regular intervals. When the aforementioned version rollback command is detected, the node layout and node connection relationships corresponding to the first version data can be updated and displayed on the aforementioned visual operation interface. For easier understanding, please refer to [link to previous document]. Figure 2 ,like Figure 2 As shown in the diagram, assuming the node layout and node connection relationships of multiple nodes in user interface 1 are first version data, and the layout shown in user interface 2 has passed device connection rule verification, when the computer device detects a user click operation on the "Save" button (i.e., the aforementioned data storage instruction), it can store the edited node layout and the edited node connection relationships in the aforementioned local storage space as the second version data of the semiconductor device layout, and update the layout rendering data to this second version data. When the computer device detects a user click operation on the "Undo" button (i.e., the aforementioned version undo instruction), it can update and display the node layout and node connection relationships corresponding to the aforementioned first version data in the aforementioned visual operation interface, that is, update and display the node layout and node connection relationships of each node in user interface 1 in user interface 2.

[0084] In this embodiment, the node layout of the plurality of first nodes and the node connection relationships between the plurality of first nodes can be the first version data of the semiconductor device layout stored in the local storage space. When the device connection rule verification passes, upon receiving a data storage instruction, the edited node layout and the edited node connection relationships can be stored in the local storage space as the second version data of the semiconductor device layout; upon receiving a version rollback instruction, the node layout and node connection relationships corresponding to the first version data can be updated and displayed in the visual operation interface. The method provided in this embodiment can save two versions of data, before and after editing, in the local storage space without relying on external software, achieving localized data version management, reducing the possibility of data loss or overwriting during the editing process, and improving data security and accuracy. Simultaneously, version rollback is supported; upon receiving a version rollback instruction, the node layout and node connection relationships corresponding to the first version data before editing can be updated and displayed.

[0085] S305, if the above device connection rule verification fails, output alarm indication information for abnormal device layout.

[0086] In some feasible implementations, the computer device can output an alarm message indicating an abnormal device layout when the device connection rules for the edited node layout and node connection relationships fail validation. Here, the computer device can output the alarm message in various ways, including but not limited to highlighting the failed nodes and connections, pop-ups, and text, depending on the actual application scenario. Highlighting includes, but is not limited to, thickening lines and changing colors, and can be determined based on the actual application scenario. For example, if... Figure 2 As shown, the user interface 1 outputs an alarm message indicating an abnormal device layout via the text "Device port 51 is not connected".

[0087] In this embodiment, when the device connection rule verification fails, the device ports, board index nodes and connection edges with potential layout problems can be highlighted to achieve visual location of potential layout problems. This facilitates quick location of erroneous device ports, board indexes or connection edges, reduces the difficulty of subsequent layout debugging and optimization, and thus improves device layout efficiency.

[0088] In summary, the graphical semiconductor device layout method provided in this application can display the node layout of multiple first nodes and the node connection relationships between multiple first nodes on a visual operation interface based on the layout rendering data of semiconductor devices. When a target user operation command is detected in the visual operation interface, the method can respond to the target user operation command to display the edited node layout and node connection relationships on the visual operation interface. After determining all device nodes as at least one device node to be verified based on the edited node layout and edited node connection relationships, the device connection rules are verified based on the device port connection edges of each device node to be verified and the grouping identifier corresponding to each device port. The method provided in this application enables node layout based on user operation commands on a visual interface, achieving a visual layout of devices and board indexes. The interface displays device nodes, board index nodes, and device placeholder nodes before and after editing, improving device layout efficiency. The device connection rule verification mechanism uses the group identifier corresponding to the device port as a reliable basis to perform static checks on the device port connection edges, improving the correctness of the connection between the device port and the board index node, thus contributing to improved device layout accuracy. Furthermore, group-based verification reduces verification pressure and improves verification efficiency, thereby enhancing device layout efficiency. Simultaneously, in cases where device connection rule verification fails, alarm information for potential layout problems is provided, facilitating timely correction of the device layout and further improving efficiency. Therefore, the graphical semiconductor device layout method provided in this application enhances user experience, strengthens product market competitiveness, and provides various enterprises with a device layout solution that offers high efficiency, high accuracy, high data security, and high readability.

[0089] Based on the description of the above-described patterned semiconductor device placement method embodiments, this application also discloses a patterned semiconductor device placement apparatus. This patterned semiconductor device placement apparatus (which can be simply referred to as the apparatus for convenience) can be applied to the above-described... Figures 3 to 9 In the illustrated embodiment of the patterned semiconductor device placement method, the steps in the patterned semiconductor device placement method are used to perform the steps. Here, the patterned semiconductor device placement apparatus can be... Figures 2 to 9 The computer device in the illustrated embodiment, i.e., the graphical semiconductor device layout apparatus, can be the one described above. Figures 3 to 9 The illustrated embodiment is the execution entity of the graphical semiconductor device layout method. See also... Figure 10 , Figure 10 This is a schematic diagram of the structure of the graphical semiconductor device placement apparatus provided in this application embodiment. In this application embodiment, the graphical semiconductor device placement apparatus 30 can operate the following modules: The rendering module 310 is used to render layout data based on semiconductor devices. It displays the node layout of multiple first nodes and the node connection relationship between the multiple first nodes in the visualization operation interface. The visualization operation interface is used for semiconductor device layout editing. The multiple first nodes include at least one board index node, at least one device node and at least one device placeholder node. The response module 320 is used to respond to the target user operation instruction on the above-mentioned visual operation interface when the target user operation instruction is detected, so as to display the edited node layout and the edited node connection relationship on the above-mentioned visual operation interface. The target user operation instruction includes a first operation to edit any one of the above-mentioned board index nodes, a second operation to edit any one of the above-mentioned device nodes, or a third operation to add a single device node to any one of the above-mentioned device placeholder nodes and the connection relationship between the single device node and the specified board index node. The determination module 330 is used to determine all device nodes as at least one device node to be verified based on the above-edited node layout and the above-edited node connection relationship, and to determine the device port of each device node to be verified and the device port connection edge of each device node to be verified, wherein each device port has a corresponding group identifier. The rule verification module 340 is used to verify, based on the device port connection edge of each of the above-mentioned device nodes to be verified and the group identifier corresponding to each of the above-mentioned device ports, whether the device ports of the same group in each of the above-mentioned device nodes to be verified are connected to the same plug-in index node, or whether the device ports of different groups in each of the above-mentioned device nodes to be verified are connected to different plug-in index nodes. In the case that there are device ports of the same group in any of the above-mentioned device nodes to be verified connected to different plug-in index nodes and / or there are device ports of different groups in any of the above-mentioned device nodes to be verified connected to the same plug-in index node, the device connection rule verification fails. The output module 350 is used to output alarm indication information for abnormal device layout when the above device connection rule verification fails.

[0090] In some feasible implementations, before the above-mentioned semiconductor device-based layout rendering data is displayed in the visualization interface, the rendering module 310 is further configured to: Obtain a two-dimensional matrix to describe the location distribution of board indexes and devices. The zero-value elements in the two-dimensional matrix are used to indicate free points, and the non-zero elements in the two-dimensional matrix are used to indicate board indexes or devices. Obtain the attribute data corresponding to the board index or device indicated by each of the above non-zero elements and the attribute data of the above free points, and convert the attribute data corresponding to the board index or device indicated by each of the above non-zero elements and the attribute data of the above free points into the layout rendering data of the above semiconductor device. The layout rendering data of the semiconductor device includes node attribute data and connection edge attribute data of the nodes corresponding to the board index, device or free point indicated by each element in the two-dimensional matrix. The connection edge attribute data includes the attribute data of the connection edge between the device port and the port of the board index.

[0091] In some feasible implementations, the rendering module 310 described above is used for: The layout rendering data of the semiconductor devices includes the aforementioned interposer index and / or the node attribute data corresponding to the devices, which are rendered to render the interposer index as an interposer index node and / or the devices as device nodes. The layout rendering data of the semiconductor devices includes the aforementioned free space nodes, which are rendered to render the free space nodes as device placeholder nodes, thereby obtaining the node layout of the plurality of first nodes. The node shape and layout position of the interposer index node, the device node, and the device placeholder node are defined by the node attribute data corresponding to the interposer index, the devices, and the free space nodes in the layout rendering data. The connection edge attribute data included in the layout rendering data of the semiconductor device is rendered to render the connection relationship between the device port of the device and the port of the board index as the connection edge between the device port and the board index node on the device node, so as to obtain the node layout of the plurality of first nodes and the node connection relationship between the plurality of first nodes, wherein the device port or board index node connected at both ends of the connection edge is defined by the connection edge attribute data in the layout rendering data of the semiconductor device.

[0092] In one possible implementation of the first aspect, the determining module 330 is configured to: The group corresponding to each of the above-mentioned device ports is determined by the group identifier corresponding to each of the above-mentioned device ports; Locate the board index node to which the device port connection edge of each of the above-mentioned device nodes to be verified is connected, so as to obtain the board index node to which each of the above-mentioned device ports is connected. Determine whether the device ports of the same group in each of the above-mentioned device nodes to be verified are connected to the same board index node, or whether the device ports of different groups in each of the above-mentioned device nodes to be verified are connected to different board index nodes.

[0093] In some feasible implementations, when device ports in different groups within each of the aforementioned device nodes to be verified are connected to different board index nodes, and each device port within the same group is connected to the same board index node, the device connection rule verification passes, and the output module 350 is further configured to: If the above device connection rule verification passes, the above layout rendering data is updated to obtain updated layout rendering data. The updated layout rendering data includes node attribute data of multiple second nodes and connection edge attribute data between the multiple second nodes. The multiple second nodes include at least one board index node that has undergone the above first operation and passed the above device connection rule verification, at least one device node that has undergone the above second operation and passed the above device connection rule verification, or at least one device placeholder node that has undergone the above third operation and passed the above device connection rule verification.

[0094] In some feasible implementations, the output module 350 is further used for: The node attribute data corresponding to the node layout of the first device node and the connection edge attribute data corresponding to the connection relationship between the first device node and at least one first board index node are added to the layout rendering data. The first device node is the device node added in response to the third operation, and any one of the first board index nodes is the board index node specified by the third operation. The node attribute data corresponding to the node layout of the second device node and the connection edge attribute data corresponding to the connection relationship between the second device node and at least one second board index node are cleared from the layout rendering data to change the second device node into a device placeholder node. The second device node is the device node deleted in response to the second operation. Any one of the second board index nodes is a board index node connected to the second device node. The node layout of the third device node is updated to the node attribute data corresponding to the third device node in the layout rendering data. The third device node is the device node whose node layout is adjusted in response to the second operation. Update at least one of the start point and the end point of the target operation connection edge to the connection edge attribute data corresponding to the target operation connection edge in the layout rendering data. The target operation connection edge is a connection edge that changes at least one of the start point and the end point in response to at least one of the first operation and the second operation.

[0095] In some feasible implementations, the node layout of the plurality of first nodes and the node connection relationships between the plurality of first nodes are first version data of the semiconductor device layout stored in local storage space; if the device connection rule verification passes, the device further includes a version management module 360, used for: Upon receiving a data storage instruction, the edited node layout and the edited node connection relationship are stored in the local storage space as the second version of the semiconductor device layout data. Upon receiving a version rollback instruction, the node layout and node connection relationships corresponding to the first version data will be updated and displayed in the aforementioned visual operation interface.

[0096] In some feasible implementations, the determining module 330 described above is used for: All device nodes included in the above-edited node layout are considered as at least one device node to be verified. The device ports of each of the aforementioned device nodes to be verified and the device port connection edges of each of the aforementioned device nodes to be verified are determined from the edited node layout and the edited node connection relationships. In some feasible embodiments, the aforementioned second operation includes a device movement operation that adjusts the layout position of a target device node, wherein the target device node is any of the aforementioned device nodes displayed on the aforementioned visual operation interface; the aforementioned response module 320 is used for: In response to the device movement operation, the layout position of the target device node is changed on the visualization interface to the target layout position indicated by the device movement operation, so as to display the edited node layout and the edited node connection relationship on the visualization interface.

[0097] In some feasible implementations, the third operation described above includes device addition and device connection edge addition operations; the response module 320 is used for: In response to the aforementioned device addition and device connection edge addition operations, a target device is added to the layout position of the target device placeholder node in the aforementioned visualization operation interface, and the target device placeholder node is updated to a target device node. A connection edge between the target device port on the target device node and the target board index node is generated on the aforementioned visualization operation interface to display the edited node layout and the edited node connection relationship on the aforementioned visualization operation interface. The target device placeholder node is any of the aforementioned device placeholder nodes displayed on the aforementioned visualization operation interface, the target device port is any device port on the aforementioned target device node, and the target board index node is the board index node indicated by the aforementioned device connection edge addition operation.

[0098] In some feasible implementations, the second operation described above includes a device removal operation; the response module 320 is configured to: In response to the device deletion operation, the connection edge connected to the target device node indicated by the device deletion operation is deleted in the above-mentioned visualization operation interface, and the target device node is updated as the device placeholder node, so as to display the edited node layout and the edited node connection relationship on the above-mentioned visualization operation interface, wherein the target device node is any of the device nodes displayed on the above-mentioned visualization operation interface.

[0099] In some feasible implementations, the second operation includes a first connection edge modification operation that adjusts the starting point of the target connection edge, and the first operation includes a second connection edge modification operation that adjusts the ending point of the target connection edge. The target connection edge is any of the node connection relationships displayed on the visualization interface. The response module 320 is used for: In response to the first connection edge modification operation, the starting point of the target connection edge is changed to the target device port indicated by the first connection edge modification operation on the visualization operation interface, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface; or in response to the second connection edge modification operation, the ending point of the target connection edge is changed to the target board index node indicated by the second connection edge modification operation on the visualization operation interface, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface.

[0100] In the embodiments of this application, the above Figure 10 The modules in the illustrated device can be individually or entirely combined into one or more other modules, or some of the modules can be further divided into multiple functionally smaller modules. This achieves the same operation without affecting the technical effects of the embodiments of this application. The above modules are based on logical function division. In practical applications, the function of one module can be implemented by multiple modules, or the function of multiple modules can be implemented by one module. In other feasible implementations of this application, the above device may also include other modules. In practical applications, these functions can also be implemented with the assistance of other modules, and can be implemented collaboratively by multiple modules, without limitation.

[0101] In some feasible implementations, the above Figures 3 to 9 The implementation methods provided for each step in the graphical semiconductor device layout method shown can be derived from... Figure 10 Each module in the illustrated graphical semiconductor device layout apparatus 30 is executed. For example, the above... Figure 3In the illustrated patterned semiconductor device layout method, step S301 can be performed by... Figure 10 The rendering module 310 in the device shown executes step S302, which can be performed by... Figure 10 The response module 320 in the device shown executes step S303, which can be performed by... Figure 10 The device shown determines that module 330 executes the step S304, which can be performed by [the following]. Figure 10 The rule verification module 340 in the device shown executes step S305, which can be performed by... Figure 10 The output module 350 in the illustrated device performs the operation. The methods executed by each of the above modules can be found in the implementation methods provided in the various steps of the above embodiments, and will not be repeated here.

[0102] In summary, the graphical semiconductor device layout apparatus provided in this application comprises at least a rendering module, a response module, a determination module, a rule verification module, and an output module. It may also include functional modules such as a version management module, which are not limited herein. This graphical semiconductor device layout apparatus can display the node layout of multiple first nodes and the node connection relationships between these first nodes on a visual operation interface based on the layout rendering data of the semiconductor device. When a target user operation command is detected in the visual operation interface, it can respond to the target user operation command to display the edited node layout and node connection relationships on the visual operation interface. After determining all device nodes as at least one device node to be verified based on the edited node layout and edited node connection relationships, the device connection rules are verified based on the device port connection edges of each device node to be verified and the grouping identifier corresponding to each device port. The method provided in this application enables node layout based on user operation commands on a visual interface, achieving a visual layout of components and board indexes. The interface displays component nodes, board index nodes, and component placeholder nodes before and after editing, improving component layout efficiency. The component connection rule verification mechanism uses the group identifier corresponding to the component port as a reliable basis to perform static checks on the connection edges of the component port, improving the correctness of the connection between the component port and the board index node, thus contributing to the accuracy of component layout. Furthermore, multiple component ports of the same component node to be verified are grouped together; that is, multiple component ports that need to connect to the same board are grouped together. Grouped verification determines whether component ports within any group are connected to the same board index node, eliminating the need for multiple port board mapping tables to determine whether component ports within the same group are connected to the same board index node, thereby reducing verification pressure and improving verification efficiency, and thus improving component layout efficiency. Simultaneously, in the event of a component connection rule verification failure, alarm information for potential layout problems is provided, facilitating timely correction of component layout and further improving component layout efficiency. Therefore, the graphical semiconductor device layout apparatus provided in this application embodiment can improve user experience and enhance the market competitiveness of products, providing various enterprises with device layout solutions that are highly efficient, accurate, secure, and readable.

[0103] See Figure 11 , Figure 11 This is a schematic diagram of the structure of the computer device provided in an embodiment of this application. Figure 11 As shown, this computer device can provide... Figure 1 The computer device 20 shown can be used to perform the above-mentioned tasks. Figures 1 to 9 The corresponding embodiments provide the implementation methods. For ease of description, computer device 20 will be used as an example below. It can be understood that... Figure 11 The computer device 20 shown may include Figure 1 The application software, operating system, and hardware functional modules in the computer device 20 shown are not limited here. The computer device 20 is used to perform the above-described... Figures 1 to 9 In the application scenarios of the corresponding embodiments, the computer device 20 may also include, but is not limited to, a processor 201, a network interface 204, and a memory 205. Simultaneously, the computer device 20 may also include a user interface 203 and at least one communication bus 202. The communication bus 202 is used to implement communication between these components. The user interface 203 may include a display screen, keyboard, mouse, etc. Optionally, the user interface 203 may also include a standard wired interface or a wireless interface. The network interface 204 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 205 may be high-speed RAM or non-volatile memory, such as at least one disk storage device. Optionally, the memory 205 may also be at least one storage device located remotely from the aforementioned processor 201. Figure 11 As shown, the memory 205, which is a computer-readable storage medium, may include an operating system, a network communication module, a user interface module, and a device control application.

[0104] The network interface 204 in the computer device 20 can also be connected to the aforementioned Figure 1 The server 10 in the corresponding embodiment establishes a network connection. Figure 11 In the computer device 20 shown, the network interface 204 provides network communication functionality; while the user interface 203 is mainly used to provide an input / output interface for the user. For example, the user can input target user operation commands through a mouse, and the computer device 20 can provide a visual operation interface for the user through a display screen. The processor 201 can be used to call the device control application stored in the memory 205 to achieve the aforementioned functions. Figure 3 The corresponding embodiment describes a graphical semiconductor device layout method.

[0105] It should be understood that the computer device 20 described in the embodiments of this application can perform the foregoing... Figure 3 The description of the patterned semiconductor device layout method in the corresponding embodiments will not be repeated here. Furthermore, the beneficial effects of using the same method will also not be repeated.

[0106] Optionally, the processor 201 mentioned above can be one or more.

[0107] Optionally, the aforementioned memory 205 can be one or more.

[0108] Optionally, the memory 205 and the processor 201 can be integrated together or set separately.

[0109] Furthermore, embodiments of this application also provide a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the methods in the various method embodiments of this application to be performed.

[0110] This application also provides a computer program product, which includes computer program code or instructions, such that when the computer program code or instructions are run on a computer, the methods in the various method embodiments of this application are executed.

[0111] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, so that the methods in the various method embodiments of this application are performed.

[0112] Furthermore, the chip may also include a communication interface. This communication interface can be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0113] It should be understood that the processor in the embodiments of this application can be an integrated circuit chip with the ability to process signals. In implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware encoding processor, or implemented by a combination of hardware and software modules in the encoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0114] The memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), and synchronous link dynamic memory (SLDRAM).

[0115] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory can be integrated into the processor.

[0116] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0117] The term "comprising," and any variations thereof, in the specification, claims, and drawings of this application are intended to cover a non-exclusive inclusion. For example, a process, method, apparatus, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to such processes, methods, apparatus, products, or devices.

[0118] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0119] The methods and related apparatuses provided in this application are described with reference to the method flowcharts and / or structural diagrams provided in this application. Specifically, each block of the method flowchart and / or structural diagram, as well as combinations of blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to create a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, generate instructions for implementing the process. Figure 1 A schematic diagram of one or more processes and / or structures. Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 A schematic diagram of one or more processes and / or structures. Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 A process or multiple processes and / or structures illustrate the steps of the functions specified in one or more boxes.

[0120] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A patterned semiconductor device layout method, characterized in that, include: Based on the layout rendering data of semiconductor devices, the node layout of multiple first nodes and the node connection relationship between the multiple first nodes are displayed in the visualization operation interface. The visualization operation interface is used for semiconductor device layout editing. The multiple first nodes include at least one board index node, at least one device node and at least one device placeholder node. Upon detecting a target user operation instruction on the visual operation interface, the system responds to the target user operation instruction to display the edited node layout and the edited node connection relationship on the visual operation interface. The target user operation instruction includes a first operation to edit any one of the board index nodes, a second operation to edit any one of the device nodes, or a third operation to add a single device node to any one of the device placeholder nodes and the connection relationship between the single device node and the specified board index node. Based on the edited node layout and the edited node connection relationship, all device nodes are determined as at least one device node to be verified, and the device port of each device node to be verified and the device port connection edge of each device node to be verified are determined, wherein each device port has a corresponding group identifier. Based on the device port connection edge of each device node to be verified and the group identifier corresponding to each device port, verify whether the device ports of the same group in each device node to be verified are connected to the same board index node, or whether the device ports of different groups in each device node to be verified are connected to different board index nodes. In any case where the device ports of the same group in any device node to be verified are connected to different board index nodes and / or the device ports of different groups in any device node to be verified are connected to the same board index node, the device connection rule verification fails. If the device connection rule verification fails, an alarm indication message indicating abnormal device layout will be output.

2. The method according to claim 1, characterized in that, Before displaying the node layout of multiple first nodes and the node connection relationships between the multiple first nodes in a visual operation interface based on the semiconductor device-based layout rendering data, the method further includes: Obtain a two-dimensional matrix to describe the location distribution of board indices and devices, wherein zero-value elements in the two-dimensional matrix are used to indicate vacant locations, and non-zero elements in the two-dimensional matrix are used to indicate board indices or devices; Obtain the attribute data corresponding to the board index or device indicated by each of the non-zero elements and the attribute data of the free point, and convert the attribute data corresponding to the board index or device indicated by each of the non-zero elements and the attribute data of the free point into the layout rendering data of the semiconductor device. The layout rendering data of the semiconductor device includes node attribute data and connection edge attribute data of the nodes corresponding to the board index, device or free point indicated by each element in the two-dimensional matrix, and the connection edge attribute data includes the attribute data of the connection edge between the device port and the port of the board index.

3. The method according to claim 2, characterized in that, The layout rendering data based on semiconductor devices displays the node layout of multiple first nodes and the node connection relationships between the multiple first nodes in a visual operation interface, including: The layout rendering data of the semiconductor device includes rendering the PCB index and / or the node attribute data corresponding to the device, to render the PCB index as a PCB index node and / or the device as a device node. The layout rendering data of the semiconductor device includes rendering the node attribute data corresponding to the free space, to render the free space as a device placeholder node, to obtain the node layout of the plurality of first nodes. The node shape and layout position of the PCB index node, the device node, and the device placeholder node are defined by the node attribute data corresponding to the PCB index, the device, and the free space in the layout rendering data. The connection edge attribute data included in the layout rendering data of the semiconductor device is rendered to render the connection relationship between the device port of the device and the port of the board index as the connection edge between the device port and the board index node on the device node, so as to obtain the node layout of the plurality of first nodes and the node connection relationship between the plurality of first nodes, wherein the device port or board index node connected at both ends of the connection edge is defined by the connection edge attribute data in the layout rendering data of the semiconductor device.

4. The method according to any one of claims 1 to 3, characterized in that, The step of verifying whether device ports in the same group within each device node to be verified are connected to the same board index node, or whether device ports in different groups within each device node to be verified are connected to different board index nodes, based on the device port connection edge of each device node to be verified and the group identifier corresponding to each device port, includes: The group corresponding to each device port is determined by the group identifier corresponding to each device port; Locate the board index node to which the device port connection edge of each of the device nodes to be verified is connected, so as to obtain the board index node to which each device port is connected; Determine whether the device ports of the same group in each of the device nodes to be verified are connected to the same plug-in index node, or whether the device ports of different groups in each of the device nodes to be verified are connected to different plug-in index nodes.

5. The method according to any one of claims 1 to 3, characterized in that, The device connection rule verification passes when device ports in different groups within each device node to be verified are connected to different board index nodes, and each device port in the same group is connected to the same board index node. The method further includes: If the device connection rule verification passes, the layout rendering data is updated to obtain updated layout rendering data. The updated layout rendering data includes node attribute data of multiple second nodes and connection edge attribute data between the multiple second nodes. The multiple second nodes include at least one board index node that has undergone the first operation and whose device connection rule verification has passed, at least one device node that has undergone the second operation and whose device connection rule verification has passed, or at least one device placeholder node that has undergone the third operation and whose device connection rule verification has passed.

6. The method according to claim 5, characterized in that, Updating the layout rendering data to obtain updated layout rendering data includes: The node attribute data corresponding to the node layout of the first device node and the connection edge attribute data corresponding to the connection relationship between the first device node and at least one first board index node are added to the layout rendering data. The first device node is the device node added in response to the third operation, and any one of the first board index nodes is the board index node specified by the third operation. The node attribute data corresponding to the node layout of the second device node and the connection edge attribute data corresponding to the connection relationship between the second device node and at least one second board index node are cleared from the layout rendering data, so as to change the second device node into a device placeholder node. The second device node is the device node deleted in response to the second operation, and any second board index node is a board index node connected to the second device node. The node layout of the third device node is updated in the node attribute data corresponding to the third device node in the layout rendering data, wherein the third device node is the device node whose node layout is adjusted in response to the second operation. Update at least one of the start point and the end point of the target operation connection edge to the connection edge attribute data corresponding to the target operation connection edge in the layout rendering data. The target operation connection edge is a connection edge that changes at least one of the start point and the end point in response to at least one of the first operation and the second operation.

7. The method according to any one of claims 1 to 3, characterized in that, The node layout of the plurality of first nodes and the node connection relationship between the plurality of first nodes are first version data of semiconductor device layout stored in local storage space; If the device connection rule verification passes, the method further includes: Upon receiving a data storage instruction, the edited node layout and the edited node connection relationship are stored in the local storage space as the second version of the semiconductor device layout data; Upon receiving a version rollback instruction, the node layout and node connection relationships corresponding to the first version data are updated and displayed in the visual operation interface.

8. The method according to any one of claims 1 to 3, characterized in that, The process of determining all device nodes as at least one device node to be verified based on the edited node layout and the edited node connection relationships, and determining the device port of each device node to be verified and the device port connection edge of each device node to be verified, includes: All device nodes included in the edited node layout are taken as at least one device node to be verified. The device port of each device node to be verified and the device port connection edge of each device node to be verified are determined from the edited node layout and the edited node connection relationship.

9. The method according to any one of claims 1 to 3, characterized in that, The second operation includes a device movement operation that adjusts the layout position of a target device node, wherein the target device node is any one of the device nodes displayed on the visual operation interface; The step of responding to the target user's operation command to display the edited node layout and the edited node connection relationships on the visual operation interface includes: In response to the device movement operation, the layout position of the target device node is changed to the target layout position indicated by the device movement operation on the visualization operation interface, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface.

10. The method according to any one of claims 1 to 3, characterized in that, The third operation includes adding devices and adding device connection edges; responding to the target user's operation command to display the edited node layout and the edited node connection relationships on the visual operation interface includes: In response to the device addition and device connection edge addition operations, a target device is added to the layout position of the target device placeholder node in the visualization operation interface, and the target device placeholder node is updated to a target device node. A connection edge between the target device port on the target device node and the target board index node is generated on the visualization operation interface to display the edited node layout and the edited node connection relationship on the visualization operation interface. The target device placeholder node is any one of the device placeholder nodes displayed on the visualization operation interface, the target device port is any one of the device ports on the target device node, and the target board index node is the board index node indicated by the device connection edge addition operation.

11. The method according to any one of claims 1 to 3, characterized in that, The second operation includes a device deletion operation; the step of responding to the target user's operation command to display the edited node layout and the edited node connection relationship on the visual operation interface includes: In response to the device deletion operation, the connection edge connected to the target device node indicated by the device deletion operation is deleted in the visualization operation interface, and the target device node is updated as the device placeholder node, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface, wherein the target device node is any one of the device nodes displayed on the visualization operation interface.

12. The method according to any one of claims 1 to 3, characterized in that, The second operation includes a first connection edge modification operation that adjusts the starting point of the target connection edge, and the first operation includes a second connection edge modification operation that adjusts the ending point of the target connection edge. The target connection edge is any of the node connection relationships displayed on the visualization operation interface. The step of responding to the target user's operation command to display the edited node layout and the edited node connection relationships on the visual operation interface includes: In response to the first connection edge modification operation, the starting point of the target connection edge is changed to the target device port indicated by the first connection edge modification operation on the visualization operation interface, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface. or In response to the second connection edge modification operation, the endpoint of the target connection edge is changed to the target insert index node indicated by the second connection edge modification operation on the visualization operation interface, so as to display the edited node layout and the edited node connection relationship on the visualization operation interface.

13. A patterned semiconductor device layout apparatus, characterized in that, include: The rendering module is used to render layout data based on semiconductor devices. It displays the node layout of multiple first nodes and the node connection relationship between the multiple first nodes in a visual operation interface. The visual operation interface is used for semiconductor device layout editing. The multiple first nodes include at least one board index node, at least one device node and at least one device placeholder node. The response module is used to respond to the target user operation instruction when a target user operation instruction is detected on the visual operation interface, so as to display the edited node layout and the edited node connection relationship on the visual operation interface. The target user operation instruction includes a first operation to edit any one of the board index nodes, a second operation to edit any one of the device nodes, or a third operation to add a single device node and the connection relationship between the single device node and the specified board index node on any one of the device placeholder nodes. The determination module is used to determine all devices as device nodes to be verified based on the edited node layout and the edited node connection relationship, and to determine the device port of each device node to be verified and the device port connection edge of each device node to be verified, wherein each device port has a corresponding group identifier; The rule verification module is used to verify, based on the device port connection edge of each device node to be verified and the group identifier corresponding to each device port, whether the device ports of the same group in each device node to be verified are connected to the same plug-in index node, or whether the device ports of different groups in each device node to be verified are connected to different plug-in index nodes. In any device node to be verified, if the device ports of the same group are connected to different plug-in index nodes and / or the device ports of different groups in any of the above-mentioned device nodes to be verified are connected to the same plug-in index node, the device connection rule verification fails. The output module is used to output alarm indication information for abnormal device layout when the device connection rule verification fails.

14. A computer device, characterized in that, The computer device includes a display, a processor, and a memory; The display, the memory, and the processor are connected together, wherein the display is used to display a visual view, the memory is used to store program code, and the processor is used to call the program code to execute the method according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program adapted to be loaded by a processor and executed as described in any one of claims 1 to 12.

16. A computer program product, characterized in that, The computer program product includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions to cause the computer device to perform the method as described in any one of claims 1 to 12.

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