Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a manufacturing method thereof, and provides a semiconductor device and a manufacturing method thereof capable of designing a desired delay with high precision using fewer steps. A manufacturing method of a semiconductor device disclosed herein arranges a plurality of circuits on a plane and connects a wiring to each circuit, the manufacturing method including: a placement step of arranging a digital circuit that operates based on a timing signal and a delay circuit configured with a plurality of delay paths having different input / output delay amounts, wherein one of the plurality of delay paths can be selected by a selection signal; a wiring step of connecting an output of the delay circuit so that it becomes a timing signal of the digital circuit; and a delay adjustment step of selecting one of the plurality of delay paths by connecting a predetermined voltage as the selection signal and selecting a delay amount so that input / output timing of the digital circuit satisfies a predetermined condition.

Description

Cross-references to related applications

[0001] The publication of Japanese Patent Application No. 2024-216428, filed on December 11, 2024, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to semiconductor devices and methods of manufacturing the same, and more particularly to semiconductor devices and methods of manufacturing the same configured to arrange a plurality of circuits on a plane and to connect wiring to each circuit. Background Technology

[0003] In semiconductor devices, miniaturization of manufacturing processes and reduction of operating power supply voltages are progressing. With the advancement of miniaturization and low voltage, the impact of clock timing defects caused by wiring delays in semiconductor devices is becoming significant.

[0004] The timing between semiconductor devices and external devices is called AC timing (analog current timing). As part of AC timing verification, it may be necessary to verify the signal via external devices. Therefore, it is necessary to consider the signal delay via external devices during verification operations.

[0005] As manufacturing processes become smaller, the operating frequency of semiconductor devices increases, creating a difference in operating speed compared to external devices. One method to reduce this delay difference is to insert a delay value to pre-slow down signal transmission. This delay value can be on the order of tens of nanoseconds.

[0006] The disclosed technologies are listed below.

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2010-146047

[0008] Patent document 1 discloses a semiconductor device for addressing clock timing defects by inserting a buffer circuit to adjust the delay time. Additionally, patent document 1 discloses providing a cell occupancy check unit to calculate the congestion level of a predetermined area, thereby preventing the buffer circuit from being locally concentrated. Summary of the Invention

[0009] As mentioned above, when using tools to automatically correct timing violations for delay value insertion, the circuit may become locally concentrated. When circuitry and wiring become locally concentrated, it can cause EM errors (electromigration errors), thus requiring manual correction of the delay by inserting the circuit.

[0010] To manually address delays, it becomes necessary to sequentially correct the locations of AC timing defects in the circuit diagram of a single layout. This presents an added challenge of rework, as power analysis needs to be performed for each layout change.

[0011] Other issues and novel features will become apparent from the description herein and from the accompanying drawings.

[0012] According to one embodiment, the method of manufacturing a semiconductor device disclosed herein involves: arranging a delay circuit capable of selecting one of a plurality of delay paths by a selection signal; connecting the output of the delay circuit to serve as a timing signal for a digital circuit; and selecting one of the plurality of delay paths by connecting a predetermined voltage as a selection signal; selecting a delay amount such that the input / output timing of the digital circuit satisfies predetermined conditions. Other features will be described in detail below.

[0013] This disclosure enables the provision of a semiconductor device and a method thereof that can be designed with high precision using fewer steps to achieve the assumed delay. Attached Figure Description

[0014] Figure 1 is a layout diagram of the semiconductor device, a configuration diagram of the delay HM, and a plan view of the semiconductor device layout according to the present disclosure.

[0015] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the present disclosure.

[0016] Figure 3 is a diagram explaining delay adjustment in the semiconductor device of this disclosure.

[0017] Figure 4 is a diagram illustrating delay adjustment in the semiconductor device of this disclosure.

[0018] Figure 5 is a diagram illustrating the switching of delay values ​​in the semiconductor device of this disclosure.

[0019] Figure 6 is a diagram illustrating the switching of delay values ​​in the semiconductor device of this disclosure.

[0020] Figure 7 is a diagram illustrating the switching of delay HM in the semiconductor device of this disclosure.

[0021] Figure 8 is a layout diagram of the relevant semiconductor equipment.

[0022] Figure 9 is a layout diagram of the relevant semiconductor equipment. Detailed Implementation

[0023] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the specification and drawings, the same or corresponding components are indicated by the same reference numerals, and repeated descriptions may be omitted. In the drawings, configurations may be omitted or simplified for ease of description. Furthermore, at least some of the embodiments can be arbitrarily combined with each other.

[0024] <First Embodiment>

[0025] Figure 1A This is a diagram showing the layout of the semiconductor device 10 of this disclosure before the insertion of the delay HM (hard macro) as a delay circuit. Figure 1A As shown, semiconductor device 10 is connected to an upstream external device 21 and a downstream external device 22. Semiconductor device 10 internally includes multiple circuits. Figure 1A In the configuration example shown, semiconductor device 10 is equipped with two trigger circuits FF_A and FF_B, which are digital circuits.

[0026] In the semiconductor device manufacturing method of this disclosure, multiple circuits are arranged on a plane, and wiring is connected to each circuit. Therefore, the deficiencies in AC timing (analog current timing) are solved by using a delay HM (which is a circuit block integrated as hardware). The semiconductor device of this disclosure is implemented based on circuit design data. Figure 1B The delay HM shown is part of an IP (intellectual property) circuit design data that is predicted to have difficulty converging AC timing.

[0027] Figure 1B This diagram illustrates the configuration of a delay HM provided in semiconductor device 10. A timing signal used to add delay is input as an input signal to the input terminal ck_in. The input signal is output via a first circuit 111 to a second circuit 112 and / or a fifth circuit 115. The first circuit 111 includes a plurality of inverter circuits 121. The second circuit 112 includes a plurality of inverter circuits 122. Therefore, the delay HM includes multiple signal paths. The first circuit 111 and the second circuit 112 each implement a delay value corresponding to the number of stages of the inverter circuits. The buffer circuit is also referred to as a delay element.

[0028] Furthermore, the semiconductor device 10 includes a fourth circuit 114 that outputs a selection signal and a fifth circuit 115 that operates as a selector circuit based on a timing signal. The fifth circuit 115 receives the selection signal and the timing signal output from the first circuit 111 and adjusts the delay determined by the signal path. The selector circuit allows the delay value to be switched using a selector.

[0029] For example, if 0 is input as a selection signal to the selector circuit, it switches to the D0 path, which does not pass through the second circuit 112; and if 1 is input as a selection signal, it switches to the D1 path, which passes through the second circuit 112. Since the delay value is determined by, for example, the number of stages of the delay elements in the D0 path, it can be delayed by the number of stages of the delay elements in the first circuit 111. Furthermore, in the D1 path, it can be delayed by the number of stages of the delay elements in both the first circuit 111 and the second circuit 112.

[0030] Therefore, the delay HM is configured as multiple delay paths with different input / output delay amounts, and one of the multiple delay paths can be selected by a selection signal. Furthermore, multiple delay HMs can be arranged. The voltage connected as the selection signal in each delay circuit can be set individually.

[0031] The signal output from the fifth circuit 115 is output from the output terminal ck_out via the sixth circuit 116. The flip-flop circuit FF_B, as a digital circuit, operates based on the timing of the delayed signal and outputs the signal to the external device 22.

[0032] Figure 1C This is a plan view of the layout of semiconductor device 10. First circuits 111 to sixth circuits 116 are configured to form a rectangular block in the plan view. For example, the first circuit 111 and the second circuit 112 can be arbitrarily changed in connection according to the desired number of inverter stages. Furthermore, the positions of the input terminal ck_in and the output terminal ck_out are fixed on the block. The input terminal ck_in and the output terminal ck_out are arranged on the same line parallel to either side of the rectangular shape.

[0033] Figure 2 This is a flowchart illustrating a method for manufacturing the semiconductor device 10 of this disclosure. First, the layout of the semiconductor device 10 is designed using delay HMs (S101). The layout design includes at least a placement process for arranging the delay HMs.

[0034] After the layout design, power analysis (S102) to verify whether the power conditions are met and verification (S103) to check whether the layout rules are met are performed in parallel. If the layout rules are not met, the layout design is performed again. If the layout rules are met, the process continues to the next steps.

[0035] First, verify whether the timing conditions are met (S104). If the timing conditions are met, proceed to the next steps. If the timing conditions are not met, switch the delay value to a level that satisfies the timing conditions (S105). Specifically, perform a wiring process to connect the delay circuit so that its output becomes a timing signal for the digital circuit. Then, by connecting a predetermined voltage as a selection signal, select one of multiple delay paths and perform a delay adjustment process to select the delay amount so that the input / output timing of the digital circuit matches the predetermined conditions. Switching the delay value at the timing violation point can be done automatically using tools or manually using a creation command.

[0036] Once the timing conditions are met, the EM (electromigration) error verification condition is verified (S106). If the EM verification condition is not met, the type of delay HM is switched to meet the EM verification condition (S107). That is, a characteristic adjustment process is performed to change the number of semiconductor elements constituting the delay path while maintaining the delay amount of the delay circuit to meet the predetermined EM characteristics. The switching of the delay HM type at the EM verification violation point can be done automatically using tools or manually through a creation command. If the EM verification condition is met, the process ends.

[0037] In semiconductor device manufacturing methods in related technical fields, design changes due to timing violations are executed sequentially, resulting in significant rework. On the other hand, the semiconductor device manufacturing method disclosed herein utilizes a delay-based design mechanism (HM), which allows for proactive problem-solving. Therefore, by using a delay-based HM, the problem is mitigated, and design time is reduced due to less rework.

[0038] Figures 3A to 3D This diagram illustrates the adjustment of the delay when outputting a signal to the downstream external device 22. In this case, timing violations occur on the clock line of the external output and in the signals from the flip-flop FF_B to the external output.

[0039] To resolve timing violations in the external output clock line, such as Figure 3B As shown, a pre-created layout is used to arrange delay HMs 131 and 132 in parallel upstream of FF_B. The configuration of delay HMs 131 and 132 is as follows: Figure 1B As shown in the diagram, the delay value in the second circuit 112 provided in delay HMs 131 and 132 is inserted into the clock line. This resolves timing violations in the clock line of the external output.

[0040] To resolve timing violations in the signals from flip-flop FF_B to the external output, such as Figure 3C As shown, a pre-created layout is used to arrange delays HM 131 and 132 in parallel downstream of FF_B. The delay values ​​in the second circuit 112 provided in delays HM 131 and 132 are inserted into the data lines. This resolves timing violations in the signals from the flip-flop FF_B to the external output.

[0041] Furthermore, delays HM 131 and 132 are configured to form rectangular blocks and are arranged on the same line parallel to either side of the rectangular shape. Therefore, as... Figure 3D As shown, pin height can be aligned by arranging delay HMs 131 and 132 in parallel.

[0042] Figures 4A to 4DThis is a diagram explaining the adjustment of the delay when a signal is input from an upstream external device 21. In this case, the timing violation occurs in the clock line of the external input and in the signal from external device 21 to flip-flop FF_A.

[0043] To resolve timing violations in externally input clock lines, such as Figure 4B As shown, a pre-created layout is used to arrange delays HM 131 and 132 in parallel upstream of FF_A in the clock line. The configuration of delays HM 131 and 132 is as follows: Figure 1B As shown in the diagram, the delay value in the second circuit 112 provided in delay HMs 131 and 132 is inserted into the clock line. This resolves timing violations in the external input clock line.

[0044] To resolve timing violations in the signal from external device 21 to trigger FF_A, such as Figure 4C As shown, a pre-created layout is used to arrange delays HM 131 and 132 in parallel upstream of FF_A in the data line. The delay values ​​in the second circuit 112 provided in delays HM 131 and 132 are inserted into the data line. This resolves timing violations in the signal from external device 21 to trigger FF_A.

[0045] Furthermore, delays HM 131 and HM 132 consist of blocks forming a rectangular shape, arranged on the same line parallel to either side of the rectangle. Therefore, as... Figure 4D As shown, the height of the pins can be aligned by arranging delays HM 131 and HM 132 in parallel.

[0046] As a comparison example, consider using Figures 8A to 8C and Figures 9A to 9C The case where a buffer circuit BUF is inserted into a semiconductor device 20 whose layout has been determined. Figure 8A and 9A A semiconductor device 20 with four flip-flops FF_A to FF_D is shown. If a delay of tens of nanoseconds is provided after the wiring process in this semiconductor device 20, the wiring that bypasses existing circuitry may complicate the design and potentially lead to a delay value greater than expected (see [link to documentation]). Figure 8B and 8C ).

[0047] Furthermore, as manufacturing processes become more refined, the delay value of each component decreases, resulting in a significant increase in the number of buffer circuits (BUFs) that need to be inserted. This leads to an increase in the number of components required to achieve the desired delay value, and consequently, an increase in workload during the design phase.

[0048] Additionally, consider the scenario where the buffer circuit BUF can be inserted into the clock line of the flip-flop FF_D after the routing process. For example, by... Figure 9B The dashed lines indicate that a design rule violation may occur between the newly inserted buffer circuit BUF, the wiring, and the existing wiring. Even if the clock line of the flip-flop FF_D is rerouted to address this... Figure 9B If the design rules are violated, the delay value may increase, causing previously satisfied timing points to become incorrect.

[0049] Furthermore, because power analysis is performed in parallel with timing design in the back-end design, accurate analysis cannot be performed until the number and type of cells to be used are determined. Therefore, there are problems in estimating leakage due to delayed insertions. Additionally, the concentration of delayed insertions may increase the likelihood of EM errors.

[0050] The semiconductor devices and manufacturing methods disclosed herein can overcome the aforementioned challenges and problems.

[0051] Next, a method for setting a fixed value in the fifth circuit 115, which is a digital circuit, will be described with reference to Figures 5 and 6. Note that in the configuration of delay HM shown in Figures 5 and 6, the [missing information - likely a typo, should be "delayed"]. Figure 1B and Figure 1C Description of the overlapping parts. Figure 5A The delay HM shown is supplied with both a power supply voltage and a ground voltage. The selection of the delay path can be performed by connecting either the power supply voltage or the ground voltage as a selection signal (see [link]). Figure 5B and 5C In other words, the delay value is switched by switching from the supply voltage to ground voltage or vice versa. Figure 6A and 6B As shown, since the latency value can only be switched by changing the connection from VDD to VSS, it has minimal impact on resolving timing violations.

[0052] In addition, components used to fix the signal value to high or low (fixed circuit (tie)-high, fixed circuit-low) can be used for switching. Furthermore, switching can be automated by using EDA (Electronic Design Automation) tools to identify the delay HM and obtain timing verification results.

[0053] As described above, countermeasures against EM errors caused by delayed HM have been implemented, but reference will be made to... Figures 7A to 7E Describe countermeasures for EM errors caused by other factors in semiconductor device 10. Note that... Figures 7A to 7E The configuration of the delay HM shown is related to Figure 1B Description of the overlapping parts.

[0054] Figure 7A As shown Figure 1B The standard delay HM shown in this disclosure. Figure 7BThe delay HM for the fourth circuit 114 used to remove the second circuit 112 and the output selection signal is shown. Figure 7C The delay HM is shown for eliminating the path from the first circuit 111 directly connected to the fifth circuit and the fourth circuit 114 that outputs the selection signal. Figure 7D The delay HM is shown, in which the second circuit 112, the fourth circuit 114 and the fifth circuit 115 for output selection signals are removed during the layout design phase. Figure 7E The delay HM is shown, where the path is directly connected from the first circuit 111 to the fifth circuit and the fourth circuit 114 that outputs the selection signal, and the fifth circuit 115 is removed during the layout design phase.

[0055] By preparing various types of delayed HMs in this way, they can be replaced with delayed HMs without selectors having fewer units (see [link]). Figure 7D and 7E This resolves the EM error.

[0056] Although the invention made by the inventors has been specifically described based on embodiments, it is not required that this disclosure be limited to the embodiments already described, and various modifications may be made without departing from its essential points.

Claims

1. A method for manufacturing a semiconductor device, the semiconductor device having a plurality of circuits arranged on a design plane and wiring connected to each circuit, the method comprising: (a) Arranging digital circuitry that operates based on timing signals; (b) Arranging a delay circuit, the delay circuit including multiple delay paths with different input / output delay amounts, wherein one of the multiple delay paths can be selected by a selection signal; (c) Connect the output terminal of the delay circuit to the input terminal of the digital circuit as the timing signal of the digital circuit; as well as (d) Select one of the plurality of delay paths by connecting a predetermined voltage as the selection signal, and select the delay amount such that the input / output timing of the digital circuit satisfies a predetermined condition.

2. The method according to claim 1, The delay circuit includes a power supply voltage and a ground voltage, and The selection of the delay path is performed by connecting the power supply voltage or the ground voltage as the selection signal.

3. The method according to claim 1, The semiconductor device includes a plurality of the delay circuits, and Each delay circuit has a voltage set individually for the connection as the selection signal for its signal path.

4. The method according to claim 1, wherein the selection step (d) further comprises: (d1) While maintaining the delay amount of the delay circuit, the number of semiconductor elements constituting the delay path is changed so that the semiconductor device satisfies a predetermined electromigration (EM) characteristic.

5. The method according to claim 1, The digital circuit and the delay circuit have rectangular shapes in the plan view of the design plane, and The positions of the input and output terminals of the delay circuit are fixed on either of the rectangular shape.

6. The method of claim 5, wherein the input terminal and the output terminal of the delay circuit are arranged on the same line parallel to either side of the rectangular shape.

7. A semiconductor device, comprising: A delay circuit is configured to take an input signal as input and output a delayed signal, the delayed signal being generated by adding a predetermined delay to the input signal; as well as The digital circuit is configured to operate based on the timing of the delayed signal and output an output signal. The delay circuit includes multiple delay elements and a selector circuit, the selector circuit being configured to select any one of multiple signal paths having different connection stages of the delay elements. The output timing of the output signal of the digital circuit is adjusted by a delay determined by the signal path selected by the selector circuit.

8. The semiconductor device according to claim 7, The delay circuit also includes a power supply voltage and a ground voltage, and The selection of the selector circuit is performed by connecting the power supply voltage or the ground voltage as the selection signal.

9. The semiconductor device of claim 8, further comprising a plurality of said delay circuits, and The signal path in each delay circuit has a voltage set individually for the connection as the selection signal.

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