A digital integrated circuit dynamic current generation method, terminal and medium

Abstract

The application provides a kind of digital integrated circuit dynamic current generation method, terminal and medium, by adopting the full node VCD activity capture of event-driven, dynamic current waveform scaling based on physical characteristics and timing superposition technology, generates high-fidelity power rail dynamic current time domain waveform;Solve the technical problems that traditional average power consumption-based current estimation method cannot reflect transient current fluctuation, leading to PDN design and chip actual working state serious deviation, so that PDN design can be based on real current characteristics for accurate optimization, significantly improve the stability and reliability of chip power supply system, while avoiding the risk of excessive design or function failure caused by improper design margin, provide key technical support for power integrity verification of high-performance chips under advanced process nodes.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a method, terminal and medium for generating dynamic current in digital integrated circuits. Background Technology

[0002] With the improvement of computing power, chip power consumption is increasing. Since chip power supply is usually a fixed value, the increase in power consumption is mainly reflected in the increase in current consumption. This is not only reflected in the I / O power rails, but also in the sharp increase and rapid changes in transient current demand on the power rails. This contradiction between power consumption and demand is even more pronounced in chips like ASICs, which implement increasingly complex functions. A power distribution network (PDN) connects the power supply to the internal transistors of the chip, and its goal is to provide a stable and clean power supply voltage to the chip under any operating state. When dynamic current flows through the PDN, it generates instantaneous voltage drops and inductor noise. If voltage fluctuations exceed the safety tolerance, it will lead to circuit malfunctions or even chip failure. Therefore, accurately predicting the dynamic current of chips like ASICs during operation has become a prerequisite for chip design.

[0003] Currently, the industry primarily relies on averaging methods to estimate power consumption and current during the chip design phase: based on the average power consumption parameters provided by standard cell libraries, combined with circuit netlists, the average power consumption of the entire chip or individual modules is calculated through probabilistic activity simulation or typical vector simulation. The average current of the power rails is simply obtained by dividing the average power consumption by the operating voltage. However, dynamic currents in ASICs directly affect PDN design, and the average current estimated based on average power consumption can cause deviations between the PDN design and the actual operating state of the chip, leading to design failure. Therefore, there is an urgent need to design a method that can accurately generate the true dynamic current of ASICs. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a method, terminal, and medium for generating dynamic current in digital integrated circuits. It uses an ASIC gate-level netlist to simulate and generate a full-node VCD file, calculates the load capacitance and switching time of internal nodes, and scales the dynamic current characteristics of standard cells to generate the actual dynamic current matching each node. Finally, it obtains the total dynamic current of the power rail through timing superposition. This solves the problem in existing technologies where average current estimation cannot reflect transient fluctuations, leading to PDN design failure, and improves the accuracy and reliability of chip power supply design.

[0005] In a first aspect, according to embodiments of the present invention, a method for generating dynamic current in a digital integrated circuit includes:

[0006] S1: Based on the gate-level netlist designed by ASIC, the simulation is run through simulation tools to generate an ASIC full-node VCD file that records the signal activities of all nodes;

[0007] S2: Calculate the load capacitance of all internal nodes of the ASIC based on the ASIC full node VCD file, and obtain the switching time and power consumption of all internal nodes of the ASIC.

[0008] S3: Based on the dynamic current characteristics of the standard cell, using the transition time and power consumption value of each node, a scaled dynamic current that matches the actual working conditions of each ASIC cell is generated through scaling calculation.

[0009] S4: Based on the VCD waveform of the node and the scaled dynamic current, the dynamic current of the node is obtained through waveform generation.

[0010] S5: Perform time-series superposition of the dynamic currents of all nodes to obtain the total dynamic current on the power rail.

[0011] Furthermore, the dynamic current characteristics of the standard cell are obtained from the standard cell library file released by the foundry, which also includes the power consumption, switching time, and capacitance data of the standard cell.

[0012] Furthermore, the dynamic current characteristics of the standard cell include a current component generated by the basic switching behavior of the logic gate;

[0013] The current components include the current components that charge or discharge the load capacitor and the internal shoot-through current components generated during state transitions.

[0014] Furthermore, the specific process of generating the dynamic current of the node is as follows:

[0015] For each signal transition event recorded in the VCD file, based on the specific time of the event and the transition direction, the scaled dynamic current is invoked to generate an independent instantaneous current waveform segment;

[0016] All instantaneous current waveform segments of the node are aligned based on the timestamps of the VCD file and spliced ​​together in chronological order to obtain the dynamic current of the node.

[0017] Specifically, for the transition from low level to high level, the instantaneous current waveform segment includes capacitive charging current characteristics.

[0018] Furthermore, in an ASIC, the internal node is the output of a unit or the driving node of a subsequent unit, and the total capacitance of the internal node is the sum of the input capacitances.

[0019] Furthermore, by applying input stimuli corresponding to different digital application scenarios to the gate-level netlist, different ASIC full-node VCD files are generated, and steps S1-S5 are repeated to obtain the total dynamic current of the power rails of the ASIC under different application scenarios.

[0020] Furthermore, the total dynamic current is a time-domain waveform, used as an input condition for the design and verification of the power distribution network, in order to analyze the voltage stability of the power distribution network under the total dynamic current.

[0021] Furthermore, the power distribution network uses the total dynamic current as the current excitation source, and iteratively adjusts the capacitance, quantity and layout of the decoupling capacitors or optimizes the impedance characteristics of the power and ground networks to ensure that the voltage response time-domain waveform meets the preset voltage tolerance requirements.

[0022] Secondly, according to another embodiment of the present invention, a terminal is also provided, the terminal including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of a dynamic current generation method for digital integrated circuits as described in any one of the first aspects.

[0023] Thirdly, according to another embodiment of the present invention, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of a dynamic current generation method for digital integrated circuits as described in any one of the first aspects.

[0024] The technical principle of this invention is as follows: Based on gate-level netlist simulation, a full-node VCD activity file is generated. Combined with the physical characteristic data of the standard cell library, for each transistor switching event, the standard current waveform is calibrated by load capacitance and transition time to generate the corresponding transient current pulse. Finally, all node currents are superimposed in the time domain to synthesize a high-fidelity power rail dynamic current waveform, providing a precise current excitation source for PDN design. This solves the core defect of the traditional average current method that cannot capture transient peaks and high-frequency noise.

[0025] Compared with existing technologies, this invention has the following advantages: By generating full-node VCD files, it solves the technical problem that traditional probabilistic statistics and finite vector simulation cannot accurately capture the coordinated switching activities and timing information inside the chip, and realizes millisecond-level accurate modeling of the real current load of ASIC in different application scenarios; by introducing a dynamic current waveform scaling mechanism, it breaks through the technical bottleneck of the mismatch between the fixed parameter model of the standard cell library and the actual working conditions, and realizes personalized and accurate characterization of the transient current pulse generated by each transistor switching event; finally, it establishes a full-node timing superposition synthesis of the total dynamic current of the power rail, overcomes the technical limitation that the traditional arithmetic average method cannot reflect the current "resonance" effect, realizes accurate prediction of the time domain waveform of the total dynamic current of the power rail, and provides a reliable current excitation source for PDN design. Attached Figure Description

[0026] Figure 1 This is a flowchart illustrating the steps of an embodiment of the present invention.

[0027] Figure 2 This is an overall framework diagram of an embodiment of the present invention.

[0028] Figure 3 This is a circuit state diagram of the inverter during the 0→1 transition according to an embodiment of the present invention.

[0029] Figure 4 This is a current waveform diagram of the inverter switching from 0 to 1 according to an embodiment of the present invention.

[0030] Figure 5 This is a circuit state diagram of the inverter 1→0 switching according to an embodiment of the present invention.

[0031] Figure 6 This is a current waveform diagram of the inverter 1→0 switching according to an embodiment of the present invention.

[0032] Figure 7 This is a diagram of the internal node structure of the ASIC according to an embodiment of the present invention.

[0033] Figure 8 This is a schematic diagram of node capacitance calculation according to an embodiment of the present invention.

[0034] Figure 9 This is a waveform diagram of the node transient current in an embodiment of the present invention.

[0035] Figure 10 This is a schematic diagram of current superposition in an embodiment of the present invention.

[0036] Figure 11 This is a typical PDN structure diagram according to an embodiment of the present invention. Detailed Implementation

[0037] The technical solutions of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0038] like Figure 1 As shown in the figure, an embodiment of the present invention proposes a method for generating dynamic current in digital integrated circuits, comprising:

[0039] S1: Based on the gate-level netlist designed by ASIC, the simulation is run through simulation tools to generate an ASIC full-node VCD file that records the signal activities of all nodes;

[0040] S2: Calculate the load capacitance of all internal nodes of the ASIC based on the ASIC full node VCD file, and obtain the switching time and power consumption of all internal nodes of the ASIC.

[0041] S3: Based on the dynamic current characteristics of the standard cell, the scaling dynamic current is generated by using the transition time and power consumption of each node through scaling calculation to match the actual working conditions of each ASIC cell.

[0042] S4: Based on the VCD waveform of the node and the scaled dynamic current, the dynamic current of the node is obtained through waveform generation.

[0043] S5: Perform time-series superposition of the dynamic currents of all nodes to obtain the total dynamic current on the power rail.

[0044] like Figure 2 As shown, the overall framework of this invention is as follows: based on the gate-level netlist and standard cell library data of the ASIC, a VCD file recording the activities of all nodes is generated through simulation, and then the node capacitance and power consumption are calculated. The dynamic current characteristics in the standard cell library are used to scale and generate the current of each node, and finally the total current of the power rail is obtained by superposition.

[0045] In step S1, a full node VCD file is generated based on the gate-level netlist.

[0046] Existing technologies often use probabilistic statistical methods or limited test vectors to estimate chip activity data. However, these methods cannot accurately capture complex logic dependencies, timing path races, and cooperative switching behaviors caused by specific functional sequences, resulting in an inability to accurately simulate the actual chip state. Therefore, this invention generates a full-node VCD file to obtain the most realistic and detailed activity data of the chip, laying a solid foundation for accurate transient analysis.

[0047] Input preparation: Obtain the gate-level netlist generated after ASIC synthesis. This netlist describes which standard units (such as AND gates, OR gates, flip-flops, etc.) constitute the circuit and their interconnections. Simultaneously, prepare a set of input stimulus vectors (Test Vectors) that fully represent the target digital application scenario.

[0048] Simulation execution: Load the gate-level netlist and input stimuli into an industry-standard simulation tool and run sequence simulation.

[0049] File generation: During the simulation process, the simulation tool will record any changes in the signal logic values ​​of all circuit nodes throughout the entire simulation time range and generate a complete VCD (Value Change Dump) file.

[0050] The VCD file precisely records the time point (picosecond precision) and type of transition (rising edge 0→1, falling edge 1→0) of each network node. Essentially, it's a detailed activity log, completely recording the precise time sequence of countless transistor switches within the chip under a specific workload. This ensures that the entire subsequent dynamic current generation process is based on the chip's real and precise behavior, completely avoiding biases introduced by probability statistics or average estimation methods, thus laying a solid data foundation for generating high-fidelity dynamic current waveforms.

[0051] In step S2, the load capacitance and power consumption parameters of the internal nodes are calculated.

[0052] Existing average power consumption estimation methods typically use a fixed unit fan-out power consumption or a simple linear model. However, they severely ignore the fact that the load capacitance of the same logic gate can vary greatly after different actual layouts and routings. If the averaging method is used to treat them as equal or approximate, it will lead to serious distortion of current estimation. Therefore, this invention calculates the actual total load capacitance of each node based on the netlist and queries the standard cell library to obtain accurate power consumption values. This ensures that the energy consumption assessment of each switching event is consistent with its physical reality, realizing a leap from logic estimation to physical calculation.

[0053] The dynamic power consumption of digital circuits mainly originates from the charging and discharging of the load capacitor. The energy consumed in a single transition (0→1 or 1→0) is approximately... Although power consumption is a power concept, the energy demand of this transition directly determines the "area" (the integral of current over time). The load capacitance determines the amount of charge that needs to be charged and discharged, while the power supply voltage is constant. Therefore, the load capacitance and transition activity are the most fundamental physical factors determining the dynamic current.

[0054] VCD parsing and event recognition: Based on the VCD file generated in step S1, identify each signal transition event recorded within it. Each event contains three key pieces of information: node name, the time point of the transition, and the direction of the transition (rising or falling).

[0055] Load capacitance calculation: For each internal node, calculate its total load capacitance. An internal node can be the output of a unit or a driving node for a subsequent unit; its total load capacitance is the sum of the capacitances of all its inputs. The precise values ​​of these input capacitors are obtained from the standard cell library files released by the wafer foundry. The output capacitance of the standard cell itself is usually very small and can be ignored here.

[0056] Power consumption parameter acquisition: The standard cell library file is a database containing various physical and electrical parameters for each cell. For each transition event identified in the VCD, the power consumption parameter is calculated based on its transition direction and the actual load capacitance. The corresponding internal power lookup table is searched in the cell library, and the specific power consumption value consumed by this transition can be obtained through interpolation.

[0057] In step S3, waveform scaling is performed based on the dynamic current characteristics of the standard cell.

[0058] Given that existing technologies using the average current method ultimately provide a DC value, which completely fails to reflect the time-domain shape of the current, and considering that the impedance of a PDN is frequency-dependent, with different frequency components of current causing different voltage drops, an incorrect waveform shape will lead to incorrect frequency-domain impedance response analysis. Therefore, this invention obtains prototype dynamic current waveforms with realistic shapes from a standard cell library and scales them based on actual load and timing, so that the generated current pulses contain the true rise / fall times, thereby accurately simulating high-frequency noise effects.

[0059] Obtaining Prototype Waveforms: From the standard cell library provided by the foundry, obtain the prototype waveform of the dynamic current characteristics of each standard cell pre-characterized under specific reference conditions. This prototype waveform is a current pulse in the time domain, which shows in detail the complete shape of the current drawn from the power supply when the cell switches under ideal reference conditions, including the peak value, width, and rise / fall edges.

[0060] Since the driving current capability of a transistor is directly related to the charging speed of the load capacitor, when the actual load capacitor is much larger than the reference capacitor, the time required to charge to a stable voltage is longer, the current pulse becomes wider, and the peak value may change due to circuit characteristics. The scaling model used in this embodiment is based on the physical characteristics of the transistor, ensuring that the scaled waveform accurately reflects the current behavior of the cell instance in the real environment of the current node, rather than a shape under ideal conditions.

[0061] Perform scaling calculations: For each node transition event identified in step S2, calculate the scaling based on its actual load capacitance. The amplitude and time scale of the corresponding prototype dynamic current waveform in the standard cell library are scaled based on the actual transition time (which may affect the pulse width).

[0062] This invention generates a scaled dynamic current waveform that perfectly matches the actual operating conditions of each unit instance in the chip. This waveform is the basic unit for constructing the final node current waveform, and its accuracy directly determines the authenticity of the final total current waveform; this step achieves a crucial transformation from standard to reality.

[0063] In step S4, dynamic current waveforms for each node are generated.

[0064] In scenarios with extremely uneven distribution of switching activity, the averaging method yields a very small average current, while the actual instantaneous current demand is enormous, enough to cause power supply failure. This invention precisely aligns and stitches the scaled current waveforms corresponding to each switching event on the timeline, perfectly preserving the discrete pulse characteristics of the current, and clearly demonstrating the detailed dynamic characteristics of when the power supply is busy and when it is idle.

[0065] Waveform alignment and stitching: The scaled dynamic current waveform obtained in step S3 is aligned with the precise transition time points of the node recorded in the VCD file. For multiple transitions of a node during the simulation time, multiple independent transient current waveform segments will be generated.

[0066] Generate node current: These time-discontinuous current waveform segments are spliced ​​together in chronological order, and the current value is set as the baseline during non-jump periods, thereby obtaining a complete and continuous dynamic current waveform of the node over the entire simulation time range.

[0067] Technical principle: The total power supply current in a digital circuit is the time-series superposition of a large number of discrete switching events. Each logic gate switching event (node ​​transition) generates a brief current pulse on the power supply; the logic gates include, but are not limited to, AND, NOT, XNOR, XOR gates and inverters, etc.

[0068] In some examples, such as Figure 3 As shown, in an inverter:

[0069] When the output node Y transitions from 0 to 1: the PMOS transistor turns on, and current flows out from the power supply VDD. This current consists of two components: one is the "internal current" used to overcome the on-resistance of the PMOS transistor itself, and the other is the main component, the "capacitor charging current" used to charge the input load capacitor of subsequent units. The total current drawn from VDD at this time is the superposition of these two components, and its waveform is as follows: Figure 4 As shown, it manifests as a distinct pulse.

[0070] like Figure 5As shown, when the output node Y transitions from 1 to 0: the NMOS transistor turns on, and the charge stored on the load capacitor discharges to ground through the NMOS transistor. This discharge current does not flow through the VDD power rail, so the current drawn from VDD is extremely small. However, at the instant of the transition, when the input voltage is in the region where both the NMOS and PMOS transistors are partially turned on, a shoot-through current is generated from VDD to GND, such as... Figure 6 As shown, the total current at this time is mainly manifested as this internal current pulse.

[0071] like Figure 7 As shown, in a real ASIC, an internal node (such as the output of a logic gate) typically drives the inputs of multiple subsequent cells, and the total capacitance of that node is the sum of the input capacitances of all the cells it drives. Figure 8 As shown, based on this total capacitance and switching information, power consumption data can be obtained from the library; then, it is scaled to obtain a dynamic current waveform that represents the actual conditions of the node.

[0072] In some examples, the transient current of a node inside the ASIC is as follows: Figure 9 As shown.

[0073] This step yields independent and precise time-domain dynamic current waveforms for each node in the chip. These waveforms accurately reflect the instantaneous power demand of the node's activity and form the microscopic basis for constructing the macroscopic total current.

[0074] In step S5, the total dynamic current of the power rail is generated by superposition.

[0075] According to Kirchhoff's Current Law (KCL), the sum of the currents flowing into a circuit node is zero. Therefore, the total current flowing back to ground is equal to the sum of the currents of all the unit nodes drawing power from VDD. Strictly superimposing these currents in the time domain simulates the combined effect of the current pulses generated by all transistor switching events superimposing and canceling each other out on the power network. This process can accurately capture the current "shaving" effect (resulting in a relatively smooth current distribution) caused by a large number of units switching simultaneously due to clock synchronization (generating huge current spikes) or by different logic path delays.

[0076] The workflow is as follows:

[0077] Timing alignment: Align the dynamic current waveforms generated by all nodes in the chip in step S4 according to a unified, high-precision time axis.

[0078] Current superposition: such as Figure 10 As shown, at each identical time point, the current values ​​of all nodes at that moment are algebraically summed (linearly superimposed). This process traverses the entire simulation time range, ultimately synthesizing a total dynamic current time-domain waveform flowing through the entire chip's digital power rail.

[0079] By applying input stimuli from different digital application scenarios to the gate-level netlist, different ASIC full-node VCD files can be generated. By repeating steps S1-S5 above, the total dynamic current waveform of the power rails of the ASIC under different application scenarios can be obtained. This feature enables the present invention to comprehensively evaluate the dynamic current characteristics of the chip under different operating modes (such as standby, light load, and peak performance), providing key data support for the formulation of system-level power management strategies.

[0080] The total dynamic current generated by this invention is a high-precision time-domain waveform, and its main application value lies in serving as an input condition for the design and verification of power distribution networks (PDN).

[0081] In some examples, such as Figure 11 In the typical PDN structure shown, by applying this current waveform as an excitation source to the impedance model of the PDN, the voltage stability of the power distribution network under this dynamic current excitation can be accurately analyzed, especially the transient IR voltage drop and power supply noise.

[0082] In the PDN design process, the total dynamic current generated by this invention is used as the current excitation source, and the voltage response is analyzed through simulation. Based on the simulation results, designers can iteratively adjust the capacitance, quantity, and layout of the decoupling capacitors, as well as optimize the impedance characteristics of the power and ground networks, so that the time-domain waveform of the voltage response generated by the PDN under dynamic current excitation meets the preset voltage tolerance requirements. This optimization method based on precise current excitation can effectively avoid the over-design or under-design problems in traditional designs.

[0083] According to another embodiment of the present invention, a terminal includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When executed by the processor, the computer program implements the steps of a dynamic current generation method for a digital integrated circuit as described in any of the above embodiments.

[0084] According to another embodiment of the present invention, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of a dynamic current generation method for a digital integrated circuit as described in any of the above embodiments.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for generating dynamic current in a digital integrated circuit, characterized in that: include: S1: Based on the gate-level netlist designed by ASIC, the simulation is run through simulation tools to generate an ASIC full-node VCD file that records the signal activities of all nodes; S2: Calculate the load capacitance of all internal nodes of the ASIC based on the ASIC full node VCD file, and obtain the switching time and power consumption of all internal nodes of the ASIC. S3: Based on the dynamic current characteristics of the standard cell, using the transition time and power consumption value of each node, a scaled dynamic current that matches the actual working conditions of each ASIC cell is generated through scaling calculation. S4: Based on the VCD waveform of the node and the scaled dynamic current, the dynamic current of the node is obtained through waveform generation. S5: Perform time-series superposition of the dynamic currents of all nodes to obtain the total dynamic current on the power rail.

2. The method for generating dynamic current in a digital integrated circuit as described in claim 1, characterized in that: The dynamic current characteristics of the standard cell are obtained from the standard cell library file released by the foundry. The standard cell library file also includes the power consumption, switching time, and capacitance data of the standard cell.

3. The method for generating dynamic current in a digital integrated circuit as described in claim 2, characterized in that: The dynamic current characteristics of the standard cell include current components generated by the basic switching behavior of logic gates. The current components include the current components that charge or discharge the load capacitor and the internal shoot-through current components generated during state transitions.

4. The method for generating dynamic current in a digital integrated circuit as described in claim 1, characterized in that: The specific process of generating the dynamic current of the node is as follows: For each signal transition event recorded in the VCD file, based on the specific time of the event and the transition direction, the scaled dynamic current is invoked to generate an independent instantaneous current waveform segment; All instantaneous current waveform segments of the node are aligned based on the timestamps of the VCD file and spliced ​​together in chronological order to obtain the dynamic current of the node. Specifically, for the transition from low level to high level, the instantaneous current waveform segment includes capacitive charging current characteristics.

5. The method for generating dynamic current in a digital integrated circuit as described in claim 1, characterized in that: In an ASIC, an internal node is the output of a unit or the driving node of a subsequent unit, and the total capacitance of the internal node is the sum of the input capacitances.

6. The method for generating dynamic current in a digital integrated circuit as described in claim 1, characterized in that: By applying input stimuli corresponding to different digital application scenarios to the gate-level netlist, different ASIC full-node VCD files are generated. Steps S1-S5 are repeated to obtain the total dynamic current of the power rails of the ASIC under different application scenarios.

7. The method for generating dynamic current in a digital integrated circuit as described in claim 1, characterized in that: The total dynamic current is a time-domain waveform used as an input condition for the design and verification of the power distribution network, in order to analyze the voltage stability of the power distribution network under the total dynamic current.

8. The method for generating dynamic current in a digital integrated circuit as described in claim 7, characterized in that: The power distribution network uses the total dynamic current as the current excitation source and iteratively adjusts the capacitance, quantity, and layout of the decoupling capacitors or optimizes the impedance characteristics of the power and ground networks to ensure that the voltage response time-domain waveform meets the preset voltage tolerance requirements.

9. A terminal, characterized in that: The terminal includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements a dynamic current generation method for digital integrated circuits as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program that, when executed by a processor, implements a dynamic current generation method for digital integrated circuits as described in any one of claims 1-8.

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