A wafer yield prediction method, system, device and medium based on an LSTM-FFNN combined model

Abstract

The present application relates to the technical field of semiconductor manufacturing, in particular to a wafer yield prediction method, system, device and medium based on LSTM-FFNN combined model; the method firstly preprocesses the obtained semiconductor manufacturing process data; then calls the LSTM model and the FFNN model to construct a feature extraction model, extracts time sequence features and non-time sequence features from the preprocessed semiconductor manufacturing process data; finally, the time sequence features and the non-time sequence features are spliced to obtain fusion features, and the fusion features are input into a full connection layer to obtain wafer yield prediction values; through type processing of time sequence and multi-modal data, higher-precision wafer yield prediction is realized, data support is provided for real-time regulation and parameter optimization of the semiconductor manufacturing process, and the production efficiency is improved while the cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically, to a wafer yield prediction method, system, device, and medium based on an LSTM-FFNN combined model. Background Technology

[0002] With the explosive growth of technologies such as smartphones, deep learning, and the Internet of Things, global semiconductor demand is increasing exponentially. However, semiconductor manufacturing involves hundreds of complex process steps, making process control extremely difficult. Wafer yield, a core indicator in semiconductor manufacturing, is defined as the ratio of the number of qualified chips on a wafer to the total number of chips, directly determining a company's productivity, cost control capabilities, and market competitiveness.

[0003] High yield means more qualified products can be obtained with the same production input, significantly reducing the cost of raw materials, equipment depreciation, and labor per chip. According to industry data, a 10% increase in wafer yield can increase a semiconductor company's net profit by 15%-20%. At the same time, a consistently high yield ensures consistent product quality, improves customer satisfaction, and provides companies with a long-term competitive advantage. Therefore, accurate wafer yield prediction is crucial for semiconductor manufacturing companies.

[0004] Traditional wafer yield prediction relies heavily on statistical models such as linear regression and principal component analysis (PCA). However, these methods have inherent flaws: in semiconductor manufacturing, there are complex nonlinear relationships between wafer-level acceptance test (WAT) parameters, process parameters, and yield. Traditional models, limited by their linear characteristics, cannot capture this nonlinear relationship involving multiple coupled factors.

[0005] Specifically, linear regression models assume a simple linear relationship between parameters and yield, failing to explain the complex impact of minute fluctuations in parameters such as lithography temperature and etching gas flow rate on yield. While PCA can achieve data dimensionality reduction, its linear transformation characteristics make it difficult to extract deep features from process data. Furthermore, some existing methods only use non-time-series data, ignoring the time correlation caused by "batch-to-batch parameter adjustments" in semiconductor manufacturing. This leads to significant deviations between predicted and actual yields, with average coefficients of determination (R²) generally below 25%, failing to provide reliable guidance for production decisions.

[0006] While existing virtual metrology technology can replace some physical measurements with equipment sensor data and reduce production time, relying solely on virtual metrology can easily lead to prediction distortion due to insufficient data consistency. Furthermore, without combining the synergistic effect of time series features and multimodal data, the prediction accuracy still needs to be improved. Summary of the Invention

[0007] This invention addresses the problem that existing virtual metrology methods cannot accurately capture the nonlinear characteristics and time dependence of wafer yield-related factors. It proposes a wafer yield prediction method, system, device, and medium based on an LSTM-FFNN combined model. By processing time series and multimodal data in a categorized manner, it achieves higher-precision wafer yield prediction, providing data support for real-time control and parameter optimization in semiconductor manufacturing processes, thereby improving production efficiency while reducing costs.

[0008] The specific implementation details of this invention are as follows: A wafer yield prediction method based on an LSTM-FFNN combined model includes the following steps: Step S1: Preprocess the acquired semiconductor manufacturing process data; Step S2: Call the LSTM model and FFNN model to build a feature extraction model, and extract time series features and non-time series features from the preprocessed semiconductor manufacturing process data; Step S3: Combine time-series features and non-time-series features to obtain fused features, and input them into the fully connected layer to obtain the wafer yield prediction value.

[0009] To better realize the present invention, step S1 further includes the following steps: Step S11: Obtain semiconductor manufacturing process data to obtain key semiconductor manufacturing process steps; the input characteristics of the key semiconductor manufacturing process steps include actual measurement data, virtual measurement data, equipment output data, and equipment information; Step S12: Based on the acquired historical data, obtain key process steps A, B, and C of semiconductor manufacturing. Step S13: Based on the Kruskal-Wallis test, obtain the high-correlation semiconductor manufacturing process steps D, E, and F.

[0010] To better realize the present invention, step S2 further includes the following steps: Step S21: Use the LSTM and FFNN models to construct a feature extraction model; Step S22: Use the double-layer stacked LSTM structure to process the key semiconductor manufacturing process step A to obtain the time series feature vector; Step S23: Call a four-layer fully connected neural network to process the equipment output data of key semiconductor manufacturing process step B and key semiconductor manufacturing process step C, and the equipment information after one-hot encoding to obtain non-time series features.

[0011] To better realize the present invention, step S22 further includes the following steps: Step S221: Use the first layer of the double-layer stacked LSTM model to extract the timing features of key process step A; Step S222: Call the temporal features of the second layer of the double-layer stacked LSTM model to compress the key process step A, obtain the hidden state of the second layer, and use it as a non-time series feature vector.

[0012] To better realize the present invention, step S23 further includes the following steps: Step S231: Call a fully connected FFNN neural network to process the equipment output data and one-hot encoded equipment information of key semiconductor manufacturing process steps B and C; the fully connected neural network includes an input layer, a hidden layer, and an output layer; Step S232: Based on the input layer weights, input layer biases, hidden layer weights, hidden layer biases, output layer weights, and output layer biases, call the activation function to obtain a 4-dimensional feature vector, and use it as a non-time series feature vector.

[0013] To better realize the present invention, step S3 further includes the following steps: Step S31: Combine time series features and non-time series features to obtain fused features; Step S32: Input the fused features into the constructed feature extraction model, and obtain the wafer yield prediction value through the single-node output layer.

[0014] To better realize the present invention, it further includes step S4: judging whether the wafer yield prediction value is qualified according to the set risk threshold; if the wafer yield prediction value is lower than the set risk threshold, an emergency control notification is generated.

[0015] Based on the wafer yield prediction method based on the LSTM-FFNN combined model proposed above, in order to better realize the present invention, a wafer yield prediction system based on the LSTM-FFNN combined model is further proposed to implement the wafer yield prediction method based on the LSTM-FFNN combined model mentioned above; including a preprocessing unit, a feature extraction unit, and an output unit; The preprocessing unit is used to preprocess the acquired semiconductor manufacturing process data; The feature extraction unit is used to call the LSTM model and FFNN model to construct a feature extraction model, and extract time series features and non-time series features from the preprocessed semiconductor manufacturing process data; The output unit is used to splice time-series features and non-time-series features to obtain fused features, which are then input into the fully connected layer to obtain the wafer yield prediction value.

[0016] Based on the wafer yield prediction method based on the LSTM-FFNN combined model proposed above, in order to better realize the present invention, an electronic device is further proposed, including a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, the wafer yield prediction method based on the LSTM-FFNN combined model is implemented.

[0017] Based on the wafer yield prediction method based on the LSTM-FFNN combination model proposed above, in order to better realize the present invention, a computer-readable storage medium is further proposed, wherein computer instructions are stored on the computer-readable storage medium; when the computer instructions are executed on the above-mentioned electronic device, the above-mentioned wafer yield prediction method based on the LSTM-FFNN combination model is realized.

[0018] The present invention has the following beneficial effects: (1) This invention captures nonlinear relationships and time dependencies that cannot be covered by linear models through categorized feature processing and model fusion; the coefficient of determination (R²) of this model reaches 34.14%, which is more than 13% higher than traditional neural networks (24.46%), support vector regression (19.50%) and other methods on average; the MSE is as low as 0.00291 and the MAE is 0.0397, and the prediction error is significantly lower than that of existing technologies.

[0019] (2) This invention integrates multi-source data such as metering, virtual metering, and equipment parameters, and combines domain knowledge and statistical methods to screen features, thus solving the problem of insufficient information of single data types; it independently constructs time-series data according to equipment chambers, avoiding data interference between different chambers.

[0020] (3) The real-time prediction capability of this invention can provide early warning of yield risk and provide engineers with precise control direction through the key parameter positioning function.

[0021] (4) The present invention adopts cross-validation and early stop strategy, and the model maintains stable performance under different process batches and equipment models, adapting to the needs of multiple scenarios in semiconductor manufacturing. Attached Figure Description

[0022] Figure 1 This is a schematic flowchart of the wafer yield prediction method based on the LSTM-FFNN combined model provided by the present invention.

[0023] Figure 2 A schematic diagram of the combined model structure based on LSTM-FFNN provided by the present invention. Detailed Implementation

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments, and therefore should not be regarded as a limitation on the scope of protection. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] Example 1: This embodiment proposes a wafer yield prediction method based on an LSTM-FFNN combined model, which specifically includes the following steps: Step S1: Preprocess the acquired semiconductor manufacturing process data; Step S1 specifically includes the following steps: Step S11: Obtain semiconductor manufacturing process data to obtain key semiconductor manufacturing process steps; the input characteristics of the key semiconductor manufacturing process steps include actual measurement data, virtual measurement data, equipment output data, and equipment information; Step S12: Based on the acquired historical data, obtain key process steps A, B, and C of semiconductor manufacturing. Step S13: Based on the Kruskal-Wallis test, obtain the high-correlation semiconductor manufacturing process steps D, E, and F.

[0027] Step S2: Call the LSTM model and FFNN model to build a feature extraction model, and extract time series features and non-time series features from the preprocessed semiconductor manufacturing process data; Step S2 specifically includes the following steps: Step S21: Use the LSTM and FFNN models to construct a feature extraction model; Step S22: Use the double-layer stacked LSTM structure to process the key semiconductor manufacturing process step A to obtain the time series feature vector; Step S22 specifically includes the following steps: Step S221: Use the first layer of the double-layer stacked LSTM model to extract the timing features of key process step A; Step S222: Call the temporal features of the second layer of the double-layer stacked LSTM model to compress the key process step A, obtain the hidden state of the second layer, and use it as a non-time series feature vector.

[0028] Step S23: Call a four-layer fully connected neural network to process the equipment output data of key semiconductor manufacturing process step B and key semiconductor manufacturing process step C, and the equipment information after one-hot encoding to obtain non-time series features.

[0029] Step S23 specifically includes the following steps: Step S231: Call a four-layer fully connected FFNN neural network to process the equipment output data and one-hot encoded equipment information of key semiconductor manufacturing process steps B and C; the four-layer fully connected neural network includes an input layer, a hidden layer, and an output layer; Step S232: Based on the input layer weights, input layer biases, hidden layer weights, hidden layer biases, output layer weights, and output layer biases, call the activation function to obtain a 4-dimensional feature vector, and use it as a non-time series feature vector.

[0030] Step S3: Combine time-series features and non-time-series features to obtain fused features, and input them into the fully connected layer to obtain the wafer yield prediction value.

[0031] Step S3 specifically includes the following steps: Step S31: Combine time series features and non-time series features to obtain fused features; Step S32: Input the fused features into the constructed feature extraction model, and obtain the wafer yield prediction value through the single-node output layer.

[0032] Step S4: Based on the set risk threshold, determine whether the predicted wafer yield is qualified. If the predicted wafer yield is lower than the set risk threshold, generate an emergency control notification.

[0033] Working principle: This embodiment achieves higher accuracy wafer yield prediction by processing time series and multimodal data in a categorized manner, providing data support for real-time control and parameter optimization of the semiconductor manufacturing process, thereby improving production efficiency and reducing production costs.

[0034] Example 2: This embodiment is based on the above embodiment 1, such as... Figure 1 As shown, this embodiment includes three core stages: data acquisition and preprocessing, model building and training, and yield prediction. The core is to build an LSTM-FFNN combined model, which divides the data in the semiconductor manufacturing process into time series data and non-time series data according to features, extracts features through LSTM and FFNN respectively, and finally fuses the two types of features to output the yield prediction result.

[0035] Step S1: Data collection and classification processing.

[0036] Data acquisition covers key semiconductor manufacturing processes (such as photolithography, etching, and ion implantation), and acquires four types of input features, including actual measurement data, virtual measurement data, equipment output data, and equipment information.

[0037] Feature selection adopts a combination of "domain knowledge + statistical analysis": from hundreds of process steps, three key steps A, B and C are selected through engineer experience, and then three highly correlated steps D, E and F (lowest p value) are determined through Kruskal-Wallis test (nonparametric analysis of variance) to ensure the effectiveness of input features, as shown in Table 1.

[0038] Step S2: Combinatorial model construction.

[0039] The core technical solution and module architecture of this embodiment aims to construct a combined model of "LSTM temporal feature extraction + FFNN multimodal feature learning," clarifying the entire technical path from data acquisition and preprocessing, model construction and training to yield prediction and control guidance, and refining the implementation logic and parameter settings of each core module. The goal is to address the shortcomings of existing technologies in capturing the nonlinear characteristics, temporal dependencies, and key feature identification of yield-related factors, achieving high-precision prediction of wafer yield throughout the semiconductor manufacturing process, and providing reliable technical support for real-time production control and parameter optimization.

[0040] Step S21: LSTM sub-model (time series feature extraction); A two-layer stacked LSTM structure is used to process the metering, virtual metering, and equipment output data in step A, and a gating mechanism is used to capture time dependencies. The first layer contains 128 neurons for preliminary extraction of the temporal features of process parameters; the second layer contains 64 neurons for further feature compression. The hidden state update formula is: ; in, Let l be the hidden state of the l-th layer at time step t. Given the input data at time step t, the final output is the hidden state of the second layer. As a time series feature vector (dimension 18).

[0041] Step S22: FFNN sub-model (non-time series feature extraction); A four-layer fully connected neural network is used to process the device output data and one-hot encoded device information in steps B and C. The input layer has 141 nodes (2 items of device output data + 139 items of device information), each hidden layer contains 128 neurons, and the ReLU activation function is used (to solve the vanishing gradient problem). The output layer outputs a 4-dimensional feature vector. The calculation formula for each layer is: ; in, , , These are the input, weights, and biases of the l-th layer, respectively. This is the ReLU activation function.

[0042] like Figure 2 As shown, there are 4 hidden layers, which is a fully connected feedforward neural network model (FFNN) with 4 hidden layers.

[0043] Figure 2 The upper half of the BiLSTM model and the lower half of the FFNN have different inputs (input layers) for different data types. The final hybrid model shares a single output (output layer). However, for the FFNN, the fully connected neural network with four hidden layers also has its own output layer, and the final encoded feature is s(4). Finally, the features h(2) and s(4) representing time series data and non-time series data are concatenated and the final wafer yield prediction value y is obtained through a fully connected neural network with a single hidden layer.

[0044] Step S3: Feature fusion and prediction output.

[0045] The 18-dimensional features output from the LSTM are concatenated with the 4-dimensional features output from the FFNN to obtain a 22-dimensional fused feature. This fused feature is then input into a fully connected layer with 32 neurons for feature fusion. Finally, the wafer yield prediction is obtained through a single-node output layer. Model training uses the Adam optimizer (learning rate 0.001) with mean squared error (MSE) as the loss function, as shown in the formula: ; in, The true yield is predicted in each iteration. These are the model's predicted values. Here, represents the model parameters, and N represents the number of samples. During training, 5-fold cross-validation and an early stopping strategy (stopping training if the validation set loss increases for 5 consecutive rounds) are used to prevent overfitting.

[0046] In this embodiment, features h(2) and s(4) representing time series data and non-time series data are concatenated and the final wafer yield prediction value y is obtained through a fully connected neural network with a single hidden layer. Here, the yield prediction value obtained by the previous model concatenation is used as input, and the predicted yield value is obtained through multiple iterations. The final model prediction value is obtained through the optimizer.

[0047] Step S4: Model training and optimization strategies; To ensure model accuracy and generalization ability, targeted training strategies were designed: 1) Dataset partitioning: The dataset was divided into a training set (parameter iteration), a validation set (hyperparameter optimization), and a test set (performance evaluation) in a 7:2:1 ratio; 2) Training control: an early stopping strategy was used to avoid overfitting, and 5-fold cross-validation was used to ensure batch stability; 3) Parameter optimization: the optimal combination of hyperparameters, such as the number of LSTM neurons and the distribution of weight coefficients, was determined through grid search to further improve model adaptability.

[0048] S5: Forecasting and Production Control Process; The model's prediction results are deeply integrated with the semiconductor production control system, forming a closed-loop mechanism of "prediction-decision-control": 1) Real-time prediction trigger: When a new batch of wafers enters a critical process node, the system automatically collects data and starts the yield prediction process, outputting the prediction results within 500ms; 2) Risk-level warning: Three yield thresholds are set (high-optimal threshold ≥90%, normal threshold 80%-90%, and risk threshold <80%). The corresponding warning level is triggered based on the prediction results, and an emergency control notification is automatically pushed when the risk threshold is reached; 3) Precise control guidance: Combining the feature weights output by the yield output module, the key parameters that cause yield risks are located, such as lithography temperature fluctuations and abnormal etching gas flow rates. With reference to the historical optimal process parameter range, specific parameter adjustment suggestions are output, such as temperature ±0.2℃ and flow rate ±5sccm, providing engineers with precise production control directions.

[0049] 1) Real-time data input: Convert real-time data collected during the production process into time series data and non-time series data according to preprocessing rules; 2) Feature extraction: Input the two types of data into LSTM and FFNN sub-models respectively, and output the corresponding feature vectors; 3) Yield prediction: Calculate the predicted yield by fusing features through a fully connected layer; 4) Adjustment decision: If the predicted yield is lower than the threshold, the system locates key influencing parameters, such as temperature and gas flow rate, and outputs parameter adjustment suggestions (refer to the historical optimal parameter range).

[0050] The other parts of this embodiment are the same as those in Embodiment 1 above, so they will not be described again.

[0051] Example 3: This embodiment is based on any one of Embodiments 1-2 above, such as Figure 2As shown, a specific embodiment will be described in detail.

[0052] Step 1: This embodiment is based on Python 3.8, uses the TensorFlow 2.5 deep learning framework, and is equipped with an Intel Xeon Gold 6248 processor and an NVIDIA A100 GPU. The dataset comes from a 3D vertical NAND flash memory production line of a semiconductor company in South Korea, containing full-process data for 89,093 wafers, involving 70 equipment chambers and covering 6 key process steps. The training and test sets are divided in an 8:2 ratio, with a time series length of 3 and a batch size of 32.

[0053] Step 2: Model training steps; 1. Data preparation: Collect metering, virtual metering, equipment output and equipment information data, preprocess according to S2, and generate 18-dimensional time series samples and 141-dimensional non-time series samples.

[0054] 2. Model initialization: Set up a two-layer LSTM structure (128+64 neurons) and a four-layer FFN structure (141-128-128-128-4). Initialize the weights using a He normal distribution and set the bias to 0.

[0055] 3. Training process: The Adam optimizer was used with a learning rate of 0.001, a loss function of MSE, and 100 training epochs. Early stopping was enabled (patience value of 5). After each training epoch, the performance was evaluated on the validation set, and the optimal model parameters were saved.

[0056] 4. Model Evaluation: Calculate the three metrics R², MSE, and MAE on the test set and compare their performance with that of the comparison models (neural network, SVR, decision tree, PLS).

[0057] A. Data preprocessing: Standardizing the WAT parameters: To eliminate differences in units and value ranges among different parameters and improve the stability and convergence speed of model training, the WAT parameters are standardized. The standardization formula used is: ; Where x is the original WAT parameter value, μ is the mean of the parameter, and σ is the standard deviation. This method maps all parameters to a standardized range, facilitating model learning.

[0058] Outlier Handling: Outlier detection and removal are performed based on the 3σ principle. Under the assumption of a normal distribution, the probability of data falling outside the mean plus or minus three standard deviations is extremely low, and these can be considered outliers. Detected outlier batches of data are removed from the training dataset to ensure data quality and prevent outliers from interfering with model training.

[0059] Constructing a 3D input tensor: The processed data is constructed into a 3D input tensor in the format [batch, time step, feature]. This tensor structure clearly organizes the data, facilitating model processing according to batches, time series, and different process features, and fully utilizing the various information in the data.

[0060] B-model construction; This embodiment presents details of the proposed model for wafer yield prediction. First, the various input features of the proposed model are described. Second, the LSTM-FFNN combined model and its ability to effectively utilize both time-series and non-time-series data are detailed.

[0061] B1 describes the input features; This embodiment uses four types of input features: actual measurements, virtual measurements, device output data, and device information. Furthermore, semiconductor manufacturing involves many parameters; therefore, selecting an appropriate and optimal dataset is essential. Among several selection methods, domain knowledge derived from practical experience and statistical analysis were employed to select features. When engineers focus on yield analysis to define root causes, they not only identify critical process steps but also, when the root cause matches specific manufacturing parameters of the critical process steps, determine the manufacturing parameters. Three critical steps, A, B, and C, were selected from hundreds of process steps, along with three additional steps, D, E, and F, determined through statistical analysis (Kruskal-Wallis). The Kruskal-Wallis test requires a non-parametric analysis of variance on several independent samples, as detailed in Table 1 below.

[0062] Table 1 Data and Attribute Correspondence Table

[0063] Step A is the most critical step; this is why measurement and virtual metrology data are obtained after Step A is completed. During the processing in Step A, it was discovered that the edge pattern differs slightly from the center pattern due to the wafer's shape. This difference is quantified through measurement and virtual metrology and directly affects the overall wafer yield. Predicting the wafer edge morphology and then interpreting it as yield and yield degradation classification is a more accurate method for determining wafer yield; however, inspecting the wafer shape is costly in terms of investment and time. Therefore, it is necessary to directly predict the edge yield. Since the proposed prediction model is for overall wafer yield, this embodiment only selected 6 measurements and 23 virtual metrology data corresponding to the wafer edge region from dozens of measurements and virtual metrologies. All virtual metrologies used correspond to data that adds measurement information to the input features. The measurement rate is less than 100%. The output data of the equipment is the plasma on-time value obtained from the process equipment. The equipment is set to plasma on by each chamber after product maintenance and set to plasma off after a defined time or after a serious event. These time values ​​confirm that start and end times affect wafer yield due to fluctuations in process throughput. This data was extracted from steps A, B, and C, along with output data from hundreds of other devices. Some of these were used as input features, but their performance was not ideal because several wafers exhibited the same value for each feature. Finally, device name information for all six steps was obtained and converted into a one-hot encoded dataset.

[0064] This embodiment summarizes the above inspection process. Y (numerical value) represents wafer yield, and X (classification value) represents all process steps. The value of X is given in Step 2, Step A. The specific implementation process is as follows: First, the scope of the entire semiconductor manufacturing process is defined, and the list of process parameters corresponding to each step is extracted. Senior process engineers combine the process failure data, yield fluctuation records and key process node documents from the past three years to initially screen out three core process steps A, B and C that are strongly related to wafer yield. At the same time, the original feature set to be included in the analysis under each step is determined, and redundant parameters that are obviously not related to yield, such as equipment number, operation team and other non-process parameters, are eliminated. Secondly, for the remaining process steps that were not initially screened, process parameter data and wafer yield data of the corresponding batches were collected for each step to construct a statistical analysis dataset, where the independent variable is the process parameter of each step and the dependent variable is the wafer yield. Subsequently, the dataset was preprocessed to remove outliers in yield (based on the 3σ criterion) and samples with a parameter missing rate exceeding 5% to ensure data integrity. Next, the Kruskal-Wallis test was performed, using the process parameters of each step to be verified as test variables. Wafer yield was divided into multiple categorical variables according to intervals. By calculating the test statistics and p-values ​​corresponding to each parameter, a p-value threshold of 0.01 was set, and steps D, E, and F with p-values ​​lower than this threshold were selected, indicating a significant statistical association between the process parameters of these steps and yield. The Kruskal-Wallis test is a nonparametric analysis of variance method used to compare multiple independent samples. The test results are shown in Table 2. Wafer yield is represented as Y (numerical variable), and all process steps are represented as X (categorical variable). Among all process steps, steps D, E, and F were found to have the lowest p-values. Steps B and A, selected based on domain knowledge, ranked fourth and fifth in the list, respectively.

[0065] Table 2 Correspondence Table of Test Results

[0066] Finally, the feature sets corresponding to the six steps A, B, C, D, E, and F are integrated to form the final model input feature pool, completing the entire technical process of feature selection.

[0067] In addition, data preprocessing includes: 1) Outlier removal: Parameter values ​​that exceed the reasonable range are deleted based on the 3σ criterion; 2) Missing value imputation: Measurement data are supplemented using the mean of the same batch of data or regression prediction methods (measurement rate <100%); 3) Normalization: All features are mapped to the [0,1] interval to eliminate dimensional differences; 4) Sequence construction: Time series are constructed independently for each equipment chamber, and the length of each sequence is set to 3 (matching the historical reference habit of engineers to adjust parameters).

[0068] B2 LSTM-FFNN combined model; The proposed prediction model combining LSTM and FFNN is discussed. The structure of the model is as follows: Figure 2 As shown.

[0069] Generally, wafer yield prediction models only use non-time-series data for each process step. However, some data clearly exhibit time-series characteristics. Each data value is correlated with another, as semiconductor manufacturing engineers reference previous parameter values ​​and make a series of fine-tuning adjustments for the next set of data, thus creating time-series data. Therefore, time-series data should be considered when using manufacturing parameters as input features. The proposed LSTM-FFNN combined model effectively utilizes both time-series and non-time-series data to improve yield prediction performance. The model structure is as follows: Figure 2As shown in the figure, this diagram illustrates the complete process of inputting time series data (measurement, virtual measurement, etc.) into the LSTM sub-model, inputting non-time series data (equipment information, etc.) into the FFNN sub-model, and outputting the yield prediction value after feature fusion.

[0070] First, features are extracted from time-series data obtained through measurements, virtual measurements, and device output data, corresponding to step A, using an LSTM architecture. A multi-layer LSTM network is employed, stacking several LSTM models together, with the hidden representations of the previous layer used as input to the next. Stacked LSTMs can solve more complex problems and extract hidden hierarchical information. Let's assume a layer represents the hidden states of time steps within that layer. The following can be calculated: ; This represents the input measurement data for each step. A two-layer stacked LSTM model is used in this process. The final encoded measurement features can be represented as... .

[0071] Secondly, features are extracted from the non-time-series data, namely the device output data in steps B and C and the one-hot encoded device name information. For this, a multi-layer neural network is used. The output of the layer can be calculated as follows:

[0072] in They are the first The layer's inputs, weights, and biases are defined by σ, which is the activation function. Rectified Linear Units (ReLU) are used as the activation function.

[0073] A fully connected neural network with four hidden layers was designed. Each hidden layer consists of 128 nodes. The final encoded features of the non-time series data can be represented as follows: .

[0074] Finally, the features representing time-series and non-time-series data are concatenated and a fully connected neural network with hidden layers is used to obtain the final wafer yield.

[0075] The network is trained using backpropagation with the Adam optimizer and a learning rate of 0.001. The mean squared error (MSE) is used as the loss function, which can be calculated as follows:

[0076] in, It is the training input. It is a wafer yield label. It is the weight of the architecture. It is the prediction function in the proposed LSTM-FFNN combined model.

[0077] Optimization directions for the B3 model; Going forward, we can enhance the LSTM's ability to identify key time steps by introducing an attention mechanism, and combine this with transfer learning to adapt to new manufacturing processes, thereby further improving the model's accuracy and adaptability.

[0078] C training strategy; Loss Function: A weighted mean squared error (MSE) loss function is used to better balance the contributions of different samples during training. For yield prediction tasks, some samples may require higher weights due to their specific process conditions or importance to production decisions. The weighted MSE loss function allows the model to focus more on these important samples, improving the model's prediction accuracy at key data points.

[0079] Optimizer: Select the Nadam optimizer with a learning rate of 0.001. The Nadam optimizer combines the advantages of Nesterov momentum and optimization algorithms such as Adagrad and Adadelta, and can adaptively adjust the learning rate during training to accelerate model convergence while maintaining good stability.

[0080] Early stopping mechanism: To prevent overfitting, an early stopping mechanism is introduced. The training process terminates when the validation loss does not decrease for five consecutive iterations. This means the model's performance on the validation set no longer improves, and continuing training might lead to overfitting. The early stopping mechanism saves the model's optimal parameters in a timely manner, avoiding resource waste and improving the model's generalization ability.

[0081] D. Experimental verification; Test Data: This embodiment uses three months of production data from a 12-inch wafer fab for experimental verification. This dataset contains 25,000 records. This data covers WAT parameters and corresponding yield information for different batches and process stages, and is broadly representative, enabling thorough testing of the model's performance in a real production environment.

[0082] Comparison metrics: The method of this embodiment is compared with the traditional LSTM model. The comparison metrics include mean absolute error (MAE), root mean square error (RMSE), and training time. Based on the comparison with the traditional LSTM model, the LSTM-FFNN model combination (i.e., the "method of this embodiment") further clarifies the model structure and optimizes the table presentation. The specific comparison results are as follows: Table 2 Comparison of Results

[0083] The comparison results clearly show that the prediction model combining LSTM and FFNN proposed in this embodiment outperforms the traditional LSTM model in all indicators, fully demonstrating the effectiveness and superiority of the technical solution in this embodiment.

[0084] Step 3: Linking forecasting applications with production control; A. Model training steps; 1. Data preparation: Collect metering and virtual metering data; equipment output and equipment information data, preprocess them according to section 3.2.2, and generate 18-dimensional time series samples and 141-dimensional non-time series samples.

[0085] 2. Model initialization: Set up a two-layer LSTM structure (128+64 neurons) and a four-layer FFNN structure (141-128-128-128-4). Initialize the weights using a He normal distribution and set the bias to 0.

[0086] 3. Training process: The Adam optimizer was used with a learning rate of 0.001, a loss function of MSE, and 100 training epochs. Early stopping was enabled (patience value of 5). After each training epoch, the performance was evaluated on the validation set, and the optimal model parameters were saved.

[0087] 4. Model Evaluation: Calculate the three metrics R², MSE, and MAE on the test set and compare their performance with that of the comparison models (neural network, SVR, decision tree, PLS).

[0088] B. The model application and control process is as follows: 1) Real-time data input: Convert real-time data collected during the production process into time series data and non-time series data according to preprocessing rules; 2) Feature extraction: Input the two types of data into LSTM and FFNN sub-models respectively, and output the corresponding feature vectors; 3) Yield prediction: Calculate the predicted yield by fusing features through a fully connected layer; 4) Adjustment decision: If the predicted yield is lower than the threshold, the system locates the key influencing parameters (temperature, gas flow rate, etc.) and outputs parameter adjustment suggestions (refer to the historical optimal parameter range).

[0089] Step 4: Practical Application Cases; A semiconductor company applied this embodiment to its 14nm logic chip production line. Before application, using a PLS regression model, the predicted R² was only 20.7%, and yield fluctuations resulted in monthly scrap losses exceeding 5 million yuan. After applying this embodiment: 1. Data Acquisition: Deploy sensors to collect parameters such as temperature (accuracy ±0.1℃), pressure (±0.01atm), and gas flow rate (±1sccm) in real time during photolithography, etching, and other processes, and simultaneously acquire equipment maintenance records and product batch information.

[0090] 2. Predictive Application: Real-time data is preprocessed and input into the model. Before each batch of wafers is produced, the model outputs the predicted yield and key influencing parameters. When the predicted yield is below 85%, the system automatically prompts to adjust the etching gas flow rate, such as from 200 sccm to 210 sccm.

[0091] 3. Application Results: After 3 months of operation, the predicted yield R² increased to 33.8%, with the deviation from the actual yield controlled within ±2%; the average wafer yield increased from 82% to 88%, the scrap rate decreased by 15%, the monthly loss was reduced by RMB 3.2 million, and the return on investment reached 180%.

[0092] The other parts of this embodiment are the same as any one of the above embodiments 1-2, so they will not be described again.

[0093] Example 4: Based on any one of Embodiments 1-3 above, this embodiment proposes a wafer yield prediction system based on an LSTM-FFNN combined model to implement the above-mentioned wafer yield prediction method based on an LSTM-FFNN combined model; it includes a preprocessing unit, a feature extraction unit, and an output unit; The preprocessing unit is used to preprocess the acquired semiconductor manufacturing process data; The feature extraction unit is used to call the LSTM model and FFNN model to construct a feature extraction model, and extract time series features and non-time series features from the preprocessed semiconductor manufacturing process data; The output unit is used to splice time-series features and non-time-series features to obtain fused features, which are then input into the fully connected layer to obtain the wafer yield prediction value.

[0094] This embodiment also proposes an electronic device, including a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, it implements the above-described wafer yield prediction method based on the LSTM-FFNN combined model.

[0095] This embodiment also proposes a computer-readable storage medium storing computer instructions; when the computer instructions are executed on the aforementioned electronic device, the aforementioned wafer yield prediction method based on the LSTM-FFNN combined model is implemented.

[0096] The other parts of this embodiment are the same as any one of the embodiments 1-3 above, so they will not be described again.

[0097] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A wafer yield prediction method based on an LSTM-FFNN combined model, characterized in that, Specifically, the following steps are included: Step S1: Preprocess the acquired semiconductor manufacturing process data; Step S2: Call the LSTM model and FFNN model to build a feature extraction model, and extract time series features and non-time series features from the preprocessed semiconductor manufacturing process data; Step S3: Combine time-series features and non-time-series features to obtain fused features, and input them into the fully connected layer to obtain the wafer yield prediction value.

2. The wafer yield prediction method based on the LSTM-FFNN combined model according to claim 1, characterized in that, Step S1 specifically includes the following steps: Step S11: Obtain semiconductor manufacturing process data to obtain key semiconductor manufacturing process steps; the input characteristics of the key semiconductor manufacturing process steps include actual measurement data, virtual measurement data, equipment output data, and equipment information; Step S12: Based on the acquired historical data, obtain key process steps A, B, and C of semiconductor manufacturing. Step S13: Based on the Kruskal-Wallis test, obtain the high-correlation semiconductor manufacturing process steps D, E, and F.

3. The wafer yield prediction method based on the LSTM-FFNN combined model according to claim 2, characterized in that, Step S2 specifically includes the following steps: Step S21: Use the LSTM and FFNN models to construct a feature extraction model; Step S22: Use the double-layer stacked LSTM structure to process the key semiconductor manufacturing process step A to obtain the time series feature vector; Step S23: Call a four-layer fully connected neural network to process the equipment output data of key semiconductor manufacturing process step B and key semiconductor manufacturing process step C, and the equipment information after one-hot encoding to obtain non-time series features.

4. The wafer yield prediction method based on the LSTM-FFNN combined model according to claim 3, characterized in that, Step S22 specifically includes the following steps: Step S221: Use the first layer of the double-layer stacked LSTM model to extract the timing features of key process step A; Step S222: Call the temporal features of the second layer of the double-layer stacked LSTM model to compress the key process step A, obtain the hidden state of the second layer, and use it as a non-time series feature vector.

5. The wafer yield prediction method based on the LSTM-FFNN combined model according to claim 3, characterized in that, Step S23 specifically includes the following steps: Step S231: Call a fully connected FFNN neural network to process the equipment output data and one-hot encoded equipment information of key semiconductor manufacturing process steps B and C; the fully connected neural network includes an input layer, a hidden layer, and an output layer; Step S232: Based on the input layer weights, input layer biases, hidden layer weights, hidden layer biases, output layer weights, and output layer biases, call the activation function to obtain a 4-dimensional feature vector, and use it as a non-time series feature vector.

6. The wafer yield prediction method based on the LSTM-FFNN combined model according to claim 1, characterized in that, Step S3 specifically includes the following steps: Step S31: Combine time series features and non-time series features to obtain fused features; Step S32: Input the fused features into the constructed feature extraction model, and obtain the wafer yield prediction value through the single-node output layer.

7. The wafer yield prediction method based on the LSTM-FFNN combined model according to claim 1, characterized in that, It also includes step S4: Based on the set risk threshold, determine whether the wafer yield prediction value is qualified. If the wafer yield prediction value is lower than the set risk threshold, generate an emergency control notification.

8. A wafer yield prediction system based on an LSTM-FFNN combined model, used to implement the wafer yield prediction method based on an LSTM-FFNN combined model as described in claim 1; characterized in that, It includes a preprocessing unit, a feature extraction unit, and an output unit; The preprocessing unit is used to preprocess the acquired semiconductor manufacturing process data; The feature extraction unit is used to call the LSTM model and FFNN model to construct a feature extraction model, and extract time series features and non-time series features from the preprocessed semiconductor manufacturing process data; The output unit is used to splice time-series features and non-time-series features to obtain fused features, which are then input into the fully connected layer to obtain the wafer yield prediction value.

9. An electronic device, characterized in that, It includes a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, it implements the wafer yield prediction method based on the LSTM-FFNN combined model as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions; when the computer instructions are executed on the electronic device as described in claim 9, they implement the wafer yield prediction method based on the LSTM-FFNN combined model as described in any one of claims 1-7.

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