Display panel substrate

Abstract

The application relates to a display panel substrate, which comprises N rows of scanning lines and a scanning driving circuit, the scanning driving circuit comprises N cascaded scanning driving units, the output end of the scanning driving unit is connected with a corresponding scanning line, N is a positive integer greater than 2; a test circuit is used for changing the voltage of one row of scanning lines in a pair of adjacent rows of scanning lines, detecting the relationship between the voltages of the two rows of scanning lines in the pair of adjacent rows of scanning lines, and detecting whether short circuit occurs in the pair of adjacent rows of scanning lines. The display panel substrate solves the problem that in the prior art, the ATT stage cannot effectively detect whether short circuit occurs in the two adjacent rows of scanning lines.

Description

Technical Field

[0001] This application relates to the field of array testing technology, and in particular to a display panel substrate. Background Technology

[0002] Currently, in the manufacturing process of array substrates, at the ATT (Array Test Technology) stage of GDL (GateDriver Array, array substrate row drive circuit), the defect detection of GDL mainly adopts the principle of "repairable defects are repaired in time, and unrepairable defects are scrapped in time". This principle can improve the yield of the back end and reduce the production cost.

[0003] To further reduce costs, DRD (Dual-Rate Driving) technology is often used in the manufacturing process of array substrates. DRD technology doubles the number of scan lines and halves the number of data lines. This technology can reduce the number of data lines by half, resulting in a significant cost advantage. Figure 1 An example is given of one type of pixel architecture in DRD technology. Figure 1 In the diagram, Gate1, Gate2, Gate3, Gate4, Gate5...GateN-1 and GateN are scan lines that connect to the output of GDL and extend to the display area, where N is an even number. Data1, Data2, Data3, and Data4 are data lines, as shown below. Figure 1 As shown, the spacing between adjacent scan lines (e.g., Gate 2 and Gate 3, Gate 4 and Gate 5) is extremely small. During the manufacturing process of the array substrate, adjacent scan lines are very prone to connecting due to etching process errors, thus forming short-circuit defects. Currently, it is not possible to effectively detect whether short circuits have occurred between adjacent scan lines at the ATT stage, allowing array substrates with potential defects to flow into the back-end processes, affecting product yield and cost control.

[0004] Therefore, how to detect whether a short circuit occurs between two adjacent scan lines during the ATT stage is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a display panel substrate to solve the problem in the prior art that the ATT stage cannot effectively detect whether a short circuit occurs between two adjacent scan lines.

[0006] In a first aspect, this application provides a display panel substrate, the display panel substrate comprising: N rows of scan lines and a scan driving circuit, the scan driving circuit comprising N cascaded scan driving units, the output terminal of the scan driving unit being connected to the corresponding scan line, where N is a positive integer greater than 2; and a test circuit, the test circuit being used to change the voltage of one row of scan lines in an adjacent row of scan lines pair and detect the relationship between the voltages of the two rows of scan lines in the adjacent row of scan lines pair, thereby detecting whether a short circuit occurs in the adjacent row of scan lines pair.

[0007] Optionally, the test circuit further includes: N / 2 first node leads and N / 2-1 second node leads, wherein the first end of the j / 2th first node lead is connected to the output terminal of the scan driving unit connected to the j-th row of the scan line, where j is an even number greater than zero and j is less than N; the first end of the j / 2th second node lead is connected to the output terminal of the scan driving unit connected to the j+1th row of the scan line; and multiple energy storage units, each energy storage unit corresponding to one of the scan lines and connected to the corresponding scan line; wherein... The first node lead of the j / 2th row is configured to apply a test voltage to the scan line of the jth row during the test phase to detect the relationship between the electric field value of the energy storage unit connected to the scan line of the jth row and the electric field value of the energy storage unit connected to the scan line of the (j+1)th row; or, the second node lead of the j / 2th row is configured to apply the test voltage to the scan line of the (j+1)th row during the test phase to detect the relationship between the electric field value of the energy storage unit connected to the scan line of the jth row and the electric field value of the energy storage unit connected to the scan line of the (j+1)th row.

[0008] Optionally, the test circuit further includes: a plurality of first switch modules, each corresponding to a scan line; the first end of the first switch module corresponding to the j-th scan line is connected to the second end of the j / 2-th first node lead-out line; the first end of the first switch module corresponding to the (j+1)-th scan line is connected to the second end of the j / 2-th second node lead-out line; a first detection line, a second detection line, and a third detection line; the first detection line is connected to the second end of the first switch module corresponding to the j-th scan line; the second detection line is connected to the second end of the first switch module corresponding to the (j+1)-th scan line; and the third detection line is connected to the control terminals of all the first switch modules. The third detection line is configured to receive a control voltage during the test phase to ensure all the first switch modules are in an open state. The first detection line is configured to receive the test voltage during the test phase to transmit the test voltage to the j-th scan line, or the second detection line is configured to receive the test voltage during the test phase to transmit the test voltage to the (j+1)-th scan line.

[0009] Optionally, the display panel substrate further includes: a first test connection terminal, a second test connection terminal, and a third test connection terminal, wherein the first test connection terminal is connected to the first detection line, the second test connection terminal is connected to the second detection line, and the third test connection terminal is connected to the third detection line; The third test connection terminal is configured to be connected to the device that outputs the control voltage during the test phase; the first test connection terminal is configured to be connected to the device that outputs the test voltage during the test phase, or the second test connection terminal is configured to be connected to the device that outputs the test voltage during the test phase.

[0010] Optionally, the display panel substrate includes a fourth test connection terminal and a fifth test connection terminal. The scan driving unit further includes a pull-down control line, wherein the pull-down control line of the j-th scan driving unit is connected to the fourth test connection terminal, the pull-down control line of the (j+1)-th scan driving unit is connected to the fifth test connection terminal, the first detection line is connected to the fourth test connection terminal, and the second detection line is connected to the fifth test connection terminal. The display panel substrate further includes a third test connection terminal, which is connected to the third detection line. The test circuit further includes a plurality of second switch modules, each of which corresponds to a first switch module. The first terminal of each second switch module is connected to the corresponding first switch module. The second end of the module is connected, and the control end of all the second switch modules is connected to the third detection line. The second switch modules correspond one-to-one with the scan lines. The second end of the second switch module corresponding to the j-th scan line is connected to the first detection line, and the second end of the second switch module corresponding to the (j+1)-th scan line is connected to the second detection line. The third test connection is configured to be connected to the device that outputs the control voltage during the test phase, so that all the second switch modules are in the open state. The fourth test connection is configured to be connected to the device that outputs the test voltage during the test phase, or the fifth test connection is configured to be connected to the device that outputs the test voltage during the test phase.

[0011] Optionally, the display panel substrate includes: a plurality of pixel units, and the energy storage unit is the pixel unit.

[0012] Optionally, the test circuit further includes a fourth detection line and a fifth detection line; the energy storage unit includes a third switch module and a first energy storage module, wherein the third switch module corresponds one-to-one with the scan lines, the control terminal of the third switch module corresponding to the j-th scan line is connected to the first detection line, and / or, the control terminal of the third switch module corresponding to the j+1 scan lines is connected to the second detection line; the first end of the third switch module is connected to the fourth detection line, the second end of the third switch module is connected to the first end of the first energy storage module, and the second end of the first energy storage module is connected to the fifth detection line; wherein, the fourth detection line is configured to receive test data voltage during the test phase, and the fifth detection line is configured to receive test common electrode voltage during the test phase, so that the corresponding first energy storage module is charged when the third switch module is in the open state.

[0013] Optionally, the display panel substrate further includes: a sixth test connection terminal and a seventh test connection terminal, wherein the sixth test connection terminal is connected to the fourth detection line, the seventh test connection terminal is connected to the fifth detection line, the sixth test connection terminal is configured to be connected to a device for outputting the test data voltage during the test phase, and the seventh test connection terminal is configured to be connected to a device for outputting the test common electrode voltage during the test phase.

[0014] Optionally, the test circuit further includes: a plurality of second energy storage modules, each corresponding to one of the scan lines; the first end of the second energy storage module corresponding to the j-th scan line is connected to the first detection line; the first end of the second energy storage module corresponding to the (j+1)-th scan line is connected to the second detection line; and the second end of the second energy storage module corresponding to the j-th scan line is connected to the second end of the second energy storage module corresponding to the (j+1)-th scan line.

[0015] Optionally, the test circuit is located on the side of the scan driving circuit near the edge of the display panel substrate.

[0016] In this embodiment, if a short circuit occurs between adjacent row scan line pairs, the voltages of the two scan lines in the adjacent row scan line pair should remain consistent. By changing the voltage of one scan line in the adjacent row scan line pair using a test circuit, the relationship between the voltages of the two scan lines in the adjacent row scan line pair is detected. If they are consistent, it indicates a short circuit between the adjacent row scan line pairs; if they are inconsistent, it indicates no short circuit. This solves the problem in the prior art where it is impossible to effectively detect whether a short circuit has occurred between two adjacent scan lines during the ATT stage. This prevents potentially defective array display panel substrates from flowing into the back-end processes, improves product yield, and reduces product production costs. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 This is a schematic diagram of a type of pixel architecture in DRD technology; Figure 2 A schematic diagram of a first type of display panel substrate provided in an embodiment of this application; Figure 3 A schematic diagram of a second type of display panel substrate provided in an embodiment of this application; Figure 4(a) is a schematic diagram of a third type of display panel substrate provided in an embodiment of this application; Figure 4(b) is a schematic diagram of the fourth type of display panel substrate provided in the embodiments of this application; Figure 5(a) is a schematic diagram of a substrate in the prior art; Figure 5(b) is a schematic diagram of a substrate provided in an embodiment of this application; Figure 6 A schematic diagram of a fifth type of display panel substrate provided in an embodiment of this application; Figure 7 A schematic diagram of a scanning drive circuit provided in an embodiment of this application; Figure 8(a) is a schematic diagram of the sixth type of display panel substrate provided in the embodiments of this application; Figure 8(b) is a schematic diagram of the seventh type of display panel substrate provided in the embodiments of this application; Figure 8(c) is a schematic diagram of the eighth type of display panel substrate provided in the embodiments of this application; Figure 9(a) is a schematic diagram of the ninth type of display panel substrate provided in the embodiments of this application; Figure 9(b) is a schematic diagram of the tenth type of display panel substrate provided in the embodiments of this application; 1. Substrate; 10. Display panel substrate; 20. Test area; 21. First test connection terminal; 22. Second test connection terminal; 23. Sixth test connection terminal; 24. Seventh test connection terminal; 25. Eighth test connection terminal; 100. Scan driving circuit; 101. Scan driving unit; 200. Test circuit; 201. First node lead-out line; 202. Second node lead-out line; 203. First detection line; 204. Second detection line; 205. Third detection line; 206. Fourth detection line; 207. Fifth detection line; 208. Pull-down control line; 210. First switch module; 211. Second switch module; 212. Energy storage unit; 213. Second energy storage module; 300. Signal input area; 301. Signal input terminal; 400. Display area. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0023] To address the technical problem in the prior art that it is impossible to effectively detect whether a short circuit occurs between two adjacent scan lines during the ATT stage, this application provides a display panel substrate that can solve the technical problem in the prior art that is unable to effectively detect whether a short circuit occurs between two adjacent scan lines during the ATT stage.

[0024] Figure 2 A display panel substrate provided in this application embodiment includes: N rows of scan lines and a scan driving circuit 100, wherein the scan driving circuit 100 includes N cascaded scan driving units 101, the output terminal of the scan driving unit 101 is connected to the corresponding scan line, and N is a positive integer greater than 2. For example, Figure 2Gate1, Gate2, Gate3, Gate4, Gate5...GateN are the 1st scan line, the 2nd scan line, the 3rd scan line, the 4th scan line, the 5th scan line...the Nth scan line, respectively.

[0025] The test circuit 200 is used to change the voltage of one row scan line in an adjacent row scan line pair and detect the relationship between the voltages of the two row scan lines in the adjacent row scan line pair, thereby detecting whether a short circuit has occurred in the adjacent row scan line pair.

[0026] For example, such as Figure 1 and Figure 2 As shown, exemplary adjacent scan line pairs can be Gate2 and Gate3, Gate4 and Gate5, etc. The spacing between the two scan lines in an adjacent scan line pair is extremely small, making short circuits prone to occur. It should be noted that, for example... Figure 1 As shown, the distance between Gate1 and Gate2 is relatively large, and the distance between GateN-1 and GateN is also relatively large. Therefore, a short circuit will not occur, short circuit detection is not required, and they are not connected to the test circuit 200.

[0027] For example, there are two ways to perform short-circuit testing on adjacent row scan line pairs, such as... Figure 2 As shown, adjacent scan line pairs are exemplarily Gate2 and Gate3. In the first test method, with the initial voltages of both Gate2 and Gate3 both at 0, during the test phase, the voltage of Gate2 is changed to the test voltage (test voltage greater than 0), and it is checked whether the voltages of Gate2 and Gate3 are consistent. If they are consistent, it indicates a short circuit between Gate2 and Gate3; if they are inconsistent, it indicates no short circuit between Gate2 and Gate3. In the second test method, with the initial voltages of both Gate2 and Gate3 both at the test voltage, the voltage of Gate2 is changed to 0, and it is checked whether the voltages of Gate2 and Gate3 are consistent. If they are consistent, it indicates a short circuit between Gate2 and Gate3, as the voltage of Gate2 is pulled high by Gate3; if they are inconsistent, it indicates no short circuit between Gate2 and Gate3. Similarly, short circuit detection can also be achieved by changing the voltage of Gate3 during the test phase.

[0028] Through the above embodiments, if a short circuit occurs in an adjacent row scan line pair, the voltages of the two scan lines in the adjacent row scan line pair should remain consistent. By changing the voltage of one scan line in the adjacent row scan line pair through a test circuit, the relationship between the voltages of the two scan lines in the adjacent row scan line pair is detected. If they are consistent, it indicates that a short circuit has occurred in the adjacent row scan line pair; if they are inconsistent, it indicates that no short circuit has occurred. This solves the problem of not being able to effectively detect whether a short circuit has occurred between two adjacent scan lines in the ATT stage, thereby preventing potentially defective array substrates from flowing into the back-end processes, improving the product yield in the back-end, and reducing the product production cost.

[0029] In one alternative embodiment, N is an even number, such as Figure 3 As shown, the test circuit 200 also includes: N / 2 first node leads 201 and N / 2-1 second node leads 202, the first end of the j / 2 first node lead 201 is connected to the output end of the scan driving unit 101 connected to the j-th row of the scan line, j is an even number greater than zero and j is less than N, the first end of the j / 2 second node lead 202 is connected to the output end of the scan driving unit 101 connected to the j+1-th row of the scan line; Multiple energy storage units, each corresponding to one of the scan lines, and each energy storage unit is connected to its corresponding scan line; Specifically, the j / 2nd first node lead-out line 201 is configured to apply a test voltage to the j-th row of the scan line during the testing phase to detect the relationship between the electric field value of the energy storage unit connected to the j-th row of the scan line and the electric field value of the energy storage unit connected to the (j+1)-th row of the scan line; or, the j / 2nd second node lead-out line 202 is configured to apply the test voltage to the (j+1)-th row of the scan line during the testing phase to detect the relationship between the electric field value of the energy storage unit connected to the j-th row of the scan line and the electric field value of the energy storage unit connected to the (j+1)-th row of the scan line.

[0030] For example, such as Figure 3As shown, the adjacent row scan line pairs are Gate2 and Gate3, respectively. When the initial voltages of both Gate2 and Gate3 are 0, during the test phase, the first node lead 201 applies a test voltage to Gate2 and detects the relationship between the electric field value of the energy storage unit connected to Gate2 and the electric field value of the energy storage unit connected to Gate3. If they are consistent, it means that the voltage of Gate2 is consistent with the voltage of Gate3, indicating that a short circuit has occurred between Gate2 and Gate3. If they are inconsistent, it means that a short circuit has not occurred between Gate2 and Gate3. Similarly, the voltage of Gate3 can also be changed during the test phase to achieve short circuit detection. The system is configured with a first node lead and a second node lead to allow external changes to the voltage of one row of scan lines in an adjacent row scan line pair. An energy storage unit is also configured to detect whether a short circuit has occurred in the adjacent row scan line pair by detecting the relationship between the electric field values ​​of the energy storage units connected to the two rows of scan lines in the adjacent row scan line pair.

[0031] In an optional embodiment, as shown in FIG4(a), the above-mentioned test circuit further includes: Multiple first switch modules 210, each of which corresponds to a scan line. The first end of the first switch module 210 corresponding to the j-th scan line is connected to the second end of the j / 2-th first node lead-out line, and the first end of the first switch module 210 corresponding to the j+1-th scan line is connected to the second end of the j / 2-th second node lead-out line. The first detection line 203, the second detection line 204, and the third detection line 205 are connected to the second end of the first switch module 210 corresponding to the j-th scan line, the second detection line 204 is connected to the second end of the first switch module 210 corresponding to the (j+1)-th scan line, and the third detection line 205 is connected to the control end of all the first switch modules 210. The third detection line 205 is configured to receive a control voltage during the test phase to ensure that all the first switch modules 210 are in the open state; the first detection line 203 is configured to receive a test voltage during the test phase to transmit the test voltage to the j-th scan line; or the second detection line 204 is configured to receive a test voltage during the test phase to transmit the test voltage to the (j+1)-th scan line.

[0032] For example, as shown in FIG4(a), the first switching module 210 includes: a first thin film transistor T0, a first terminal of the first switching module 210 being the drain of the first thin film transistor T0, a second terminal of the first switching module 210 being the source of the first thin film transistor T0, and a control terminal of the first switching module 210 being the gate of the first thin film transistor T0.

[0033] For example, as shown in Figure 4(a), a first switch module 210 and a third detection line 205 are configured. Only during the testing phase (specifically, the short-circuit test of adjacent row scan lines), the third detection line 205 receives a control voltage to keep all first switch modules 210 in the open state. At this time, even-numbered row scan lines such as Gate2 and Gate4 are connected to the first detection line 203, and odd-numbered row scan lines such as Gate3 and Gate5 are connected to the second detection line 204. During the non-testing phase, the third detection line 205 does not receive a control voltage, and all first switch modules 210 are in the closed state. At this time, even-numbered row scan lines such as Gate2 and Gate4 are disconnected from the first detection line 203. Odd-numbered scan lines such as Gate3 and Gate5 are disconnected from the second detection line 204 to avoid interference from external detection lines to the scan drive circuit. Since even-numbered scan lines such as Gate2 and Gate4 are connected to the first detection line 203, and odd-numbered scan lines such as Gate3 and Gate5 are connected to the second detection line 204, during the testing phase, the test voltage can be transmitted to even-numbered scan lines such as Gate2 and Gate4 in one go through the first detection line 203, or to odd-numbered scan lines such as Gate3 and Gate5 in one go through the second detection line 204, to complete the short-circuit test task of all adjacent scan line pairs and speed up the testing process.

[0034] In an optional embodiment, as shown in FIG4(b), the display panel substrate further includes: The test connection terminal 21, the second test connection terminal 22, and the third test connection terminal are provided. The first test connection terminal 21 is connected to the first detection line 203, the second test connection terminal 22 is connected to the second detection line 204, and the third test connection terminal is connected to the third detection line. For example, Figure 4(b) only shows the first test connection terminal 21 and the second test connection terminal 22, and does not show the third test connection terminal.

[0035] The third test connection terminal is configured to be connected to the device that outputs the control voltage during the test phase; the first test connection terminal 21 is configured to be connected to the device that outputs the test voltage during the test phase, or the second test connection terminal 22 is configured to be connected to the device that outputs the test voltage during the test phase.

[0036] For example, as shown in FIG5(a), the substrate 1 includes: a plurality of display panel substrates 10, each display panel substrate 10 having a signal input area 300, the signal input area 300 including: a plurality of signal input terminals 301, the display panel substrate 10 further including: a plurality of test areas 20, the test areas 20 corresponding one-to-one with the signal input areas 300, the test areas 20 including: a plurality of eighth test connection terminals 25, the eighth test connection terminals 25 in the test areas corresponding one-to-one with the signal input terminals 301 of the corresponding signal input areas 300, the eighth test connection terminals 25 and the signal input terminals 301 The connection is shown in Figure 5(a) only as an example, illustrating the connection relationship between the four eighth test connection terminals 25 and the four signal input terminals 301. As shown in Figures 4(b) and 5(b), this application provides a first test connection terminal 21, a second test connection terminal 22 and a third test connection terminal in the test area 20. The first test connection terminal 21 is connected to the first detection line 203, the second test connection terminal 22 is connected to the second detection line 204, and the third test connection terminal is connected to the third detection line, so as to facilitate the application of test voltage to the scan line and control voltage to the first switch module from the outside.

[0037] In an optional embodiment, the display panel substrate includes a fourth test connection terminal and a fifth test connection terminal. The scan driving unit further includes a pull-down control line, wherein the pull-down control line of the j-th scan driving unit is connected to the fourth test connection terminal, the pull-down control line of the (j+1)-th scan driving unit is connected to the fifth test connection terminal, the first detection line is connected to the fourth test connection terminal, and the second detection line is connected to the fifth test connection terminal. The display panel substrate further includes a third test connection terminal, which is connected to the third detection line. Figure 6 As shown, the test circuit 200 also includes: Multiple second switch modules 211 are provided, each corresponding to a first switch module 210. The first end of each second switch module 211 is connected to the second end of the corresponding first switch module 210. The control end of all the second switch modules 211 is connected to the third detection line. Each second switch module 211 corresponds to a scan line. The second end of the second switch module 211 corresponding to the j-th scan line is connected to the first detection line 203. The second end of the second switch module 211 corresponding to the (j+1)-th scan line is connected to the second detection line 204. For example, as shown in FIG4(a), the second switching module 211 includes: a second thin film transistor T1, a first terminal of the second switching module 211 being the drain of the second thin film transistor T1, a second terminal of the second switching module 211 being the source of the second thin film transistor T1, and a control terminal of the second switching module 211 being the gate of the second thin film transistor T1.

[0038] For example, as shown in FIG5(a), the substrate 1 in the prior art includes: a plurality of display panel substrates 10. In the test area 20 of the display panel substrate 10, a fourth test connection terminal and a fifth test connection terminal are provided. The fourth test connection terminal and the fifth test connection terminal are two of a plurality of eighth test connection terminals 25. The pull-down control lines of an even number of scan driving units are connected to the fourth test connection terminal, and the pull-down control lines of an odd number of scan driving units are connected to the fifth test connection terminal. Therefore, in this application, the first detection line is directly connected to the fourth test connection terminal, and the second detection line is connected to the aforementioned fifth test connection terminal to apply a test voltage to the scan line from the fourth test connection terminal or the fifth test connection terminal. Only a third test connection terminal is provided in the test area 20 of the display panel substrate 10. The third test connection terminal is connected to the aforementioned third detection line to apply a control voltage to the first switch module and the second switch module from the fifth test connection terminal. That is, the eighth test connection terminal 25 in the test area 20 of the display panel substrate 10 in the prior art is shared, thereby reducing the short circuit test cost.

[0039] For example, in the tests related to the pull-down control line connected to the fourth test connection terminal, the voltage applied to the fourth test connection terminal will change from high voltage to low voltage (applying high and low voltages is equivalent to applying a test voltage). Therefore, the tests related to this pull-down control line can be performed simultaneously with short-circuit tests, such as... Figure 6 As shown, a first switch module 210 is disposed between the fourth test connection terminal and the scan line. This first switch module 210 includes a first thin-film transistor T0. The first terminal of the first switch module 210 is the drain of the first thin-film transistor T0, the second terminal is the source of the first thin-film transistor T0, and the control terminal is the gate of the first thin-film transistor T0. Because parasitic capacitance exists between the gate, source, and drain of the first thin-film transistor T0, when the voltage at the fourth test connection terminal changes, this voltage change will be transmitted through the first thin-film transistor T0. The parasitic capacitance of transistor T0 is coupled to the scan line, causing fluctuations in the output voltage of the connected scan line, which in turn affects the accuracy of short circuit detection. To address this, a second switch module 211 is set up, which is equivalent to adding an electrode between the fourth test connection terminal and the scan line. This changes the direct coupling path of the original single parasitic capacitance to a path of two parasitic capacitances connected in series. This weakens the coupling of the voltage jump to the scan line through the voltage divider effect of the capacitor, avoiding large fluctuations in the output voltage of the scan line and ensuring the accuracy of short circuit detection. The same principle applies to the pull-down control line connected to the fifth test connection terminal.

[0040] For example, such as Figure 7As shown, the first node lead 201 is connected to the drain of the output transistor T4 of the even-numbered row scanning drive unit, the second node lead 202 is connected to the drain of the output transistor T4 of the odd-numbered row scanning drive unit, and 208 is a pull-down control line.

[0041] The third test connection terminal is configured to be connected to the device that outputs the control voltage during the test phase, so that all the second switch modules 211 are in the open state; the fourth test connection terminal is configured to be connected to the device that outputs the test voltage during the test phase, or the fifth test connection terminal is configured to be connected to the device that outputs the test voltage during the test phase.

[0042] In one optional embodiment, the display panel substrate includes a plurality of pixel units, and the energy storage unit is one of the pixel units.

[0043] For example, as shown in FIG4(b), the display panel substrate further includes: a display area 400, which includes: a plurality of pixel units, each pixel unit including: a capacitor and a thin film transistor, the gate of the thin film transistor is connected to a scan line, the drain of the thin film transistor is connected to one end of the capacitor, the other end of the capacitor is connected to a common electrode, and the source of the thin film transistor is connected to a data line. When the scan line outputs a scan signal, the thin film transistor is in the open state. At this time, if the data line outputs a data voltage signal, the data line charges the capacitor through the thin film transistor. Therefore, the pixel unit is an energy storage unit.

[0044] For example, existing detection devices can detect whether the electric field value of the capacitor in a pixel unit is normal, in order to detect whether the pixel unit can be charged normally and whether it can be lit. If the detection device detects that the electric field value of the capacitor in the pixel unit is normal, the pixel unit is displayed as bright on the detection device; otherwise, the pixel unit is displayed as dark on the detection device. Figure 3As shown, adjacent scan line pairs are exemplarily Gate2 and Gate3. With the initial voltages of both Gate2 and Gate3 at 0, during the testing phase, a test voltage is applied to Gate2. If there is no short circuit between Gate2 and Gate3, the row of pixel units connected to Gate2 should be in a bright state, and the row of pixel units connected to Gate3 should be in a dark state. If there is a short circuit between Gate2 and Gate3, the voltage of Gate2 is the same as the voltage of Gate3, and this voltage is less than the test voltage. If this voltage does not reach the turn-on voltage of the thin-film transistor of the pixel unit, the capacitor cannot be charged, and the row of pixel units connected to Gate2 and the row of pixel units connected to Gate3 should both be in a dark state. If this voltage reaches the turn-on voltage of the thin-film transistor of the pixel unit, the capacitor can be charged. If the electric field of the capacitor... The electric field value can reach the value that enables the pixel unit to display normally. The row of pixel units connected to Gate2 and the row of pixel units connected to Gate3 should all be in a bright state; otherwise, they should all be in a dark state. In summary, if there is no short circuit between Gate2 and Gate3, the bright and dark states of the row of pixel units connected to Gate2 are inconsistent with the bright and dark states of the pixel units connected to Gate3; otherwise, they are consistent. Therefore, the existing detection equipment can be used to detect whether the bright and dark states of the row of pixel units connected to Gate2 are consistent with the bright and dark states of the pixel units connected to Gate3. If they are consistent, it means that the voltage of Gate2 is consistent with the voltage of Gate3, indicating that there is a short circuit between Gate2 and Gate3. If they are inconsistent, it means that there is no short circuit between Gate2 and Gate3. Similarly, the voltage of Gate3 can also be changed during the testing phase to achieve short circuit detection.

[0045] In an optional embodiment, as shown in FIG8(a), the test circuit further includes: a fourth detection line 206 and a fifth detection line 207; the energy storage unit 212 includes: The third switch module and the first energy storage module are respectively connected. The third switch module corresponds one-to-one with the scan lines. The control terminal of the third switch module corresponding to the j-th scan line is connected to the first detection line 203, and / or the control terminal of the third switch module corresponding to the (j+1)-th scan line is connected to the second detection line. The first end of the third switch module is connected to the fourth detection line 206, the second end of the third switch module is connected to the first end of the first energy storage module, and the second end of the first energy storage module is connected to the fifth detection line 207. For example, as shown in FIG8(a), the third switching module includes: a third thin film transistor T3, the first terminal of the third switching module being the source of the third thin film transistor T3, the second terminal of the third switching module being the drain of the third thin film transistor T3, and the control terminal of the third switching module being the gate of the third thin film transistor T3; the first energy storage module includes: a first capacitor C1.

[0046] The fourth detection line 206 is configured to receive test data voltage during the test phase, and the fifth detection line 207 is configured to receive test common electrode voltage during the test phase, so that the third switch module can charge the corresponding first energy storage module when it is in the open state.

[0047] For example, the third switch module and the first energy storage module are used to simulate the above-mentioned pixel unit. The method of using the third switch module and the first energy storage module to detect whether adjacent row scan line pairs are short-circuited is the same as the method of using the above-mentioned pixel unit to detect whether adjacent row scan line pairs are short-circuited.

[0048] For example, as shown in Figures 8(b) and 8(c), the display panel substrate has a double-sided scanning drive circuit 100. For the double-sided scanning drive circuit 100, as shown in Figure 8(b), an energy storage unit 212 can be configured for each row of scan lines, and a total of N-1 energy storage units 212 can be configured. As shown in Figure 8(b), for the left scanning drive circuit 100, an energy storage unit 212 can be configured for each even-numbered row of scan lines. As shown in Figure 8(c), for the right scanning drive circuit 100, an energy storage unit 212 can be configured for each odd-numbered row of scan lines.

[0049] In an optional embodiment, as shown in Figures 8(b) and 8(c), the display panel substrate further includes: The sixth test connection terminal 23 and the seventh test connection terminal 24 are configured to be connected to the fourth detection line 206 and the seventh test connection terminal 24 are connected to the fifth detection line 207. The sixth test connection terminal 23 is configured to be connected to the device that outputs the test data voltage during the test phase, and the seventh test connection terminal is configured to be connected to the device that outputs the test common electrode voltage during the test phase.

[0050] For example, a sixth test connection terminal 23 and a seventh test connection terminal 24 are provided in the test area 20 to facilitate the application of test data voltage to the third switching module and the application of test common electrode voltage to the first energy storage module from the outside.

[0051] In an optional embodiment, as shown in FIG9(a), the test circuit 200 further includes: Multiple second energy storage modules 213 are provided, each corresponding to one of the scan lines. The first end of the second energy storage module 213 corresponding to the j-th scan line is connected to the first detection line 203. The first end of the second energy storage module 213 corresponding to the (j+1)-th scan line is connected to the second detection line 204. The second end of the second energy storage module 213 corresponding to the j-th scan line is connected to the second end of the second energy storage module 213 corresponding to the (j+1)-th scan line.

[0052] For example, as shown in Figures 9(a) and 9(b), the second energy storage module 213 includes a second capacitor C2.

[0053] For example, as shown in FIG9(a), the adjacent row scan line pairs are Gate2 and Gate3. When the initial voltages of both Gate2 and Gate3 are 0, during the test phase, a test voltage is applied to Gate2. If a short circuit occurs between Gate2 and Gate3, Gate2 charges the second energy storage module 213 connected to Gate2 and Gate3. The second energy storage module 213 fully discharges the energy storage unit connected to Gate3 to ensure that the voltage of Gate2 is consistent with the voltage of Gate3, which helps to detect the short circuit between the voltage of Gate2 and Gate3.

[0054] In one alternative embodiment, the test circuit is located on the side of the scan driving circuit near the edge of the display panel substrate.

[0055] For example, the test circuit is located on the side of the scanning drive circuit near the edge of the display panel substrate, so as to facilitate cutting off the test circuit in subsequent processes.

[0056] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0057] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A display panel substrate, characterized in that, The display panel substrate includes: N rows of scan lines and a scan driving circuit, wherein the scan driving circuit includes N cascaded scan driving units, and the output terminal of the scan driving unit is connected to the corresponding scan line, where N is a positive integer greater than 2; The test circuit is used to change the voltage of one row scan line in an adjacent row scan line pair and detect the relationship between the voltages of the two row scan lines in the adjacent row scan line pair, thereby detecting whether a short circuit occurs in the adjacent row scan line pair. The test circuit also includes: N / 2 first node leads and N / 2-1 second node leads, the first end of the j / 2th first node lead is connected to the output end of the scan driving unit connected to the scan line in the jth row, where j is an even number greater than zero and j is less than N, and the first end of the j / 2th second node lead is connected to the output end of the scan driving unit connected to the scan line in the j+1th row. Multiple energy storage units, each corresponding to a scan line, and each energy storage unit is connected to its corresponding scan line; Wherein, the first node lead of the j / 2th row is configured to apply a test voltage to the scan line of the jth row during the test phase to detect the relationship between the electric field value of the energy storage unit connected to the scan line of the jth row and the electric field value of the energy storage unit connected to the scan line of the (j+1)th row; or, the second node lead of the j / 2th row is configured to apply the test voltage to the scan line of the (j+1)th row during the test phase to detect the relationship between the electric field value of the energy storage unit connected to the scan line of the jth row and the electric field value of the energy storage unit connected to the scan line of the (j+1)th row.

2. The display panel substrate according to claim 1, characterized in that, The test circuit also includes: Multiple first switch modules are provided, each corresponding to a scan line. The first end of the first switch module corresponding to the j-th scan line is connected to the second end of the j / 2-th first node lead-out line, and the first end of the first switch module corresponding to the j+1-th scan line is connected to the second end of the j / 2-th second node lead-out line. The system comprises a first detection line, a second detection line, and a third detection line. The first detection line is connected to the second end of the first switch module corresponding to the j-th scan line. The second detection line is connected to the second end of the first switch module corresponding to the (j+1)-th scan line. The third detection line is connected to the control ends of all the first switch modules. The third detection line is configured to receive a control voltage during the test phase to put all the first switch modules in the open state; the first detection line is configured to receive the test voltage during the test phase to transmit the test voltage to the j-th scan line, or the second detection line is configured to receive the test voltage during the test phase to transmit the test voltage to the (j+1)-th scan line.

3. The display panel substrate according to claim 2, characterized in that, The display panel substrate further includes: The test connection includes a first test connection terminal, a second test connection terminal, and a third test connection terminal. The first test connection terminal is connected to the first detection line, the second test connection terminal is connected to the second detection line, and the third test connection terminal is connected to the third detection line. The third test connection terminal is configured to be connected to the device that outputs the control voltage during the test phase; the first test connection terminal is configured to be connected to the device that outputs the test voltage during the test phase, or the second test connection terminal is configured to be connected to the device that outputs the test voltage during the test phase.

4. The display panel substrate according to claim 2, wherein the display panel substrate comprises: The fourth test connection terminal and the fifth test connection terminal, the scan driving unit further includes: a pull-down control line, the pull-down control line of the j-th scan driving unit is connected to the fourth test connection terminal, and the pull-down control line of the (j+1)-th scan driving unit is connected to the fifth test connection terminal, characterized in that the first detection line is connected to the fourth test connection terminal, the second detection line is connected to the fifth test connection terminal, the display panel substrate further includes: a third test connection terminal, the third test connection terminal is connected to the third detection line, and the test circuit further includes: Multiple second switch modules are provided, each corresponding to a first switch module. The first end of each second switch module is connected to the second end of the corresponding first switch module. The control ends of all second switch modules are connected to the third detection line. Each second switch module corresponds to a scan line. The second end of the second switch module corresponding to the j-th scan line is connected to the first detection line. The second end of the second switch module corresponding to the (j+1)-th scan line is connected to the second detection line. The third test connection terminal is configured to be connected to the device that outputs the control voltage during the test phase, so that all the second switch modules are in the open state; the fourth test connection terminal is configured to be connected to the device that outputs the test voltage during the test phase, or the fifth test connection terminal is configured to be connected to the device that outputs the test voltage during the test phase.

5. The display panel substrate according to claim 4, characterized in that, The display panel substrate includes: a plurality of pixel units, and the energy storage unit is the pixel unit.

6. The display panel substrate according to any one of claims 2 to 4, characterized in that, The test circuit further includes: a fourth detection line and a fifth detection line; the energy storage unit includes: A third switching module and a first energy storage module, wherein the third switching module corresponds one-to-one with each scan line, the control terminal of the third switching module corresponding to the j-th scan line is connected to the first detection line, and / or, the control terminal of the third switching module corresponding to the j+1 scan lines is connected to the second detection line; the first end of the third switching module is connected to the fourth detection line, the second end of the third switching module is connected to the first end of the first energy storage module, and the second end of the first energy storage module is connected to the fifth detection line; The fourth detection line is configured to receive test data voltage during the test phase, and the fifth detection line is configured to receive test common electrode voltage during the test phase, so that the corresponding first energy storage module is charged when the third switch module is in the open state.

7. The display panel substrate according to claim 6, characterized in that, The display panel substrate further includes: The sixth test connection terminal and the seventh test connection terminal are provided. The sixth test connection terminal is connected to the fourth detection line, and the seventh test connection terminal is connected to the fifth detection line. The sixth test connection terminal is configured to be connected to the device that outputs the test data voltage during the test phase, and the seventh test connection terminal is configured to be connected to the device that outputs the test common electrode voltage during the test phase.

8. The display panel substrate according to claim 4, characterized in that, The test circuit also includes: Multiple second energy storage modules are provided, each corresponding to one of the scan lines. The first end of the second energy storage module corresponding to the j-th scan line is connected to the first detection line, the first end of the second energy storage module corresponding to the (j+1)-th scan line is connected to the second detection line, and the second end of the second energy storage module corresponding to the j-th scan line is connected to the second end of the second energy storage module corresponding to the (j+1)-th scan line.

9. The display panel substrate according to claim 3, characterized in that, The test circuit is located on the side of the scan driving circuit near the edge of the display panel substrate.

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