A DCM time-multiplexing controller for dual-input dual-output buck-boost and its output driving circuit

Abstract

The application belongs to the technical field of integrated circuits, and discloses a DCM time-multiplexing controller for a double-input double-output BUCK-BOOST and an output driving circuit thereof, which comprises a working mode selector, a DCM time-multiplexing controller and a driver. The DCM time-multiplexing controller is composed of a peak current detection circuit (PCD), a zero current detection circuit (ZCD), a multiplexer (MUX), a DCM controller and a transmission gate (TG), and can select the current peak signal and the current zero-crossing signal of the corresponding power path under the control of the working mode selector to generate the on-off control signal of the switching MOS tube. The driver is composed of a driving cone and an output driving circuit, can drive the output side switching MOS tube according to the output of the working mode selector and the DCM time-multiplexing controller, and can prevent the leakage caused by the excessive gate-source voltage difference of the P-type switching MOS tube when the two-way output voltage is inconsistent. The DCM time-multiplexing controller and the output driving circuit thereof have the advantages of simple structure, small chip area, low power consumption and high energy transfer efficiency.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a DCM time-division multiplexing controller for dual-input dual-output BUCK-BOOST and its output driving circuit. Background Technology

[0002] Dual-input dual-output BUCK-BOOST topologies are widely used in micro-energy harvesting power management circuits. This topology efficiently harvests energy from two ambient energy harvesters to power the load, while excess energy can be used to charge the battery. When the front-end energy is insufficient, the energy stored in the battery can also contribute to powering the load.

[0003] Because the dual-input dual-output BUCK-BOOST circuit topology has multiple current paths, ordinary control circuits typically design a separate controller for each path. This inevitably increases power consumption in the control section and expands the circuit layout area, resulting in low energy conversion efficiency and increased chip manufacturing costs. Furthermore, due to... V OUT and V BAT The magnitude relationship is uncertain, so a traditional multi-stage inverter is used as the output side. P When driving a channeled MOSFET switch, leakage current may occur to the side with the lower voltage. Summary of the Invention

[0004] To address the first problem mentioned above, this invention proposes a DCM time-division multiplexing controller. This controller simplifies the control logic of multiple current paths into a single logic controller. The front end uses a multiplexer to select the current sampling signal and transmits it to the DCM controller to generate... PWM The signal is then dynamically distributed by the back-end transmission gate to each switching MOSFET driver for switching control.

[0005] To address the second problem mentioned above, this invention proposes an output drive circuit. When the converter outputs energy to one of the outputs, this circuit can apply the larger voltage value from the two outputs to the other output, which should be turned off, to completely shut down that output and prevent the aforementioned leakage problem.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A time-division multiplexing controller (DCM) for dual-input dual-output BUCK-BOOST and its output drive circuit are disclosed, comprising a working mode selector, a DCM time-division multiplexing controller, and a driver. The working mode selector is characterized in that it can sample and determine the over / under voltage conditions of the input and output, and output a working mode enable signal. ModeThe signal is sent to the DCM time-division multiplexing controller and driver. The DCM time-division multiplexing controller can enable the operating mode. Mode Under the action of the signal, the peak current signal and the zero-crossing current signal of the corresponding power path are selected to generate conduction and turn-off signals, and correspondingly seven signals are generated for the control of the dual-input dual-output BUCK-BOOST switching MOSFET. The driver consists of a drive cone and an output drive circuit, which can charge and discharge the gate of the switching MOSFET to control the switching MOSFET's on and off state.

[0008] The DCM time-division multiplexing controller generates seven signals for controlling the switching MOSFETs of the dual-input dual-output BUCK-BOOST circuit. Specifically, the DCM time-division multiplexing controller consists of a peak current detector (PCD), a zero-crossing current detector (ZCD), and a first multiplexer 1. st MUX, Second Multiplexer 2 nd It consists of a MUX, a DCM controller, a transmission gate TG, and a logic OR gate. The peak current detector PCD input signal... C p1 The fourth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 4 The input signal of the peak current detector PCD C p2 The fifth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 5 The output signal of the peak current detector PCD I p1 Connect the first multiplexer 1 st The 0 input terminal of the MUX, and the output signal of the peak current detector PCD. I p2 Connect the first multiplexer 1 st The input signal of the zero-crossing current detector ZCD is at input terminal 1 of the MUX. C z1 The seventh switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 7 The input signal of the zero-crossing current detector ZCD C z2 The third switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 3 The input signal of the zero-crossing current detector ZCD C z3 The sixth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuitS 6 The output signal of the zero-crossing current detector ZCD I z1 Connect the second multiplexer 2 nd The 00 select terminal of the MUX, the output signal of the zero-crossing current detector ZCD I z2 Connect the second multiplexer 2 nd The 10-gating pin of the MUX, the output signal of the zero-crossing current detector ZCD I z3 Connect the second multiplexer 2 nd The MUX's 0 / 1 selector terminal, and the control terminals of the first and second multiplexers are connected to the output operating mode enable. Mode Signal, the first multiplexer 1 st The output of the MUX is connected to the DCM controller. I peak Input terminal, second multiplexer 2 nd The output of the MUX is connected to the DCM controller. I zero The input terminal of the DCM controller ON The output terminal is connected to the D 1 D 4 , D 2 D 4 , D 5 D 7 The input terminal of the transmission gate TG, the DCM controller OFF The output terminal is connected to the D 1 D 7 , D 1 D 6 , D 3 D 7 , D 3 D 6 The input terminal of the transmission gate TG, and the control terminal of the transmission gate TG are connected to the output operating mode enable. Mode The signal, the input of the OR gate is connected to the output of the transmission gate TG, and the output of the OR gate is connected to the input of the driver. D 1 -D 7 .

[0009] The DCM controller processes clock signals, peak current signals, and current zero-crossing signals, generating turn-on and turn-off signals for the switching MOSFETs respectively within a single clock cycle. Specifically, the DCM controller consists of a first D flip-flop 1. st DFF, Second D Flip-Flop 2 nd DFF, First AND Gate 1 st AND, Second AND Gate 2 nd Composed of AND. The first D flip-flop 1 st DFF D When the terminal is connected to a high level, the first D flip-flop 1 st DFF's clock CLK The terminal is connected to an external input clock signal, and the first D flip-flop 1 st DFF reset R Terminal connected to the first multiplexer 1 st The MUX output is the DCM controller. I peak The input terminal, the first D flip-flop 1 st DFF output Q Terminal connected to the first AND gate 1 st The first input terminal of AND, the first D flip-flop 1 st The inverting output of DFF is connected to the second AND gate 2. nd The second input terminal of AND, the second D flip-flop 2 nd DFF D When the terminal is connected to a high level, the second D flip-flop 2 nd DFF's clock CLK The terminal is connected to an external input clock signal, and the second D flip-flop 2 nd DFF reset R Terminal connected to the second multiplexer 2 nd The MUX output is the DCM controller. I zero Input terminal, the second D flip-flop 2 nd DFF output Q Terminal connected to the first AND gate 1 st The second input of AND and the second AND gate 2 nd AND with the first input terminal. The first AND gate 1. st The output of AND is connected to the DCM controller. ON Output terminal, second AND gate 2 nd The output of AND is connected to the DCM controller. OFF Output terminal.

[0010] The driver contains the sixth and seventh switching MOSFETs of the dual-input dual-output BUCK-BOOST circuit. S 6 , S 7 The circuit providing the drive signal consists of a first output drive circuit, a second output drive circuit, and an inverter. The enable terminal of the second output drive circuit... EN B The drive signal of the second output drive circuit is connected to the left output of the inverter. SG 6 The output of the external drive cone is connected, and the power supply signal of the second output drive circuit is connected to the positive terminal of the battery. V BAT and the output V OUT Positive terminal, the output signal of the second output drive circuit SD 6 The sixth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 6 The gate of the first output drive circuit, the enable terminal of the first output drive circuit. EN O The drive signal of the first output drive circuit is connected to the right input of the inverter. SG 7 The output of the external drive cone is connected, and the power supply signal of the first output drive circuit is connected to the positive terminal of the battery. V BAT and the output V OUT Positive terminal, the output signal of the first output drive circuit SD 7 The seventh switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 7 The gate.

[0011] When the front-end input source is directed to V OUT When powered by the terminal, the first output drive circuit is the seventh switching MOSFET. S 7 The gate provides 0 V and V OUT Two voltage levels control the switching on and off of the MOSFET. When the front-end input source... V BAT When powered by the terminal, the seventh switching MOSFET of the first output drive circuit is turned off. S 7 supply V BATand V OUT The higher of the two voltages is used as the gate bias voltage to prevent leakage caused by excessive gate-source voltage difference. Specifically, the first output drive circuit includes a first MOSFET. M 1 Second MOSFET M 2 Third MOSFET M 3 Fourth MOSFET M 4 Fifth MOSFET M 5 The sixth MOSFET M 6 The seventh MOSFET M 7 Eighth MOSFET M 8 Ninth MOSFET M 9 The tenth MOSFET M 10 Eleventh MOSFET M 11 The twelfth MOSFET M 12 The thirteenth MOSFET M 13 Fourteenth MOSFET M 14 The fifteenth MOSFET M 15 The sixteenth MOSFET M 16 The seventeenth MOSFET M 17 NAND gate. The first MOS transistor. M 1a Termination of positive output terminal V OUT The first MOS transistor M 1b Termination of the second MOS transistor M 2a Terminal, fifteenth MOSFET M 15b Terminal and the fourteenth MOSFET M 14 Gate, the first MOS transistor M 1 The gate is connected to the third MOS transistor M 3 Gate, i.e., signal line SG 7 The first MOS transistor M 1Body potential connected to the fourteenth MOS transistor M 14 Body potential, the fifteenth MOS transistor M 15 Body potential, the fifteenth MOS transistor M 15a Terminal and the fourteenth MOS transistor M 14b Terminal, the fourteenth MOS transistor M 14a Terminal connected to the positive output terminal V OUT The second MOS transistor M 2 Gate connection EN D Invert the signal, the second MOSFET M 2b Terminal connection to the third MOSFET M 3 Drain, second MOSFET M 2 Body potential, the fifth MOS transistor M 5b Terminal and the fifth MOS transistor M 5 Body potential, i.e., signal line SD 7 The third MOS transistor M 3 The source and body potentials are grounded, and the fourth MOS transistor M 4a Terminal connected to the positive terminal of the battery V BAT The fourth MOS transistor M 4 Body potential connected to the sixteenth MOS transistor M 16 Body potential, the seventeenth MOS transistor M 17 Body potential, the sixteenth MOS transistor M 16b Terminal and the seventeenth MOS transistor M 17a Terminal, the sixteenth MOS transistor M 16a Terminal connected to the positive terminal of the battery V BAT The fourth MOS transistor M 4b Terminal connected to the fifth MOS transistor M 5a Terminal, the seventeenth MOS transistor M 17b Terminal and the sixteenth MOS transistorM 16 Gate, the fourth MOS transistor M 4 The gate is connected to the output of the NAND gate. EN D Signal, the fifth MOS transistor M 5 Gate connection signal line EN D2 The sixth MOS transistor M 6 The source and body potentials are connected to the positive terminal of the battery. V BAT The sixth MOS transistor M 6 The drain is connected to the seventh MOS transistor. M 7 The drain and the upper input of the NAND gate, the sixth MOS transistor M 6 Gate connection bias voltage V BP The seventh MOS transistor M 7 Body potential and source ground, the seventh MOS transistor M 7 Gate connection enable signal EN O The eighth MOS transistor M 8 Body potential and source electrode connected to the positive electrode of the battery V BAT The eighth MOS transistor M 8 The drain is connected to the lower input of the NAND gate and the ninth MOS transistor. M 9 Drain, the eighth MOS transistor M 8 The gate is connected to the tenth MOS transistor M 10 Gate, the tenth MOS transistor M 10 Drain and the eleventh MOS transistor M 11 Drain, the ninth MOS transistor M 9 The gate is connected to the eleventh MOS transistor. M 11 Gate and the thirteenth MOS transistor M 13 Gate, i.e., signal line V BN The ninth MOS transistor M 9Body potential and source ground, the tenth MOS transistor M 10 The source and body potential are connected to the output positive terminal. V OUT The eleventh MOS transistor M 11 The source and body potentials are grounded, and the twelfth MOS transistor M 12 The source and body potential are connected to the output positive terminal. V OUT The twelfth MOS transistor M 12 Gate connection EN D Invert the signal, the twelfth MOS transistor M 12 The drain is connected to the thirteenth MOS transistor. M 13 Drain, i.e., signal line EN D2 The thirteenth MOS transistor M 13 The source and body potential are grounded.

[0012] When the front-end input source is directed to V BAT When powered by the terminal, the second output drive circuit is the sixth switching MOSFET. S 6 The gate provides 0 V and V BAT Two voltage levels control the switching on and off of the MOSFET. When the front-end input source... V OUT When powered by the terminal, the sixth switching MOSFET of the second output drive circuit is turned off. S 6 supply V BAT and V OUT The higher of the two voltages is used as the gate bias voltage to prevent leakage caused by excessive gate-source voltage difference. Specifically, the second output drive circuit includes a first MOSFET. K 1 Second MOSFET K 2 Third MOSFET K 3 Fourth MOSFET K 4 Fifth MOSFET K 5 The sixth MOSFET K 6 The seventh MOSFET K7 Eighth MOSFET K 8 Ninth MOSFET K 9 The tenth MOSFET K 10 Eleventh MOSFET K 11 The twelfth MOSFET K 12 The thirteenth MOSFET K 13 Fourteenth MOSFET K 14 The fifteenth MOSFET K 15 The sixteenth MOSFET K 16 The seventeenth MOSFET K 17 NAND gate. The first MOS transistor. K 1a Connect to the positive terminal of the battery V BAT The first MOS transistor K 1b Termination of the second MOS transistor K 2a Terminal, fifteenth MOSFET K 15b Terminal and the fourteenth MOSFET M 14 Gate, the first MOS transistor K 1 The gate is connected to the third MOS transistor K 3 Gate, i.e., signal line SG 6 The first MOS transistor K 1 Body potential connected to the fourteenth MOS transistor K 14 Body potential, the fifteenth MOS transistor K 15 Body potential, the fifteenth MOS transistor K 15a Terminal and the fourteenth MOS transistor K 14b Terminal, the fourteenth MOS transistor K 14a Terminal connected to the positive terminal of the battery V BAT The second MOS transistor K 2 Gate connection EN DInvert the signal, the second MOSFET K 2b Terminal connection to the third MOSFET K 3 Drain, second MOSFET K 2 Body potential, the fifth MOS transistor K 5b Terminal and the fifth MOS transistor K 5 Body potential, i.e., signal line SD 6 The third MOS transistor K 3 The source and body potentials are grounded, and the fourth MOS transistor K 4a Terminal connected to the positive output terminal V OUT The fourth MOS transistor K 4 Body potential connected to the sixteenth MOS transistor K 16 Body potential, the seventeenth MOS transistor K 17 Body potential, the sixteenth MOS transistor K 16b Terminal and the seventeenth MOS transistor K 17a Terminal, the fourth MOS transistor K 4b Terminal connected to the fifth MOS transistor K 5a Terminal, the seventeenth MOS transistor K 17b Terminal and the sixteenth MOS transistor K 16 Gate, the fourth MOS transistor K 4 The gate is connected to the output of the NAND gate. EN D Signal, the fifth MOS transistor K 5 Gate connection signal line EN D2 The sixth MOS transistor K 6 The source and body potential are connected to the output positive terminal. V OUT The sixth MOS transistor K 6 The drain is connected to the seventh MOS transistor. K 7 The drain and the upper input of the NAND gate, the sixth MOS transistor K 6Gate connection bias voltage V BP The seventh MOS transistor K 7 Body potential and source ground, the seventh MOS transistor K 7 Gate connection enable signal EN B The eighth MOS transistor K 8 Body potential and source connection output positive terminal V OUT The eighth MOS transistor K 8 The drain is connected to the lower input of the NAND gate and the ninth MOS transistor. K 9 Drain, the eighth MOS transistor K 8 The gate is connected to the tenth MOS transistor K 10 Gate, the tenth MOS transistor K 10 Drain and the eleventh MOS transistor K 11 Drain, the ninth MOS transistor K 9 The gate is connected to the eleventh MOS transistor. K 11 Gate and the thirteenth MOS transistor K 13 Gate, i.e., signal line V BN The ninth MOS transistor K 9 Body potential and source ground, the tenth MOS transistor K 10 The source and body potential are connected to the positive terminal of the battery. V BAT The eleventh MOS transistor K 11 The source and body potentials are grounded, and the twelfth MOS transistor K 12 The source and body potential are connected to the positive terminal of the battery. V BAT The twelfth MOS transistor K 12 Gate connection EN D Invert the signal, the twelfth MOS transistor K 12 The drain is connected to the thirteenth MOS transistor. K 13 Drain, i.e., signal line END2 The thirteenth MOS transistor K 13 The source and body potential are grounded.

[0013] The dual-input dual-output BUCK-BOOST converter has two input paths and two output paths. When the first input voltage is higher than the set maximum power point voltage (overvoltage) and the second input voltage is lower than the set maximum power point voltage (undervoltage), the first input voltage is prioritized for energy acquisition; otherwise, the second input voltage is prioritized. When both input voltages are higher than the set maximum power point voltage, within one switching cycle... T on and T off During this period, energy is collected from two sources. When both input voltages are lower than the set maximum power point voltage and the energy storage end... V BAT When there is no undervoltage, energy comes from V BAT Transferred to V OUT Regarding the output terminal, in terms of output voltage... V OUT When the voltage is below the preset value (undervoltage), energy is preferentially transferred to V OUT ,exist V OUT Once the energy reaches the preset value (overvoltage), the excess energy is transferred to the energy storage terminal. V BAT .

[0014] Compared with existing technologies, the advantages of this invention are as follows: This invention proposes a DCM time-division multiplexing controller and its output drive circuit for dual-input dual-output BUCK-BOOST circuits. Under the control of a mode enable signal, the DCM time-division multiplexing controller selects one of three current zero-crossing signals and one of two peak current signals, and combines this with clock signal processing to obtain the on and off signals of the corresponding mode's upper and lower transistors. This control architecture adopts a time-division multiplexing approach, simplifying current path control in multiple modes into a single multiplexed controller combined with a front-end multiplexer and a back-end transmission gate design. This saves circuit layout area, reduces control power consumption, thereby significantly reducing chip manufacturing costs and improving the efficiency of the energy harvesting circuit. The output drive circuit can detect and compare the higher of the two output voltages, then drive the switching MOSFET that should transmit energy, while providing a reliable gate potential bias for the one that should be turned off to avoid leakage problems, thus preventing a decrease in energy conversion efficiency. Attached Figure Description

[0015] Figure 1This invention discloses an overall block diagram of a DCM time-division multiplexing controller for dual-input dual-output BUCK-BOOST and its output drive circuit, including a power stage and a control stage;

[0016] Figure 2 This is a circuit block diagram of the DCM time-division multiplexing controller described in this invention;

[0017] Figure 3 This is a block diagram of the dual-input dual-output BUCK-BOOST output driver circuit described in this invention;

[0018] Figure 4 This is the first output driving circuit of the present invention;

[0019] Figure 5 This is the second output driving circuit of the present invention;

[0020] Figure 6 This is the logical truth table for the multiplexer and the transmission gate described in this invention. Detailed Implementation

[0021] like Figure 1 As shown, a DCM time-division multiplexing controller for dual-input dual-output BUCK-BOOST and its output drive circuit are disclosed, comprising a working mode selector, a DCM time-division multiplexing controller, and a driver. The working mode selector is characterized in that it can sample and determine the over / under voltage conditions of the input and output, and output a working mode enable signal. Mode The signals are sent to the DCM time-division multiplexing controller and driver. The DCM time-division multiplexing controller, under the control of the operating mode selector, can select the current peak signal and current zero-crossing signal corresponding to the power path, generating turn-on and turn-off signals, and correspondingly generating seven signals for the control of the dual-input dual-output BUCK-BOOST switching MOSFET. The driver consists of a drive cone and its output drive circuit, capable of charging and discharging the gate of the switching MOSFET to control its on / off state.

[0022] like Figure 2 As shown, the DCM time-division multiplexing controller generates seven signals for controlling the switching MOSFETs of the dual-input dual-output BUCK-BOOST circuit. Specifically, the DCM time-division multiplexing controller consists of a peak current detector PCD, a zero-crossing current detector ZCD, and a first multiplexer 1. st MUX, Second Multiplexer 2 nd It consists of a MUX, a DCM controller, a transmission gate TG, and a logic OR gate. The peak current detector PCD input signal... C p1 The fourth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S4 The input signal of the peak current detector PCD C p2 The fifth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 5 The output signal of the peak current detector PCD I p1 Connect the first multiplexer 1 st The 0 input terminal of the MUX, and the output signal of the peak current detector PCD. I p2 Connect the first multiplexer 1 st The input signal of the zero-crossing current detector ZCD is at input terminal 1 of the MUX. C z1 The seventh switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 7 The input signal of the zero-crossing current detector ZCD C z2 The third switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 3 The input signal of the zero-crossing current detector ZCD C z3 The sixth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 6 The output signal of the zero-crossing current detector ZCD I z1 Connect the second multiplexer 2 nd The 00 select terminal of the MUX, the output signal of the zero-crossing current detector ZCD I z2 Connect the second multiplexer 2 nd The 10-gating pin of the MUX, the output signal of the zero-crossing current detector ZCD I z3 Connect the second multiplexer 2 nd The MUX's 0 / 1 strobe, the first and second multiplexers 2 nd The control terminal of the MUX is connected to enable the output operating mode. Mode Signal, the first multiplexer 1 st The output of the MUX is connected to the DCM controller. I peak Input terminal, second multiplexer 2 nd The output of the MUX is connected to the DCM controller. I zeroThe input terminal of the DCM controller ON The output terminal is connected to the D 1 D 4 , D 2 D 4 , D 5 D 7 The input terminal of the transmission gate TG, the DCM controller OFF The output terminal is connected to the D 1 D 7 , D 1 D 6 , D 3 D 7 , D 3 D 6 The input terminal of the transmission gate TG, and the control terminal of the transmission gate TG are connected to the output operating mode enable. Mode The signal, the input of the OR gate is connected to the output of the transmission gate TG, and the output of the OR gate is connected to the input of the driver. D 1 - D 7 .

[0023] like Figure 2 As shown, the DCM controller processes clock signals, peak current signals, and current zero-crossing signals, generating turn-on and turn-off signals for the switching MOSFETs respectively within a single clock cycle. Specifically, the DCM controller consists of a first D flip-flop 1. st DFF, Second D Flip-Flop 2 nd DFF, First AND Gate 1 st AND, Second AND Gate 2 nd Composed of AND. The first D flip-flop 1 st DFF D When the terminal is connected to a high level, the first D flip-flop 1 st DFF's clock CLK The terminal is connected to an external input clock signal, and the first D flip-flop 1 st DFF reset R Terminal connected to the first multiplexer 1 st The MUX output is the DCM controller. I peakThe input terminal, the first D flip-flop 1 st DFF output Q Terminal connected to the first AND gate 1 st The first input terminal of AND, the first D flip-flop 1 st The inverting output of DFF is connected to the second AND gate 2. nd The second input terminal of AND, the second D flip-flop 2 nd DFF D When the terminal is connected to a high level, the second D flip-flop 2 nd DFF's clock CLK The terminal is connected to an external input clock signal, and the second D flip-flop 2 nd DFF reset R Terminal connected to the second multiplexer 2 nd The MUX output is the DCM controller. I zero Input terminal, the second D flip-flop 2 nd DFF output Q Terminal connected to the first AND gate 1 st The second input of AND and the second AND gate 2 nd AND with the first input terminal. The first AND gate 1. st The output of AND is connected to the DCM controller. ON Output terminal, second AND gate 2 nd The output of AND is connected to the DCM controller. OFF Output terminal.

[0024] like Figure 3 As shown, the driver contains the sixth and seventh switching MOSFETs of the dual-input dual-output BUCK-BOOST circuit. S 6 , S 7 The circuit providing the drive signal consists of a first output drive circuit, a second output drive circuit, and an inverter. The enable terminal of the second output drive circuit... EN B The drive signal of the second output drive circuit is connected to the left output of the inverter. SG 6 The output of the external drive cone is connected, and the power supply signal of the second output drive circuit is connected to the positive terminal of the battery. V BAT and the output V OUT Positive terminal, the output signal of the second output drive circuit SD 6 The sixth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S6 The gate of the first output drive circuit, the enable terminal of the first output drive circuit. EN O The drive signal of the first output drive circuit is connected to the right input of the inverter. SG 7 The output of the external drive cone is connected, and the power supply signal of the first output drive circuit is connected to the positive terminal of the battery. V BAT and the output V OUT Positive terminal, the output signal of the first output drive circuit SD 7 The seventh switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 7 The gate.

[0025] like Figure 4 As shown, the current input source is directed to... V OUT When powered by the terminal, the first output drive circuit is the seventh switching MOSFET. S 7 The gate provides 0 V and V OUT Two voltage levels control the switching on and off of the MOSFET. When the front-end input source... V BAT When powered by the terminal, the seventh switching MOSFET of the first output drive circuit is turned off. S 7 supply V BAT and V OUT The higher of the two voltages is used as the gate bias voltage to prevent leakage caused by excessive gate-source voltage difference. Specifically, the first output drive circuit includes a first MOSFET. M 1 Second MOSFET M 2 Third MOSFET M 3 Fourth MOSFET M 4 Fifth MOSFET M 5 The sixth MOSFET M 6 The seventh MOSFET M 7 Eighth MOSFET M 8 Ninth MOSFET M 9 The tenth MOSFET M10 Eleventh MOSFET M 11 The twelfth MOSFET M 12 The thirteenth MOSFET M 13 Fourteenth MOSFET M 14 The fifteenth MOSFET M 15 The sixteenth MOSFET M 16 The seventeenth MOSFET M 17 NAND gate. The first MOS transistor. M 1a Termination of positive output terminal V OUT The first MOS transistor M 1b Termination of the second MOS transistor M 2a Terminal, fifteenth MOSFET M 15b Terminal and the fourteenth MOSFET M 14 Gate, the first MOS transistor M 1 The gate is connected to the third MOS transistor M 3 Gate, i.e., signal line SG 7 The first MOS transistor M 1 Body potential connected to the fourteenth MOS transistor M 14 Body potential, the fifteenth MOS transistor M 15 Body potential, the fifteenth MOS transistor M 15a Terminal and the fourteenth MOS transistor M 14b Terminal, the fourteenth MOS transistor M 14a Terminal connected to the positive output terminal V OUT The second MOS transistor M 2 Gate connection EN D Invert the signal, the second MOSFET M 2b Terminal connection to the third MOSFET M 3 Drain, second MOSFET M2 Body potential, the fifth MOS transistor M 5b Terminal and the fifth MOS transistor M 5 Body potential, i.e., signal line SD 7 The third MOS transistor M 3 The source and body potentials are grounded, and the fourth MOS transistor M 4a Terminal connected to the positive terminal of the battery V BAT The fourth MOS transistor M 4 Body potential connected to the sixteenth MOS transistor M 16 Body potential, the seventeenth MOS transistor M 17 Body potential, the sixteenth MOS transistor M 16b Terminal and the seventeenth MOS transistor M 17a Terminal, the sixteenth MOS transistor M 16a Terminal connected to the positive terminal of the battery V BAT The fourth MOS transistor M 4b Terminal connected to the fifth MOS transistor M 5a Terminal, the seventeenth MOS transistor M 17b Terminal and the sixteenth MOS transistor M 16 Gate, the fourth MOS transistor M 4 The gate is connected to the output of the NAND gate. EN D Signal, the fifth MOS transistor M 5 Gate connection signal line EN D2 The sixth MOS transistor M 6 The source and body potentials are connected to the positive terminal of the battery. V BAT The sixth MOS transistor M 6 The drain is connected to the seventh MOS transistor. M 7 The drain and the upper input of the NAND gate, the sixth MOS transistor M 6 Gate connection bias voltage VBP The seventh MOS transistor M 7 Body potential and source ground, the seventh MOS transistor M 7 Gate connection enable signal EN O The eighth MOS transistor M 8 Body potential and source electrode connected to the positive electrode of the battery V BAT The eighth MOS transistor M 8 The drain is connected to the lower input of the NAND gate and the ninth MOS transistor. M 9 Drain, the eighth MOS transistor M 8 The gate is connected to the tenth MOS transistor M 10 Gate, the tenth MOS transistor M 10 Drain and the eleventh MOS transistor M 11 Drain, the ninth MOS transistor M 9 The gate is connected to the eleventh MOS transistor. M 11 Gate and the thirteenth MOS transistor M 13 Gate, i.e., signal line V BN The ninth MOS transistor M 9 Body potential and source ground, the tenth MOS transistor M 10 The source and body potential are connected to the output positive terminal. V OUT The eleventh MOS transistor M 11 The source and body potentials are grounded, and the twelfth MOS transistor M 12 The source and body potential are connected to the output positive terminal. V OUT The twelfth MOS transistor M 12 Gate connection EN D Invert the signal, the twelfth MOS transistor M 12 The drain is connected to the thirteenth MOS transistor. M 13 Drain, i.e., signal line EN D2 The thirteenth MOS transistorM 13 The source and body potential are grounded.

[0026] like Figure 5 As shown, the current input source is directed to... V BAT When powered by the terminal, the second output drive circuit is the sixth switching MOSFET. S 6 Gate provides 0 V and V BAT Two voltage levels control the switching on and off of the MOSFET. When the front-end input source... V OUT When powered by the terminal, the sixth switching MOSFET of the second output drive circuit is turned off. S 6 supply V BAT and V OUT The higher of the two voltages is used as the gate bias voltage to prevent leakage caused by excessive gate-source voltage difference. Specifically, the second output drive circuit includes a first MOSFET. K 1 Second MOSFET K 2 Third MOSFET K 3 Fourth MOSFET K 4 Fifth MOSFET K 5 The sixth MOSFET K 6 The seventh MOSFET K 7 Eighth MOSFET K 8 Ninth MOSFET K 9 The tenth MOSFET K 10 Eleventh MOSFET K 11 The twelfth MOSFET K 12 The thirteenth MOSFET K 13 Fourteenth MOSFET K 14 The fifteenth MOSFET K 15 The sixteenth MOSFET K 16 The seventeenth MOSFET K 17 NAND gate. The first MOS transistor.K 1a Connect to the positive terminal of the battery V BAT The first MOS transistor K 1b Termination of the second MOS transistor K 2a Terminal, fifteenth MOSFET K 15b Terminal and the fourteenth MOSFET M 14 Gate, the first MOS transistor K 1 The gate is connected to the third MOS transistor K 3 Gate, i.e., signal line SG 6 The first MOS transistor K 1 Body potential connected to the fourteenth MOS transistor K 14 Body potential, the fifteenth MOS transistor K 15 Body potential, the fifteenth MOS transistor K 15a Terminal and the fourteenth MOS transistor K 14b Terminal, the fourteenth MOS transistor K 14a Terminal connected to the positive terminal of the battery V BAT The second MOS transistor K 2 Gate connection EN D Invert the signal, the second MOSFET K 2b Terminal connection to the third MOSFET K 3 Drain, second MOSFET K 2 Body potential, the fifth MOS transistor K 5b Terminal and the fifth MOS transistor K 5 Body potential, i.e., signal line SD 6 The third MOS transistor K 3 The source and body potentials are grounded, and the fourth MOS transistor K 4a Terminal connected to the positive output terminal V OUT The fourth MOS transistor K 4Body potential connected to the sixteenth MOS transistor K 16 Body potential, the seventeenth MOS transistor K 17 Body potential, the sixteenth MOS transistor K 16b Terminal and the seventeenth MOS transistor K 17a Terminal, the fourth MOS transistor K 4b Terminal connected to the fifth MOS transistor K 5a Terminal, the seventeenth MOS transistor K 17b Terminal and the sixteenth MOS transistor K 16 Gate, the fourth MOS transistor K 4 The gate is connected to the output of the NAND gate. EN D Signal, the fifth MOS transistor K 5 Gate connection signal line EN D2 The sixth MOS transistor K 6 The source and body potential are connected to the output positive terminal. V OUT The sixth MOS transistor K 6 The drain is connected to the seventh MOS transistor. K 7 The drain and the upper input of the NAND gate, the sixth MOS transistor K 6 Gate connection bias voltage V BP The seventh MOS transistor K 7 Body potential and source ground, the seventh MOS transistor K 7 Gate connection enable signal EN B The eighth MOS transistor K 8 Body potential and source connection output positive terminal V OUT The eighth MOS transistor K 8 The drain is connected to the lower input of the NAND gate and the ninth MOS transistor. K 9 Drain, the eighth MOS transistor K 8 The gate is connected to the tenth MOS transistor K10 Gate, the tenth MOS transistor K 10 Drain and the eleventh MOS transistor K 11 Drain, the ninth MOS transistor K 9 The gate is connected to the eleventh MOS transistor. K 11 Gate and the thirteenth MOS transistor K 13 Gate, i.e., signal line V BN The ninth MOS transistor K 9 Body potential and source ground, the tenth MOS transistor K 10 The source and body potential are connected to the positive terminal of the battery. V BAT The eleventh MOS transistor K 11 The source and body potentials are grounded, and the twelfth MOS transistor K 12 The source and body potential are connected to the positive terminal of the battery. V BAT The twelfth MOS transistor K 12 Gate connection EN D Invert the signal, the twelfth MOS transistor K 12 The drain is connected to the thirteenth MOS transistor. K 13 Drain, i.e., signal line EN D2 The thirteenth MOS transistor K 13 The source and body potential are grounded.

[0027] The dual-input dual-output BUCK-BOOST converter has two input paths and two output paths. When the first input voltage is higher than the set maximum power point voltage (overvoltage) and the second input voltage is lower than the set maximum power point voltage (undervoltage), the first input voltage is prioritized for energy acquisition. Conversely, the second input voltage is prioritized for energy acquisition. When both input voltages are higher than the set maximum power point voltage, within one switching cycle... T on and T off During this period, energy is collected from two sources. When both input voltages are lower than the set maximum power point voltage and the energy storage end... V BAT When there is no undervoltage, energy comes from V BATTransferred to V OUT Regarding the output terminal, in terms of output voltage... V OUT When the voltage is below the preset value (undervoltage), energy is preferentially transferred to V OUT ,exist V OUT Once the energy reaches the preset value (overvoltage), the excess energy is transferred to the energy storage terminal. V BAT From the above control logic, we can obtain the following: Figure 6 The logic truth table of the multiplexer and transmission gate shown, i.e., the operating mode enable, is shown below. Mode The signal contains control information.

[0028] In summary, this invention proposes a DCM time-division multiplexing controller and its output drive circuit for dual-input dual-output BUCK-BOOST circuits. Under the control of a mode enable signal, the DCM time-division multiplexing controller selects one of three current zero-crossing signals and one of two peak current signals, and combines this with clock signal processing to obtain the on and off signals for the corresponding mode's upper and lower transistors. This control architecture employs time-division multiplexing technology, simplifying current path control in multiple modes into a single multiplexed controller combined with a front-end multiplexer and a back-end transmission gate design. This saves circuit layout area, reduces control power consumption, and thus significantly reduces chip manufacturing costs and improves the efficiency of the energy harvesting circuit. The output drive circuit can detect and compare the higher of the two output voltages, then drive the switching MOSFET that should transmit energy, while providing a reliable gate potential bias for the transistor that should be turned off to avoid leakage current problems, thereby preventing a decrease in energy conversion efficiency.

[0029] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. It will be apparent to those skilled in the art that various modifications can be made to the above embodiments, and the general principles described herein can be applied to other embodiments without inventive effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A time-division multiplexing controller (DCM) for dual-input dual-output BUCK-BOOST and its output drive circuit, characterized in that, Includes a working mode selector, a DCM time-division multiplexing controller, and a driver; The DCM time-division multiplexing controller consists of a peak current detector PCD, a zero-crossing current detector ZCD, and a first multiplexer 1. st MUX, Second Multiplexer 2 nd Composed of a MUX, DCM controller, transmission gate TG, and logic OR gate; the peak current detector PCD input signal C p1 The fourth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 4 The input signal of the peak current detector PCD C p2 The fifth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 5 The output signal of the peak current detector PCD I p1 Connect the first multiplexer 1 st The 0 input terminal of the MUX, and the output signal of the peak current detector PCD. I p2 Connect the first multiplexer 1 st The input signal of the zero-crossing current detector ZCD is at input terminal 1 of the MUX. C z1 The seventh switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 7 The input signal of the zero-crossing current detector ZCD C z2 The third switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 3 The input signal of the zero-crossing current detector ZCD C z3 The sixth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 6 The output signal of the zero-crossing current detector ZCD I z1 Connect the second multiplexer 2 nd The 00 select terminal of the MUX, the output signal of the zero-crossing current detector ZCD I z2 Connect the second multiplexer 2 nd The 10-gating pin of the MUX, the output signal of the zero-crossing current detector ZCD I z3 Connect the second multiplexer 2 nd The MUX's 0 / 1 selector terminal, and the control terminals of the first and second multiplexers are connected to the output of the operating mode selector. Mode Signal, the first multiplexer 1 st The output of the MUX is connected to the DCM controller. I peak Input terminal, second multiplexer 2 nd The output of the MUX is connected to the DCM controller. I zero The input terminal of the DCM controller ON The output terminal is connected to the D 1 D 4 , D 2 D 4 , D 5 D 7 The input terminal of the transmission gate TG, the DCM controller OFF The output terminal is connected to the D 1 D 7 , D 1 D 6 , D 3 D 7 , D 3 D 6 The input terminal of the transmission gate TG is connected to the control terminal of the operating mode selector. Mode The signal, the input of the OR gate is connected to the output of the transmission gate TG, and the output of the OR gate is connected to the input of the driver. D 1 - D 7 ; The driver contains the sixth and seventh switching MOSFETs of the dual-input dual-output BUCK-BOOST circuit. S 6 , S 7 The circuit providing the drive signal consists of a first output drive circuit, a second output drive circuit, and an inverter; the enable terminal of the second output drive circuit... EN B Operating mode enable of the inverter's left output and the operating mode selector Mode Signal, the drive signal of the second output drive circuit SG 6 The output of the external drive cone is connected, and the power supply signal of the second output drive circuit is connected to the positive terminal of the battery. V BAT and the output V OUT Positive terminal, the output signal of the second output drive circuit SD 6 The sixth switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 6 The gate of the first output drive circuit, the enable terminal of the first output drive circuit. EN O Operating mode enable that connects the right input of the inverter and the operating mode selector Mode Signal, the drive signal of the first output drive circuit SG 7 The output of the external drive cone is connected, and the power supply signal of the first output drive circuit is connected to the positive terminal of the battery. V BAT and the output V OUT Positive terminal, the output signal of the first output drive circuit SD 7 The seventh switching MOSFET connected to the dual-input dual-output BUCK-BOOST circuit S 7 The gate.

2. The DCM time-division multiplexing controller and its output drive circuit for dual-input dual-output BUCK-BOOST as described in claim 1, characterized in that: The DCM controller is composed of a first D flip-flop 1 st DFF, Second D Flip-Flop 2 nd DFF, First AND Gate 1 st AND, Second AND Gate 2 nd AND composition; the first D flip-flop 1 st DFF D When the terminal is connected to a high level, the first D flip-flop 1 st DFF's clock CLK The terminal is connected to an external input clock signal, and the first D flip-flop 1 st DFF reset R Terminal connected to the first multiplexer 1 st The MUX output is the DCM controller. I peak The input terminal, the first D flip-flop 1 st DFF output Q Terminal connected to the first AND gate 1 st The first input terminal of AND, the first D flip-flop 1 st The inverting output of DFF is connected to the second AND gate 2. nd The second input terminal of AND, the second D flip-flop 2 nd DFF D When the terminal is connected to a high level, the second D flip-flop 2 nd DFF's clock CLK The terminal is connected to an external input clock signal, and the second D flip-flop 2 nd DFF reset R Terminal connected to the second multiplexer 2 nd The MUX output is the DCM controller. I zero Input terminal, the second D flip-flop 2 nd DFF output Q Terminal connected to the first AND gate 1 st The second input of AND and the second AND gate 2 nd AND first input terminal, first AND gate 1 st The output of AND is connected to the DCM controller. ON Output terminal, second AND gate 2 nd The output of AND is connected to the DCM controller. OFF Output terminal.

3. The DCM time-division multiplexing controller and its output drive circuit for dual-input dual-output BUCK-BOOST as described in claim 1, characterized in that: The first output drive circuit includes a first MOSFET. M 1 Second MOSFET M 2 Third MOSFET M 3 Fourth MOSFET M 4 Fifth MOSFET M 5 The sixth MOSFET M 6 The seventh MOSFET M 7 Eighth MOSFET M 8 Ninth MOSFET M 9 The tenth MOSFET M 10 Eleventh MOSFET M 11 The twelfth MOSFET M 12 The thirteenth MOSFET M 13 Fourteenth MOSFET M 14 The fifteenth MOSFET M 15 The sixteenth MOSFET M 16 The seventeenth MOSFET M 17 NAND gate; the first MOS transistor M 1a Termination of positive output terminal V OUT The first MOS transistor M 1b Termination of the second MOS transistor M 2a Terminal, fifteenth MOSFET M 15b Terminal and the fourteenth MOSFET M 14 Gate, the first MOS transistor M 1 The gate is connected to the third MOS transistor M 3 Gate, i.e., signal line SG 7 The first MOS transistor M 1 Body potential connected to the fourteenth MOS transistor M 14 Body potential, the fifteenth MOS transistor M 15 Body potential, the fifteenth MOS transistor M 15a Terminal and the fourteenth MOS transistor M 14b Terminal, the fourteenth MOS transistor M 14a Terminal connected to the positive output terminal V OUT The second MOS transistor M 2 Gate connection EN D Invert the signal, the second MOSFET M 2b Terminal connection to the third MOSFET M 3 Drain, second MOSFET M 2 Body potential, the fifth MOS transistor M 5b Terminal and the fifth MOS transistor M 5 Body potential, i.e., signal line SD 7 The third MOS transistor M 3 The source and body potentials are grounded, and the fourth MOS transistor M 4a Terminal connected to the positive terminal of the battery V BAT The fourth MOS transistor M 4 Body potential connected to the sixteenth MOS transistor M 16 Body potential, the seventeenth MOS transistor M 17 Body potential, the sixteenth MOS transistor M 16b Terminal and the seventeenth MOS transistor M 17a Terminal, the sixteenth MOS transistor M 16a Terminal connected to the positive terminal of the battery V BAT The fourth MOS transistor M 4b Terminal connected to the fifth MOS transistor M 5a Terminal, the seventeenth MOS transistor M 17b Terminal and the sixteenth MOS transistor M 16 Gate, the fourth MOS transistor M 4 The gate is connected to the output of the NAND gate. EN D Signal, the fifth MOS transistor M 5 Gate connection signal line EN D2 The sixth MOS transistor M 6 The source and body potentials are connected to the positive terminal of the battery. V BAT The sixth MOS transistor M 6 The drain is connected to the seventh MOS transistor. M 7 The drain and the upper input of the NAND gate, the sixth MOS transistor M 6 Gate connection bias voltage V BP The seventh MOS transistor M 7 Body potential and source ground, the seventh MOS transistor M 7 Gate connection enable signal EN O The eighth MOS transistor M 8 Body potential and source electrode connected to the positive electrode of the battery V BAT The eighth MOS transistor M 8 The drain is connected to the lower input of the NAND gate and the ninth MOS transistor. M 9 Drain, the eighth MOS transistor M 8 The gate is connected to the tenth MOS transistor M 10 Gate, the tenth MOS transistor M 10 Drain and the eleventh MOS transistor M 11 Drain, the ninth MOS transistor M 9 The gate is connected to the eleventh MOS transistor M 11 Gate and the thirteenth MOS transistor M 13 Gate, i.e., signal line V BN The ninth MOS transistor M 9 Body potential and source ground, the tenth MOS transistor M 10 The source and body potential are connected to the output positive terminal. V OUT The eleventh MOS transistor M 11 The source and body potentials are grounded, and the twelfth MOS transistor M 12 The source and body potential are connected to the output positive terminal. V OUT The twelfth MOS transistor M 12 Gate connection EN D Invert the signal, the twelfth MOS transistor M 12 The drain is connected to the thirteenth MOS transistor. M 13 Drain, i.e., signal line EN D2 The thirteenth MOS transistor M 13 The source and body potential are grounded; The second output drive circuit includes a first MOSFET. K 1 Second MOSFET K 2 Third MOSFET K 3 Fourth MOSFET K 4 Fifth MOSFET K 5 The sixth MOSFET K 6 The seventh MOSFET K 7 Eighth MOSFET K 8 Ninth MOSFET K 9 The tenth MOSFET K 10 Eleventh MOSFET K 11 The twelfth MOSFET K 12 The thirteenth MOSFET K 13 Fourteenth MOSFET K 14 The fifteenth MOSFET K 15 The sixteenth MOSFET K 16 The seventeenth MOSFET K 17 NAND gate; the first MOS transistor K 1a Connect to the positive terminal of the battery V BAT The first MOS transistor K 1b Termination of the second MOS transistor K 2a Terminal, fifteenth MOSFET K 15b Terminal and the fourteenth MOSFET M 14 Gate, the first MOS transistor K 1 The gate is connected to the third MOS transistor K 3 Gate, i.e., signal line SG 6 The first MOS transistor K 1 Body potential connected to the fourteenth MOS transistor K 14 Body potential, the fifteenth MOS transistor K 15 Body potential, the fifteenth MOS transistor K 15a Terminal and the fourteenth MOS transistor K 14b Terminal, the fourteenth MOS transistor K 14a Terminal connected to the positive terminal of the battery V BAT The second MOS transistor K 2 Gate connection EN D Invert the signal, the second MOSFET K 2b Terminal connection to the third MOSFET K 3 Drain, second MOSFET K 2 Body potential, the fifth MOS transistor K 5b Terminal and the fifth MOS transistor K 5 Body potential, i.e., signal line SD 6 The third MOS transistor K 3 The source and body potentials are grounded, and the fourth MOS transistor K 4a Terminal connected to the positive output terminal V OUT The fourth MOS transistor K 4 Body potential connected to the sixteenth MOS transistor K 16 Body potential, the seventeenth MOS transistor K 17 Body potential, the sixteenth MOS transistor K 16b Terminal and the seventeenth MOS transistor K 17a Terminal, the fourth MOS transistor K 4b Terminal connected to the fifth MOS transistor K 5a Terminal, the seventeenth MOS transistor K 17b Terminal and the sixteenth MOS transistor K 16 Gate, the fourth MOS transistor K 4 The gate is connected to the output of the NAND gate. EN D Signal, the fifth MOS transistor K 5 Gate connection signal line EN D2 The sixth MOS transistor K 6 The source and body potential are connected to the output positive terminal. V OUT The sixth MOS transistor K 6 The drain is connected to the seventh MOS transistor. K 7 The drain and the upper input of the NAND gate, the sixth MOS transistor K 6 Gate connection bias voltage V BP The seventh MOS transistor K 7 Body potential and source ground, the seventh MOS transistor K 7 Gate connection enable signal EN B The eighth MOS transistor K 8 Body potential and source connection output positive terminal V OUT The eighth MOS transistor K 8 The drain is connected to the lower input of the NAND gate and the ninth MOS transistor. K 9 Drain, the eighth MOS transistor K 8 The gate is connected to the tenth MOS transistor K 10 Gate, the tenth MOS transistor K 10 Drain and the eleventh MOS transistor K 11 Drain, the ninth MOS transistor K 9 The gate is connected to the eleventh MOS transistor K 11 Gate and the thirteenth MOS transistor K 13 Gate, i.e., signal line V BN The ninth MOS transistor K 9 Body potential and source ground, the tenth MOS transistor K 10 The source and body potential are connected to the positive terminal of the battery. V BAT The eleventh MOS transistor K 11 The source and body potentials are grounded, and the twelfth MOS transistor K 12 The source and body potential are connected to the positive terminal of the battery. V BAT The twelfth MOS transistor K 12 Gate connection EN D Invert the signal, the twelfth MOS transistor K 12 The drain is connected to the thirteenth MOS transistor. K 13 Drain, i.e., signal line EN D2 The thirteenth MOS transistor K 13 The source and body potential are grounded.

4. The DCM time-division multiplexing controller and its output drive circuit for dual-input dual-output BUCK-BOOST as described in claim 1, characterized in that, The operating mode selector samples and judges the system state according to the following logic: The dual-input dual-output BUCK-BOOST converter has two input paths and two output paths. When the first input voltage is higher than the set maximum power point voltage (overvoltage) and the second input voltage is lower than the set maximum power point voltage (undervoltage), the first input voltage is sampled first; otherwise, the second input voltage is sampled first. When both input voltages are higher than the set maximum power point voltage, within one switching cycle... T on and T off During this period, two energy sources are collected separately; when both input voltages are lower than the set maximum power point voltage and the energy storage end... V BAT When there is no undervoltage, energy comes from V BAT Transferred to V OUT For the output terminal, in terms of output voltage V OUT When the voltage is below the preset value (undervoltage), energy is preferentially transferred to V OUT ,exist V OUT Once the energy reaches the preset value (overvoltage), the excess energy is transferred to the energy storage terminal. V BAT .

Images