Low-dropout linear voltage regulator and chip

Abstract

The application relates to a low-dropout linear voltage regulator and a chip. The low-dropout linear voltage regulator comprises a voltage stabilizing main circuit and a plurality of voltage stabilizing branch circuits, the voltage stabilizing main circuit is connected with the control end of each voltage stabilizing branch circuit, the input end of each voltage stabilizing branch circuit is connected with a power supply, the output end of each voltage stabilizing branch circuit is respectively connected with a corresponding load in a phase-locked loop, and the voltage stabilizing main circuit is connected with the power supply; the voltage stabilizing main circuit is used for outputting a driving signal to each voltage stabilizing branch circuit according to a received reference signal, so as to drive each voltage stabilizing branch circuit to work; each voltage stabilizing branch circuit is used for inhibiting noise in the received power supply signal in a working state, and outputting a target signal to the corresponding load, so as to supply power to the corresponding load; and the voltage stabilizing main circuit is further used for adjusting the voltage of the driving signal according to the voltage of the reference signal and the voltage of the target signal, and outputting the adjusted driving signal to each voltage stabilizing branch circuit. Thus, the occupied area is reduced while realizing separate power supply, and the stability of the power supply is ensured.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a low-dropout linear regulator and chip. Background Technology

[0002] In high-speed clock systems such as PLLs (Phase-Locked Loops), high demands are placed on the power supply stability and driving capability of the power supply module. Currently, a separate power supply approach is commonly used, such as employing multiple isolated LDOs (Low Dropout Linear Regulators) to independently power each module of the PLL. However, this approach occupies a significant amount of space. While some systems utilize multiple constant current sources with very high bias current connected to diodes to achieve separate power supply, this method offers weak isolation between modules and requires large output capacitors, making it unsuitable for on-chip PMUs (Power Management Units). Summary of the Invention

[0003] Therefore, it is necessary to provide a low-dropout linear regulator and chip that can achieve separate power supply and occupy a small area to address the above-mentioned technical problems.

[0004] In a first aspect, this application provides a low-dropout linear regulator applied in a phase-locked loop (PLL). The low-dropout linear regulator includes a main voltage regulator circuit and multiple voltage regulator branches. The main voltage regulator circuit is connected to the control terminal of each voltage regulator branch. The input terminal of each voltage regulator branch is connected to a power supply, and the output terminal of each voltage regulator branch is connected to a corresponding load in the PLL. The main voltage regulator circuit is connected to the power supply. The main voltage regulator circuit is used to output a drive signal to each voltage regulator branch based on a received reference signal to drive each voltage regulator branch to operate. Each voltage regulator branch is used to suppress noise in the received power supply signal and output a target signal to the corresponding load to supply power to the corresponding load during operation. The main voltage regulator circuit is also used to adjust the voltage of the drive signal based on the voltage of the reference signal and the voltage of the target signal, and output the adjusted drive signal to each voltage regulator branch.

[0005] In an optional implementation, each voltage regulator branch includes a first-stage transistor and a second-stage transistor. The drain of the first-stage transistor is connected to the power supply, the gate is connected to the voltage regulator main circuit, and the source is connected to the drain of the second-stage transistor. The gate of the second-stage transistor is connected to the voltage regulator main circuit, and the source is connected to the load.

[0006] In an optional implementation, each voltage regulator branch further includes a capacitor, one end of which is connected to the source of the second-stage transistor and the other end of which is grounded.

[0007] In an optional embodiment, the main voltage regulator circuit includes a first error amplifier, a second error amplifier, a first transistor, and a second transistor; the power supply terminal of the first error amplifier is connected to a power source, the non-inverting input terminal is used to receive a first reference signal, the inverting input terminal is connected to the source of the first transistor, the output terminal is connected to the gate of the first transistor, and the drain of the first transistor is connected to a power source; the power supply terminal of the second error amplifier is connected to a power source, the non-inverting input terminal is used to receive a second reference signal, the inverting input terminal is connected to the source of the second transistor, the output terminal is connected to the gate of the second transistor, and the drain of the second transistor is connected to the source of the first transistor; the output terminal of the first error amplifier is also connected to the gate of the first-stage transistor in each voltage regulator branch; the output terminal of the second error amplifier is also connected to the gate of the second-stage transistor in each voltage regulator branch.

[0008] In an optional embodiment, the main voltage regulator circuit further includes a charge pump; the input terminal of the charge pump is connected to a power supply, and the output terminal of the charge pump is connected to the power supply terminals of the first error amplifier and the second error amplifier.

[0009] In an optional embodiment, the main voltage regulator circuit further includes a bias circuit and a main transistor, and each voltage regulator branch further includes a slave transistor; the first input terminal of the bias circuit is used to receive a first bias signal, the second input terminal is used to receive a second bias signal, the first output terminal is connected to the bias terminals of the first error amplifier and the second error amplifier, and the second output terminal is connected to the gate of the main transistor and the gate of the slave transistor in each voltage regulator branch; the drain of the main transistor is connected to the source of the second transistor, and the source of the main transistor is grounded; the drain of the slave transistor is connected to the source of the second-stage transistor in the corresponding voltage regulator branch, and the source of the slave transistor is grounded.

[0010] In an optional embodiment, the load of the phase-locked loop includes a front buffer, a delay unit, a digital control circuit, an output comparator, and a rear buffer, and the plurality of voltage regulation branches are four voltage regulation branches; the source of the second-stage transistor in the first voltage regulation branch is connected to the power supply terminal of the front buffer and the power supply terminal of the rear buffer; the source of the second-stage transistor in the second voltage regulation branch is connected to the power supply terminal of the digital control circuit; the source of the second-stage transistor in the third voltage regulation branch is connected to the power supply terminal of the output comparator; and the source of the second-stage transistor in the fourth voltage regulation branch is connected to the power supply terminal of the delay unit.

[0011] In an optional implementation, the aspect ratio of the transistors in the fourth voltage regulator branch, the second voltage regulator branch, the first voltage regulator branch, and the third voltage regulator branch decreases sequentially.

[0012] In an optional implementation, the capacitance value in the fourth voltage-stabilizing branch is equal to the capacitance value in the third voltage-stabilizing branch, the capacitance value in the third voltage-stabilizing branch is greater than the capacitance value in the first voltage-stabilizing branch, and the capacitance value in the first voltage-stabilizing branch is greater than the capacitance value in the second voltage-stabilizing branch.

[0013] Secondly, this application also provides a chip, including a phase-locked loop (PLL) and a low-dropout linear regulator as described in any of the foregoing embodiments. The PLL includes a front buffer, a delay unit, a digital control circuit, an output comparator, and a back buffer. The low-dropout linear regulator includes a main voltage regulator circuit and four voltage regulator branches. The main voltage regulator circuit is connected to the control terminal of each voltage regulator branch, and the input terminal of each voltage regulator branch is connected to a power supply. The main voltage regulator circuit is connected to the power supply. The output terminal of the first voltage regulator branch is connected to the power supply terminals of the front buffer and the back buffer. The output terminal of the second voltage regulator branch is connected to the power supply terminal of the digital control circuit. The output terminal of the third voltage regulator branch is connected to the power supply terminal of the output comparator. The output terminal of the fourth voltage regulator branch is connected to the power supply terminal of the delay unit. The delay unit is connected to the front buffer, the digital control circuit, and the output comparator. The output comparator is connected to the back buffer.

[0014] The low-dropout linear regulator and chip provided in this application include a main voltage regulator circuit and multiple voltage regulator branches. The main voltage regulator circuit is connected to the control terminal of each voltage regulator branch. The input terminal of each voltage regulator branch is connected to a power supply, and the output terminal of each voltage regulator branch is connected to the corresponding load in a phase-locked loop. The main voltage regulator circuit is connected to the power supply. The main voltage regulator circuit outputs a drive signal to each voltage regulator branch based on a received reference signal to drive each voltage regulator branch to operate. Each voltage regulator branch, in operation, suppresses noise in the received power supply signal and outputs a target signal to the corresponding load to supply power to the corresponding load. The main voltage regulator circuit also adjusts the voltage of the drive signal based on the voltage of the reference signal and the voltage of the target signal, and outputs the adjusted drive signal to each voltage regulator branch. This achieves separate power supply while reducing the footprint and ensuring power supply stability.

[0015] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This paper shows one of the structural schematic diagrams of a low-dropout linear regulator provided in an embodiment of this application;

[0018] Figure 2 This is a second schematic diagram of the low-dropout linear regulator provided in an embodiment of this application;

[0019] Figure 3 The third schematic diagram of the low dropout linear regulator provided in this application embodiment is shown.

[0020] Figure 4 The fourth schematic diagram of the low dropout linear regulator provided in this application embodiment is shown.

[0021] Figure 5 The fifth schematic diagram shows the structure of the low-dropout linear regulator provided in the embodiments of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0024] Please see Figure 1This is a schematic diagram of a low-dropout linear regulator provided in an embodiment of this application. This low-dropout linear regulator is applied to a phase-locked loop (PLL) and includes a main voltage regulator circuit and multiple voltage regulator branches, such as K voltage regulator branches, where K is a positive integer greater than 1. The main voltage regulator circuit is connected to the control terminal of each voltage regulator branch, the input terminal of each voltage regulator branch is connected to a power supply, and the output terminal of each voltage regulator branch is connected to the corresponding load in the PLL. The main voltage regulator circuit is also connected to the power supply. It can be understood that the total number of loads F is equal to or greater than the total number of voltage regulator branches K.

[0025] The main voltage regulator circuit is used to output a drive signal to each voltage regulator branch based on the received reference signal, so as to drive each voltage regulator branch to work; each voltage regulator branch is used to suppress noise in the received power supply signal and output a target signal to the corresponding load in the working state, so as to supply power to the corresponding load; the main voltage regulator circuit is also used to adjust the voltage of the drive signal according to the voltage of the reference signal and the voltage of the target signal, and output the adjusted drive signal to each voltage regulator branch.

[0026] In this embodiment, the power supply is provided by a main voltage regulator circuit. Based on a reference signal, the main voltage regulator circuit outputs a drive signal to drive each voltage regulator branch. Each voltage regulator branch, under the influence of the drive signal, filters the received power signal to suppress noise and converts the power signal into a target signal with a preset voltage value, then outputs the target signal to supply power to the corresponding load. This can be understood as the target signal output by each voltage regulator branch having the same voltage and a preset voltage value, which refers to the required supply voltage for the load. Furthermore, the main voltage regulator circuit also adjusts the voltage of the drive signal based on the reference signal voltage to improve the stability of the drive signal, ensuring stable operation of each voltage regulator branch and thus guaranteeing the stability of the power supply to each load.

[0027] In essence, the low-dropout linear regulator in this application uses a main circuit to drive multiple branches to supply power to various loads. This main-branch structure achieves separate power supply, reduces noise interference between modules, and eliminates the need for multiple isolated regulators, thus reducing the footprint. Furthermore, the main circuit adjusts the drive signal based on the output of the branches to ensure the stable operation of the regulated branches, thereby guaranteeing the stability of the power supply.

[0028] Please see Figure 2 This is another structural schematic diagram of the low dropout linear regulator provided in the embodiments of this application. Each voltage regulation branch of the low dropout linear regulator includes a first-stage transistor and a second-stage transistor, and the first-stage transistor and the second-stage transistor can be NMOS transistors (N-channel Metal-Oxide-Semiconductor Field-Effect Transistors).

[0029] It is understandable that the first-stage transistors and second-stage transistors in each voltage regulation branch are connected in the same way. For simplicity, the following explanation uses the k-th voltage regulation branch as an example. In voltage regulation branch k, the drain d of the first-stage transistor Nk is connected to the power supply VDD, the gate g is connected to the main voltage regulation circuit, and the source s is connected to the drain d of the second-stage transistor N2k. The gate g of the second-stage transistor N2k is connected to the main voltage regulation circuit, and the source s is connected to the load, where k = 1, ..., K-1, K.

[0030] In this embodiment, the voltage regulator branch employs a two-stage cascaded NMOS transistor configuration, which progressively suppresses power ripple and improves the PSR (Power Supply Rejection) of the low-dropout linear regulator, ensuring the stability of the output target signal and thus providing stable power to the load. Furthermore, based on the local oscillator response of the NMOS transistors, it can also respond quickly to transient currents. When the voltage regulator branch experiences a large transient load current, the output voltage of the voltage regulator branch decreases, meaning the source voltage of the second-stage NMOS transistor decreases. This increases the voltage difference between the gate and source of the second-stage NMOS transistor, thereby increasing the current of the second-stage NMOS transistor. This increases the output current of the voltage regulator branch to charge the load, thus pulling back the voltage drop at the output and stabilizing the supply voltage before the next clock transition.

[0031] Please continue reading. Figure 2 The main voltage regulator circuit of the low dropout linear regulator includes a first error amplifier, a second error amplifier, a first transistor, and a second transistor, and the first transistor and the second transistor can be NMOS transistors.

[0032] The first error amplifier EA1 has its power supply terminal connected to power supply VDD, its non-inverting input terminal for receiving a first reference signal, its inverting input terminal connected to the source (s) of the first transistor Q1, and its output terminal connected to the gate (g) of the first transistor Q1. The drain (d) of the first transistor Q1 is connected to power supply VDD. The second error amplifier EA2 has its power supply terminal connected to power supply VDD, its non-inverting input terminal for receiving a second reference signal, its inverting input terminal connected to the source (s) of the second transistor Q2, and its output terminal connected to the gate (g) of the second transistor Q2. The drain (d) of the second transistor Q2 is connected to the source (s) of the first transistor Q1. The output terminal of the first error amplifier EA1 is also connected to the gate (g) of the first-stage transistor in each voltage regulation branch, and the output terminal of the second error amplifier EA2 is also connected to the gate (g) of the second-stage transistor in each voltage regulation branch. The first reference signal can be a voltage signal Vref1, the second reference signal can be a voltage signal Vref1, and the voltage of the first reference signal is greater than the voltage of the second reference signal.

[0033] In this embodiment, the first error amplifier EA1 is used to drive the first-stage transistor in each voltage regulation branch, and the voltage of the drive signal can also be adjusted by the first transistor Q1. The non-inverting input of the first error amplifier EA1 receives the first reference signal Vref1, and outputs the first drive signal to the gate g of the first transistor Q1 and the gate g of the first-stage transistor in each voltage regulation branch to drive each first-stage transistor to work.

[0034] Since the connection relationship between the first transistor Q1 and the second transistor Q2 is the same as the connection method of the first-stage transistor and the second-stage transistor in each voltage regulator branch, the voltage at the source s of the first transistor Q1 is the same as the voltage at the source s of each first-stage transistor. Furthermore, the inverting input of the first error amplifier EA1 is connected to the source s of the first transistor Q1. Therefore, the first error amplifier EA1 can compare the voltage fed back from the source s of the first transistor Q1 with the voltage of the received first reference signal Vref1, and adjust the voltage of its output first drive signal based on the comparison result. This ensures the stability of the first drive signal and guarantees the stable operation of the first-stage transistor in each voltage regulator branch.

[0035] Similar to the first error amplifier EA2, the second error amplifier EA2 is used to drive the second-stage transistor in each voltage regulation branch, and the voltage of the drive signal can also be adjusted by the second transistor Q2. The non-inverting input of the second error amplifier EA2 receives the second reference signal Vref2, and outputs the second drive signal to the gate g of the second transistor Q2 and the gate g of the second-stage transistor in each voltage regulation branch to drive each second-stage transistor.

[0036] Since the connection relationship between the first transistor Q1 and the second transistor Q2 is the same as the connection method of the first-stage transistor and the second-stage transistor in each voltage regulator branch, the voltage at the source s of the second transistor Q2 is the same as the voltage at the source s of each second-stage transistor. Furthermore, the inverting input of the second error amplifier EA2 is connected to the source s of the second transistor Q2. Therefore, the second error amplifier EA2 can compare the voltage fed back from the source s of the second transistor Q2 with the voltage of the received second reference signal Vref2, and adjust the voltage of its output second drive signal based on the comparison result. This ensures the stability of the second drive signal and guarantees the stable operation of the second-stage transistor in each voltage regulator branch.

[0037] It is understandable that the drain voltage of the first-stage transistor is the power supply voltage, and its gate voltage is stable under the action of the first error amplifier EA1 and the first transistor Q1. Therefore, the source voltage of the first-stage transistor is also stable. The drain of the second-stage transistor is connected to the source of the first-stage transistor, so the drain voltage of the second-stage transistor is stable. At the same time, its gate voltage is stable under the action of the second error amplifier EA2 and the second transistor Q2. Therefore, the source voltage of the second-stage transistor is also stable. In this way, the power supply voltage output by the voltage regulator branch to the load is stable, thus ensuring the stability of the power supply.

[0038] Please see Figure 3 This is another structural schematic diagram of the low-dropout linear regulator provided in the embodiments of this application. Each voltage regulation branch of this low-dropout linear regulator also includes a capacitor. For ease of understanding, the k-th voltage regulation branch, i.e., voltage regulation branch k, will continue to be used as an example for explanation. In voltage regulation branch k, one end of capacitor Ck is connected to the source s of the second-stage transistor N2k, and the other end of capacitor Ck is grounded.

[0039] In the embodiments of this application, the capacitor in the voltage regulation branch can improve the voltage regulation of the power supply. Based on the above description, when the transient load current increases or decreases, the capacitor discharges or charges to absorb or provide the current of the voltage regulation branch before the transistor responds, that is, the voltage regulation of the power supply is improved under transient conditions through the charging and discharging characteristics of the capacitor.

[0040] Please continue reading. Figure 3 The main voltage regulation circuit of this low-dropout linear regulator also includes a charge pump CP, which is a boost charge pump. The input terminal of the charge pump CP is connected to the power supply VDD, and the output terminal of the charge pump is connected to the power supply terminals of the first error amplifier EA1 and the second error amplifier EA1.

[0041] Understandably, in some scenarios, the external power supply VDD voltage is 1.8V, while the required power supply voltage for each module in the phase-locked loop is 1.2V. This means the source voltage of the second-stage NMOS transistor is 1.2V, and the NMOS transistor requires a gate-source voltage difference exceeding a threshold voltage to operate. Therefore, if only the 1.8V VDD power supply is used to power the first and second error amplifiers, the output drive voltage will not be sufficient to drive the NMOS transistor.

[0042] Therefore, in this embodiment of the application, a boost charge pump is used to boost the 1.8V power supply VDD voltage to 3.3V to power the first error amplifier and the second error amplifier. This enables the first error amplifier and the second error amplifier to output a sufficiently large drive voltage, that is, to increase the gate voltage of the first stage transistor and the second stage transistor to drive the first stage transistor and the second stage transistor to work.

[0043] Furthermore, based on the power supply voltage VDD being 1.8V, the charge pump output voltage being 3.3V, and the load requiring a power supply voltage of 1.2V, the voltage of the second reference signal Vref2 is set to 1.2V, and the voltage of the first reference signal Vref1 can be set to 1.5V.

[0044] Please see Figure 4 This is another schematic diagram of the low dropout linear regulator provided in the embodiments of this application. The main voltage regulator circuit also includes a bias circuit and a main transistor, and each voltage regulator branch also includes a slave transistor, and the main transistor and each slave transistor can be NMOS transistors.

[0045] The bias circuit has a first input terminal for receiving a first bias signal, a second input terminal for receiving a second bias signal, a first output terminal connected to the bias terminals of the first error amplifier EA1 and the second error amplifier EA2, and a second output terminal connected to the gate g of the main transistor M1 and the gate g of each slave transistor (M2 to MK+1) in each voltage regulation branch. The drain d of the main transistor M1 is connected to the source s of the second transistor Q2, and the source s of the main transistor M1 is grounded. In the voltage regulation branch k, the drain d of the slave transistor Mk+1 is connected to the source s of the second-stage transistor N2k, and the source s of the slave transistor Mk+1 is grounded. The first bias signal can be a current signal Ibias1, and the second bias signal can be a current signal Ibias2.

[0046] In this embodiment of the application, the bias circuit receives the first bias signal Ibias1 through the first input terminal and transmits the first bias signal Ibias1 to the first error amplifier EA1 and the second error amplifier EA2 through the first output terminal, so as to provide static bias current to the first error amplifier EA1 and the second error amplifier EA2, so that the first error amplifier EA1 and the second error amplifier EA2 are in a suitable working state.

[0047] The bias circuit receives the second bias signal Ibias2 through the second input terminal and transmits it to the main transistor M1, slave transistor M2, and slave transistor MK+1 through the second output terminal. Then, the main transistor M1 provides static bias current to the first transistors Q1 and Q2, ensuring they are in a suitable operating state. Furthermore, the slave transistor Mk+1 provides static bias current to the first-stage transistor Mk and the second-stage transistor N2k in the voltage regulation branch k, ensuring that the first-stage and second-stage transistors in each voltage regulation branch are in a suitable operating state.

[0048] This application implements a method that uses a bias module, a master transistor, and a slave transistor to provide corresponding static bias currents to the two error amplifiers and the two-stage transistors in each voltage regulator branch. This allows the operating state of each device in the low-dropout linear regulator to match the load, thereby improving the stability of the power supply.

[0049] Optionally, based on the load in the phase-locked loop including a pre-buffer, a delay unit, a digital control circuit, an output comparator, and a post-buffer, this application also provides another structural schematic diagram of a low-dropout linear regulator. Please refer to [link to relevant documentation]. Figure 5 The low-dropout linear regulator includes a main voltage regulator circuit and four voltage regulator branches.

[0050] In the main voltage regulation circuit, the input terminal of the charge pump CP is connected to the power supply VDD, and the output terminal of the charge pump is connected to the power supply terminals of the first error amplifier EA1 and the second error amplifier EA1.

[0051] The non-inverting input of the first error amplifier EA1 is used to receive the first reference signal, the inverting input is connected to the source s of the first transistor Q1, and the output is connected to the gate g of the first transistor Q1. The drain d of the first transistor Q1 is connected to the power supply VDD. The non-inverting input of the second error amplifier EA2 is used to receive the second reference signal, the inverting input is connected to the source s of the second transistor Q2, and the output is connected to the gate g of the second transistor Q2. The drain d of the second transistor Q2 is connected to the source s of the first transistor Q1.

[0052] The first input terminal of the bias circuit is used to receive the first bias signal, the second input terminal is used to receive the second bias signal, the first output terminal is connected to the bias terminal of the first error amplifier EA1 and the bias terminal of the second error amplifier EA2, and the second output terminal is connected to the gate g of the main transistor M1 and the gate g of the transistors M2 to MK+1 in each voltage regulation branch; the drain d of the main transistor M1 is connected to the source s of the second transistor Q2, and the source s of the main transistor M1 is grounded.

[0053] In the first voltage regulation branch, namely voltage regulation branch 1, the drain (d) of the first-stage transistor N1 is connected to the power supply VDD, the gate (g) is connected to the output of the first error amplifier EA1, and the source (s) is connected to the drain (d) of the second-stage transistor N2. The gate (g) of the second-stage transistor N2 is connected to the output of the second error amplifier EA2, and the source (s) is connected to the power supply terminals of the front buffer and the rear buffer. One end of the first capacitor C1 is connected to the source (s) of the second-stage transistor N2, and the other end is grounded. The drain (d) of transistor M2 is connected to the source (s) of the second-stage transistor N2, and the source (s) of transistor M2 is grounded. The voltage supply VDD_BUF_REST provided by voltage regulation branch 1 to the front and rear buffers is 1.2V.

[0054] In the second voltage regulation branch, namely voltage regulation branch 2, the drain (d) of the first-stage transistor N3 is connected to the power supply VDD, its gate (g) is connected to the output of the first error amplifier EA1, and its source (s) is connected to the drain (d) of the second-stage transistor N4. The gate (g) of the second-stage transistor N4 is connected to the output of the second error amplifier EA2, and its source (s) is connected to the power supply of the digital control circuit. One end of the second capacitor C2 is connected to the source (s) of the second-stage transistor N4, and the other end is grounded. The drain (d) of transistor M3 is connected to the source (s) of the second-stage transistor N5, and the source (s) of transistor M3 is grounded. The voltage regulation branch 2 provides a power supply voltage VDD_DIG of 1.2V to the digital control circuit.

[0055] In the third voltage regulation branch, namely voltage regulation branch 3, the drain (d) of the first-stage transistor N5 is connected to the power supply VDD, its gate (g) is connected to the output terminal of the first error amplifier EA1, and its source (s) is connected to the drain (d) of the second-stage transistor N6. The gate (g) of the second-stage transistor N6 is connected to the output terminal of the second error amplifier EA2, and its source (s) is connected to the power supply terminal of the output comparator. One end of the third capacitor C3 is connected to the source (s) of the second-stage transistor N6, and the other end is grounded. The drain (d) of transistor M4 is connected to the source (s) of the second-stage transistor N6, and the source (s) of transistor M4 is grounded. The power supply voltage VDD_BUF_OUT provided by voltage regulation branch 3 to the output comparator is 1.2V.

[0056] In the fourth voltage regulation branch, namely voltage regulation branch 4, the drain (d) of the first-stage transistor N7 is connected to the power supply VDD, its gate (g) is connected to the output of the first error amplifier EA1, and its source (s) is connected to the drain (d) of the second-stage transistor N8. The gate (g) of the second-stage transistor N8 is connected to the output of the second error amplifier EA2, and its source (s) is connected to the power supply of the delay unit. One end of the fourth capacitor C4 is connected to the source (s) of the second-stage transistor N8, and the other end is grounded. The drain (d) of transistor M5 is connected to the source (s) of the second-stage transistor N8, and the source (s) of transistor M5 is grounded. The voltage regulation branch 3 provides a power supply voltage VDD_DLY of 1.2V to the delay unit.

[0057] Furthermore, in the phase-locked loop, the input terminal of the front buffer is used to receive the first clock signal CLK_IN, the output terminal is connected to the first input terminal of the delay unit, the digital control circuit is connected to the second input terminal of the delay unit, the output terminal of the delay unit is connected to the input terminal of the output comparator, the output terminal of the output comparator is connected to the input terminal of the back buffer, and the output terminal of the back buffer is used to output the second clock signal CLK_OUT.

[0058] Understandably, the transistors in each regulator branch can be biased in the subthreshold region so that the drain current of the NMOS transistor has an exponential relationship with the gate-source voltage. This means that a small change in the gate voltage of the NMOS transistor can cause a large current change, thus achieving low power consumption. Furthermore, compared to the saturation region, the exponential current-voltage relationship of the NMOS transistor can reduce the power supply ripple of the regulator branch output voltage during load switching.

[0059] Furthermore, given the differences in the magnitude of transient pulse currents among the modules in the phase-locked loop (PLL), the width-to-length ratio of the transistors in each voltage regulation branch can be set accordingly. In the PLL, the transient pulse currents of the delay unit, digital controller, pre-buffer, post-buffer, and output comparator are successively smaller. Therefore, the width-to-length ratio of the transistors in voltage regulation branch 4, voltage regulation branch 2, voltage regulation branch 1, and voltage regulation branch 3 can be set to decrease sequentially. For example, the width-to-length ratio of the first-stage transistor N1 : width-to-length ratio of the first-stage transistor N3 : width-to-length ratio of the first-stage transistor N5 : width-to-length ratio of the first-stage transistor N7 = width-to-length ratio of the second-stage transistor N2 : width-to-length ratio of the second-stage transistor N4 : width-to-length ratio of the second-stage transistor N6 : width-to-length ratio of the second-stage transistor N8 = 3.5 : 10 : 3 : 14.

[0060] Furthermore, since the pre- and post-buffers and the digital control circuit can withstand significant voltage undershoot, smaller capacitors can be selected to save area; while the output comparator and delay unit are sensitive to voltage jitter and require larger capacitors. That is, based on the device characteristics of each module in the phase-locked loop, the capacitor values ​​in each voltage regulation branch can be set accordingly. The capacitance value of the fourth capacitor C4 in voltage regulation branch 4 is equal to the capacitance value of the third capacitor C3 in voltage regulation branch 3. The capacitance value of the third capacitor C3 in voltage regulation branch 3 is greater than the capacitance value of the first capacitor C1 in voltage regulation branch 1, and the capacitance value of the first capacitor C1 in voltage regulation branch 1 is greater than the capacitance value of the second capacitor C2 in voltage regulation branch 2. For example, the fourth capacitor C4 and the third capacitor C3 are both 80pF, the first capacitor C1 is 30pF, and the second capacitor C2 is 20pF. By setting appropriate capacitor sizes according to the characteristics of each load, the capacitor area can be reduced, thereby reducing the area occupied by the low-dropout linear regulator.

[0061] Meanwhile, since the pre-buffer, post-buffer, and digital control circuits can withstand significant voltage undershoot, a smaller static bias current can be selected to save power consumption; however, the output comparator and delay unit are sensitive to voltage jitter and require a higher static bias current. Based on the device characteristics of each module in the phase-locked loop, the static bias current of the transistors in each voltage regulation branch can also be set according to a corresponding relationship. For example, taking the static bias currents of the first and second transistors in the main voltage regulation circuit as a reference, the static bias current ratio of the transistors in the main voltage regulation circuit to those in voltage regulation branch 1 is 1:2:2:5:5.

[0062] Optionally, this application embodiment also provides a chip, which includes a phase-locked loop and the low dropout linear regulator provided in the above embodiment. The phase-locked loop includes a front buffer, a delay unit, a digital control circuit, an output comparator, and a back buffer. The low dropout linear regulator includes a main voltage regulator circuit and four voltage regulator branches.

[0063] The main voltage regulator is connected to the control terminal of each voltage regulator branch. The input terminal of each voltage regulator branch is connected to the power supply. The main voltage regulator is connected to the power supply. The output terminal of the first voltage regulator branch is connected to the power supply terminals of the front buffer and the rear buffer. The output terminal of the second voltage regulator branch is connected to the power supply terminal of the digital control circuit. The output terminal of the third voltage regulator branch is connected to the power supply terminal of the output comparator. The output terminal of the fourth voltage regulator branch is connected to the power supply terminal of the delay unit. The delay unit is connected to the front buffer, the digital control circuit, and the output comparator. The output comparator is connected to the rear buffer.

[0064] To better understand the technical effects of this application, an example is also provided in the embodiments of this application. For example, the power supply voltage is 1.8V, the power supply voltage required by each module in the phase-locked loop is 1.2V, the clock frequency of the phase-locked loop is 200MHz, and the period is 5ns. The low dropout linear regulator provided in this application is used to power the phase-locked loop.

[0065] For the front and rear buffers, with a pulse current of 2mA and a pulse width of 1.7ns, the undershoot voltage is 12.7mV, the transient recovery time is 3.4ns, and the PSR is -46.05dB. For the digital control circuit, with a pulse current of 14mA and a pulse width of 0.7ns, the undershoot voltage is 12.7mV, the transient recovery time is 3.4ns, and the PSR is -42.09dB. For the output comparator, with a pulse current of 1.9mA and a pulse width of 1.5ns, the undershoot voltage is 6.4mV, the transient recovery time is 3.3ns, and the PSR is -43.33dB. For the delay unit, with a pulse current of 12.5mA and a pulse width of 1ns, the undershoot voltage is 20.8mV, the transient recovery time is 3.8ns, and the PSR is -41.62dB. The transient recovery time of all four voltage regulation branches is less than the clock period of the phase-locked loop (PLL), i.e., 5 ns, and the undershoot voltage is less than 41 mV. Therefore, the low-dropout linear regulator provided in this embodiment can ensure power supply stability, thereby reducing the overall phase noise of the PLL and improving its synchronization accuracy.

[0066] Furthermore, when using the low-dropout linear regulator provided in this application to power the phase-locked loop, at low frequencies, the PSR of the pre- and post-buffers is -46.83dB, the PSR of the digital control circuit is -46.68dB, the PSR of the output comparator is -46.89dB, and the PSR of the delay unit is -46.76dB. At a frequency of 200MHz, the PSR of the pre- and post-buffers is -46.05dB, the PSR of the digital control circuit is -42.09dB, the PSR of the output comparator is -43.33dB, and the PSR of the delay unit is -41.62dB.

[0067] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0068] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A low-dropout linear regulator, characterized in that, Applied to phase-locked loops, the low-dropout linear regulator includes a main voltage regulator circuit and multiple voltage regulator branches. The main voltage regulator circuit is connected to the control terminal of each voltage regulator branch. The input terminal of each voltage regulator branch is connected to the power supply. The output terminal of each voltage regulator branch is connected to the corresponding load in the phase-locked loop. The main voltage regulator circuit is connected to the power supply. The main voltage regulator circuit is used to output a drive signal to each voltage regulator branch based on the received reference signal, so as to drive each voltage regulator branch to work. Each voltage regulator branch is used to suppress noise in the received power signal during operation and output the target signal to the corresponding load to supply power to the corresponding load. The main voltage regulator circuit is also used to adjust the voltage of the drive signal according to the voltage of the reference signal and the voltage of the target signal, and output the adjusted drive signal to each voltage regulator branch.

2. The low-dropout linear regulator according to claim 1, characterized in that, Each voltage regulator branch includes a first-stage transistor and a second-stage transistor. The drain of the first-stage transistor is connected to the power supply, the gate is connected to the voltage regulator main circuit, and the source is connected to the drain of the second-stage transistor. The gate of the second-stage transistor is connected to the voltage regulator main circuit, and the source is connected to the load.

3. The low-dropout linear regulator according to claim 2, characterized in that, Each voltage regulator branch also includes a capacitor, one end of which is connected to the source of the second-stage transistor, and the other end of which is grounded.

4. The low-dropout linear regulator according to claim 2, characterized in that, The voltage regulation main circuit includes a first error amplifier, a second error amplifier, a first transistor, and a second transistor; The power supply terminal of the first error amplifier is connected to the power supply, the non-inverting input terminal is used to receive the first reference signal, the inverting input terminal is connected to the source of the first transistor, the output terminal is connected to the gate of the first transistor, and the drain of the first transistor is connected to the power supply. The power supply terminal of the second error amplifier is connected to the power supply, the non-inverting input terminal is used to receive the second reference signal, the inverting input terminal is connected to the source of the second transistor, the output terminal is connected to the gate of the second transistor, and the drain of the second transistor is connected to the source of the first transistor. The output of the first error amplifier is also connected to the gate of the first-stage transistor in each voltage regulation branch; The output of the second error amplifier is also connected to the gate of the second-stage transistor in each voltage regulation branch.

5. The low-dropout linear regulator according to claim 4, characterized in that, The voltage stabilizing main circuit also includes a charge pump; The input terminal of the charge pump is connected to a power supply, and the output terminal of the charge pump is connected to the power supply terminals of the first error amplifier and the second error amplifier.

6. The low-dropout linear regulator according to claim 4, characterized in that, The main voltage regulator circuit also includes a bias circuit and a main transistor, and each voltage regulator branch also includes a slave transistor; The first input terminal of the bias circuit is used to receive a first bias signal, the second input terminal is used to receive a second bias signal, the first output terminal is connected to the bias terminal of the first error amplifier and the bias terminal of the second error amplifier, and the second output terminal is connected to the gate of the main transistor and the gate of the slave transistor in each voltage regulation branch. The drain of the main transistor is connected to the source of the second transistor, and the source of the main transistor is grounded. The drain of the slave transistor is connected to the source of the second-stage transistor in the corresponding voltage regulation branch, and the source of the slave transistor is grounded.

7. The low-dropout linear regulator according to any one of claims 3-6, characterized in that, The load of the phase-locked loop includes a front buffer, a delay unit, a digital control circuit, an output comparator, and a rear buffer, and the multiple voltage regulation branches are four voltage regulation branches. The source of the second-stage transistor in the first voltage regulator branch is connected to the power supply terminal of the front buffer and the power supply terminal of the rear buffer. The source of the second-stage transistor in the second voltage regulator branch is connected to the power supply terminal of the digital control circuit. The source of the second-stage transistor in the third voltage regulation branch is connected to the power supply terminal of the output comparator. The source of the second-stage transistor in the fourth voltage regulation branch is connected to the power supply terminal of the delay unit.

8. The low-dropout linear regulator according to claim 7, characterized in that, The width-to-length ratio of the transistors in the fourth voltage regulator branch, the second voltage regulator branch, the first voltage regulator branch, and the third voltage regulator branch decreases sequentially.

9. The low-dropout linear regulator according to claim 7, characterized in that, The capacitance value in the fourth voltage regulator branch is equal to the capacitance value in the third voltage regulator branch, the capacitance value in the third voltage regulator branch is greater than the capacitance value in the first voltage regulator branch, and the capacitance value in the first voltage regulator branch is greater than the capacitance value in the second voltage regulator branch.

10. A chip, characterized in that, The device includes a phase-locked loop and a low-dropout linear regulator as described in any one of claims 1-9. The phase-locked loop includes a front buffer, a delay unit, a digital control circuit, an output comparator, and a rear buffer. The low-dropout linear regulator includes a main voltage regulator circuit and four voltage regulator branches. The main voltage regulator circuit is connected to the control terminal of each voltage regulator branch, and the input terminal of each voltage regulator branch is connected to the power supply. The main voltage regulator circuit is connected to the power supply. The output terminal of the first voltage regulator branch is connected to the power supply terminal of the front buffer and the power supply terminal of the rear buffer. The output terminal of the second voltage regulator branch is connected to the power supply terminal of the digital control circuit. The output terminal of the third voltage regulator branch is connected to the power supply terminal of the output comparator. The output terminal of the fourth voltage regulator branch is connected to the power supply terminal of the delay unit. The delay unit is connected to the front buffer, the digital control circuit, and the output comparator, and the output comparator is connected to the rear buffer.

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