A high-efficiency low overshoot pulsed laser current source control method and system

Abstract

This application discloses a high-efficiency, low-overshoot pulsed laser current source control method and system, relating to semiconductor laser technology. It is applied to a pulsed constant current source comprising a DC-DC buck-boost circuit, a soft-start circuit, a pulse generation circuit, and an FPGA digital control circuit. The DC-DC buck-boost circuit and the FPGA digital control circuit are controlled by the FPGA digital control circuit. The control method includes: the FPGA digital control circuit as the control core, acquiring the current signal from the pulse current output terminal of the pulse generation circuit as a feedback signal; adjusting the gate voltage UGS of the power MOSFET Q6 of the pulse generation circuit and the output voltage VOUT of the DC-DC buck-boost circuit according to the feedback signal; the control method includes four stages: a pre-trigger stage, a fast rise stage, an overshoot suppression stage, and a constant output stage. This application achieves the dual goals of microsecond-level current response and high-efficiency, stable operation through dynamic matching.

Description

Technical Field

[0001] This application relates to the field of semiconductor laser technology, and in particular to a method and system for controlling a high-efficiency, low-overshoot pulsed laser current source. Background Technology

[0002] Semiconductor lasers (LDs), as efficient and compact light sources, have been widely used in communications, medical, and industrial fields since their invention in the 1960s due to their tunable wavelength, high modulation rate, and low power consumption. The performance of pulsed lasers, such as output energy, pulse stability, and lifespan, is largely determined by the performance of their driving source—the pulsed constant current source. An ideal pulsed constant current source needs to simultaneously meet three core performance indicators: high waveform accuracy, fast dynamic response speed, and high efficiency. These indicators are crucial for ensuring the quality of the laser pulse, the repetition rate, and the reliability of the entire system.

[0003] Currently, pulsed constant current source engineering solutions widely used in industrial and scientific research generally suffer from insufficient performance. In the field of low-voltage, high-current pulsed lasers, existing technologies typically struggle to achieve the aforementioned performance indicators simultaneously, with actual measured system energy efficiencies mostly between 50% and 60%, and pulse waveform rise times usually exceeding 20 μs.

[0004] This performance level cannot meet the stringent requirements of high-end applications for laser drive sources. In the design of pulsed constant current sources, there is an inherent and irreconcilable technical contradiction between "high precision," "fast response," and "high efficiency." This technical bottleneck severely restricts the application and development of advanced pulsed laser technology in related fields.

[0005] Current control based on capacitor energy storage is one of the implementation methods of pulsed constant current sources. It is widely used due to its simple structure and high reliability, but it suffers from a core technical contradiction: the incompatibility between "system energy efficiency" and "output waveform quality." The power loss of its core power device (MOSFET) directly determines the overall system efficiency, creating an irreconcilable conflict with output waveform quality. To obtain a high-quality output waveform, the MOSFET needs to operate at a large drain-source voltage UDS, but this results in significant heat loss and low system efficiency. Conversely, to pursue high efficiency, the drain-source voltage UDS needs to be minimized to reduce MOSFET losses, but this leads to distortions in the output waveform, such as slow rise time and overshoot, affecting laser performance. Summary of the Invention

[0006] This application provides a method and system for controlling the current source of a high-efficiency, low-overshoot pulsed laser, achieving the dual goals of dynamic matching to achieve microsecond-level current response and efficient and stable operation.

[0007] This application provides a high-efficiency, low-overshoot pulsed laser current source control method, applied to a pulsed constant current source including a DC-DC buck-boost circuit, a soft-start circuit, a pulse generation circuit, and an FPGA digital control circuit. The DC-DC buck-boost circuit is controlled by the FPGA digital control circuit and connected to the soft-start circuit. The soft-start circuit is connected to the pulse generation circuit, and the pulse generation circuit is connected to the FPGA digital control circuit. The control method includes: The FPGA digital control circuit serves as the control core, and collects the current signal from the pulse current output terminal of the pulse generation circuit as a feedback signal. Based on the feedback signal, adjust the gate voltage UGS of the power MOSFET Q6 in the pulse generation circuit and the output voltage VOUT of the DC-DC buck-boost circuit; The control method comprises four stages: a pre-trigger stage, a rapid rise stage, an overshoot suppression stage, and a constant output stage. During the pre-trigger phase, the gate voltage UGS is increased to a first proportional range of the threshold voltage of the power MOSFET Q6; During the rapid rise phase, a gate voltage U1 higher than the threshold voltage is applied, causing the drain current ID of the power MOSFET Q6 to rise rapidly to the second proportional range of the set value ISET. During the overshoot suppression phase, the gate voltage is reduced to slow down the current rise inertia until the drain current ID reaches the set value ISET. During the constant output phase, the gate voltage UGS is maintained while the drain current ID is stabilized at the set value ISET, and the output voltage VOUT is kept stable.

[0008] This application also proposes a high-efficiency, low-overshoot pulsed laser current source control system, including: A DC-DC step-up / step-down circuit is used to provide an adjustable output voltage; The pulse generation circuit includes a power MOSFET Q6 and a load laser, which are connected to the DC-DC buck-boost circuit and the FPGA digital control circuit. A current sampling circuit, connected to the pulse generation circuit, is used to collect the load current in real time; The FPGA digital control circuit is connected to the DC-DC buck-boost circuit and the pulse generation circuit to execute the control method described above and output the gate drive signal of the power MOSFET Q6 and the control signal of the DC-DC buck-boost circuit.

[0009] This application uses an FPGA as the "control core" and real-time current status as the core feedback basis to synchronously regulate the gate voltage (U_GS) of the power MOSFET and the output voltage of the DC-DC converter. Through dynamic matching, it achieves the dual goals of microsecond-level current response and efficient and stable operation.

[0010] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 The basic circuit topology of the pulse constant current source for the high-efficiency low-overshoot pulsed laser current source control method in this application embodiment is as follows: Figure 2 This is a schematic diagram of the pulse constant current source circuit for the high-efficiency low-overshoot pulsed laser current source control method according to an embodiment of this application; Figure 3 This is a schematic diagram of the FPGA digital control circuit for the high-efficiency low-overshoot pulsed laser current source control method according to an embodiment of this application. Figure 4 This is a waveform illustration of the high-efficiency low-overshoot pulsed laser current source control method according to an embodiment of this application; Figure 5 This is a schematic diagram of the MOSFET operating trajectory of the high-efficiency low-overshoot pulsed laser current source control method according to an embodiment of this application; Figure 6 This is a schematic diagram illustrating the implementation process of the high-efficiency low-overshoot pulsed laser current source control method according to an embodiment of this application. Detailed Implementation

[0012] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0013] This application provides a method for controlling a high-efficiency, low-overshoot pulsed laser current source, applied to a pulsed constant current source including a DC-DC step-up / step-down circuit, a soft-start circuit, a pulse generation circuit, and an FPGA digital control circuit. The basic circuit topology of the pulsed constant current source used in this application is as follows: Figure 1 As shown, this is a DC-DC circuit and a linear current control method circuit based on capacitor energy storage. The overall circuit framework is as follows: Figure 2 As shown, the system includes a DC-DC buck-boost circuit, a soft-start circuit, a pulse generation circuit, and an FPGA digital control circuit. The DC-DC buck-boost circuit is controlled by the FPGA digital control circuit and connected to the soft-start circuit. The soft-start circuit is connected to the pulse generation circuit, which is also connected to the FPGA digital control circuit. The control method includes: Using the FPGA digital control circuit as the control core, the current signal at the pulse current output terminal of the pulse generation circuit is collected as the feedback signal. In a specific example, the current signal at the pulse current output terminal of the pulse generation circuit can be collected through a current sampling circuit.

[0014] Based on the feedback signal, adjust the gate voltage UGS of the power MOSFET Q6 in the pulse generation circuit and the output voltage VOUT of the DC-DC buck-boost circuit.

[0015] The control method comprises four stages: a pre-trigger stage, a rapid rise stage, an overshoot suppression stage, and a constant output stage. During the pre-trigger phase, the gate voltage UGS is increased to a first proportional range of the threshold voltage of the power MOSFET Q6. In some embodiments, the first proportional range is 90%-96% of the threshold voltage of the power MOSFET Q6; during the pre-trigger phase, the MOSFET (power MOSFET Q6) is in a critical conduction state, and the drain-source voltage U_DS decreases slowly. Figure 4 As shown, during the pre-trigger phase (i.e., from point A to point B), the exemplary gate-source voltage (UGS) rises to 0.95Uth (95% of the threshold voltage). At this point, the MOSFET (power MOSFET Q6) is in a critical conduction state, and the drain-source voltage (U_DS) slowly decreases. The pre-trigger mechanism is designed to accelerate the subsequent rise of UGS.

[0016] During the rapid rise phase, a gate voltage U1 higher than the threshold voltage is applied, causing the drain current ID of the power MOSFET Q6 to rapidly rise to a second proportional range of the set value ISET. In some embodiments, during the rapid rise phase, the value of the gate voltage U1 is determined according to the selected MOSFET model and dynamic characteristics; during the rapid rise phase, the drain current ID of the power MOSFET Q6 is rapidly increased to 85%-92% of the set value ISET.

[0017] like Figure 4 As shown, the fast rise phase (i.e., from point C to point D) is initiated by applying a large gate-source voltage U1, causing the MOSFET to turn on rapidly. Consequently, the drain current (ID) quickly rises to 90% of the set current value (ISET), and UDS drops sharply. The selection of U1 depends on the type of MOSFET used; if U1 is continuously applied during this phase, it will cause ID to overshoot. Active overshoot suppression is implemented in this embodiment.

[0018] During the overshoot suppression phase, the gate voltage is reduced to control the MOSFET's on-state, slowing down the current rise inertia until the drain current ID reaches the set value ISET. In practical applications, such as... Figure 4 As shown, as the parasitic capacitance discharges, UGS decreases smoothly, thus mitigating the inertia of current rise, while UDS increases with changes in on-resistance. When ID rises to ISET, the system enters a constant output phase: the gate voltage is adjusted to the voltage value required by ID, achieving a smooth transition and stable maintenance of UGS, ultimately allowing ID to be precisely controlled and stabilized until the end of the pulse period.

[0019] During the constant output phase, the gate voltage UGS is maintained to stabilize the drain current ID at a set value ISET and keep the output voltage VOUT stable. In some embodiments, during the constant output phase, the power MOSFET Q6 is controlled to operate in the linear region. During the constant output phase, UGS is related to the on-resistance and ID. The voltage drop across the load (LD) also varies with ID. This application uses a front-end DC-DC buck-boost converter to achieve adaptive input voltage control. During the initial cycle of system operation, the DC-DC converter adjusts the input voltage (VOUT) through current feedback until ID reaches ISET, after which VOUT remains stable. The design of this application realizes active control of the MOSFET gate-source voltage and adaptive regulation of the input voltage in the pulse generation circuit.

[0020] In some embodiments, during the overshoot suppression phase, a smooth decrease in the gate voltage UGS is achieved by adjusting the output impedance of the gate drive circuit of the FPGA digital control circuit. In embodiments of this application, such as... Figure 3 As shown, the gate drive circuit is implemented through the FPGA digital control circuit. The FPGA digital control circuit is used to control the gate drive voltage of the MOSFET and also to control the output voltage of the DC-DC circuit.

[0021] In some embodiments, the DC-DC buck-boost circuit is a buck-boost converter whose output voltage VOUT is adaptively adjusted based on feedback from the drain current ID.

[0022] The method of this application effectively solves the contradiction between high efficiency and output waveform quality in pulse constant current sources. While achieving high efficiency, it enables the output pulse waveform to have the characteristics of fast rise edge, no overshoot and flat top stability. Ultimately, it can achieve multi-parameter settable pulse output with adjustable current of 10A-50A in 1A steps, pulse width of 150μs-400μs, and repetition frequency of 1Hz-100Hz, and is suitable for various loads.

[0023] This application also proposes an implementation example of a microsecond-level active gate drive and adaptive input voltage control method based on current feedback. In this example, the control waveform and MOSFET operating trajectory are as follows: Figure 4 , Figure 5 As shown, the control strategy includes four stages: pre-trigger stage, rapid rise stage, overshoot suppression stage, and constant output stage, as follows: Figure 6 As shown: Furthermore, during the pre-trigger phase (i.e., from point A to point B), the gate-source voltage (UGS) rises to 0.95Uth (95% of the threshold voltage), at which point the MOSFET is in a critical conduction state, and the drain-source voltage (UDS) slowly decreases. The pre-trigger mechanism is designed to accelerate the subsequent rise of UGS.

[0024] Furthermore, the fast rise phase (from point C to point D) is initiated by applying a large gate-source voltage U1, causing the MOSFET to turn on rapidly. Consequently, the drain current (ID) quickly rises to 90% of the set current value (ISET), and UDS drops sharply. The selection of U1 depends on the type of MOSFET used; if U1 is continuously applied during this phase, it will cause ID to overshoot, thus requiring active overshoot suppression.

[0025] Furthermore, the overshoot suppression phase (from point E to point F) controls the MOSFET's on-state by reducing the gate drive voltage. In practical applications, as the parasitic capacitance discharges, UGS decreases smoothly, thus mitigating the current rise inertia, while UDS increases with changes in on-resistance. When ID rises to ISET, the system enters a constant output phase: the gate voltage is adjusted to the value required for ID, achieving a smooth transition and stable maintenance of UGS, ultimately allowing ID to be precisely controlled and stabilized until the end of the pulse cycle.

[0026] Furthermore, during the constant output phase, the MOSFET operates in the linear region, and its UDS is related to the on-resistance and ID. The voltage drop across the load (LD) also varies with ID; therefore, a front-end DC-DC buck-boost converter is used to achieve adaptive input voltage control. During the initial cycle of system operation, the DC-DC converter regulates the input voltage (VOUT) through current feedback until ID reaches ISET, after which VOUT remains stable. This design achieves active control of the MOSFET gate-source voltage in the pulse generation circuit and adaptive regulation of the input voltage.

[0027] This application also proposes a high-efficiency, low-overshoot pulsed laser current source control system, including: A DC-DC step-up / step-down circuit is used to provide an adjustable output voltage; The pulse generation circuit includes a power MOSFET Q6 and a load laser, which are connected to the DC-DC buck-boost circuit and the FPGA digital control circuit. A current sampling circuit, connected to the pulse generation circuit, is used to collect the load current in real time; The FPGA digital control circuit is connected to the DC-DC buck-boost circuit and the pulse generation circuit to execute the control method described above and output the gate drive signal of the power MOSFET Q6 and the control signal of the DC-DC buck-boost circuit.

[0028] In some embodiments, a soft-start circuit is also included, disposed between the DC-DC buck-boost circuit and the pulse generation circuit, for limiting the current surge during system startup.

[0029] It should be noted that, in the embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0030] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0031] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0032] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. A method for controlling the current source of a high-efficiency, low-overshoot pulsed laser, characterized in that, A pulse constant current source is applied to a DC-DC buck-boost circuit, a soft-start circuit, a pulse generation circuit, and an FPGA digital control circuit. The DC-DC buck-boost circuit is controlled by the FPGA digital control circuit and connected to the soft-start circuit. The soft-start circuit is connected to the pulse generation circuit, and the pulse generation circuit is connected to the FPGA digital control circuit. The control method includes: The FPGA digital control circuit serves as the control core, and collects the current signal from the pulse current output terminal of the pulse generation circuit as a feedback signal. Based on the feedback signal, adjust the gate voltage UGS of the power MOSFET Q6 in the pulse generation circuit and the output voltage VOUT of the DC-DC buck-boost circuit; The control method comprises four stages: a pre-trigger stage, a rapid rise stage, an overshoot suppression stage, and a constant output stage. During the pre-trigger phase, the gate voltage UGS is increased to a first proportional range of the threshold voltage of the power MOSFET Q6; During the rapid rise phase, a gate voltage U1 higher than the threshold voltage is applied, causing the drain current ID of the power MOSFET Q6 to rise rapidly to the second proportional range of the set value ISET. During the overshoot suppression phase, the gate voltage is reduced to slow down the current rise inertia until the drain current ID reaches the set value ISET. During the constant output phase, the gate voltage UGS is maintained while the drain current ID is stabilized at the set value ISET, and the output voltage VOUT is kept stable.

2. The high-efficiency low-overshoot pulsed laser current source control method as described in claim 1, characterized in that, The first ratio range is 90%-96% of the threshold voltage of the power MOSFET Q6; During the pre-trigger phase, the MOSFET is in a critical conduction state, and the drain-source voltage U_DS decreases slowly.

3. The high-efficiency low-overshoot pulsed laser current source control method as described in claim 1, characterized in that, During the rapid rise phase, the value of the gate voltage U1 is determined based on the selected MOS transistor model and dynamic characteristics. During the rapid rise phase, the drain current ID of the power MOSFET Q6 is rapidly increased to 85%-92% of the set value ISET.

4. The high-efficiency low-overshoot pulsed laser current source control method as described in claim 1, characterized in that, During the overshoot suppression stage, the gate voltage UGS is smoothly reduced by adjusting the output impedance of the gate drive circuit of the FPGA digital control circuit.

5. The high-efficiency low-overshoot pulsed laser current source control method as described in claim 1, characterized in that, During the constant output phase, the power MOSFET Q6 is controlled to operate in the linear region.

6. The high-efficiency low-overshoot pulsed laser current source control method as described in claim 1, characterized in that, The DC-DC buck-boost circuit is a buck-boost converter, and its output voltage VOUT is adaptively adjusted based on feedback from the drain current ID.

7. A high-efficiency, low-overshoot pulsed laser current source control system, characterized in that, include: A DC-DC step-up / step-down circuit is used to provide an adjustable output voltage; The pulse generation circuit includes a power MOSFET Q6 and a load laser, which are connected to the DC-DC buck-boost circuit and the FPGA digital control circuit. A current sampling circuit, connected to the pulse generation circuit, is used to collect the load current in real time; The FPGA digital control circuit is connected to the DC-DC buck-boost circuit and the pulse generation circuit to execute the control method as described in any one of claims 1-6, and output the gate drive signal of the power MOSFET Q6 and the control signal of the DC-DC buck-boost circuit.

8. The high-efficiency low-overshoot pulsed laser current source control system as described in claim 7, characterized in that, It also includes a soft-start circuit, which is located between the DC-DC buck-boost circuit and the pulse generation circuit, to limit the current surge during system startup.

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