A corelet interrupt management method, device, circuit and multi-corelet system

Abstract

The application provides a kind of core particle interruption management method, device, circuit and multi-core particle system, comprising: if receiving external interruption signal, then inquiring target mailbox state, and obtaining standard MSI message based on external interruption signal;If target mailbox state is idle within timeout threshold time, then send the standard MSI message to target mailbox;Otherwise, return to the step of waiting to receive external interruption signal;Judge whether standard MSI message meets the requirements, if yes, then output the standard MSI message to target core particle address;Otherwise, send the standard MSI message to target mailbox again;Wait to receive feedback signal of target core particle, if correct, then clear this round data;If error, then output standard MSI message to target core particle address again.The application can save IO resource;Reduce transmission interference error probability;Support sending message to different target core particle;Improve transmission reliability;Multiple sending ends concurrent without conflict, no interruption loss.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a chip interruption management method, device, circuit, and multi-chip system. Background Technology

[0002] Traditional chiplet interrupt transmissions currently typically use dedicated pins or simple bus transmissions, which have the following drawbacks: 1) It uses a dedicated interrupt pin, which consumes a lot of I / O resources and has high wiring complexity; 2) Without a data verification mechanism, transmission is susceptible to interference and errors, resulting in low reliability; 3) There is no timeout protection or retransmission mechanism, and transmission cannot be automatically recovered when it is stuck.

[0003] Therefore, it is necessary to provide a chip interruption management method, device, circuit, and multi-chip system to effectively solve the above problems. Summary of the Invention

[0004] This invention provides a chip interruption management method, device, circuit, and multi-chip system.

[0005] This invention provides a chip interrupt management method, comprising: Waiting to receive an external interrupt signal; if an external interrupt signal is received, querying the target mailbox status and obtaining a standard MSI message based on the external interrupt signal; the standard MSI message includes the target chip address information corresponding to the external interrupt signal; If the target mailbox is idle within the timeout threshold period, then send the standard MSI message to the target mailbox; otherwise, return to the step of waiting to receive an external interrupt signal. Determine whether the standard MSI message meets the requirements. If it does, output the standard MSI message to the target kernel address; otherwise, resend the standard MSI message to the target mailbox. Wait to receive feedback signals from the target chip. If a correct feedback signal is received, clear the data for this round. If an incorrect feedback signal is received, re-output the standard MSI message to the target chip address.

[0006] Preferably, the number of external interrupt signals is greater than or equal to 2 and less than or equal to 1024; obtaining the standard MSI message based on the external interrupt signals includes: Obtain the highest priority external interrupt signal from all the external interrupt signals mentioned; The standard MSI message is obtained based on the highest priority external interrupt signal.

[0007] Preferably, the standard MSI message also includes the source chip ID, target chip ID, interrupt number, interrupt priority, and check bit information corresponding to the external interrupt signal.

[0008] Preferably, determining whether the standard MSI message meets the requirements includes: Determine whether the check bit is correct; Determine whether the target core ID is correct; If both conditions are met, then the standard MSI message is compliant.

[0009] Preferably, if the target mailbox is idle within the timeout threshold period, the standard MSI message is sent to the target mailbox; otherwise, the step of returning to the waiting to receive the external interrupt signal further includes outputting a timeout interrupt signal if the number of times the step of returning to the waiting to receive the external interrupt signal exceeds a preset number.

[0010] Preferably, the chip interrupt management method is configured with multiple transmitters to output the standard MSI message to different target chip addresses respectively; in the chip interrupt management method: each transmitter sends its own standard MSI message to the corresponding target chip.

[0011] The present invention also provides a chip interruption management device, comprising: The query module is used to wait for an external interrupt signal. If an external interrupt signal is received, it queries the target mailbox status and obtains a standard MSI message based on the external interrupt signal. The standard MSI message includes the target chip address information corresponding to the external interrupt signal. The timeout handling module is used to send the standard MSI message to the target mailbox if the target mailbox is idle within the timeout threshold period; otherwise, it returns to the step of waiting to receive an external interrupt signal. The verification module is used to determine whether the standard MSI message meets the requirements. If it does, it outputs the standard MSI message to the target kernel address; otherwise, it resends the standard MSI message to the target mailbox. The feedback module is used to wait for the feedback signal from the target chip. If the correct feedback signal is received, the data of this round is cleared; if the incorrect feedback signal is received, the standard MSI message is re-output to the target chip address.

[0012] The present invention also provides a chip interrupt management circuit, comprising: The IPSO packet unit and the MSI_Tx unit are respectively used to wait for external interrupt signals. If an external interrupt signal is received, the MSI_Tx unit queries the target mailbox status, and the IPSO packet unit obtains a standard MSI message based on the external interrupt signal. The standard MSI message includes the target chip address information corresponding to the external interrupt signal. If the target mailbox status is idle within the timeout threshold, the MSI_Tx unit sends the standard MSI message to the target mailbox; otherwise, the process returns to the step of waiting for external interrupt signals. The encoding / decoding unit is used to determine whether the standard MSI message meets the requirements. If it does, the standard MSI message is output to the target kernel address; otherwise, the standard MSI message is resent to the target mailbox. The response processing unit is used to wait for the feedback signal from the target chip. If the correct feedback signal is received, the data of this round is cleared; if the incorrect feedback signal is received, the standard MSI message is re-output to the target chip address.

[0013] Preferably, the number of external interrupt signals is greater than or equal to 2 and less than or equal to 1024; the chip interrupt management circuit further includes a PLIC preprocessing module, which is used to compare and obtain the highest priority external interrupt signal among all the external interrupt signals; the IPSO packetization unit obtains the standard MSI message based on the highest priority external interrupt signal.

[0014] The present invention also provides a multi-core system, including multiple source cores, multiple target cores, and a core interrupt management circuit as described above. Each source core and each target core is communicatively connected to the core interrupt management circuit. The core interrupt management circuit is used to receive the external interrupt signal output by the source core and output the standard MSI message to the corresponding target core.

[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: The chip interrupt management method, device, circuit, and multi-chip system provided in this invention adopt Message Signaled Interrupt (MSI). MSI is a mechanism that triggers interrupts through bus messages rather than dedicated pins. Therefore, it does not require dedicated interrupt pins to occupy a large amount of IO resources. MSI message transmission replaces dedicated pins, saving more than 70% of IO resources. Through standard MSI message verification, the probability of transmission interference errors is reduced. Information can be sent to the corresponding target chip based on the target chip address, thereby supporting the sending of messages to different target chips. Through data verification, automatic retransmission, and timeout protection, the transmission reliability is improved to nearly 100%. Through the mailbox exclusive mechanism, multiple sending ends can operate concurrently without conflict and without interrupt loss. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention, but not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart of a chip interruption management method provided in one embodiment of the present invention; Figure 2 A system architecture diagram of a chip interrupt management method provided in an embodiment of the present invention; Figure 3 MSI_Tx state machine transition diagram provided for one embodiment of the present invention; Figure 4 This is a structural diagram of a chip interruption management device provided in one embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0020] To address the problems existing in the prior art, embodiments of the present invention provide a chip interruption management method, device, circuit, and multi-chip system.

[0021] Figure 1 A flowchart illustrating a chip interruption management method provided according to an embodiment of the present invention. Figure 1 As shown, a chip interruption management method includes: Step S110: Wait to receive an external interrupt signal.

[0022] Step S120: Determine whether an external interrupt signal has been received.

[0023] If an external interrupt signal is received, step S121 is executed to query the target mailbox status, and step S122 is executed to obtain a standard MSI message based on the external interrupt signal. The standard MSI message includes the target chip address information corresponding to the interrupt signal.

[0024] Specifically, in combination Figure 2 As shown in the overall architecture diagram of the chip interrupt management method, the external interrupt signal can be an interrupt signal sent by the source chip. The source chip can have an internal inter-chip packet controller transmission unit (ICPC_Tx) module to collect local interrupts, with a maximum of 1024 interrupts (IRQ [0]~IRQ

[1023] ). In this embodiment, the external interrupt signal waiting to be received can be an interrupt signal sent by a source chip; it can also be multiple interrupt signals sent by a source chip; or it can be interrupt signals sent by multiple (N) source chips respectively, wherein each source chip can send one or multiple interrupt signals.

[0025] Specifically, upon receiving an external interrupt signal, step S122 is executed to obtain a standard MSI message based on the external interrupt signal. In some implementations, when only one external interrupt signal is received, a standard MSI message can be directly packaged according to a specific format based on the external interrupt signal.

[0026] In other implementations, when only one source chip sends multiple external interrupt signals, these external interrupt signals can be preprocessed. For example, this preprocessing may include obtaining the highest-priority external interrupt signal among all external interrupt signals from the source chip; and obtaining a standard MSI message based on the highest-priority external interrupt signal, where the standard MSI message corresponds to the highest-priority interrupt signal among the multiple external interrupt signals sent by the single source chip.

[0027] In some other implementations, when the received external interrupt signal is from multiple external interrupt signals emitted by multiple source chips, for example, all external interrupt signals from each source chip can be preprocessed. The preprocessing process may include comparing the priorities of all external interrupt signals from a source chip to obtain the highest priority, and forming a corresponding standard MSI message based on the highest priority external interrupt signal. Each source chip undergoes this processing, so that each source chip that emitted the interrupt signal forms a corresponding standard MSI message, which is then sent to the corresponding target chip.

[0028] It should be noted that at the same time, the target mailbox can receive only one standard MSI message formed by a source chip.

[0029] It should be noted that this application is not limited to the process of processing external interrupt signals when there is one or more than two external interrupt signals.

[0030] Furthermore, in embodiments where a single source chip emits multiple external interrupt signals or multiple source chips emit multiple external interrupt signals, other processing such as threshold comparison processing can be performed on the multiple external interrupt signals. This application does not limit these processing procedures.

[0031] In some implementations, during the process of obtaining the external interrupt signal to be output and forming a standard MSI message, the standard MSI message can be configured to include the target chip address information, source chip ID, target chip ID, interrupt number, interrupt priority, check bit information, etc., corresponding to the external interrupt signal.

[0032] Step S130: Determine whether the target mailbox is idle within the timeout threshold period.

[0033] If the target mailbox is idle within the timeout threshold, proceed to step S131 to send a standard MSI message to the target mailbox; otherwise, return to step S110 to wait for an external interrupt signal.

[0034] Specifically, when querying the status of a target mailbox, for example, the status of the target mailbox can be stored in a register. When an external interrupt signal is received, the corresponding location in the register can be used to query the status of the target mailbox, and based on the queried status, it can be determined whether the mailbox is in an idle state. In another example, an interrupt request signal can be sent to the target mailbox. Upon receiving the interrupt request signal, the target mailbox will send back its status signal, and based on this status signal, it can be determined whether the target mailbox is in an idle state. In yet another example, the target mailbox can periodically send its status signal, and by querying the status signal sent by the target mailbox, it can be determined whether it is in an idle state.

[0035] Specifically, in this embodiment, the status query of the target email address is also configured with a timeout threshold. Each email address can be configured with the same timeout threshold for management, or different timeout thresholds can be configured for different target email addresses.

[0036] Within the threshold time, the target mailbox can remain in a state of querying or receiving status feedback from the target mailbox. If the target mailbox is idle within the timeout threshold time, step S131 is executed to send a standard MSI message to the target mailbox. If the target mailbox remains occupied or no relevant feedback signal is received within the timeout threshold time, the process returns to step S110 to wait for an external interrupt signal.

[0037] In some implementations, the chip interrupt management method further includes outputting a timeout interrupt signal if the number of times the step of returning to wait for receiving an external interrupt signal exceeds a preset number.

[0038] Specifically, in this implementation, a timeout threshold is defined as one round. Each time the target mailbox remains in an occupied state or no relevant feedback signal is received within the timeout threshold, it is recorded once. If this number exceeds a certain number, it indicates that the system has malfunctioned, such as abnormal mailbox occupancy. In this case, a timeout interrupt signal is output to report the error, thereby enabling manual intervention to investigate the problem.

[0039] Step S140: Determine whether the standard MSI message meets the requirements.

[0040] If yes, then execute step S141 to output a standard MSI message to the target chip address; otherwise, return to execute step S131 to send a standard MSI message to the target mailbox.

[0041] Specifically, each external interrupt signal is configured with a corresponding target chip. If the standard MSI message meets the requirements, it can be sent to the corresponding target chip based on the target chip address information in the MSI message. Specifically, the standard MSI message can be decoded first to obtain all the information of the corresponding interrupt signal, and then the interrupt signal portion can be verified.

[0042] In some implementations, each source chip can have a corresponding target chip. When only one source chip sends an external interrupt signal, the external interrupt signal can be processed and sent to the target chip corresponding to that source chip; when only one source chip sends multiple external interrupt signals, the highest priority interrupt signal among all the external interrupt signals of that source chip can be processed and sent to the target chip corresponding to that source chip; when multiple source chips send external interrupt signals, the external interrupt signals of each source chip can be processed to obtain the corresponding highest priority interrupt signal, and then processed and sent to the corresponding target chip.

[0043] In other embodiments, one source chip may correspond to multiple (M) target chips, and the external interrupt signal preprocessing process may be similar to the previous embodiment. The final processed signal may be sent to all corresponding target chips simultaneously.

[0044] Step S150: Wait for the feedback signal from the target chip to be received, and determine whether the received feedback signal from the target chip is correct.

[0045] If a correct feedback signal is received, execute S151 to clear the data for this round; if an incorrect feedback signal is received, return to execute step S141 again to output a standard MSI message to the target chip address.

[0046] Specifically, after sending the standard MSI message to the corresponding target chip, the system waits to receive a feedback signal from the target chip and determines whether the received feedback signal is correct. In some implementations, determining whether the standard MSI message meets the requirements in step S140 includes: determining whether the check bit is correct; and determining whether the target chip ID is correct. If both are satisfied, the standard MSI message meets the requirements. For example, this verification can employ error checking and error correcting code (ECC) verification.

[0047] In some implementations, such as Figure 2 The illustrated chip interrupt management method is configured with multiple transmitters to output standard MSI messages to different target chip addresses. In the chip interrupt management method, each transmitter sends its own standard MSI message to the corresponding target chip. "Source2TargetConnection" represents the communication connection from the source chip to the target chip.

[0048] Specifically, the chip interrupt management method can be configured with one source chip, and different external interrupt signals of this source chip can correspond to different target chips. When comparing priorities, the highest priority external interrupt signal can correspond to different target chips, so the standard MSI message corresponding to the final external interrupt signal may be sent to different target chips. In other embodiments, the chip interrupt management method can be configured with multiple source chips, each corresponding to one target chip. Regardless of which external interrupt signal is determined to be the highest priority, a source chip sends the message to the target chip corresponding to that source chip. In other embodiments, the chip interrupt management method can be configured with multiple source chips, each corresponding to multiple target chips. The highest priority external interrupt signal ultimately determined by a source chip corresponds to one or more of the multiple target chips corresponding to that source chip, and which target chip it sends the message to depends on which external interrupt signal is ultimately determined to be the highest priority. Other cases will not be elaborated further, but it should be understood that the embodiments of multiple transmitters in this application are not limited to the situations described herein.

[0049] Each transmitter sends its generated standard MSI message to the corresponding target chip. The target chip receives the standard MSI message through its Inter-Chiplet Packet Controller Receive (ICPC_Rx) unit, decodes it to obtain the relevant information of the transmission interruption, and further sends it to the Platform-Level Interrupt Controller (PLIC) and / or Central Processing Unit (CPU) in the target chip. Specifically, ICPC_Rx supports input MSI status latching. For each MSI message interrupt, the following status can be read: 1.1 Interrupt Gateway (MSI Gateway) status: a value of 1 indicates that there is currently an MSI message interrupt latch. ICPC_Rx can independently configure the following attributes for each MSI message interrupt: 2.1 Clear signal: writing 1 clears the corresponding Interrupt Gateway (MSI Gateway) status value; 2.2 Local PLIC enable signal: up to 8 local PLICs can be enabled. ICPC_Rx supports automatic acknowledgment after MSI reception without CPU intervention. ICPC_Rx supports receiving multiple MSI message interrupts sent by ICPC_Tx (up to 8). ICPC_Rx supports sending decoded interrupts to multiple target PLICs (up to 8), with different enable bits configured. ICPC_Rx supports ECC data verification.

[0050] In one specific embodiment, such as Figure 3 As shown, the state machine logic of this application can be as follows: The initial state is STATE_RD0. If an interrupt is received, data is loaded and the process jumps to STATE_RD1; otherwise, the process remains in the STATE_RD0 state (e.g., ...). Figure 3 (As indicated by the "else" arrow on STATE_RD0). In STATE_RD1, the bus initiates a read operation, then jumps to STATE_RD2. In STATE_RD2, the target mailbox status is queried. If the target mailbox is accessible, it jumps to STATE_WR0; otherwise, it waits in STATE_RD2, continuing to query the target mailbox status during this waiting period (e.g., ...). Figure 3 (As indicated by the "else" arrow on STATE_RD2), if the waiting time exceeds the counter timeout threshold, it will jump back to the STATE_RD0 state (e.g., ...). Figure 3 (See the "else" arrows from STATE_RD2 to STATE_RD0). In STATE_WR0, the address and data to be sent are loaded, then the process jumps to STATE_WR1. In STATE_WR1, the bus is started, initiating a write operation, then the process jumps to STATE_WR2. In STATE_WR2, all data is written, then the process jumps to STATE_NOP; otherwise (i.e., not all data has been written), the process waits in STATE_WR2 (e.g., ...). Figure 3 (As indicated by the "else" arrow on STATE_WR2). The STATE_NOP state waits for a feedback signal from the target chip. Upon receiving the feedback signal, it jumps back to the STATE_RD0 state; otherwise, it waits in the STATE_NOP state (e.g., ...). Figure 3 (As indicated by the "else" arrow on STATE_NOP) If the feedback signal indicates that the data was received correctly, it is cleared and waits for new interrupt data; if the feedback signal indicates that the data was received incorrectly, the data from the previous round is retransmitted.

[0051] In one specific embodiment, the complete interrupt transmission and acknowledgment process may include: An interrupt gateway receives and latches interrupt signals triggered by interrupt sources. Once an interrupt gateway has latched an interrupt signal, it will not receive any new interrupt signals from the interrupt source until it has processed the current interrupt and cleared the gateway.

[0052] The interrupt gateway sends an interrupt request to the Platform-Level Interrupt Controller (PLIC).

[0053] PLIC selects the highest priority interrupt and sends it to the packetization unit of the interrupt message serialization and output unit and the MSI sender.

[0054] The MSI sender determines whether to send an MSI interrupt (standard MSI message) based on the availability of the target mailbox: Specifically, the MSI sender continuously sends status query requests to the target mailbox until the target mailbox returns a usable status response.

[0055] The MSI sender sends an MSI interrupt, and the target mailbox receives an MSI interrupt.

[0056] The target mailbox sends the MSI interrupt to the ECC decoder.

[0057] If the ECC error correction code is incorrect, an error message indicating an ECC decoding error is sent to the MSI transmitter, and the MSI transmitter retransmits the current MSI interrupt.

[0058] If the ECC error correction code is correct, it is fed back to the MSI transmitter, indicating that the current MSI interrupt has been successfully received.

[0059] The received interrupt is a valid interrupt, which is triggered and latched in the local gateway in the target chip, and then reported to the local platform-level interrupt controller (PLIC).

[0060] The local PLIC reports interrupts to the central processing unit (CPU).

[0061] CPU interrupt handling includes: CPU handles interrupts from remote chip interrupt sources; The CPU writes a remote completion instruction to the interrupt controller of the remote core, clearing and releasing the PLIC kernel and gateway resources; The CPU sends a cleanup completion indication signal to the interrupt gateway of the local chip.

[0062] The next round is interrupted.

[0063] This application also provides a chip interruption management device 10, such as Figure 4 As shown, it includes: The query module 11 is used to wait for an external interrupt signal. If an external interrupt signal is received, it queries the target mailbox status and obtains a standard MSI message based on the external interrupt signal. The standard MSI message includes the target chip address information corresponding to the external interrupt signal. The timeout handling module 12 is used to send a standard MSI message to the target mailbox if the target mailbox is idle within the timeout threshold period; otherwise, it returns to the step of waiting to receive an external interrupt signal. The verification module 13 is used to determine whether the standard MSI message meets the requirements. If it does, it outputs the standard MSI message to the target kernel address; otherwise, it resends the standard MSI message to the target mailbox. Feedback module 14 is used to wait for feedback signals from the target chip. If a correct feedback signal is received, the data for this round is cleared; if an incorrect feedback signal is received, a standard MSI message is re-output to the target chip address.

[0064] This application also provides a chip interrupt management circuit (not shown in the figure), including: an interrupt packet serialization and output (IPSO) unit, an MSI_Tx unit, an encoding and decoding unit, and an acknowledgment processing unit.

[0065] The IPSO packet unit and the MSI_Tx unit are used to wait for external interrupt signals. If an external interrupt signal is received, the MSI_Tx unit queries the target mailbox status, and the IPSO packet unit obtains a standard MSI message based on the external interrupt signal. The standard MSI message includes the target chip address information corresponding to the external interrupt signal. If the target mailbox status is idle within the timeout threshold, the MSI_Tx unit sends a standard MSI message to the target mailbox; otherwise, it returns to the step of waiting for external interrupt signals.

[0066] The encoding / decoding unit is used to determine whether the standard MSI message meets the requirements. If it does, the standard MSI message is output to the target kernel address; otherwise, the standard MSI message is resent to the target mailbox. The response processing unit is used to wait for feedback signals from the target chip. If a correct feedback signal is received, the data for this round is cleared; if an incorrect feedback signal is received, a standard MSI message is re-output to the target chip address.

[0067] In some implementations, the number of external interrupt signals is greater than or equal to 2 and less than or equal to 1024; the chip interrupt management circuit also includes a PLIC preprocessing module, which is used to compare and obtain the highest priority external interrupt signal among all external interrupt signals; the IPSO packet unit obtains the standard MSI message based on the highest priority external interrupt signal.

[0068] This application also provides a multi-core system, including multiple source cores, multiple target cores, and a core interrupt management circuit as described in any of the above embodiments. Each source core and each target core is communicatively connected to the core interrupt management circuit. The core interrupt management circuit is used to receive external interrupt signals output by the source cores and output standard MSI messages to the corresponding target cores.

[0069] The chip interruption management device, chip interruption management circuit, and multi-chip system provided in this application can implement the manner provided in any of the embodiments of the above-described chip interruption management method, and will not be described in detail here.

[0070] The chip interrupt management method, device, circuit, and multi-chip system provided in this invention adopt MSI, a mechanism that triggers interrupts through bus messages rather than dedicated pins. Therefore, it eliminates the need for dedicated interrupt pins that consume significant I / O resources, saving over 70% of I / O resources. Standard MSI message verification reduces the probability of transmission interference errors. Information can be sent to corresponding target chips based on their addresses, supporting message sending to different target chips. Data verification, automatic retransmission, and timeout protection improve transmission reliability to nearly 100%. A dedicated mailbox mechanism ensures conflict-free and interrupt-free concurrent operation of multiple senders. Furthermore, configuring multiple senders enables one-to-many transmission, meeting the needs of large-scale multi-chip systems. The hardware circuit automatically completes querying, sending, data verification, and retransmission without CPU intervention, reducing load by over 50%, making it particularly suitable for multi-chip systems in data centers and automotive electronics.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip interruption management method, characterized in that, include: Waiting to receive an external interrupt signal; if an external interrupt signal is received, querying the target mailbox status and obtaining a standard MSI message based on the external interrupt signal; The standard MSI message includes the target chip address information corresponding to the external interrupt signal; If the target mailbox is idle within the timeout threshold period, then send the standard MSI message to the target mailbox; otherwise, return to the step of waiting to receive an external interrupt signal. Determine whether the standard MSI message meets the requirements. If it does, output the standard MSI message to the target kernel address; otherwise, resend the standard MSI message to the target mailbox. Wait to receive the feedback signal from the target core; if the correct feedback signal is received, clear the data for this round. If an incorrect feedback signal is received, the standard MSI message is re-output to the target core address.

2. The chip interruption management method according to claim 1, characterized in that, The number of external interrupt signals is greater than or equal to 2 and less than or equal to 1024; the process of obtaining standard MSI messages based on the external interrupt signals includes: Obtain the highest priority external interrupt signal from all the external interrupt signals mentioned; The standard MSI message is obtained based on the highest priority external interrupt signal.

3. The chip interruption management method according to claim 1, characterized in that, The standard MSI message also includes the source chip ID, target chip ID, interrupt number, interrupt priority, and checksum information corresponding to the external interrupt signal.

4. The chip interruption management method according to claim 3, characterized in that, The determination of whether the standard MSI message meets the requirements includes: Determine whether the check bit is correct; Determine whether the target core ID is correct; If both conditions are met, then the standard MSI message is compliant.

5. The chip interruption management method according to claim 1, characterized in that, If the target mailbox is idle within the timeout threshold period, the standard MSI message is sent to the target mailbox; otherwise, the step of returning to the waiting to receive an external interrupt signal further includes outputting a timeout interrupt signal if the number of times the step of returning to the waiting to receive an external interrupt signal exceeds a preset number.

6. The chip interruption management method according to claim 1, characterized in that, The chip interrupt management method is configured with multiple sending ends to output the standard MSI message to different target chip addresses respectively; in the chip interrupt management method: each sending end sends the standard MSI message it has formed to the corresponding target chip.

7. A chip interruption management device, characterized in that, include: The query module is used to wait for an external interrupt signal. If an external interrupt signal is received, it queries the target mailbox status and obtains a standard MSI message based on the external interrupt signal. The standard MSI message includes the target chip address information corresponding to the external interrupt signal. The timeout handling module is used to send the standard MSI message to the target mailbox if the target mailbox is idle within the timeout threshold period; otherwise, it returns to the step of waiting to receive an external interrupt signal. The verification module is used to determine whether the standard MSI message meets the requirements. If it does, it is used to output the standard MSI message to the target chip address. Otherwise, resend the standard MSI message to the target mailbox; The feedback module is used to wait for the feedback signal from the target core. If the correct feedback signal is received, the data for this round is cleared. If an incorrect feedback signal is received, the standard MSI message is re-output to the target core address.

8. A chip interrupt management circuit, characterized in that, include: The IPSO packet unit and the MSI_Tx unit are respectively used to wait for external interrupt signals. If an external interrupt signal is received, the MSI_Tx unit queries the target mailbox status, and the IPSO packet unit obtains a standard MSI message based on the external interrupt signal. The standard MSI message includes the target chip address information corresponding to the external interrupt signal. If the target mailbox status is idle within the timeout threshold, the MSI_Tx unit sends the standard MSI message to the target mailbox; otherwise, the process returns to the step of waiting for external interrupt signals. The encoding / decoding unit is used to determine whether the standard MSI message meets the requirements. If so, it outputs the standard MSI message to the target chip address. Otherwise, resend the standard MSI message to the target mailbox; The response processing unit is used to wait for the feedback signal from the target chip, and if the correct feedback signal is received, the data of this round is cleared. If an incorrect feedback signal is received, the standard MSI message is re-output to the target core address.

9. The chip interrupt management circuit according to claim 8, characterized in that, The number of external interrupt signals is greater than or equal to 2 and less than or equal to 1024; the chip interrupt management circuit also includes a PLIC preprocessing module, which is used to compare and obtain the highest priority external interrupt signal among all the external interrupt signals; the IPSO packetization unit obtains the standard MSI message based on the highest priority external interrupt signal.

10. A multi-core particle system, characterized in that, It includes multiple source chips, multiple target chips, and a chip interrupt management circuit as described in any one of claims 8-9. Each source chip and each target chip is communicatively connected to the chip interrupt management circuit. The chip interrupt management circuit is used to receive the external interrupt signal output by the source chip and output the standard MSI message to the corresponding target chip.

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