An OTG analog circuit conforming to USB2.0 protocol

Abstract

The application relates to the technical field of communication interface circuit and its control, in particular to an OTG simulation circuit conforming to the USB2.0 protocol requirement, which comprises a master-slave identification circuit, an ADP circuit and an SRP circuit; the master-slave identification circuit identifies the host or the slave by judging whether the external resistance is in the grounded state or the floating state; in the process of identifying the host or the slave, the ADP circuit synchronously completes the detection of the disconnection or connection of the equipment, judges the connection state of the VBUS bus and provides the judgment basis for the host; in the process of identifying the host or the slave and detecting the disconnection or connection, the SRP circuit is in the closed state; when the master-slave identification circuit and the ADP circuit are closed, the SRP circuit is opened; when the slave needs to use the VBUS bus, the SRP circuit requests the host to enable the VBUS bus. In the master-slave identification process, the ADP circuit synchronously completes the disconnection detection, and no additional reference voltage generating circuit is needed, so that the chip area is obviously reduced.

Description

Technical Field

[0001] This invention relates to the field of communication interface circuits and their control technology, specifically to an OTG analog circuit conforming to the USB 2.0 protocol. Background Technology

[0002] The USB 2.0 specification introduced On-The-Go (OTG) functionality to enable direct communication between devices without a traditional host. To support OTG, the related circuitry needs several functions, such as master / slave identification, Additional Power Detection (ADP), and Session Request Protocol (SRP). Master / slave identification distinguishes between master and slave devices by detecting different resistance values ​​of an external resistor, thus determining the device's role during connection. ADP determines device connection and disconnection based on the capacitor charging and discharging characteristics of the VBUS bus. When a device connects or disconnects, the capacitance changes, resulting in different voltage rise times. By monitoring and comparing these rise times, the device's insertion / removal status can be determined. SRP reduces system power consumption. When the VBUS bus is idle, the host disables VBUS power to reduce energy consumption; when a slave device needs to use the VBUS bus, it requests the host to re-enable the VBUS bus via the SRP circuitry, thus providing power to non-self-powered modules. According to the USB 2.0 protocol, the data line must be in a low-level state before initiating a session, and the VBUS voltage must be lower than the session validity threshold. During charging, it is also necessary to detect whether the VBUS bus voltage reaches the power supply requirement threshold of approximately 4.4V to ensure that the power supply capacity meets the normal use requirements.

[0003] However, existing OTG circuits generally suffer from problems such as large circuit area, high power consumption, complex reference voltage generation, and insufficient master-slave identification accuracy when implementing the above functions. There is an urgent need for a new circuit design scheme to improve reliability and meet the requirements of the USB 2.0 protocol. Summary of the Invention

[0004] To address the technical problems existing in the prior art, this invention provides an OTG analog circuit compliant with the USB 2.0 protocol. This invention aims to improve circuit reliability and protocol compatibility by optimizing the design of the master-slave identification, Additional Power Detection (ADP), and Session Request (SRP) circuit structures, reducing reliance on the reference voltage generation module, lowering circuit area and power consumption, and improving the accuracy of master-slave identification.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: an OTG analog circuit conforming to the USB 2.0 protocol requirements, comprising a master-slave identification circuit, an ADP circuit, and an SRP circuit. The master-slave identification circuit identifies the master or slave device by determining whether the external resistor is in a grounded or floating state. During the master-slave identification process, the ADP circuit simultaneously detects the disconnection or connection of the device and determines the connection status of the VBUS bus, providing a basis for the master's judgment. During the master-slave identification and disconnection or connection detection, the SRP circuit is in a closed state. When the master-slave identification circuit and the ADP circuit are closed, the SRP circuit is open. When the slave device needs to use the VBUS bus, the SRP circuit requests the master to enable the VBUS bus.

[0006] Preferably, the master-slave identification circuit includes an ACA circuit, which is connected to the external resistor. At its connection node, a reference voltage signal Ref_prb is generated by voltage division. The comparator of the ACA circuit compares the reference voltage signal Ref_prb with the voltage signal generated by voltage division under the action of the control signal PU generated by the external circuit, and inputs the comparison result to the logic circuit to generate a master-slave identification signal. The master and slave devices are determined by detecting the high or low level of the master-slave identification signal.

[0007] Preferably, the ACA circuit includes comparators Comp1 to Comp4, a current unit composed of a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, and a fifth PMOS transistor M5, a voltage divider unit composed of voltage divider resistors R1 to R9, and the logic circuit composed of NOR gates NOR1 to NOR3, an inverter INV1, and a NAND gate NAND1. The current from the current unit is divided by the voltage divider resistors in the voltage divider unit to form voltage signals, which are then input to comparators Comp1 to Comp4 to obtain voltage comparison results a1 to a4. These results are then input to the logic circuit for logical operations to generate master-slave identification signals ridfloat and ridgnd. When ridfloat is detected to be low and ridgnd to be high, it indicates that the resistance value of the external resistor is in the ground range, and the device is determined to be the master. When ridfloat is detected to be high and ridgnd to be low, it indicates that the resistance value of the external resistor is in the floating range, and the device is determined to be the slave.

[0008] Preferably, the gates of PMOS transistors M1 to M5 are connected and serve as the input terminals of the ACA circuit, with their sources connected to a voltage source; the drain of the first PMOS transistor M1 is connected to a voltage divider resistor R1; the other end of the voltage divider resistor R1 serves as the first output terminal of the ACA circuit and is connected to the negative input terminals of comparators Comp1 to Comp4 respectively; the drain of the second PMOS transistor M2 is connected to a voltage divider resistor R2; the other end of the voltage divider resistor R2 is connected to a voltage divider resistor R3 and is connected to the positive input terminal of comparator Comp1; the drain of the third PMOS transistor M3 is connected to a voltage divider resistor R4; the other end of the voltage divider resistor R4 is connected to a voltage divider resistor R5 and is connected to the positive input terminal of comparator Comp2; the drain of the fourth PMOS transistor M4 is connected to a voltage divider resistor R6; the other end of the voltage divider resistor R6 is connected to a voltage divider resistor R7 and is connected to the positive input terminal of comparator Comp3; the drain of the fifth PMOS transistor M5 is connected to a voltage divider resistor R8; the other end of the voltage divider resistor R8 is connected to a voltage divider resistor R9. The outputs of comparators are connected to the positive input of comparator Comp4; the other ends of voltage divider resistors R3, R5, R7, and R9 are grounded; the output a1 of comparator Comp1 is connected to one input of NOR gate NOR2; the output a2 of comparator Comp2 is connected to one input of NOR gate NOR3 and serves as the second output of the ACA circuit; the output a3 of comparator Comp3 is connected to one input of NOR gate NOR3; the output a4 of comparator Comp4 is connected to one input of NOR gate NOR2; the outputs of NOR gates NOR2 and NOR3 are respectively connected to the inputs of NAND gate NAND1, and the output of NAND gate NAND1 is connected to one input of NOR gate NOR1; the input of inverter INV1 is connected to the gates of PMOS transistors M1 to M5, and its output is connected to the other input of NOR gate NOR1; the output of NOR gate NOR1 serves as the third output of the ACA circuit; the output logic expression is: ridfloat = a2; ridgnd = .

[0009] Preferably, the ADP circuit includes a voltage divider sampling charge / discharge circuit and an ADP comparator. The voltage divider sampling charge / discharge circuit receives voltage signals V1, V2, a charging signal, and a discharging signal generated by an external circuit, and generates several voltage divider signals. The voltage divider sampling charge / discharge circuit has input / output ports, which are connected to the ADP comparator via a VBUS bus. The ADP comparator compares the voltage divider signals output from the input / output ports with the reference voltage signal Ref_prb, and outputs a disconnection detection signal. The disconnection or connection status of the device is determined based on the time required for the disconnection detection signal to change.

[0010] Preferably, under the control of the charging signal, the voltage divider sampling charge-discharge circuit charges the equivalent capacitance of the VBUS bus to increase the voltage on the VBUS bus; when the voltage on the VBUS bus rises to be equal to the reference voltage signal Ref_prb, the output signal of the ADP comparator jumps to a high level. If the time of the high level jump is short, it is determined to be a disconnected state; if the time of the high level jump is long, it is determined to be a connected state.

[0011] Preferably, the SRP circuit includes a session valid comparator and a VBUS valid comparator. The session valid comparator receives the divided voltage signal generated by the voltage divider sampling charge-discharge circuit and the reference voltage signal SESSVREF generated by the external circuit, and outputs a session valid signal. When the session valid signal jumps to a high level, it is transmitted to the host computer for processing. The VBUS valid comparator receives the divided voltage signal generated by the voltage divider sampling charge-discharge circuit and the reference voltage signal VBUSVREF generated by the external circuit, and outputs a VBUS valid signal. When the VBUS valid signal jumps to a high level, it is transmitted to the host computer for processing.

[0012] Preferably, the input / output port is connected to an external regulated charge pump. When the ADP comparator is turned off, the VBUS bus is charged through the external regulated charge pump. The voltage divider sampling charge / discharge circuit divides the voltage of the VBUS bus to obtain two different voltage divider signals, which are respectively connected to the session valid comparator and the VBUS valid comparator.

[0013] Preferably, the voltage divider sampling charge-discharge circuit includes PMOS transistors M1, M2, M5, M6, M8, M13, M15 to M18, M20, M22 and M23, NMOS transistors M3, M4, M7, M9 to M12, M14, M19, M21 and M24 to M26, resistors R1 to R11, inverter INV1, NAND gate NAND1, and current source CS1. The gates of PMOS transistors M1 and M2 are interconnected with the gates of NMOS transistors M3 and M4, and connected to the drain of PMOS transistor M8 and one end of resistors R4 and R6. The source of M1 is connected to the source of M8, the gate of NMOS transistor M19, the source of PMOS transistor M22, and the gate of PMOS transistor M4. The gate of transistor M23 is connected to resistor R1 and serves as the first input terminal of the voltage divider sampling charge-discharge circuit, receiving voltage signal V2. The drain of M1 is connected to the source of M2, and together with the other end of R1 and the source of PMOS transistor M5, it is connected to the power supply. The drain of M2 is connected to the drain of M3, and is connected to the gates of PMOS transistors M5 and M6, and NMOS transistor M7. The source of M3 is connected to the drain of M4, and the source of M4 is grounded. The drain of M5 is connected to the source of M6, and the drains of M6 and M7 are connected together to one input terminal of NAND gate NAND1, and the source of M7 is grounded. The gate of M8 is connected to a voltage source via resistor R11. One end of current source CS1 serves as the voltage divider sampling charge-discharge circuit. The second input terminal is controlled by voltage signal V1, and its output terminal is connected to resistor R2 and the gates of NMOS transistors M9 and M11; the other end of R2 is connected to the drain of M9 and the gates of NMOS transistors M10 and M12. The sources of M9 and M11 are connected to the drains of M10 and M12, respectively, and the sources of M10 and M12 are grounded; the drain of M11 is connected to the source of NMOS transistor M14, and the drain of M14 is connected to the drain of PMOS transistor M13, and together they are connected to resistor R3 and the gates of PMOS transistors M16 and M18; the gates of M13 and M14 are connected, serving as the third input terminal of the voltage divider sampling charge-discharge circuit, controlled by the charging signal, and the source of M13 is connected to the power supply; R3 The other end is connected to the drain of M16 and the gates of PMOS transistors M15 and M17. The sources of M15 and M17 are both connected to the power supply, and their drains are connected to the sources of M16 and M18, respectively. The drain of M18 is connected to the drain of M19, and the source of M19 is connected to the drain of NMOS transistor M26. The input of inverter INV1 is connected to the gate of NMOS transistor M21 and serves as the fourth input of the voltage divider sampling charge-discharge circuit, receiving the discharge signal. Its output is connected to the other input of NAND1. The output of NAND1 is connected to the gate of PMOS transistor M20. The source of M20 is connected to the power supply, and its drain is connected to the drain of M21 and the drain of NMOS transistor M24. The source of M21 is grounded.The gate of M24 is connected to the power supply, and its source is connected to the drain of NMOS transistor M25. The gate of PMOS transistor M22 is connected to resistors R7 and R8, as well as the drain of PMOS transistor M23. The source of M23 is connected to the drain of M22, and together they are connected to the gates of M25 and M26. The drain of M23 and the sources of M25 and M26 are connected to the VBUS bus via resistors R8, R9, and R10, respectively, serving as the input and output ports of the voltage divider sampling charge-discharge circuit. The other end of R7 is connected to R6, serving as the first output terminal of the voltage divider sampling charge-discharge circuit, outputting a divided voltage signal of 7 / 20VBUS. The other end of R6 is connected to R4, and the other end of R4 is connected to resistor R5, serving as the second output terminal of the voltage divider sampling charge-discharge circuit, outputting a divided voltage signal of 1 / 4VBUS. The other end of R5 is grounded.

[0014] Compared with the prior art, the advantages of the present invention are as follows: 1. This invention innovatively completes disconnection detection synchronously through an ADP circuit during the master-slave identification process, eliminating the need for an additional reference voltage generation circuit, thereby significantly reducing chip area. Simultaneously, the required precise reference voltage can be flexibly adjusted and generated by adjusting internal or external resistors.

[0015] 2. By introducing an ACA circuit to detect the voltage drop across an external resistor, this design can accurately determine whether the external resistor is in a grounded or floating state, thus achieving automatic identification between the master and slave devices. Compared to traditional methods that rely on fixed resistors or external circuits, this design simplifies the circuit structure, reduces implementation difficulty, and improves the reliability and flexibility of identification. Attached Figure Description

[0016] Figure 1 This is a structural block diagram of the present invention.

[0017] Figure 2 This is a circuit structure diagram of the ACA circuit in this invention.

[0018] Figure 3 This is a circuit diagram of the voltage divider sampling charge-discharge circuit in this invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] First, the terms used in this invention are explained: The reference voltage signal Ref_prb is the voltage reference signal generated by the ACA circuit and the external resistor through voltage division; the control signal PU is a control signal generated by the external circuit, used to drive the ACA circuit; the voltage signal V1 is a voltage signal provided by the external circuit, used to control the working state of the current source CS1 in the voltage divider sampling charge / discharge circuit; the voltage signal V2 is a voltage signal provided by the external circuit, supplied to the voltage divider sampling charge / discharge circuit; both the charging signal and the discharging signal are generated by the external circuit, used to control the charging and discharging processes of the voltage divider sampling charge / discharge circuit respectively; the reference voltage signal SESSVREF is a voltage reference signal generated by the external circuit, used as the positive input voltage reference of the session valid comparator, used to determine the session valid state; the reference voltage signal VBUSVREF is a voltage reference signal generated by the external circuit, used as the positive input voltage reference of the VBUS valid comparator, used to determine the VBUS valid state; the VBUS bus is the power transmission line in the OTG circuit, used to transmit the voltage signal VBUS.

[0021] like Figure 1 As shown, this invention provides an OTG analog circuit conforming to the USB 2.0 protocol, which includes a master-slave identification circuit, an ADP circuit, and an SRP circuit. The master-slave identification circuit implements the master-slave identification function. The essence of this function is that, through an external resistor, two USB devices can quickly negotiate and determine the master / slave relationship without an external host, thereby enabling direct data transmission or peripheral expansion. Specifically, the master-slave identification circuit includes an ACA circuit. One end of the ACA circuit can be connected to two external resistors of different values, forming a voltage divider at the connection node, thereby generating a reference voltage signal Ref_prb. Under the action of the received control signal PU, the ACA circuit outputs master-slave identification signals Ridgnd and Ridfloat.

[0022] like Figure 2As shown, the ACA circuit consists of a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, and a fifth PMOS transistor M5 forming a current unit, and voltage divider units consisting of voltage divider resistors R1 to R9. It further includes comparators Comp1 to Comp4 for voltage comparison and logic circuits that implement logic functions through NOR gates NOR1 to NOR3, inverter INV1, and NAND gate NAND1. The specific connection is as follows: the gates of PMOS transistors M1 to M5 are connected and serve as the input terminals of the ACA circuit, with their sources connected to a voltage source; the drain of the first PMOS transistor M1 is connected to the voltage divider resistor R1; the other end of the voltage divider resistor R1 serves as the first output terminal of the ACA circuit and is connected to the negative input terminals of comparators Comp1 to Comp4 respectively; the drain of the second PMOS transistor M2 is connected to the voltage divider resistor R2; the other end of the voltage divider resistor R2 is connected to the voltage divider resistor R3 and is connected to the positive input terminal of comparator Comp1; the drain of the third PMOS transistor M3 is connected to the voltage divider resistor R4; the other end of the voltage divider resistor R4 is connected to the voltage divider resistor R5 and is connected to the positive input terminal of comparator Comp2; the drain of the fourth PMOS transistor M4 is connected to the voltage divider resistor R6; the other end of the voltage divider resistor R6 is connected to the voltage divider resistor R7 and is connected to the positive input terminal of comparator Comp3; the drain of the fifth PMOS transistor M5 is connected to the voltage divider resistor R8; the other end of the voltage divider resistor R8 is connected to the voltage divider resistor R9. The outputs of comparators are connected to the positive input of comparator Comp4; the other ends of voltage divider resistors R3, R5, R7, and R9 are grounded; the output a1 of comparator Comp1 is connected to one input of NOR gate NOR2; the output a2 of comparator Comp2 is connected to one input of NOR gate NOR3 and serves as the second output of the ACA circuit; the output a3 of comparator Comp3 is connected to one input of NOR gate NOR3; the output a4 of comparator Comp4 is connected to one input of NOR gate NOR2; the outputs of NOR gates NOR2 and NOR3 are respectively connected to the inputs of NAND gate NAND1, and the output of NAND gate NAND1 is connected to one input of NOR gate NOR1; the input of inverter INV1 is connected to the gates of PMOS transistors M1 to M5, and its output is connected to the other input of NOR gate NOR1; the output of NOR gate NOR1 serves as the third output of the ACA circuit; the resulting output logic expression is: ridfloat = a2; ridgnd = .

[0023] When the OTG circuit starts, under the control signal PU, PMOS transistors M1 to M5 are all in the conducting state. The first output terminal of the ACA circuit is connected to an external resistor. At the connection node, a reference voltage signal Ref_prb is generated through voltage division and sent to the negative input terminals of comparators Comp1 to Comp4 respectively. At the same time, the drain current of PMOS transistors M2 to M5 forms voltage signals through their respective voltage divider resistors, which serve as the positive input voltages of comparators Comp1 to Comp4 respectively. Through the above comparison process, the voltage comparison results a1 to a4 are obtained and input to the logic circuit for logical operation, finally generating the master-slave identification signals ridfloat and ridgnd. In master mode, the external resistor is less than 15kΩ. The ACA circuit performs voltage division comparison and logical operation, and the output signal ridfloat is low and ridgnd is high. In slave mode, the external resistor is greater than 220kΩ. After the same processing, the output signal ridfloat is high and ridgnd is low. The internal master-slave identification function can be realized by detecting the levels of the output signals ridfloat and ridgnd.

[0024] In summary, the output signals ridfloat and ridgnd of the ACA circuit are always logically opposite. When the output signal ridfloat is high, it indicates that the external resistor value is in the floating range, thus determining that the circuit is a slave; when the output signal ridgnd is high, it indicates that the external resistor value is in the ground range, thus determining that the circuit is a master.

[0025] This invention also includes an ADP circuit, which is used to detect disconnection while performing master-slave identification and to determine the connection status of the VBUS bus. By having the function of detecting the disconnection or connection status of external devices, the ADP circuit can provide the host with a basis for judgment, enabling it to confirm whether the appropriate driver has been loaded and the correct communication channel has been established when connecting external devices. Specifically, the ADP circuit includes a voltage divider sampling charge-discharge circuit and an ADP comparator. The input terminal of the voltage divider sampling charge-discharge circuit receives voltage signals V1, V2, a charging signal, and a discharging signal; its input and output ports are connected to an external regulated charge pump, and are also connected to the positive input terminal of the ADP comparator through the VBUS bus; the voltage divider sampling charge-discharge circuit is also connected to the SRP circuit, and inputs the generated divided voltage signals 7 / 20VBUS and 1 / 4VBUS to the SRP circuit respectively; the negative input terminal of the ADP comparator is connected to the reference voltage signal Ref_prb, and its output is the disconnection detection signal Adpprb.

[0026] like Figure 3As shown, the voltage divider sampling charge-discharge circuit includes PMOS transistors M1, M2, M5, M6, M8, M13, M15 to M18, M20, M22 and M23, NMOS transistors M3, M4, M7, M9 to M12, M14, M19, M21 and M24 to M26, resistors R1 to R11, inverter INV1, NAND gate NAND1 and current source CS1. The specific connection is as follows: the gates of PMOS transistors M1 and M2 are interconnected with the gates of NMOS transistors M3 and M4, and connected to the drain of PMOS transistor M8 and one end of resistors R4 and R6; the source of M1 is connected to the source of M8, the gate of NMOS transistor M19, the source of PMOS transistor M22, the gate of PMOS transistor M23, and resistor R1, and serves as the first input terminal of the voltage divider sampling charge-discharge circuit, receiving the voltage signal V2; the drain of M1 is connected to the source of M2, and together with the other end of R1 and the source of PMOS transistor M5, it is connected to the power supply; the drain of M2 is connected to the drain of M3... The gates of M3, M4, and M5 and M6, and the gates of M7 are connected together; the source of M3 is connected to the drain of M4, and the source of M4 is grounded; the drain of M5 is connected to the source of M6, and the drains of M6 and M7 are connected together to one input of the NAND gate NAND1, and the source of M7 is grounded; the gate of M8 is connected to a voltage source via resistor R11; one end of the current source CS1 serves as the second input of the voltage divider sampling charge-discharge circuit, controlled by the voltage signal V1, and its output is connected to resistor R2 and the gates of NMOS transistors M9 and M11; the other end of R2 is connected to the drain of M9 and the gate of the NMOS transistor. The gates of transistors M10 and M12, and the sources of transistors M9 and M11 are connected to the drains of transistors M10 and M12, respectively. The sources of transistors M10 and M12 are grounded. The drain of M11 is connected to the source of NMOS transistor M14. The drain of M14 is connected to the drain of PMOS transistor M13, and both are connected to resistor R3 and the gates of PMOS transistors M16 and M18. The gates of M13 and M14 are connected, serving as the third input terminal of the voltage divider sampling charge-discharge circuit, controlled by the charging signal. The source of M13 is connected to the power supply. The other end of R3 is connected to the drain of M16 and the gates of PMOS transistors M15 and M17. The sources of M15 and M17 are both connected to the power supply, and their drains are connected to the sources of M16 and M18, respectively. The drain of M18 is connected to the drain of M19, and the source of M19 is connected to the drain of NMOS transistor M26. The input of inverter INV1 is connected to the gate of NMOS transistor M21 and serves as the fourth input of the voltage divider sampling charge-discharge circuit, receiving the discharge signal. Its output is connected to another input of NAND1. The output of NAND1 is connected to the gate of PMOS transistor M20. The source of M20 is connected to the power supply, and its drain is connected to the drain of M21 and the drain of NMOS transistor M24. The source of M21 is grounded.The gate of M24 is connected to the power supply, and its source is connected to the drain of NMOS transistor M25. The gate of PMOS transistor M22 is connected to resistors R7 and R8, as well as the drain of PMOS transistor M23. The source of M23 is connected to the drain of M22, and together they are connected to the gates of M25 and M26. The drain of M23 and the sources of M25 and M26 are connected to the VBUS bus via resistors R8, R9, and R10, respectively, serving as the input and output ports of the voltage divider sampling charge-discharge circuit. The other end of R7 is connected to R6, serving as the first output terminal of the voltage divider sampling charge-discharge circuit, outputting a divided voltage signal of 7 / 20VBUS. The other end of R6 is connected to R4, and the other end of R4 is connected to resistor R5, serving as the second output terminal of the voltage divider sampling charge-discharge circuit, outputting a divided voltage signal of 1 / 4VBUS. The other end of R5 is grounded.

[0027] After connecting an external resistor, the reference voltage signal Ref_prb obtained by voltage division is input to the negative input terminal of the ADP comparator, while the positive input terminal of the ADP comparator is connected to the VBUS bus. Because there is capacitance on the VBUS bus, and the equivalent capacitance value differs between the disconnected and connected states, the voltage rise time during charging differs. During operation, under the control of the charging signal, the voltage divider sampling charge-discharge circuit charges the VBUS bus capacitor. When the voltage on the VBUS bus rises to equal the reference voltage signal Ref_prb, the output signal of the ADP comparator jumps to a high level. According to the USB 2.0 protocol, the equivalent capacitance of the VBUS bus is approximately 6.5uF. Using this as a reference, a VBUS bus capacitance of 6.5uF corresponds to the disconnected state, and an increase to approximately 13uF corresponds to the connected state. Since the charging times differ, the disconnected / connected state can be detected by comparing the time required for the ADP comparator output signal to transition. Before the OTG circuit performs the SRP function, the ADP circuit will perform disconnection / connection detection at a set period; after the detection is completed, the voltage divider sampling charge and discharge circuit will discharge the VBUS bus under the control of the discharge signal.

[0028] This invention also includes an SRP circuit for implementing the SRP function. In the OTG circuit, to reduce unnecessary power consumption, the host suspends the VBUS bus when it is idle. When the slave device needs to use the VBUS bus, it requests the host to enable the VBUS bus through the SRP circuit, thereby providing power to non-self-powered modules. Specifically, as... Figure 1As shown, the SRP circuit includes a session valid comparator and a VBUS valid comparator. The divided voltage signals 7 / 20VBUS and 1 / 4VBUS are respectively input to the negative input terminals of the session valid comparator and the VBUS valid comparator. The positive input terminal of the session valid comparator is connected to the reference voltage signal SESSVREF, and the output is the session valid signal Sessvalid. The positive input terminal of the VBUS valid comparator is connected to the reference voltage signal VBUSVREF, and the output is the VBUS valid signal Vbusvalid.

[0029] During master-slave identification and disconnection detection, the SRP circuit is in the off state. After the above functions are completed, the master-slave identification circuit and ADP comparator will be turned off, while the VBUS valid comparator and session valid comparator will be turned on. During the SRP function implementation, according to the USB 2.0 protocol requirements, the VBUS bus needs to be charged to approximately 4.4V within approximately 100ms by an external regulated charge pump to meet the power supply requirements of other modules. To prevent damage to the MOSFETs in the circuit due to overvoltage, the VBUS voltage needs to be divided. Specifically, the VBUS voltage is reduced to approximately 7 / 20 VBUS by the voltage divider sampling charge-discharge circuit and then connected to the negative input terminal of the session valid comparator, which is compared with the reference voltage signal SESSVREF. When the VBUS voltage reaches approximately 0.6V, the output of the session valid comparator will jump to a high level, indicating that the charging process has started, and then the session valid signal Sessvalid will be transmitted to the host computer for processing. Simultaneously, the VBUS voltage, after being reduced to approximately 1 / 4 VBUS by the voltage divider sampling and charging / discharging circuit, is connected to the negative input of the VBUS valid comparator and compared with the reference voltage signal VBUSVREF (1.1V). When the VBUS voltage reaches 4.4V, the output of the VBUS valid comparator will jump to a high level, indicating that the voltage on the VBUS bus has reached the power supply requirement, and then the VBUS valid signal Vbusvalid will be transmitted to the host computer for processing. When both the session valid signal Sessvalid and the VBUS valid signal Vbusvalid jump to a high level, it indicates that the SRP function is complete. However, it should be noted that the output of the VBUS valid comparator jumping to a high level only indicates that the voltage on the VBUS bus has reached the power supply threshold (4.4V), and does not mean that the charging process is over. According to the USB 2.0 protocol requirements, the voltage on the VBUS bus will continue to rise and remain stable thereafter (its final stable value depends on the design parameters of the external regulated charge pump that charges the VBUS bus) to meet the needs of normal operation and power supply.

[0030] Finally, it should be noted that in this invention, the voltage divider sampling charge-discharge circuit plays different roles in different operating stages: During disconnection detection, the voltage divider sampling charge-discharge circuit charges and discharges the VBUS bus under the control of charging and discharging signals (its input / output ports are used as outputs at this time), essentially charging and discharging the equivalent capacitance on the VBUS bus. Since the bus capacitance differs between the disconnected and connected states, disconnection detection can be achieved by comparing the time required for the capacitor to fully charge; the voltage amplitude involved is relatively low at this time. However, when performing the SRP function, an external regulated charge pump charges the VBUS bus (the input / output ports of the voltage divider sampling charge-discharge circuit are used as inputs at this time), raising the bus voltage to approximately 4.4V to meet power supply requirements. At this time, the voltage divider sampling charge-discharge circuit divides this VBUS voltage to obtain 7 / 20VBUS and 1 / 4VBUS divided voltage signals, which are used for comparison and judgment by the session valid comparator and the VBUS valid comparator, respectively, thereby realizing the SRP function.

[0031] This invention utilizes a master-slave identification circuit, an ADP circuit, and an SRP circuit working in concert to identify the master and slave devices during connection, detect disconnection / connection status, and determine whether the VBUS bus voltage has reached the session validity threshold and power supply requirement threshold. The master-slave identification circuit and the ADP circuit share an external resistor, allowing for simultaneous disconnection detection during master-slave identification without the need for an additional reference voltage generation circuit, thus reducing chip area. Furthermore, the required reference voltage signal Ref_prb can be flexibly generated by adjusting the internal or external resistor, improving the circuit's reliability and adaptability.

Claims

1. An OTG analog circuit conforming to the USB 2.0 protocol, comprising a master-slave identification circuit, an ADP circuit, and an SRP circuit, characterized in that: The master-slave identification circuit identifies the master or slave device by determining whether the external resistor is in a grounded or floating state. During the master-slave identification process, the ADP circuit simultaneously detects the disconnection or connection of the device and determines the connection status of the VBUS bus, providing a basis for the master's judgment. When identifying the master or slave device and detecting disconnection or connection, the SRP circuit is in a closed state. When the master-slave identification circuit and the ADP circuit are closed, the SRP circuit is open. When the slave device needs to use the VBUS bus, the SRP circuit requests the master to enable the VBUS bus.

2. The OTG analog circuit conforming to the USB 2.0 protocol requirements according to claim 1, characterized in that: The master-slave identification circuit includes an ACA circuit, which is connected to the external resistor. At its connection node, a reference voltage signal Ref_prb is generated by voltage division. The comparator of the ACA circuit compares the reference voltage signal Ref_prb with the voltage signal generated by voltage division under the action of the control signal PU generated by the external circuit, and inputs the comparison result to the logic circuit to generate a master-slave identification signal. The master and slave are determined by detecting the high or low level of the master-slave identification signal.

3. The OTG analog circuit conforming to the USB 2.0 protocol requirements according to claim 2, characterized in that: The ACA circuit includes comparators Comp1 to Comp4, a current unit composed of a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, and a fifth PMOS transistor M5, a voltage divider unit composed of voltage divider resistors R1 to R9, and the logic circuit composed of NOR gates NOR1 to NOR3, an inverter INV1, and a NAND gate NAND1. The current from the current unit is divided by the voltage divider resistors in the voltage divider unit to form voltage signals, which are then input to comparators Comp1 to Comp4 to obtain voltage comparison results a1 to a4. These results are then input to the logic circuit for logical operations to generate master-slave identification signals ridfloat and ridgnd. When ridfloat is detected to be low and ridgnd to be high, it indicates that the resistance of the external resistor is in the ground range, and the device is determined to be the master. When ridfloat is detected to be high and ridgnd to be low, it indicates that the resistance of the external resistor is in the floating range, and the device is determined to be the slave.

4. The OTG analog circuit conforming to the USB 2.0 protocol requirements according to claim 3, characterized in that: The gates of PMOS transistors M1 to M5 are connected and serve as the input terminals of the ACA circuit, with their sources connected to a voltage source. The drain of the first PMOS transistor M1 is connected to a voltage divider resistor R1. The other end of the voltage divider resistor R1 serves as the first output terminal of the ACA circuit and is connected to the negative input terminals of comparators Comp1 to Comp4, respectively. The drain of the second PMOS transistor M2 is connected to a voltage divider resistor R2. The other end of the voltage divider resistor R2 is connected to a voltage divider resistor R3 and is connected to the positive input terminal of comparator Comp1. The drain of the third PMOS transistor M3 is connected to a voltage divider resistor R4. The other end of the voltage divider resistor R4 is connected to a voltage divider resistor R5 and is connected to the positive input terminal of comparator Comp2. The drain of the fourth PMOS transistor M4 is connected to a voltage divider resistor R6. The other end of the voltage divider resistor R6 is connected to a voltage divider resistor R7 and is connected to the positive input terminal of comparator Comp3. The drain of the fifth PMOS transistor M5 is connected to a voltage divider resistor R8. The other end of the voltage divider resistor R8 is connected to a voltage divider resistor R9 and is connected to a voltage divider resistor R9. Connect the positive input terminal of comparator Comp4; the other ends of voltage divider resistors R3, R5, R7, and R9 are grounded; the output a1 of comparator Comp1 is connected to one input terminal of NOR gate NOR2; the output a2 of comparator Comp2 is connected to one input terminal of NOR gate NOR3 and serves as the second output terminal of the ACA circuit; the output a3 of comparator Comp3 is connected to one input terminal of NOR gate NOR3; the output a4 of comparator Comp4 is connected to one input terminal of NOR gate NOR2; the output terminals of NOR gates NOR2 and NOR3 are respectively connected to the input terminals of NAND gate NAND1, and the output terminal of NAND gate NAND1 is connected to one input terminal of NOR gate NOR1; the input terminal of inverter INV1 is connected to the gate of PMOS transistors M1 to M5, and the output terminal is connected to another input terminal of NOR gate NOR1; the output terminal of NOR gate NOR1 serves as the third output terminal of the ACA circuit; the output logic relationship expression is: ridfloat = a2; ridgnd = .

5. The OTG analog circuit conforming to the USB 2.0 protocol requirements according to claim 2, 3, or 4, characterized in that: The ADP circuit includes a voltage divider sampling charge / discharge circuit and an ADP comparator. The voltage divider sampling charge / discharge circuit receives voltage signals V1, V2, a charging signal, and a discharging signal generated by an external circuit, and generates several voltage divider signals. The voltage divider sampling charge / discharge circuit has input / output ports, which are connected to the ADP comparator via a VBUS bus. The ADP comparator compares the voltage divider signals output from the input / output ports with the reference voltage signal Ref_prb, and outputs a disconnection detection signal. The disconnection or connection status of the device is determined based on the time required for the disconnection detection signal to change.

6. The OTG analog circuit conforming to the USB 2.0 protocol requirements according to claim 5, characterized in that: Under the control of the charging signal, the voltage divider sampling charge-discharge circuit charges the equivalent capacitance of the VBUS bus to increase the voltage on the VBUS bus; when the voltage on the VBUS bus rises to be equal to the reference voltage signal Ref_prb, the output signal of the ADP comparator jumps to a high level. If the time of the high level jump is short, it is determined to be in a disconnected state; if the time of the high level jump is long, it is determined to be in a connected state.

7. The OTG analog circuit conforming to the USB 2.0 protocol requirements according to claim 6, characterized in that: The SRP circuit includes a session valid comparator and a VBUS valid comparator. The session valid comparator receives the divided voltage signal generated by the voltage divider sampling charge-discharge circuit and the reference voltage signal SESSVREF generated by the external circuit, and outputs a session valid signal. When the session valid signal jumps to a high level, it is transmitted to the host computer for processing. The VBUS valid comparator receives the divided voltage signal generated by the voltage divider sampling charge-discharge circuit and the reference voltage signal VBUSVREF generated by the external circuit, and outputs a VBUS valid signal. When the VBUS valid signal jumps to a high level, it is transmitted to the host computer for processing.

8. The OTG analog circuit conforming to the USB 2.0 protocol requirements according to claim 7, characterized in that: The input / output ports are connected to an external regulated charge pump. When the ADP comparator is turned off, the VBUS bus is charged through the external regulated charge pump. The voltage divider sampling charge / discharge circuit divides the voltage of the VBUS bus to obtain two different voltage divider signals, which are then connected to the session valid comparator and the VBUS valid comparator, respectively.

9. The OTG analog circuit conforming to the USB 2.0 protocol requirements according to claim 8, characterized in that: The voltage divider sampling charge-discharge circuit includes PMOS transistors M1, M2, M5, M6, M8, M13, M15 to M18, M20, M22 and M23, NMOS transistors M3, M4, M7, M9 to M12, M14, M19, M21 and M24 to M26, resistors R1 to R11, inverter INV1, NAND gate NAND1, and current source CS1. The gates of PMOS transistors M1 and M2 are interconnected with the gates of NMOS transistors M3 and M4, and connected to the drain of PMOS transistor M8 and one end of resistors R4 and R6. The source of M1 is connected to the source of M8, the gate of NMOS transistor M19, the source of PMOS transistor M22, and the PMOS transistor... The gate of transistor M23 is connected to resistor R1 and serves as the first input terminal of the voltage divider sampling charge-discharge circuit, receiving voltage signal V2. The drain of M1 is connected to the source of M2, and together with the other end of R1 and the source of PMOS transistor M5, it is connected to the power supply. The drain of M2 is connected to the drain of M3, and is connected to the gates of PMOS transistors M5 and M6, and NMOS transistor M7. The source of M3 is connected to the drain of M4, and the source of M4 is grounded. The drain of M5 is connected to the source of M6, and the drains of M6 and M7 are connected together to one input terminal of NAND gate NAND1, and the source of M7 is grounded. The gate of M8 is connected to a voltage source via resistor R11. One end of current source CS1 serves as the voltage divider sampling charge-discharge circuit. The second input terminal of the circuit is controlled by voltage signal V1. Its output terminal is connected to resistor R2 and the gates of NMOS transistors M9 and M11. The other end of R2 is connected to the drain of M9 and the gates of NMOS transistors M10 and M12. The sources of M9 and M11 are connected to the drains of M10 and M12, respectively, and the sources of M10 and M12 are grounded. The drain of M11 is connected to the source of NMOS transistor M14. The drain of M14 is connected to the drain of PMOS transistor M13 and is connected to resistor R3 and the gates of PMOS transistors M16 and M18. The gates of M13 and M14 are connected, serving as the third input terminal of the voltage divider sampling charge-discharge circuit, controlled by the charging signal. The source of M13 is connected to... Power supply; the other end of R3 is connected to the drain of M16 and the gates of PMOS transistors M15 and M17. The sources of M15 and M17 are both connected to the power supply, and their drains are connected to the sources of M16 and M18, respectively. The drain of M18 is connected to the drain of M19, and the source of M19 is connected to the drain of NMOS transistor M26. The input of inverter INV1 is connected to the gate of NMOS transistor M21 and serves as the fourth input of the voltage divider sampling charge-discharge circuit, receiving the discharge signal. Its output is connected to the other input of NAND1. The output of NAND1 is connected to the gate of PMOS transistor M20. The source of M20 is connected to the power supply, and its drain is connected to the drain of M21 and the drain of NMOS transistor M24. The source of M21 is grounded; the gate of M24 is connected to the power supply, and its source is connected to the drain of NMOS transistor M25; the gate of PMOS transistor M22 is connected to resistors R7 and R8 and the drain of PMOS transistor M23; the source of M23 is connected to the drain of M22, and together they are connected to the gates of M25 and M26; the drain of M23 and the sources of M25 and M26 are connected to the VBUS bus via resistors R8, R9, and R10 respectively, and serve as the input and output ports of the voltage divider sampling charge and discharge circuit; the other end of R7 is connected to R6, serving as the first output terminal of the voltage divider sampling charge and discharge circuit, outputting a divided voltage signal of 7 / 20VBUS; the other end of R6 is connected to R4, and the other end of R4 is connected to resistor R5, serving as the second output terminal of the voltage divider sampling charge and discharge circuit, outputting a divided voltage signal of 1 / 4VBUS; the other end of R5 is grounded.

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