Pixel driving circuit, display screen and electronic device

Abstract

The present application provides a pixel driving circuit, a display screen and an electronic device, and belongs to the technical field of display. The pixel driving circuit comprises: a first driving unit, configured to generate a first driving current according to an amplitude modulation signal included in a data signal, and drive a pixel to emit light through the first driving current in a pulse amplitude modulation period included in a frame period, the data signal comprising N bits, the amplitude modulation signal comprising n consecutive bits in the data signal, N being a positive integer, and n being an integer greater than 1 and less than N; and a second driving unit, configured to control the on time of a second driving current according to a width modulation signal included in the data signal in a pulse width modulation period included in the frame period, the second driving current driving the pixel to emit light when turned on, the width modulation signal comprising N-n bits in the data signal except the amplitude modulation signal. The present application can solve the problems of visual flicker, motion blur and color separation.

Description

Technical Field

[0001] This article relates to the field of display technology, and in particular to a pixel driving circuit, a display screen, and an electronic device. Background Technology

[0002] Micro-LEDs (Micro Light Emitting Diodes) combine advantages such as high brightness, long lifespan, high contrast, and low power consumption, and are one of the development directions of next-generation display technologies.

[0003] Currently, Micro-LED display devices typically use a digital pulse width modulation (D-PWM) driving scheme.

[0004] However, when driving Micro-LEDs using the D-PWM driving scheme, in order to solve problems such as visual flicker, motion blur, and color separation in Micro-LED display devices, it is necessary to increase the frame rate for compensation. However, the duration of the subframes corresponding to the lower bits of the data signal is relatively short, which limits the increase in frame rate and cannot effectively solve the problems of visual flicker, motion blur, and color separation. Summary of the Invention

[0005] In view of this, a pixel driving circuit, a display screen, and an electronic device are provided to at least solve or alleviate the above-mentioned problems.

[0006] In one scenario, a pixel driving circuit is provided, comprising: a first driving unit, configured to generate a first driving current based on an amplitude modulation signal included in a data signal, and drive a pixel to emit light through the first driving current during a pulse amplitude modulation period included in a frame period, wherein the data signal is used to indicate the grayscale level of the pixel, the data signal includes N bits, and the amplitude modulation signal includes n consecutive bits of the data signal, where N is a positive integer and n is an integer greater than 1 and less than N; and a second driving unit, configured to control the conduction time of a second driving current based on a width modulation signal included in the data signal during a pulse width modulation period included in the frame period, wherein the second driving current drives the pixel to emit light when it is on, and the width modulation signal includes Nn bits of the data signal excluding the amplitude modulation signal.

[0007] In another scenario, a display screen is provided, comprising a plurality of pixels and a plurality of the aforementioned pixel driving circuits, each of the pixels being electrically connected to one of the pixel driving circuits.

[0008] In another case, an electronic device is provided, including the aforementioned display screen.

[0009] Based on the above scheme, a first driving current is generated according to the amplitude modulation signal included in the data signal. During the pulse amplitude modulation period, the first driving current drives the pixel to emit light, and grayscale level control is achieved through pulse amplitude modulation. During the pulse width modulation period, the conduction time of the second driving current is controlled according to the width modulation signal included in the data signal, and grayscale level control is achieved through pulse width modulation. The amplitude modulation signal corresponds to one subframe, and the duration of the subframe corresponding to the amplitude modulation signal is relatively short. If pulse width modulation is used, it will be difficult to achieve accurate grayscale control due to the narrow allocated pulse width interval, and it may even be impossible to form an effective driving pulse. Pulse amplitude modulation is used for the amplitude modulation signal, and grayscale expression is achieved by directly adjusting the driving current amplitude, without relying on the pulse width duty cycle. This adapts to the short subframe timing, solves the problem that pulse width modulation is not applicable to bit positions in short subframes, and ensures the accuracy of grayscale control. Using pulse amplitude modulation within short subframes can reduce the clock frequency, thereby reducing the power consumption of the pixel driving circuit. The subframe time corresponding to the width-modulated signal is relatively long, providing sufficient temporal space for pulse width allocation. By reasonably increasing the frame rate, problems such as visual flicker, motion blur, and color separation can be effectively solved. For the differences in subframe duration corresponding to different bit bits, pulse amplitude modulation and pulse width modulation are used respectively to match the driving method with the temporal structure. This ensures complete grayscale resolution while improving driving reliability and image stability, reducing display defects such as flicker and false outlines. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the examples or prior art described herein, the accompanying drawings used in the description of the examples or prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some examples recorded in this article, and those skilled in the art can obtain other drawings based on these drawings.

[0011] Figure 1 This is a schematic diagram of a pixel driving circuit as an example in this article; Figure 2 This is a schematic diagram of another example of a pixel driving circuit in this article; Figure 3 This is a schematic diagram illustrating the correspondence between data signals and sub-time periods, as exemplified in this article. Figure 4 This is another example in this article illustrating the correspondence between data signals and sub-time periods; Figure 5 This is another example in this article illustrating the correspondence between data signals and sub-time periods; Figure 6 This is a schematic diagram of a timing pattern used in an example of this article; Figure 7 This is a schematic diagram of another timing pattern in this article; Figure 8 This is a schematic diagram illustrating the temporal pattern distribution of an example from this article; Figure 9 This is a schematic diagram of the temporal pattern distribution, another example from this article. Detailed Implementation

[0012] The examples herein will now be described in more detail with reference to the accompanying drawings. While some examples of this document are shown in the drawings, it should be understood that this document can be implemented in various forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided to provide a more thorough and complete understanding of this document. It should be understood that the accompanying drawings and examples are for illustrative purposes only and are not intended to limit the scope of this document.

[0013] It should be noted that the headings of any section / subsection provided herein are not restrictive. Various examples are described throughout this document, and examples of any type may be included under any section / subsection. Furthermore, examples described in any section / subsection may be combined in any way with any other examples described in the same section / subsection and / or different sections / subsections.

[0014] In the description of the examples in this document, the term "including" and similar terms should be understood as open inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an example" or "the example" should be understood as "at least one example". The term "some examples" should be understood as "at least some examples". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0015] The examples in this document may involve user data, data acquisition, and / or use. All of these aspects comply with relevant laws, regulations, and rules. In the examples presented herein, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing each example in this document, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario; the scope of this document is not limited in this regard.

[0016] In this manual and the sample solutions, any processing of personal information will be conducted only under legal grounds (such as obtaining the consent of the data subject or being necessary for the performance of a contract) and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

[0017] First, some nouns or terms that appear in the description of the examples in this article shall be interpreted as follows: Micro-LEDs: Micro-LEDs are miniaturized light-emitting diodes made from inorganic compound semiconductor materials, with a single chip side length of no more than 100μm. They are active-matrix self-emissive display units capable of pixel-level independent addressing and driving. Unlike the passive light-emitting architecture of Liquid Crystal Displays (LCDs), the organic light-emitting material system of Organic Light-Emitting Diodes (OLEDs), and Mini-LED technology used only as a backlight solution, Micro-LEDs offer advantages such as high brightness, long lifespan, high contrast, and low power consumption, making them one of the development directions for next-generation display technologies.

[0018] Frame rate: Frame rate refers to the number of complete frames displayed per unit of time, and the unit is Hertz (Hz) or frames per second (fps).

[0019] Frame period: The frame period refers to the total time from the start of a scan to the end of the scan and the start of the next frame. It is the reciprocal of the frame rate. For example, when the frame rate is 60Hz, the frame period is approximately 16.67ms.

[0020] Digital Pulse Width Modulation (D-PWM) refers to a modulation method that generates a pulse sequence with a fixed frequency and amplitude digitally and precisely adjusts the high-level duration (width) of the pulses using digital control, thereby changing the equivalent average value of the output signal.

[0021] Pulse Amplitude Modulation (PAM) is a modulation method that adjusts the signal magnitude by changing the amplitude (voltage / current amplitude) of a pulse signal while keeping the pulse width and frequency essentially constant.

[0022] Grayscale: Grayscale refers to the entire range of pixel brightness that varies continuously from pure black (lowest brightness) to pure white (highest brightness), as well as the different brightness levels that can be presented within this range.

[0023] The pixel driving circuit, display screen, and electronic device provided herein are described in detail below with reference to the accompanying drawings.

[0024] Pixel driving circuit Figure 1 A schematic diagram of a pixel driving circuit 10 is shown. (As shown) Figure 1 As shown, the pixel driving circuit 10 includes a first driving unit 11 and a second driving unit 12.

[0025] The first driving unit 11 can generate a first driving current based on the amplitude modulation signal included in the data signal, and drive the pixel to emit light through the first driving current during the pulse amplitude modulation period included in the frame period. The data signal can indicate the grayscale level of the pixel, and the grayscale level indicates the brightness of the pixel; different grayscale levels correspond to different brightness levels of the pixel. During the display screen's image display process, each frame corresponds to a data signal. The pixel can be a Micro-LED.

[0026] An amplitude-modulated signal consists of n consecutive bits from a data signal. The data signal contains N bits, where N is a positive integer and n is an integer greater than 1 and less than N. A data signal containing N bits can indicate N levels of grayscale, meaning different data signals indicate different grayscale levels. The data signal can indicate 2^N grayscale levels. N There are 2 gray levels. In one example, if N equals 8, the data signal can indicate 2. 8 There are 8 gray levels, corresponding to 8 bits of grayscale; if N equals 10, the data signal can indicate 2 10 Each gray level corresponds to 10 grayscale levels.

[0027] The amplitude modulation signal can be located at any position in the data signal. If the amplitude modulation signal is located in the low-order bits of the data signal, then the low n bits of the data signal are the amplitude modulation signal. If the amplitude modulation signal is located in the high-order bits of the data signal, then the high n bits of the data signal are the amplitude modulation signal. If the amplitude modulation signal is located in the middle position of the data signal, then bits i to i+n-1 of the data signal are the amplitude modulation signal, where i is an integer greater than 1 and less than N-n+1.

[0028] In one example, n takes the value 2, and the data signal includes 10 bits. If the data signal is [1001110010], the amplitude modulation signal is the lower 2 bits of the data signal, and the lower 2 bits of the data signal are

[10] , so the first driving unit 11 generates the corresponding first driving current according to

[10] . If the data signal is [0110001101], the amplitude modulation signal is the higher 2 bits of the data signal, and the higher 2 bits of the data signal are

[01] , so the first driving unit 11 generates the corresponding first driving current according to

[01] . If the data signal is [1001110010], the amplitude modulation signal is the lower 5-6 bits of the data signal, and the lower 5-7 bits of the data signal are

[111] , so the first driving unit 11 generates the corresponding first driving current according to

[111] .

[0029] The second driving unit 12 can control the conduction time of the second driving current according to the width modulation signal included in the data signal during the pulse width modulation period included in the frame period. When the second driving current is turned on, it drives the pixel to emit light. The width modulation signal includes Nn bits of the data signal excluding the amplitude modulation signal. If the amplitude modulation signal is the lower n bits of the data signal, then the width modulation signal is the higher Nn bits of the data signal. If the amplitude modulation signal is the higher n bits of the data signal, then the width modulation signal is the lower Nn bits of the data signal. If the amplitude modulation signal is the lower i to i+n-1 bits of the data signal, where i is an integer greater than 1 and less than N-n+1, ​​then the width modulation signal is the lower 1 to i-1 bits and the lower i+n to N bits of the data signal.

[0030] The frame period consists of a pulse amplitude modulation (PAM) period and a pulse width modulation (PWM) period. The PAM period precedes the PWM period; for example, the end time of the PAM period is the start time of the PWM period. The duration of the frame period is greater than or equal to the sum of the durations of the PAM and PWM periods, and there is no overlap between them. In one example, the duration of the PAM period is shorter than the duration of the PWM period, and the ratio of the PAM to PWM durations is related to the number of bits in the data signal, for example, it is negatively correlated with the number of bits in the data signal.

[0031] Given a constant first driving current, the conduction time of the second driving current during the pulse width modulation (PWM) period is positively correlated with the pixel brightness; that is, the longer the conduction time of the second driving current, the higher the pixel brightness in the corresponding frame. The conduction time of the second driving current varies during the PWM period depending on the PWM signal, therefore the PWM signal can indicate 2... N-n Each grayscale level.

[0032] Given a fixed conduction time for the second driving current, the current value of the first driving current is related to the pixel brightness. For example, the current value of the first driving current is positively correlated with the pixel brightness; that is, the larger the first driving current, the higher the pixel brightness in the corresponding frame. The first driving current varies depending on the amplitude modulation signal, and the first driving unit 11 can generate different values ​​based on the amplitude modulation signal. n The first drive current, therefore the amplitude modulation signal can indicate 2 n Each grayscale level.

[0033] Based on a data signal containing N bits, n-bit grayscale control can be achieved through pulse amplitude modulation during the pulse amplitude modulation period, and Nn-bit grayscale control can be achieved through pulse width modulation during the pulse width modulation period. Combining pulse amplitude modulation and pulse width modulation can achieve N-bit grayscale control.

[0034] A first driving current is generated based on the amplitude modulation signal included in the data signal. During the pulse amplitude modulation period, the first driving current drives the pixel to emit light, and grayscale level control is achieved through pulse amplitude modulation. During the pulse width modulation period, the conduction time of the second driving current is controlled according to the width modulation signal included in the data signal, and grayscale level control is achieved through pulse width modulation. The amplitude modulation signal corresponds to one subframe, and the duration of the subframe corresponding to the amplitude modulation signal is relatively short. If pulse width modulation is used, it will be difficult to achieve accurate grayscale control due to the narrow allocated pulse width interval, and it may even be impossible to form an effective driving pulse. Pulse amplitude modulation is used for the amplitude modulation signal, and grayscale expression is achieved by directly adjusting the driving current amplitude, without relying on the pulse width duty cycle. This adapts to the short subframe timing and solves the problem that bit bits cannot be used with PWM modulation in short subframes, ensuring the accuracy of grayscale control. Using pulse amplitude modulation within short subframes can reduce the clock frequency, thereby reducing the power consumption of the pixel driving circuit. The subframe time corresponding to the width modulation signal is relatively long, providing sufficient timing space to allocate the pulse width. By reasonably increasing the frame rate, problems such as visual flicker, motion blur, and color separation can be effectively solved. To address the differences in subframe duration corresponding to different bit positions, PAM modulation and PWM modulation are adopted respectively to match the driving method with the timing structure. While ensuring complete grayscale resolution, this improves driving reliability and image stability, and reduces display defects such as flickering and false outlines.

[0035] In one scenario, when the amplitude modulation signal is different, the first driving unit 11 generates different first driving currents, and the first driving current is less than the second driving current.

[0036] Amplitude modulation signals consist of n bits, each bit can take the value 1 or 0, and the n bits can be arranged in combinations to form 2. n Therefore, the first driving unit 11 can generate 2 different amplitude modulation signals.n There are four different first drive currents. For example, when the amplitude modulation signal includes two bits, the amplitude modulation signal can be

[00] ,

[01] ,

[10] or

[11] , so the first drive unit 11 can generate four different first drive currents.

[0037] By setting the first driving current to be less than the second driving current, fine-tuning of the n-bit grayscale can be achieved using a smaller amplitude first driving current during the amplitude modulation period. This avoids the problem of excessive adjustment of low-bit grayscale and decreased brightness control precision due to excessive current. Different amplitude modulation signals correspond to different magnitudes of the first driving current, enabling precise and linear multi-level fine-tuning of the n-bit grayscale, ensuring delicate low-bit display layers and smooth transitions. Setting the first driving current to be less than the second driving current allows for a reasonable distribution of brightness contribution between the two driving methods, matching the subframe duration corresponding to the bit. This prevents short-duration PAM subframes from becoming too bright due to excessive current, ensuring uniform brightness across the entire frame, further improving screen flicker and brightness unevenness, and enhancing display quality.

[0038] In one scenario, the first driving unit 11 includes n first current sources and n first switches. Each first current source is electrically connected to a pixel via a first switch, and different first current sources are electrically connected to the pixel via different first switches. The output currents of the n first current sources are respectively... to The product of the second drive current.

[0039] In a set of n first switches, the i-th first switch is closed or open based on the i-th bit of the amplitude modulation signal, where i is a positive integer less than or equal to n. For example, when the i-th bit of the amplitude modulation signal is 1, the i-th first switch is closed; when the i-th bit of the amplitude modulation signal is 0, the i-th first switch is open.

[0040] In one example, the amplitude-modulated signal consists of two consecutive bits from the data signal. For example... Figure 2 The schematic diagram of the pixel driving circuit 10 shown includes a first driving unit 11 comprising a first current source I11, a first current source I12, a first switch S11, and a first switch S12. The first current source I11 is electrically connected to one end of the first switch S11, and the other end of the first switch S11 is electrically connected to the source of the switching transistor M1. The first current source I12 is electrically connected to one end of the first switch S12, and the other end of the first switch S12 is electrically connected to the source of the switching transistor M1. The drain of the switching transistor M1 is electrically connected to the anode of the pixel (light-emitting diode) D, and the cathode of the pixel D is grounded. An emission enable (EM) signal is input to the gate of the switching transistor M1; the switching transistor M1 is turned on when the data signal drives the pixel D to emit light.

[0041] The second driving current has a value of I0, the output current of the first current source I11 has a value of I0 / 2, and the output current of the first current source I12 has a value of I0 / 4. Depending on the amplitude modulation signal, the first switches S11 and S12 are selectively closed. In one example, when the amplitude modulation signal is

[00] , both the first switches S11 and S12 are open, and the first driving current is 0. When the amplitude modulation signal is

[01] , the first switch S11 is open while the first switch S12 is closed, and the first driving current is I0 / 4. When the amplitude modulation signal is

[10] , the first switch S11 is closed while the first switch S12 is open, and the first driving current is I0 / 2. When the amplitude modulation signal is

[11] , both the first switches S11 and S12 are closed, and the first driving current is I03 / 4.

[0042] A first driving unit 11 is constructed by setting n first current sources and n first switches, and the output current of each first current source is the second driving current multiplied by [missing information]. to It can correspond one-to-one with the n bits of the amplitude modulation signal to achieve binary weighted amplitude modulation. Each first switch is independently turned on or off according to the corresponding bit of the amplitude modulation signal, which can accurately combine multiple levels of first drive current to ensure high linearity of grayscale adjustment, uniform quantization, and precise control.

[0043] The first driving unit 11 adopts a binary weighted current source structure, which has a regular circuit structure and is easy to integrate. It can realize multi-level current output without complex digital-to-analog conversion circuits, simplifying the driving circuit structure and reducing hardware implementation costs and control complexity. The weights of each first current source are strictly corresponding to the bits, which makes the brightness matching degree between the n-bit grayscale adjustment of the amplitude modulation signal and the Nn-bit grayscale adjustment of the width modulation signal higher, improving the brightness consistency of the whole frame and avoiding the false contour and flickering problems caused by uneven pulse amplitude modulation.

[0044] In one scenario, the pulse width modulation (PWM) period comprises M sub-periods, where M equals Nn, meaning each bit of the PWM signal corresponds to one sub-period. The amplitude modulation (AM) signal controls the current value of the first drive current within an independent sub-period, while the PWM signal controls the duty cycle of the second drive current over the Nn sub-periods. This divides the frame period into N-n+1 sub-periods, with one sub-period using pulse amplitude modulation and the other Nn sub-periods using pulse width modulation. Each sub-period corresponds to a subframe, and a frame is divided into N-n+1 subframes, each corresponding to a sub-period. The brightness of a pixel within a single frame is controlled by adjusting the brightness of the pixel in each subframe.

[0045] The second driving unit 12 can control the second driving current to be turned on or off within a corresponding sub-period based on the bit position of the width modulation signal. When the second driving current is on, the pixel emits light; when the second driving current is off, the pixel is off. For each bit in the width modulation signal, if the bit is a first bit value, the second driving unit 12 controls the second driving current to be turned on within the sub-period corresponding to that bit; if the bit is a second bit value, the second driving unit 12 controls the second driving current to be turned off within the sub-period corresponding to that bit.

[0046] The first and second bits can be either binary 0 or 1. When the first bit is binary 0, the second bit is binary 1. When the first bit is binary 1, the second bit is binary 0.

[0047] In one example, such as Figure 3 The diagram shows the correspondence between the data signal and the sub-time periods. The data signal consists of 10 bits, with the lower 2 bits representing the amplitude modulation signal and the higher 8 bits representing the width modulation signal. The sub-time period corresponding to the amplitude modulation signal is sub-time period XA. Following the order from the lowest bit to the highest bit, the sub-time periods corresponding to the 8 bits of the width modulation signal are sub-time periods X0 to X7, respectively.

[0048] The first driving unit 11 controls the current value of the first driving current in sub-segment XA according to the lower 2 bits (amplitude modulation signal) of the data signal, thereby realizing pulse amplitude modulation in sub-segment XA. Following the order from low to high bits, the second driving unit 12 controls whether the second driving current is turned on in sub-segment X(i-3) according to the i-th bit of the data signal. For example, it controls whether the second driving current is turned on in sub-segment X0 according to the 3-th bit of the data signal, whether it is turned on in sub-segment X2 according to the 5-th bit of the data signal, and whether it is turned on in sub-segment X7 according to the 10-th bit of the data signal, thereby realizing pulse width modulation in sub-segments X0 to X7.

[0049] The pulse width modulation (PWM) period is divided into M sub-periods, where M is equal to the number of bits in the PWM signal. This allows each bit of the PWM signal to be driven and controlled independently within a sub-period, achieving bit-by-bit sub-frame PWM. The grayscale control logic is clear, and the timing is well-defined. The second driving unit 12 controls the second driving current to be turned on or off within the corresponding sub-period based on the value of the corresponding bit, enabling precise brightness weighted adjustment and ensuring good linearity and high precision in brightness control. The one-to-one correspondence between sub-periods and the number of bits fully utilizes the longer sub-frame timing space, avoiding driving instability caused by excessively narrow pulse widths. Combined with a high frame rate, this further improves screen flicker. This driving method complements the amplitude modulation of the first driving unit 11; the amplitude modulation signal and the PWM signal drive do not interfere with each other, resulting in complete overall grayscale levels, smooth screen transitions, and a simple circuit control timing, making it easy for the driving chip to implement.

[0050] In one scenario, a width-modulated signal comprises m source bits and k associated bits, where m + k equals Nn, and m and k are both positive integers. This means the sum of the number of source bits and associated bits equals the total number of bits in the width-modulated signal. Each associated bit corresponds to one source bit. Some of the m source bits have corresponding associated bits, and a source bit with an associated bit can correspond to one or more associated bits. The bit value of the associated bit is the same as the corresponding source bit. Therefore, the data signal can indicate 2... m+n A grayscale level, a certain data signal indicates 2. m+n One of the grayscale levels. k associated bits correspond to sub-segments of the same duration, and the duration of the sub-segment corresponding to the source bit is less than or equal to the duration of the sub-segment corresponding to the associated bit.

[0051] like Figure 4 The diagram illustrates the correspondence between the data signal and the sub-time period. The data signal comprises 14 bits, with the lower 2 bits representing the amplitude modulation signal and the higher 12 bits representing the width modulation signal. The sub-time period corresponding to the amplitude modulation signal is sub-time period XA. Following the order from least significant bit to most significant bit, bits 1 to 7 of the width modulation signal are the source bits, bit 8 is the associated bit corresponding to bit 7, bit 9 is the source bit, and bits 10-12 are the three associated bits corresponding to bit 9. In other words, the width modulation signal comprises 8 source bits and 4 associated bits.

[0052] like Figure 4As shown, in order from least significant bit to most significant bit, the first bit of the width modulated signal corresponds to sub-segment X0, the second bit to sub-segment X1, the third bit to sub-segment X2, the fourth bit to sub-segment X3, the fifth bit to sub-segment X4, the sixth bit to sub-segment X5, the seventh bit to sub-segment X6_0, the eighth bit to sub-segment X6_1, the ninth bit to sub-segment X7_0, the tenth bit to sub-segment X7_1, the eleventh bit to sub-segment X7_2, and the twelfth bit to sub-segment X7_3. In one example, L is defined as... Xi Let L be the duration of sub-time period Xi. X0 <L X1 <L X2 <L X3 <L X4 <L X5 =L X6_0 =L X6_1 =L X7_0 =L X7_1 =L X7_2 =L X7_3 .

[0053] In width-modulated signals, the source bit and its corresponding associated bit are not adjacent. For example... Figure 5 The diagram illustrates the correspondence between the data signal and the sub-time period. The data signal comprises 14 bits, with the lower 2 bits representing the amplitude modulation signal and the higher 12 bits representing the width modulation signal. The sub-time period corresponding to the amplitude modulation signal is sub-time period XA. Following the order from least to most significant bit, the 2nd, 5th, 7th, 8th, 9th, 10th, 11th, and 12th bits of the width modulation signal are the source bits; the 1st, 3rd, and 6th bits are the associated bits corresponding to the 9th bit; and the 4th bit is the associated bit corresponding to the 7th bit. In other words, the width modulation signal comprises 8 source bits and 4 associated bits.

[0054] like Figure 5As shown, in order from least significant bit to most significant bit, the first bit of the width modulated signal corresponds to sub-segment X7_1, the second bit to sub-segment X1, the third bit to sub-segment X7_2, the fourth bit to sub-segment X6_1, the fifth bit to sub-segment X4, the sixth bit to sub-segment X7_3, the seventh bit to sub-segment X6_0, the eighth bit to sub-segment X0, the ninth bit to sub-segment X7_0, the tenth bit to sub-segment X2, the eleventh bit to sub-segment X3, and the twelfth bit to sub-segment X4. In one example, L is defined as... Xi Let L be the duration of sub-time period Xi. X0 <L X1 <L X2 <L X3 <L X4 <L X5 =L X6_0 =L X6_1 =L X7_0 =L X7_1 =L X7_2 =L X7_3 .

[0055] It should be noted that, provided that the source bit and the corresponding associated bit are not adjacent, the associated bit can be located at any position in the width modulated signal.

[0056] Without increasing the number of effective grayscale levels or improving grayscale resolution, the width modulation signal is divided into source bits and associated bits. This splits the driving period corresponding to the same brightness weight into multiple non-adjacent sub-periods, preventing excessive concentration of brightness energy in time. This improves visual flicker caused by excessively bright or dark areas and solves color separation problems. Although the total number of bits in the data signal increases, the number of effective grayscale levels remains unchanged, avoiding increased driving control complexity and circuit costs due to excessive grayscale levels. By repeating the bit value corresponding to the source bit in the associated bit, a uniform distribution of brightness is achieved within the frame period, improving the softness and comfort of the image display. Setting the sub-periods corresponding to the associated bits to the same duration, and ensuring that the duration of the sub-period corresponding to the source bit is no greater than the duration of the sub-period corresponding to the associated bit, makes the brightness weight allocation and temporal distribution more reasonable. Without expanding the dynamic range, this improves luminous stability and reduces flicker and visual fatigue. By ensuring that the source bits and their corresponding associated bits are not adjacent in time, the brightness superposition effect caused by the continuous arrangement of conduction periods with the same brightness weight can be avoided, further smoothing the brightness distribution within the frame and significantly improving the display quality while maintaining the original grayscale levels.

[0057] In one scenario, among the m source bits in a width-modulated signal, h source bits correspond to different durations of their respective sub-segments, where h is an integer greater than 1 and less than m. Furthermore, among the m source bits in the width-modulated signal, m-h+1 source bits correspond to sub-segments whose durations are equal to the durations of the sub-segments corresponding to the associated bit bits.

[0058] In one example, such as Figure 4 As shown, in order from least significant bit to most significant bit, the 1st to 7th and 9th bits of the width modulation signal are source bits. The width modulation signal includes 8 source bits and 4 associated bits, i.e., m equals 8.

[0059] Following the order from least significant bit to most significant bit, the first bit of the width modulated signal corresponds to sub-segment X0, the second bit to sub-segment X1, the third bit to sub-segment X2, the fourth bit to sub-segment X3, the fifth bit to sub-segment X4, the sixth bit to sub-segment X5, the seventh bit to sub-segment X6_0, and the ninth bit to sub-segment X7_0. Define L... Xi Let L be the duration of sub-time period Xi. X0 <L X1 <L X2 <L X3 <L X4 <L X5 =L X6_0 =LX7_0 .

[0060] Following the order from least significant bit to most significant bit, the durations of the sub-segments corresponding to the 1st to 6th bits of the width modulated signal are all different, i.e., h equals 6. The durations of the sub-segments corresponding to the 6th, 7th, and 9th bits of the width modulated signal are all equal to the duration of the sub-segment corresponding to the associated bit, i.e., m-h+1 equals 3.

[0061] The width-modulated signal includes m-h+1 source bits with corresponding sub-segments of equal duration, of which mh source bits have corresponding associated bits. For example, such as Figure 4 As shown, in order from low to high bits, the 6th bit of the width modulation signal has no corresponding associated bit, the 7th and 9th bits of the width modulation signal correspond to the same duration of the sub-segment, the 8th bit of the width modulation signal is the associated bit corresponding to the 7th bit, and the 10th to 12th bits of the width modulation signal are the associated bits corresponding to the 9th bit.

[0062] By setting corresponding associated bits for the m-h+1 source bits, the problem of allocating excessively long single-segment time periods due to the lack of corresponding associated bits for these source bits is avoided, effectively improving the screen flicker and strobe defects caused by long pulse widths. Combined with the non-adjacent timing arrangement of source bits and their corresponding associated bits, the conduction period can be further evenly distributed throughout the entire pulse width modulation period, making pixel emission more continuous and brightness distribution more uniform within the frame period. While maintaining the original grayscale control precision, this improves the smoothness and stability of the displayed image, while also solving the color separation problem.

[0063] In one scenario, the width-modulated signal comprises h source bits, each corresponding to a different sub-time period. The durations of these h source bits are products of 2 raised to the power of n to n+h-1 and a unit duration, where the unit duration is multiplied by... The product of these equals the frame period.

[0064] In one example, the frame rate is 60Hz, then the unit duration The durations of the sub-time periods corresponding to the h source bits are as follows: , … For example, such as Figure 4 As shown, the data signal includes 14 bits, the amplitude modulation signal includes 2 bits, the width modulation signal includes 8 source bits and 4 associated bits, and the width modulation signal includes 6 source bits with different durations corresponding to sub-time periods. Therefore, n equals 2 and h equals 6.

[0065] Following the order from least significant bit to most significant bit, the durations of the sub-segments corresponding to the 1st to 6th bits of the width modulated signal are all different. The duration of the sub-segment X0 corresponding to the 1st bit of the width modulated signal is... The duration of sub-time period X1 corresponding to the second bit of the width-modulated signal is The duration of the sub-time period X2 corresponding to the 3rd bit of the width-modulated signal is The duration of sub-time period X3 corresponding to the 4th bit of the width-modulated signal is The duration of the sub-time period X4 corresponding to the 5th bit of the width-modulated signal is The duration of sub-segment X5 corresponding to the 6th bit of the width-modulated signal is .

[0066] The duration of the sub-time period XA corresponding to the amplitude modulation signal is Following the order from least significant bit to most significant bit, the 7th and 9th bits of the width modulated signal are the source bits. The duration of the sub-segment X6_0 corresponding to the 7th bit of the width modulated signal is... The duration of the sub-segment X7_0 corresponding to the 9th bit of the width-modulated signal is Following the order from least significant bit to most significant bit, the 8th, 10th, 11th, and 12th bits of the width modulated signal are associated bits. The duration of the sub-time period X6_1 corresponding to the 8th bit of the width modulated signal is... The duration of the sub-time period X7_1 corresponding to the 10th bit of the width-modulated signal is The duration of the sub-segment X7_2 corresponding to the 11th bit of the width-modulated signal is The duration of the sub-segment X7_3 corresponding to the 12th bit of the width-modulated signal is .

[0067] h source bits are used to The binary weighted duration setting corresponds to the pulse amplitude modulation. to The current weighting forms a continuous and complete m+n bit binary weighting system. This setting ensures that the weights of the lower grayscale levels of pulse amplitude modulation and the higher grayscale levels of pulse width modulation are perfectly matched without misalignment, maintaining consistent brightness control accuracy across the entire grayscale range and preventing any imbalance in the sensitivity of high and low grayscale adjustment. The h source bits correspond to bits with lower weights and shorter sub-segment durations; standard binary weighting is sufficient to guarantee grayscale control accuracy, eliminating the need for additional associated bits and simplifying the control logic. The remaining m... h+1 source bits, corresponding to higher weights and longer native single-segment time periods, can disperse long pulse widths through accompanying associated bits, solving the problem of screen flickering easily caused by long pulse widths in high-order bits of traditional binary PWM. This improves the flicker issue without sacrificing grayscale accuracy. The binary weighted duration division corresponds one-to-one with the grayscale bits, making the timing conversion logic simple and clear. It eliminates the need for complex nonlinear correction circuits and timing operation units, significantly reducing the design difficulty and hardware cost of the driver chip, and making it easy to apply in existing high-resolution, high-refresh-rate display driver solutions.

[0068] In one scenario, among the m source bits in the width-modulated signal, the source bit corresponding to the longest original single-segment sub-time period corresponds to... Each associated bit, that is, the original single-segment sub-time period corresponding to the source bit is divided into... Each duration is Sub-time periods. In one example, such as Figure 4 As shown, in ascending order from least significant bit to most significant bit, the original single-segment sub-times corresponding to the 9 bits of the width modulated signal are the sum of sub-times X7_0, X7_1, X7_2, and X7_3. The width modulated signal includes 8 source bits (m), and the number of source bits with different durations corresponding to each sub-time is 6 (h). Therefore, the original single-segment sub-time corresponding to the 9th bit of the width modulated signal is divided into 4 (…). There are four sub-time periods, namely sub-time period X7_0, sub-time period X7_1, sub-time period X7_2, and sub-time period X7_3. The duration of each sub-time period X7_0, sub-time period X7_1, sub-time period X7_2, and sub-time period X7_3 is equal to... .

[0069] The longest original single-segment sub-segment is split into Each sub-segment is equivalent to increasing the frame rate by [percentage] in the longest native single-segment sub-segment. The frame rate is the reciprocal of the frame period. Due to the persistence of vision, a low frame rate results in pixel flickering that is perceptible to the human eye. A flickering frame rate threshold is defined as the maximum frame rate at which pixel flickering is observable to the human eye; that is, pixel flickering is perceptible to the human eye when the frame rate is lower than the flickering frame rate threshold. If the product of the frame rate and the frame rate is greater than or equal to the flicker frame rate threshold, it is equivalent to raising the frame rate above the flicker frame rate threshold during the longest native single-segment sub-period, thereby solving the problem of visual flicker.

[0070] In one example, the flicker frame rate threshold is 180~240Hz. For example... Figure 4As shown, at a frame rate of 60Hz, the longest native single-segment sub-segment (the sum of sub-segment X7_0, sub-segment X7_1, sub-segment X7_2 and sub-segment X7_3) is split into 4 sub-segments, which is equivalent to increasing the frame rate to 240Hz in the longest native single-segment sub-segment to exceed the flicker frame rate threshold, thereby solving the visual flicker problem.

[0071] The longest native single-segment sub-period is the primary period producing visual flicker. This is achieved by breaking down the longest native single-segment sub-period into... Each sub-period is equivalent to increasing the frame rate within the longest sub-period. This multiplier ensures that the equivalent frame rate during the longest native single-segment time period is greater than or equal to the flicker frame rate threshold, thereby eliminating the perceptible flicker phenomenon from a visual mechanism perspective, improving the stability and smoothness of the displayed image, and enhancing the visual experience.

[0072] In one scenario, the pulse amplitude modulation period and the pulse width modulation period together comprise M sub-periods to form M+1 sub-periods. The timing pattern can indicate the timing of these M+1 sub-periods, and different timing patterns indicate different timings of these M+1 sub-periods.

[0073] In one example, the data signal consists of 8 bits. The lower 4 bits of the data signal are the amplitude modulation signal, and the higher 4 bits are the width modulation signal. The pulse amplitude modulation period corresponding to the amplitude modulation signal is XA. The first bit of the width modulation signal corresponds to sub-period X0, the second bit corresponds to sub-period X1, the third bit corresponds to sub-period X2, and the fourth bit corresponds to sub-period X3. The duration of sub-period XA is extended by blanking to... The duration of sub-time period X0 is The duration of sub-time period X1 is The duration of sub-time period X2 is The duration of sub-time period X3 is , The duration is expressed in units of time.

[0074] like Figure 6 The diagram shows the timing patterns. Timing pattern 1 indicates the sub-time period sequence as XA→X3→X1→X0→X2, timing pattern 2 indicates the sub-time period sequence as X3→X2→X0→XA→X1, and timing pattern 3 indicates the sub-time period sequence as X2→X1→X3→XA→X0.

[0075] In another example, such as Figure 4As shown, the pulse amplitude modulation period corresponding to the amplitude modulation signal is XA. Following the order from least significant bit to most significant bit, the first bit of the width modulation signal corresponds to sub-period X0, the second bit to sub-period X1, the third bit to sub-period X2, the fourth bit to sub-period X3, the fifth bit to sub-period X4, the sixth bit to sub-period X5, the seventh bit to sub-period X6_0, the eighth bit to sub-period X6_1, the ninth bit to sub-period X7_0, the tenth bit to sub-period X7_1, the eleventh bit to sub-period X7_2, and the twelfth bit to sub-period X7_3.

[0076] The duration of sub-time period XA is extended by blanking to The duration of sub-time period X0 is The duration of sub-time period X1 is The duration of sub-time period X2 is The duration of sub-time period X3 is The duration of sub-time period X4 is The duration of sub-time period X5 is The duration of sub-time period X6_0 is The duration of sub-time period X6_0 is The duration of sub-time period X7_0 is The duration of sub-time period X7_1 is The duration of sub-time period X7_2 is The duration of sub-time period X7_3 is , The duration is expressed in units of time.

[0077] like Figure 7The diagram shows the timing patterns. Timing pattern 1 indicates the sub-time period sequence as XA→X3→X0→X7_2→X7_1→X7_0→X6_1→X1→X4→X7_3→X6_0→X5→X2; timing pattern 2 indicates the sub-time period sequence as X5→X7_3→X0→XA→X7_2→X3→X7_1→X1→X2→X6_1→X7_0→X6_0→X4; and timing pattern 3 indicates the sub-time period sequence as X0→X7_1→X The timing sequence of the sub-period indicated by timing mode 4 is X0→X7_1→X2→X6_0→X4→X3→X7_0→X6_1→X7_3→X5→XA→X1→X7_2. The timing sequence of the sub-period indicated by timing mode 5 is X0→X7_0→X7_2→X3→X7_3→X7_1→XA→X6_1→X5→X2→X4→X1 →X6_0, the sub-time sequence indicated by timing mode 6 is X7_1→X5→X7_3→X1→X7_2→X4→X2→X6_0→X7_0→X0→X3→XA→X6_1, the sub-time sequence indicated by timing mode 7 is X1→X2→X7_1→XA→X7_0→X5→X4→X7_2→X0→X3→X7_3→X6_1→X6_0, and the sub-time sequence indicated by timing mode 8 is X1→X7_3→X0→X7_2→ X5→X6_0→X4→XA→X7_1→X3→X6_1→X2→X7_0, the sub-time sequence indicated by timing mode 9 is X6_0→X2→X1→X5→X4→XA→X3→X7_3→X6_1→X7_0→X0→X7_1→X7_2, and the sub-time sequence indicated by timing mode 10 is X5→X6_0→X6_1→X1→X7_0→XA→X7_1→X7_2→X7_3→X0→X2→X3→X4.

[0078] exist Figure 7 In the middle, the number of scans is equal to , The duration is expressed in units of time.

[0079] It should be noted that, provided the number of timing patterns is greater than 1, any number of timing patterns can be set. This article does not limit the number of timing patterns.

[0080] like Figure 6 and Figure 7As shown, no two timing modes indicate sub-segments with the same start time; that is, at most one sub-segment can start scanning under the same scan count. By setting multiple scanning modes, the scan drive circuit can drive pixels located in different pixel rows at staggered times, thereby balancing the power distribution of the scan drive circuit, reducing the power load on the scan drive circuit, and thus reducing the design difficulty and cost of the scan drive circuit.

[0081] The display screen includes multiple pixel rows, each corresponding to at least two timing modes. Each pixel row corresponds to one timing mode, and all pixels in a pixel row are driven using the timing mode corresponding to that pixel row. When driving the connected pixels, the second driving unit 12 controls the conduction time of the second driving current within the pulse width modulation time according to the timing mode corresponding to the pixel and the width modulation signal.

[0082] By configuring at least two different timing modes for different pixel rows in the display screen, and controlling the second drive current of each pixel row according to its position using the corresponding timing mode, while ensuring that the sub-time periods indicated by any two timing modes do not have the same start time, the staggered arrangement and staggered triggering of the drive timing between pixel rows are achieved. This setting can prevent multiple rows of pixels from entering the pulse amplitude modulation period or the same sub-time period drive conduction stage at the same time, preventing problems such as a sudden increase in instantaneous power consumption, increased power supply noise, and aggravated crosstalk caused by a large number of pixels being turned on at the same time, thus improving the stability of panel power supply and drive reliability. By staggering the start times of M+1 sub-time periods, including the pulse amplitude modulation period, between different pixel rows, the light emission time within the frame period can be further dispersed. Combined with the visual persistence effect, the overall light emission is more uniform and continuous, further suppressing the overall flicker and stripe interference in the row direction, and improving the uniformity and comfort of the entire screen display. Different pixel rows adopt differentiated timing modes, optimizing the overall light emission distribution without increasing the physical frame rate or circuit complexity. The control method is flexible and easy to implement with driver chips, adapting to the driving requirements of high-resolution and large-size display panels.

[0083] In one scenario, the pixel rows of the display screen correspond to multiple timing modes sequentially from top to bottom. Alternatively, the display screen includes at least two pixel regions, each containing multiple adjacent pixel rows. Pixel rows within the same pixel region correspond to the same timing mode, while pixel rows in different pixel regions correspond to different timing modes.

[0084] In one example, the display screen consists of 480 pixel rows. For example... Figure 8The diagram showing the temporal pattern distribution, in top-to-bottom order, shows that the 10a-9th pixel row corresponds to temporal pattern 1, the 10a-8th pixel row to temporal pattern 2, the 10a-7th pixel row to temporal pattern 3, the 10a-6th pixel row to temporal pattern 4, the 10a-5th pixel row to temporal pattern 5, the 10a-4th pixel row to temporal pattern 6, the 10a-3th pixel row to temporal pattern 7, the 10a-2th pixel row to temporal pattern 8, the 10a-1st pixel row to temporal pattern 9, and the 10ath pixel row to temporal pattern 10. 'a' is a positive integer less than or equal to 48.

[0085] In another example, the display screen consists of 480 pixel rows. (e.g.) Figure 9 The schematic diagram of the timing pattern distribution shown is as follows, from top to bottom: rows 1-48 correspond to timing pattern 1, rows 49-96 correspond to timing pattern 2, rows 97-144 correspond to timing pattern 3, rows 145-192 correspond to timing pattern 4, rows 193-240 correspond to timing pattern 5, rows 241-288 correspond to timing pattern 6, rows 289-336 correspond to timing pattern 7, rows 337-384 correspond to timing pattern 8, rows 385-432 correspond to timing pattern 9, and rows 433-480 correspond to timing pattern 10.

[0086] By having the pixel rows of the display screen cycle through at least two timing modes in a top-to-bottom order, or by dividing the pixel rows into multiple pixel regions and configuring different timing modes for different regions, it is possible to achieve orderly interleaving and uniform staggering of driving timings across the entire screen, ensuring that the start times of sub-periods for pixels in each row do not overlap. This method can achieve both row-by-row cyclical interleaving and region-based grouping interleaving, resulting in a neat layout, simple control logic, and easy timing scheduling by the driver chip.

[0087] In one situation, such as Figure 1 As shown, the second driving unit 12 includes a second current source I2, a memory 121, and a second switch S2. The second switch S2 is connected between the second current source I2 and the pixel D. For example, the second current source I2 is electrically connected to one end of the second switch S2, the other end of the second switch S2 is electrically connected to the source of the switching transistor M1, the drain of the switching transistor M1 is electrically connected to the anode of the pixel (light-emitting diode) D, and the cathode of the pixel D is grounded. The gate of the switching transistor M1 receives an emission enable (EM) signal, and the switching transistor M1 is turned on when the data signal drives the pixel D to emit light.

[0088] The memory 121 stores the M bit values ​​of the width modulation signal sequentially from the least significant bit to the most significant bit, with a bit width of 1 bit. The second switch S2 can be controlled to be turned on or off within a corresponding sub-period based on the bit value stored in the memory 121. For example, when the bit value stored in the memory 121 is a binary 1, the second switch S2 is turned on during the corresponding sub-period, driving pixel D to emit light; when the bit value stored in the memory 121 is a binary 0, the second switch S2 is turned off during the corresponding sub-period, and pixel D does not emit light.

[0089] The second switch S2 can be turned on for a corresponding duration according to the position of the bit value stored in the memory 121 in the width modulation signal, so as to control the pixel D to emit light in the corresponding sub-period.

[0090] By configuring the second driving unit 12 with a structure including a second current source I2, a memory 121 with a bit width of only 1 bit, and a second switch S2, precise control of the second driving current is achieved while simplifying the hardware circuit structure. The memory 121 stores the M bit values ​​of the width modulation signal sequentially from the least significant bit to the most significant bit. Only 1 bit width is needed to complete bit-by-bit buffering and output, saving storage resources and reducing chip area and hardware cost. The second switch S2 is turned on or off in the corresponding sub-period according to the bit values ​​stored in the memory 121. The control logic is direct and simple, without the need for complex decoding and calculation circuits, effectively reducing the complexity of driving control and improving timing response speed. The circuit structure of the second driving unit 12 is highly compatible with the timing of sub-period driving, and can stably work with the interleaved timing mode of different pixel rows, ensuring reliable execution of the width modulation signal and improving overall driving stability and display consistency.

[0091] Display screen This document also provides a display screen comprising a plurality of pixels and a plurality of the aforementioned pixel driving circuits, each pixel being electrically connected to one pixel driving circuit. The pixel driving circuits can drive the connected pixels according to a data signal, causing the pixels to emit light at a brightness matching the data signal within a frame period.

[0092] In one scenario, the multiple pixels of the display screen can be divided into multiple pixel blocks, with each pixel block comprising multiple pixels. For example, if the display screen comprises 480 rows × 640 columns of pixels, it can be divided into 24 rows × 32 columns, totaling 768 pixel blocks, with each pixel block comprising 20 rows × 20 columns, totaling 400 pixels.

[0093] Each pixel block is equipped with a corresponding secondary current source, and a primary current source is located outside the display screen. The primary current source provides a stable current input to the secondary current sources corresponding to all pixel blocks, and the secondary current sources provide a stable current input to all pixel driving circuits within the corresponding pixel block. This ensures that the pixel driving circuits can obtain a stable and accurate current input while reducing the power consumption of the primary current source.

[0094] It should be noted that the display screen in this article is a specific application of the pixel driving circuit in the aforementioned example. The structure and beneficial effects of the pixel driving circuit in electronic devices can be found in the description of the aforementioned pixel driving circuit example, and will not be repeated here.

[0095] electronic devices This document also provides an electronic device that includes any of the aforementioned display screens. The electronic device can be a mobile phone, television, laptop computer, tablet computer, video player, music player with a display screen, computer monitor, smartwatch, smart bracelet, in-vehicle display, virtual reality (VR) glasses, augmented reality (AR) glasses, mixed reality (MR) glasses, etc. This document does not limit the specific type of electronic device.

[0096] It should be noted that the electronic device in this article is a specific application of the display screen in the aforementioned example. The structure and beneficial effects of the display screen in the electronic device can be found in the description of the aforementioned display screen and pixel driving circuit example, and will not be repeated here.

[0097] It should be understood that the examples in this specification are described in a progressive manner. Similar or identical parts between examples can be referred to interchangeably. Each example focuses on highlighting its differences from the others. In particular, the method examples are relatively simple in description because they are fundamentally similar to the methods described in the device and system examples; relevant details can be found in the descriptions of other examples.

[0098] It should be understood that the foregoing describes specific examples in this specification. Other examples are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than those shown in the examples and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0099] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0100] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more examples in this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean the exclusion of any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A pixel driving circuit, comprising: The first driving unit is configured to generate a first driving current based on the amplitude modulation signal included in the data signal, and drive the pixel to emit light through the first driving current during the pulse amplitude modulation period included in the frame period. The data signal is used to indicate the gray level of the pixel. The data signal includes N bits, and the amplitude modulation signal includes n consecutive bits in the data signal. N is a positive integer, and n is an integer greater than 1 and less than N. The second driving unit is configured to control the conduction time of the second driving current according to the width modulation signal included in the data signal during the pulse width modulation period included in the frame period. When the second driving current is turned on, the pixel is driven to emit light. The width modulation signal includes Nn bits in the data signal excluding the amplitude modulation signal.

2. The circuit according to claim 1, wherein, The first driving unit is configured to generate different first driving currents when the amplitude modulation signals are different, and the first driving current is less than the second driving current.

3. The circuit according to claim 2, wherein, The first driving unit includes n first current sources and n first switches. Each first current source is electrically connected to the pixel through a first switch. The output currents of the n first current sources are respectively... to The product of the second drive current; The i-th first switch among the n first switches is closed or opened according to the i-th bit of the amplitude modulation signal, where i is a positive integer less than or equal to n.

4. The circuit according to claim 1, wherein, The pulse width modulation period includes M sub-periods, where M equals Nn, and each bit of the width modulation signal corresponds to one of the sub-periods. The second driving unit is configured to control the second driving current to be turned on during the sub-period corresponding to the bit when the bit is a first bit value, and to control the second driving current to be turned off during the sub-period corresponding to the bit when the bit is a second bit value.

5. The circuit according to claim 4, wherein, The width-modulated signal includes m source bits and k associated bits, where Nn equals m+k, and m and k are both positive integers; the data signal indicates a grayscale level of 2. m+n Any one of the gray levels; in the width modulation signal, each of the associated bits has the same bit value as the corresponding source bit; the k associated bits correspond to the sub-time periods of the same duration, and the duration of the sub-time period corresponding to the source bit is less than or equal to the duration of the sub-time period corresponding to the associated bit; The source bit and the corresponding associated bit are not adjacent.

6. The circuit according to claim 5, wherein, The durations of the sub-segments corresponding to the m source bits, including h source bits, are all different, where h is an integer greater than 1 and less than m; the durations of the sub-segments corresponding to the m-h+1 source bits are equal to the duration of the sub-segment corresponding to the associated bit.

7. The circuit according to claim 6, wherein, The durations of the sub-time periods corresponding to the h source bits are products of 2 raised to the power of n to n+h-1 and the unit duration, where the unit duration and... The product of these is equal to the frame period.

8. The circuit according to claim 7, wherein, The product of the frame rate and the frame rate is greater than or equal to the flicker frame rate threshold, where the frame rate is equal to the reciprocal of the frame period, and the flicker frame rate threshold is the maximum frame rate at which the flicker of the pixel can be observed by the human eye.

9. The circuit according to claim 6, wherein, The second driving unit is configured to control the conduction time of the second driving current during the pulse width modulation time based on the pixel row in which the pixel is located on the display screen, the corresponding timing mode, and the width modulation signal. The display screen includes multiple pixel rows corresponding to at least two timing modes, each pixel row corresponding to one timing mode. The timing mode is used to indicate the timing of M+1 sub-time periods. Different timing modes indicate different timing periods, and no two timing modes indicate sub-time periods with the same start time. The M+1 sub-time periods include the M sub-time periods and the pulse amplitude modulation time period.

10. The circuit according to claim 9, wherein, The display screen includes pixel rows that correspond to the at least two timing modes in a top-to-bottom order; or, the display screen includes at least two pixel regions, each pixel region including multiple adjacent pixel rows, where pixel rows in the same pixel region correspond to the same timing mode, and pixel rows in different pixel regions correspond to different timing modes.

11. The circuit according to any one of claims 4-10, wherein, The second driving unit includes a second current source, a memory, and a second switch, wherein the second switch is connected between the second current source and the pixel; The memory is used to store the M bit values ​​of the width modulation signal in order from the least significant bit to the most significant bit, and the bit width of the memory is 1 bit. The second switch is used to control the second switch to be turned on or off within the corresponding sub-period based on the bit value stored in the memory.

12. A display screen comprising a plurality of pixels and a plurality of pixel driving circuits as described in any one of claims 1-11, wherein each pixel is electrically connected to one of the pixel driving circuits.

13. An electronic device comprising the display screen as described in claim 12.

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