A phase-locked loop circuit structure

By introducing a pulse width expansion unit and control circuit into the phase-locked loop circuit, the problem that the digital modulator cannot work properly when the voltage-controlled oscillator outputs a high-frequency signal is solved, and the normal operation and low noise performance of the high-frequency broadband fractional phase-locked loop are realized.

CN122226031APending Publication Date: 2026-06-16CHENGDU SICORE SEMICON CORP LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
CHENGDU SICORE SEMICON CORP LTD
Filing Date
2024-12-16
Publication Date
2026-06-16

AI Technical Summary

Technical Problem

When the voltage-controlled oscillator outputs a high-frequency signal, the high-level pulse width of the digital modulator is less than the sum of the setup time and hold time required for normal operation, causing the fractional phase-locked loop to lose lock and fail to function properly.

Method used

A pulse width expansion unit and a control circuit are introduced into the phase-locked loop circuit. The output signal of the multi-mode frequency divider is pulse-width expanded by a delay circuit and an OR gate. The control circuit controls the start, stop or delay of the pulse width expansion circuit according to the output signal of the multi-mode frequency divider to ensure the normal operation of the digital modulator.

Benefits of technology

This invention enables the digital modulator to continue operating normally when the voltage-controlled oscillator outputs a high-frequency signal, broadens the output frequency bandwidth of the fractional phase-locked loop (PLL), and does not affect the phase noise performance of the PLL. It features a simple structure, low power consumption, and easy expansion.

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Abstract

The application discloses a phase-locked loop circuit structure and relates to the field of electronic equipment, which comprises a frequency discriminator, a charge pump, a low-pass filter, a voltage-controlled oscillator, a multi-mode frequency divider and a digital modulator, and further comprises a pulse width spreading unit which is used for spreading the pulse width of the input signal of the digital modulator; the multi-mode frequency divider outputs the clock signal after the pulse width is spread, and then the clock signal is provided to the digital modulator, so that the digital modulator can still work normally when the voltage-controlled oscillator outputs a high-frequency signal, and the output frequency bandwidth of the fractional phase-locked loop is widened.
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