A multi-channel synchronous acquisition isolation circuit and PCB structure

Abstract

The application discloses a kind of multi-channel synchronous acquisition isolation circuits and PCB structure, including multi-channel analog differential signal conditioning circuit, synchronous A / D converter, MCU main control chip, EtherCAT communication circuit and multi-stage isolation power supply architecture;Multi-channel analog differential signal conditioning circuit output end is connected with synchronous A / D converter input end;Synchronous A / D converter is connected with MCU main control chip by SPI bus;MCU main control chip is connected with EtherCAT communication circuit by separate SPI bus;Multi-stage isolation power supply architecture is connected with multi-channel analog differential signal conditioning circuit, synchronous A / D converter, MCU main control chip and EtherCAT communication circuit respectively.In high-precision industrial measurement, the rigorous synchronization of signal and extremely low crosstalk are guaranteed.

Description

Technical Field

[0001] This invention belongs to the field of signal acquisition circuits and relates to a multi-channel synchronous acquisition isolation circuit and its PCB structure. Background Technology

[0002] In fields such as high-precision industrial measurement and analysis and multi-channel vibration monitoring, the demand for strictly synchronized and high-fidelity acquisition of multi-channel sensor signals is becoming increasingly urgent. The performance limits of such systems depend not only on the selection of high-performance synchronous sampling analog-to-digital converters (ADCs), but also on the underlying circuit design and PCB implementation to achieve their performance.

[0003] In terms of power system architecture, existing solutions often fail to rigorously coordinate the electrical isolation of power conversion links with the physical area segmentation on the PCB. Systems typically employ shared power supplies or insufficiently isolated step-down solutions, and often neglect to provide deeply independent power branches for specific high-noise sources such as high-speed communication physical layers (e.g., EtherCAT). This results in high-frequency switching noise and ground bounce interference easily coupling backward through the power network, severely contaminating sensitive analog front-end circuitry and significantly reducing the system's signal-to-noise ratio and ADC quantization accuracy.

[0004] In terms of PCB physical layout and grounding strategies, traditional analog / digital ground plane partitioning is often based on a rough division of functional modules, and the partition boundaries are often disconnected from the physical layout of the ADC chip pins. This unreasonable partitioning can lead to the interruption of signal return paths and sudden changes in reference impedance. At the same time, due to the lack of strict, full-layer isolation in vertical three-dimensional space, there are large parasitic capacitances between the copper planes, which makes it easy for high-frequency digital noise to couple across regions to the analog area through displacement current, causing serious inter-channel crosstalk and electromagnetic interference. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a multi-channel synchronous acquisition isolation circuit and PCB structure that ensures tight signal synchronization and extremely low crosstalk in high-precision industrial measurement.

[0006] To achieve the above objectives, the present invention employs the following technical solution: A multi-channel synchronous acquisition isolation circuit includes a multi-channel analog differential signal conditioning circuit, a synchronous analog-to-digital converter, an MCU main control chip, an EtherCAT communication circuit, and a multi-level isolation power supply architecture; The output of the multi-channel analog differential signal conditioning circuit is connected to the input of the synchronous analog-to-digital converter; The synchronous analog-to-digital converter is connected to the MCU main control chip via the SPI bus; The MCU main control chip is connected to the EtherCAT communication circuit via a separate SPI bus; The multi-level isolated power supply architecture connects to the multi-channel analog differential signal conditioning circuit, synchronous analog-to-digital converter, MCU main control chip and EtherCAT communication circuit respectively.

[0007] Optionally, the multi-channel analog differential signal conditioning circuit includes six channel signal conditioning circuits, each channel signal conditioning circuit processes one differential signal, and the outputs of all six channel signal conditioning circuits are connected to the input of a synchronous analog-to-digital converter.

[0008] Optionally, the multi-stage isolated power supply architecture includes DC-DC modules, analog 5V_LDO modules, and digital 5V_LDO modules; The DC-DC module input is connected to a DC voltage. The DC-DC module output is divided into two power supply paths: the first path connects to the input of the digital 5V_LDO module, and the second path connects to the input of the analog 5V_LDO module. The analog 5V_LDO module outputs the REF reference voltage from the multi-channel analog differential signal conditioning circuit and directly connects to the analog reference voltage pin in the synchronous analog-to-digital converter. The digital 5V_LDO module output is divided into three power supply links.

[0009] Optionally, the multi-level isolated power supply architecture also includes a digital 3.3V1_LDO module and a digital 3.3V2_LDO module; the first power supply link at the output of the digital 5V_LDO module forms an AVDD voltage through a series inductor and is directly connected to the synchronous analog-to-digital converter; the second power supply link is connected to the input of the digital 3.3V1_LDO module, and the output of the digital 3.3V1_LDO module is connected to the synchronous analog-to-digital converter and the MCU main control chip respectively; the third power supply link is connected to the input of the digital 3.3V2_LDO module, and the output of the digital 3.3V2_LDO module is separately connected to the EtherCAT communication circuit.

[0010] Optionally, the DC voltage is connected to the input terminal of the DC-DC module via a series diode; the output terminal of the DC-DC module is connected to a diode, with the cathode of the diode connected to the output line and the anode grounded; the output line is connected in series with an inductor to form a 6.5V voltage node, and two capacitors are connected in parallel between the 6.5V voltage node and ground; the first branch of the DC-DC module output is connected to a 0-ohm resistor and a ground capacitor is connected in parallel at this point; the second branch is connected to a 0-ohm resistor and a ground capacitor.

[0011] A PCB structure for a multi-channel synchronous acquisition isolation circuit, comprising layers one through six; The multi-channel analog differential signal conditioning circuit, synchronous analog-to-digital converter, MCU main control chip, analog 5V_LDO module, digital 3.3V1_LDO module, digital 3.3V2_LDO module and DC-DC module are placed on the first layer; The digital 5V LDO module, EtherCAT communication circuit, and CAN module are located on the sixth layer. The first layer is the top layer, the second layer is a continuous copper-plated analog ground layer, the third layer is the internal signal layer, the fourth layer is the power layer, the fourth layer is physically divided into multiple copper islands with different voltage domains, the fifth layer is a large-area copper-plated digital ground layer, and the sixth layer is the bottom layer.

[0012] Optionally, layers one through six are electrically isolated into analog circuit regions and digital circuit regions; Using the physical package projection area of ​​the synchronous analog-to-digital converter as the geometric reference, along the physical boundary line between analog and digital pins in the synchronous analog-to-digital converter package, copper-free partition lines with completely consistent positions and vertical alignment are synchronously defined and drawn on layers one to six; the copper-free partition lines physically divide the copper-paved areas of each layer into two halves, one side is defined as the analog circuit area, and the other side is defined as the digital circuit area. The physical separation gap of the multi-layer vertical ground plane dividing line is controlled to a minimum of 30mil; the silicon-based bonding wire inside the synchronous analog-to-digital converter becomes the only signal connection medium between the analog circuit area and the digital circuit area.

[0013] Optionally, the physical extension of the analog circuit area boundary covers all component areas of the multi-channel analog differential signal conditioning circuit, all analog signal input pins of the synchronous analog-to-digital converter, operational amplifier excitation voltage input pins, output excitation voltage pads, and the corresponding pads for the reference voltage pins; The physical extension of the digital circuit area boundary covers all digital interface pins of the synchronous analog-to-digital converter, pins of the multi-level isolated power supply architecture, MCU main control chip pads, and EtherCAT communication circuit pads. No digital signal traces are allowed to cross through any adjacent layers in the vertical three-dimensional space corresponding to the analog circuit area.

[0014] Optionally, the multi-channel analog differential signal conditioning circuit components within the analog circuit area follow a homogeneous physical layout rule; Each channel of the multi-channel analog differential signal conditioning circuit has a complete physical signal link path through an RC anti-aliasing filter and an amplifier to the analog input pin of the synchronous analog-to-digital converter; In a multi-channel analog differential signal conditioning circuit, all physical packages of all devices and interconnecting copper traces in each channel are confined to the first layer. The absolute difference in physical trace length of the symmetrical differential signal path between each acquisition channel is controlled within 10 mil.

[0015] Optionally, an independent power isolation zone can be defined within the digital circuit area; The digital circuit area is subdivided and independent local reference ground planes are established for each level of power module; The DC-DC module is placed in the power isolation area, and the positive network and ground network of the DC-DC module output are connected at a single point by a 0-ohm resistor connected across the output ground plane dividing line.

[0016] Compared with the prior art, the present invention has the following beneficial effects: This invention combines multi-channel differential signal conditioning, synchronous analog-to-digital conversion, MCU main control processing, and EtherCAT high-speed communication, supplemented by a multi-level isolated power supply architecture at the underlying level, to construct a complete high-fidelity signal acquisition and transmission closed loop. It physically separates the sensitive analog signal acquisition node from the high-frequency digital processing node, and utilizes the SPI bus and EtherCAT circuitry to achieve efficient data protocol conversion and external transmission, thereby ensuring tight signal synchronization and extremely low crosstalk in high-precision industrial measurements.

[0017] Furthermore, six independent signal conditioning channels are set up in parallel, each processing one differential signal. This fully parallel symmetrical hardware structure avoids the time difference and charge injection crosstalk between channels caused by time-division sampling of traditional multiplexers. Through independent filtering and amplification links directly to the synchronous ADC, it ensures that the multiple weak differential signals have a high degree of consistency and independence before quantization.

[0018] Furthermore, after the DC-DC module steps down the voltage, the power supply path is physically and electrically split into two, with independent low-dropout linear regulators (LDOs) supplying power to the analog and digital circuits respectively. This cuts off the path of high-frequency switching noise from the digital circuits to the analog side via the power network, and the analog 5V LDO provides an extremely clean reference voltage (REF) for the synchronous analog-to-digital converter, thereby maximizing the signal-to-noise ratio and sampling accuracy of the ADC.

[0019] Furthermore, a secondary power supply division was performed on the digital area, equipping the digital terminals of the MCU / ADC and the EtherCAT communication circuit with independent 3.3V LDO modules. Industrial Ethernet physical layer chips such as EtherCAT generate strong switching noise and ground bounce interference during high-speed communication. By completely separating their power supply from the main control MCU and the digital power supply of the synchronous analog-to-digital converter at the voltage regulation end, deep isolation of the noise source can be achieved, preventing high-speed communication noise from polluting the core digital logic circuit of the system.

[0020] Furthermore, an LC low-pass filter network consisting of a series diode, an inductor, and a parallel capacitor is used at the DC-DC output, with a 0-ohm resistor and a grounding capacitor introduced at the branch points. Utilizing the current-blocking characteristics of the inductor and the energy-storing bypass characteristics of the capacitor, the high-frequency switching ripple generated by the primary DC-DC converter is filtered out to the greatest extent possible. The addition of the 0-ohm resistor not only creates a clear single-point physical isolation and test point on the PCB trace, but also, in conjunction with the capacitor, further absorbs high-frequency glitches on the circuit, improving the power supply rejection ratio of the subsequent LDO.

[0021] Furthermore, the PCB structure employs a six-layer stack-up structure comprising a top layer, analog ground plane, inner signal layers, power layers, digital ground plane, and a bottom layer. This provides the shortest physical return path for high-speed and weak signals, effectively controlling the characteristic impedance of signal traces and reducing return inductance. Simultaneously, the power layers and adjacent ground planes form natural interlayer distributed capacitance, providing excellent high-frequency decoupling capabilities, while the inner signal layers are shielded by the ground planes, avoiding spatial orthogonal crosstalk to critical signals on the surface layers.

[0022] Furthermore, using the synchronous analog-to-digital converter (ADC) as a reference, a vertical copper-free partition trench at least 30 mil wide was simultaneously excavated on all six electrical layers, strictly dividing the entire board into analog and digital regions. This design utilizes a sufficiently wide air and insulating resin dielectric to block the displacement current coupling path of high-frequency noise between the copper-clad planes on both sides, greatly reducing parasitic capacitance. The silicon-based bonding wires inside the synchronous ADC thus become the only signal connection medium spanning the two regions, forcibly achieving optimal single-point bridging without ground loops from a three-dimensional physical structure perspective.

[0023] Furthermore, the physical component coverage boundaries between the analog and digital zones were clearly defined, and any digital signal traces were strictly prohibited from crossing the corresponding vertical three-dimensional space of the analog zone. From the perspective of electromagnetic field theory, high-frequency digital signals radiate alternating electromagnetic fields to the surroundings when they undergo state transitions. Strict regional isolation and the prohibition of vertical crossings cut off the path for this alternating electromagnetic field to undergo near-field spatial coupling and crosstalk to weak analog signals, thus creating a clean electromagnetic environment for the analog front end.

[0024] Furthermore, all components of the analog link are placed on the top layer, and the absolute difference in the length of the differential traces for each channel is controlled within 10 mil. This homogeneous layout eliminates parasitic inductance, capacitance, and impedance discontinuities caused by vias, preventing reflection losses when high-frequency signals travel between layers. The stringent 10-mil equal-length rule directly controls the time difference of electromagnetic wave propagation in the PCB medium, ensuring a high degree of consistency in the transmission delay when multi-channel analog signals arrive at the ADC pins, thus eliminating phase synchronization errors between channels from a physical level.

[0025] Furthermore, a separate power isolation zone was designated in the digital area to house the DC-DC module, with a single-point connection established by bridging the output ground plane with a 0-ohm resistor. This confines the primary power conversion module, which operates at high switching frequencies and is subject to strong electromagnetic interference, within this localized island, preventing its return current from flowing through the reference ground plane of sensitive circuits. The single-point bridging with the 0-ohm resistor ensures a uniform DC potential and blocks the diffusion of high-frequency common-mode noise into subsequent precision circuits. Attached Figure Description

[0026] Figure 1 This is a diagram of the multi-channel synchronous acquisition isolation circuit architecture of the present invention; Figure 2 This is a schematic diagram of the PCB structure of the multi-channel synchronous acquisition isolation circuit of the present invention; Figure 3 This is a schematic diagram showing the interconnection relationship between the modules of the multi-channel synchronous acquisition isolation circuit of the present invention; Figure 4 This is a schematic diagram of the multi-level isolated power supply design for the multi-channel synchronous acquisition isolation circuit of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] like Figure 1 As shown, this embodiment provides a multi-channel synchronous acquisition isolation circuit, including a multi-channel analog differential signal conditioning circuit, a multi-level isolation power supply architecture, a synchronous analog-to-digital converter (synchronous ADC circuit), an MCU main control chip, and an EtherCAT communication circuit.

[0030] The multi-channel analog differential signal conditioning circuit comprises six parallel signal conditioning channels: Channel 1, Channel 2, Channel 3, Channel 4, Channel 5, and Channel 6. The inputs of these six channels respectively receive externally input differential signals AIN1±, AIN2±, AIN3±, AIN4±, AIN5±, and AIN6±. The outputs of channels 1 through 6 are all connected to the input of a synchronous analog-to-digital converter (ADC), enabling filtering, amplification, and analog signal quantization of weak differential signals through differential cross-linking. The ADC is connected to the MCU (Microcontroller Unit) chip via an SPI bus. The MCU chip performs signal processing and protocol conversion on the quantized digital signals. The MCU chip is further connected to an EtherCAT communication circuit via a separate SPI bus. The EtherCAT communication circuit's communication terminal is connected to an Ethernet interface for external data transmission.

[0031] The multi-channel analog differential signal conditioning circuit and the synchronous analog-to-digital converter are differentially linked to achieve the functions of filtering, amplifying and quantizing analog signals of weak differential signals. The MCU master controller is linked with the synchronous analog-to-digital converter through the SPI bus to perform signal processing and protocol conversion on the quantized digital signal. The converted digital signal is transmitted to the outside through the EtherCAT communication circuit.

[0032] In a multi-stage isolated power supply architecture, the externally input DC 12-48V voltage is first connected to the input terminal of the DC-DC module via a series diode. A diode is connected to the output terminal of the DC-DC module, with its cathode connected to the output line and its anode grounded. An inductor is then connected in series with the output line to form a 6.5V voltage node. Two capacitors are connected in parallel between the 6.5V voltage node and ground. The 6.5V voltage line then branches into two power supply paths. The first branch passes through a 0-ohm resistor, with a grounded capacitor connected in parallel at this point, before connecting to the input terminal of the digital 5V_LDO module. The second branch also passes through a 0-ohm resistor, with a grounded capacitor connected in parallel, before connecting to the input terminal of the analog 5V_LDO module.

[0033] like Figure 3As shown, the output of the analog 5V_LDO module outputs the REF reference voltage from the multi-channel analog differential signal conditioning circuit. This reference voltage is directly connected to the analog reference voltage pin in the synchronous analog-to-digital converter (SADC), and this node also outputs the REF_5V signal externally. The output of the digital 5V_LDO module has three power supply links. The first power supply link generates an AVDD voltage through a series inductor, which is directly connected to the SADC. The second power supply link connects to the input of the digital 3.3V1_LDO module, whose DVDD1 voltage is connected to both the SADC and the MCU main control chip. The third power supply link connects to the input of the digital 3.3V2_LDO module, whose DVDD2 voltage is separately connected to the EtherCAT communication circuit, providing power to the EtherCAT communication circuit independently.

[0034] The external DC voltage is divided into two 5V LDO modules after passing through a DC-DC converter. One analog 5V LDO module is dedicated to powering the signal conditioning circuit and the analog reference in the synchronous analog-to-digital converter. The other digital 5V LDO module is divided into two 3.3V LDO modules. One digital 3.3V1 LDO module powers the MCU main control chip and the synchronous analog-to-digital converter, while the other digital 3.3V2 LDO module powers the EtherCAT communication circuit separately.

[0035] like Figure 2 As shown, this embodiment provides a PCB structure for a multi-channel synchronous acquisition isolation circuit, and the PCB board adopts a six-layer stacked physical structure.

[0036] From a vertical perspective, the stack-up order, from top to bottom, consists of layers one through six. Layer one, the top layer, is primarily used to house all active chips, passive components, and surface microstrip wiring for core high-frequency signals and weak analog signals. This includes multi-channel analog differential signal conditioning circuits, synchronous analog-to-digital converters, MCU main control chips, analog 5V LDO modules, digital 3.3V1 LDO modules, digital 3.3V2 LDO modules, and DC-DC modules. Layer two is the analog ground plane, a continuous copper-clad plane located below the top layer, separated only by a very thin insulating medium. It provides the shortest physical return path for all analog signals on the top layer, effectively controlling the characteristic impedance of the signal traces and reducing return inductance. Layer three is the inner signal layer, used for routing high-density control signals or low-frequency digital signal striplines, avoiding physical crosstalk to critical signals on the top layer. The fourth layer is the power layer, physically divided into multiple copper islands with different voltage domains. This layer carries the power supply current required by each module and forms inter-layer distributed capacitance with the adjacent ground layer, providing additional high-frequency decoupling capability. The fifth layer is the digital ground layer, also a large copper plane, primarily providing return current references for the digital logic signals of the bottom and inner layers. The sixth layer is the bottom layer, used to house some secondary passive components or decoupling capacitors and for auxiliary routing, including the digital 5V_LDO module, EtherCAT communication circuit, and CAN module.

[0037] In terms of the physical spatial layout and layer division of the PCB board, this embodiment adopts a full-layer segmentation strategy from top to bottom, completely isolating the entire physical board into analog circuit and digital circuit regions electrically. The core geometric reference of this segmentation design is the physical package projection area of ​​the synchronous analog-to-digital converter (SADC) on the top layer of the PCB board. At this reference position, along the physical boundary line between analog and digital pins in the SADC package, a copper-free segmentation line is simultaneously defined and drawn on the top layer (first layer), analog ground layer (second layer), inner signal layer (third layer), power layer (fourth layer), digital ground layer (fifth layer), and bottom layer (sixth layer). This copper-free segmentation trench, which runs vertically through all six layers, physically divides the copper-paved areas of each layer in half. One side of the segmentation line is defined as the analog circuit region, and the other side is defined as the digital circuit region.

[0038] The boundary of the analog circuit area physically extends to encompass all components of the multi-channel analog differential signal conditioning circuit, all analog signal input pins of the synchronous analog-to-digital converter (SADC), operational amplifier excitation voltage input pins, output excitation voltage pads, and the pads corresponding to the reference voltage pins. The boundary of the digital circuit area physically extends to encompass all digital interface pins of the SADC, multi-level isolated power supply architecture pins, MCU main control chip pads, and EtherCAT communication circuit pads. Within the SADC package projection area, the multi-layer vertical ground plane partition line has a physical partition gap width controlled to a minimum of 30 mil. This dimension not only meets the impedance control and etching process accuracy requirements of the physical manufacturing process but, more importantly, establishes a sufficiently wide air and insulating resin dielectric isolation band at the electrical level, greatly reducing the parasitic capacitance between the two copper planes, thereby blocking the displacement current coupling path of high-frequency noise. Due to this three-dimensional through-isolation design across all copper planes from the top to the bottom, the SADC and its internal silicon-based bonding wires become the only signal connection medium spanning the analog and digital circuit areas, physically forcing an optimal single-point bridging path.

[0039] Within the top-level analog circuit area, all multi-channel analog signal conditioning circuit components adhere to a homogeneous physical layout. The complete physical signal path for each channel, starting from the connector input pin, passes through the RC anti-aliasing filter and amplifier, all the way to the analog input pin of the synchronous analog-to-digital converter. All physical packages and interconnecting copper traces of these components are confined to the first layer of the PCB, the top component layer. This homogeneous layout completely eliminates parasitic inductance and impedance discontinuities caused by via structures, avoiding reflections and losses that occur when high-frequency signals travel between different layers. Simultaneously, the homogeneous layout allows the analog ground plane on the second layer below to provide a complete and continuous mirror reference plane for all analog traces on the top layer. No digital signal traces are allowed to cross over any adjacent layers within the corresponding vertical space of this analog circuit area, preventing vertical crosstalk coupling of weak analog signals caused by the alternating electromagnetic fields generated during digital signal transitions.

[0040] Furthermore, to address the data synchronization requirements of the multi-channel analog differential signal conditioning circuit, quantized trace length matching rules were implemented in the top-level analog circuit area. The absolute difference in physical trace length between the symmetrical differential signal paths of each acquisition channel is controlled within 10 mil. In the glass fiber epoxy resin medium of the PCB board, the propagation speed of electromagnetic waves is finite. This physical length constraint directly corresponds to the control of minute differences in electromagnetic wave propagation time, ensuring a high degree of consistency in the physical transmission delay of multiple weak analog signals when they reach the synchronous analog-to-digital converter pins, eliminating phase errors between channels caused by inconsistent printed line lengths. Simultaneously, all physical device pins and surface traces within the analog circuit area are required to maintain sufficient physical distance from the edge of the digital circuit area and the 30 mil separation gap. This distance is typically set to a sufficiently wide physical dimension to form an effective spatial noise isolation band. Utilizing the inverse square law of distance attenuation, potential near-field electromagnetic radiation energy is dissipated, creating a clean analog acquisition environment.

[0041] The multi-stage isolated power supply architecture that supplies power to the analog circuit region and the digital circuit region adopts a multi-stage architecture with cross-region segmentation and isolation. Specifically, it includes: dividing the digital circuit region into independent reference ground planes for each stage of power supply module in sequence; the output of the first-stage isolated DC-DC module is powered by an isolation device connected across the division line of its output ground plane to the subsequent two independent low-noise low-dropout linear regulators (LDOs).

[0042] In the analog circuit area, the power supply is converted into the reference voltage of the analog circuit through the first low-noise LDO (analog 5V_LDO module). The output of the LDO directly supplies power to the reference voltage (REF) pin, the operational amplifier excitation voltage input pin, and the output excitation voltage pad of the ADC chip. The power supply supplies the secondary voltage regulator module in the digital circuit area through the second low-noise LDO (digital 5V_LDO module).

[0043] Within the digital circuitry area, the output of the second low-noise LDO is further divided into at least two independent third-stage LDO power branches (two 3.3V LDO modules), one of which is dedicated to powering the EtherCAT communication circuitry.

[0044] The PCB structure design process is as follows: First, import the package model of the selected synchronous analog-to-digital converter (e.g., AD77xx series) into the PCB design and fix it in the preset layout position. Then, using the actual projected area of ​​the synchronous analog-to-digital converter package on the PCB as an immutable physical reference, simultaneously draw two ground plane dividing lines with identical positions and shapes, designated as the analog ground plane (layer 2) and the digital ground plane (layer 5). These dividing lines separate the two ground planes into two electrically isolated continuous copper areas.

[0045] The area definition rules are as follows: The boundary of the analog circuit area must extend outwards to completely cover the component layout area of ​​all multi-channel analog signal conditioning circuits (including instrumentation amplifiers, RC filters, etc.), as well as the pads of all analog signal input pins (AINx±) and reference voltage (REF) pins of the synchronous analog-to-digital converter. The boundary of the digital circuit area must cover all digital interface pins (such as SPI, CLK, CS), digital power supply pins (DVDD), and digital circuits such as the MCU main control chip, memory, and EtherCAT communication circuits of the synchronous analog-to-digital converter.

[0046] Beneath the core area covered by the synchronous analog-to-digital converter (SADC) package projection, it must be ensured that the width of the partition gap (i.e., the copper-free area) between the analog and digital circuitry areas is no less than 30 mils everywhere. This design makes the pins of the SADC and its internal connections the only low-impedance signal bridging path connecting the analog and digital areas, thus physically forcing optimal single-point grounding and noise isolation.

[0047] When laying out and routing the analog circuit area, for any acquisition channel, starting from the differential signal input, through RC filtering and instrumentation amplifier, and finally to the analog input pin of the synchronous analog-to-digital converter, all passive and active components such as resistors, capacitors, and operational amplifiers should be placed on the same layer of the PCB (preferably the top layer). The adjacent layer directly below the top layer must be a continuous and complete analog ground layer, and no digital signal lines (such as clock and data lines) are allowed to cross the analog circuit area of ​​the analog ground layer.

[0048] Timing optimization is performed on symmetrical signal paths (e.g., differential pairs) for all channels to ensure that the length difference of corresponding traces between channels is strictly controlled within 10 mil, thereby guaranteeing the sampling synchronization accuracy between channels. In addition, all devices and traces in the analog circuit area should maintain sufficient physical spacing (generally recommended to be no less than 50 mil) from the partition boundary of the digital circuit area to form an effective spatial noise isolation band.

[0049] Within the defined digital circuitry area, a separate power isolation zone is designated in a corner away from the analog front-end circuitry. This digital circuitry area needs to be further subdivided to establish independent, unconnected local reference ground planes for subsequent power modules at each stage.

[0050] like Figure 4 As shown, the multi-level isolated power supply architecture consists of a three-level architecture.

[0051] Level 1: Isolation and Primary Conversion. The input power is first connected to an isolated DC-DC module. Due to the significant switching noise it generates during operation, this module must be placed within the aforementioned power isolation zone. Its output positive (VOUT+) and ground (Power-) networks must be connected at a single point through an isolation device (typically a 0Ω resistor) bridging the output ground plane divider, achieving initial electrical isolation and noise blocking.

[0052] Stage Two: Independent voltage regulation for analog and digital circuit areas. The isolation voltage output from Stage One is connected to two independent low-noise, low-dropout linear regulators (LDOs). The first LDO (analog 5V LDO module) is dedicated to powering the analog circuit area, and its output should directly and cleanly power the reference voltage (REF) pin of the synchronous analog-to-digital converter, the power supply pin of the analog signal conditioning operational amplifier, and the external reference voltage test pad. The second LDO (digital 5V LDO module) provides the main power supply for the digital circuit area.

[0053] Level 3: Deep noise source isolation. Within the digital circuitry area, the output of the second LDO is further split. At least two independent third-level LDOs (two 3.3V LDO modules) are required: one LDO (digital 3.3V2 LDO module) is dedicated to powering the physical layer (PHY) chip of EtherCAT or other industrial bus communication circuits. The other LDO (digital 3.3V1 LDO module) powers the remaining digital circuits such as the MCU and CAN.

[0054] By implementing the full-dimensional through-segmentation and homogenization rules in the PCB board geometry and the multi-level independent branch power supply in the power architecture, this embodiment changes the distribution of the electromagnetic field and the return flow of the signal current, thereby producing a mutually reinforcing technical effect and comprehensively improving the system's timing consistency, signal integrity and overall anti-interference capability.

[0055] Regarding timing consistency, the core requirement of a multi-channel high-precision acquisition system is to capture the transient values ​​of each physical channel simultaneously. The synchronous analog-to-digital converter (ADC) itself relies on a unified internal system clock to trigger the sample-and-hold switches of each channel. However, at the physical board level, due to the distributed inductance and capacitance of the traces, the signal propagation on the PCB traces has a physical delay on the order of nanoseconds or even picoseconds. The 10mil trace length matching rule established in this embodiment physically compresses the phase difference of the symmetrical signal paths propagating in the glass fiber epoxy medium of each channel to an extremely low limit. Combined with the homogeneous layout of analog devices on the top layer, it avoids the group delay distortion caused by parasitic capacitance and inductance attached to vias, thus fundamentally eliminating the spatial propagation time error introduced by the discrete physical layout and path asymmetry from the root of electromagnetic wave transmission principles. This ensures that the weak analog signal waveforms reaching the pins of the synchronous ADC are highly aligned on the time axis, guaranteeing timing synchronization and signal amplitude consistency among multiple channels, allowing the hardware platform to approach the theoretical limit of synchronous acquisition accuracy.

[0056] In terms of signal integrity, the core lies in the absolute control and impedance matching of the signal return path. When an AC signal propagates forward along the top physical copper trace, its return current automatically seeks the path with the least inductance on the reference plane immediately below the trace to flow back to the source. This embodiment specifies a homogeneous layout within the analog region with a continuous and complete bottom layer, providing a seamless low-impedance mirror reference plane for all analog traces, minimizing the loop area of ​​the signal path, and reducing waveform reflection and attenuation caused by parasitic inductance. More importantly, through a completely consistent synchronous partition from the top layer to the digital ground plane, and maintaining a 30mil physical gap below the chip, a physical isolation band for the return current is forcibly defined. When the fast transient return current generated by the digital logic pins flips at high frequencies flows back to the digital region power supply, due to the physical cutoff at the 30mil gap between each ground plane, the return charge cannot cross the vacuum or the insulating medium of the substrate to enter the analog ground plane, thus completely blocking the common impedance coupling voltage drop generated by the digital return current on the analog reference plane. The synchronous analog-to-digital converter (ADC) is designed as the sole bridging path, which essentially optimizes the signal return path at the source. It constructs a physical model similar to a star-shaped single-point grounding, ensuring that the reference potential of each weak analog signal is not modulated by digital switching noise, minimizing the impact of noise on synchronization accuracy, and guaranteeing high-fidelity signal integrity.

[0057] In terms of overall system anti-interference capability, the multi-level power architecture with cross-regional segmentation and the physical shielding strategy in the ground plane work in strict coordination to construct a system-level deep noise suppression network. Regarding power conduction interference suppression, the first-stage isolated DC-DC module, through the magnetic core coupling of its internal high-frequency transformer, blocks common-mode surge currents from the external industrial power grid or the system's main power line to the physical primary side, cutting off the channel for external transient interference to be injected into sensitive measurement circuits. The second and third stages of low-noise, low-dropout linear regulators utilize their internal high-gain error feedback amplification network to dynamically adjust the on-resistance of the series power transistors through a high-frequency bandwidth negative feedback mechanism, actively canceling voltage ripples in the range of tens of kilohertz to several megahertz on the power supply line, providing deeply independent and clean power to the analog front-end, digital core, and high-speed communication modules. In particular, the independent digital 3.3V2_LDO module for the EtherCAT communication circuit, through isolated power supply branches, cuts off the propagation path of transient resonant energy excited at the power level when the Ethernet transformer drive signal undergoes a sudden change. In terms of suppressing spatial radiation interference, the strict three-dimensional wiring rule prohibiting any digital signal lines from crossing the analog area, along with sufficient physical edge spacing, eliminates near-field alternating electromagnetic field coupling channels caused by distributed capacitance and mutual inductance in the physical space. This entire approach transforms complex and abstract electromagnetic compatibility design experience into quantifiable and executable engineering physical rules, significantly improving the design success rate and the robustness and signal-to-noise ratio of multi-channel synchronous acquisition systems from the physical levels of geometric layout and power architecture.

[0058] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0059] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0060] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0061] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0062] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

[0063] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this patent should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed inventive subject matter.

Claims

1. A multi-channel synchronous acquisition isolation circuit, characterized in that, This includes a multi-channel analog differential signal conditioning circuit, a synchronous analog-to-digital converter, an MCU main control chip, an EtherCAT communication circuit, and a multi-level isolated power supply architecture; The output of the multi-channel analog differential signal conditioning circuit is connected to the input of the synchronous analog-to-digital converter; The synchronous analog-to-digital converter is connected to the MCU main control chip via the SPI bus; The MCU main control chip is connected to the EtherCAT communication circuit via a separate SPI bus; The multi-level isolated power supply architecture connects to the multi-channel analog differential signal conditioning circuit, synchronous analog-to-digital converter, MCU main control chip and EtherCAT communication circuit respectively.

2. The multi-channel synchronous acquisition isolation circuit according to claim 1, characterized in that, The multi-channel analog differential signal conditioning circuit contains six channel signal conditioning circuits. Each channel signal conditioning circuit processes one differential signal. The outputs of all six channel signal conditioning circuits are connected to the input of a synchronous analog-to-digital converter.

3. The multi-channel synchronous acquisition isolation circuit according to claim 1, characterized in that, The multi-level isolated power supply architecture includes a DC-DC module, an analog 5V LDO module, and a digital 5V LDO module; The DC-DC module input is connected to a DC voltage. The DC-DC module output is divided into two power supply paths: the first path connects to the input of the digital 5V_LDO module, and the second path connects to the input of the analog 5V_LDO module. The analog 5V_LDO module outputs the REF reference voltage from the multi-channel analog differential signal conditioning circuit and directly connects to the analog reference voltage pin in the synchronous analog-to-digital converter. The digital 5V_LDO module output is divided into three power supply links.

4. The multi-channel synchronous acquisition isolation circuit according to claim 3, characterized in that, The multi-level isolated power supply architecture also includes a digital 3.3V1_LDO module and a digital 3.3V2_LDO module; the first power supply link at the output of the digital 5V_LDO module forms an AVDD voltage through a series inductor and is directly connected to the synchronous analog-to-digital converter; the second power supply link is connected to the input of the digital 3.3V1_LDO module, and the output of the digital 3.3V1_LDO module is connected to the synchronous analog-to-digital converter and the MCU main control chip respectively; the third power supply link is connected to the input of the digital 3.3V2_LDO module, and the output of the digital 3.3V2_LDO module is separately connected to the EtherCAT communication circuit.

5. The multi-channel synchronous acquisition isolation circuit according to claim 3, characterized in that, The DC voltage is connected to the input terminal of the DC-DC module through a series diode; the output terminal of the DC-DC module is connected to a diode, with the cathode of the diode connected to the output line and the anode grounded; the output line is connected in series with an inductor to form a 6.5V voltage node, and two capacitors are connected in parallel between the 6.5V voltage node and ground; The first branch of the DC-DC module output passes through a 0-ohm resistor and is connected to ground via a capacitor; the second branch passes through a 0-ohm resistor and is connected to ground via a capacitor.

6. A PCB structure based on the multi-channel synchronous acquisition isolation circuit according to any one of claims 1-5, characterized in that, Including the first to sixth floors; The multi-channel analog differential signal conditioning circuit, synchronous analog-to-digital converter, MCU main control chip, analog 5V_LDO module, digital 3.3V1_LDO module, digital 3.3V2_LDO module and DC-DC module are placed on the first layer; The digital 5V LDO module, EtherCAT communication circuit, and CAN module are located on the sixth layer. The first layer is the top layer, the second layer is a continuous copper-plated analog ground layer, the third layer is the internal signal layer, the fourth layer is the power layer, the fourth layer is physically divided into multiple copper islands with different voltage domains, the fifth layer is a large-area copper-plated digital ground layer, and the sixth layer is the bottom layer.

7. The PCB structure of the multi-channel synchronous acquisition isolation circuit according to claim 6, characterized in that, The first to sixth layers are electrically isolated into analog circuit regions and digital circuit regions; Using the physical package projection area of ​​the synchronous analog-to-digital converter as the geometric reference, along the physical boundary line between analog and digital pins in the synchronous analog-to-digital converter package, copper-free partition lines with completely consistent positions and vertical alignment are synchronously defined and drawn on layers one to six; the copper-free partition lines physically divide the copper-paved areas of each layer into two halves, one side is defined as the analog circuit area, and the other side is defined as the digital circuit area. The physical separation gap of the multi-layer vertical ground plane dividing line is controlled to a minimum of 30mil; the silicon-based bonding wire inside the synchronous analog-to-digital converter becomes the only signal connection medium between the analog circuit area and the digital circuit area.

8. The PCB structure of the multi-channel synchronous acquisition isolation circuit according to claim 7, characterized in that, The physical extension of the analog circuit area boundary covers all component areas of the multi-channel analog differential signal conditioning circuit, all analog signal input pins of the synchronous analog-to-digital converter, operational amplifier excitation voltage input pins, output excitation voltage pads, and corresponding pads for the reference voltage pins. The physical extension of the digital circuit area boundary covers all digital interface pins of the synchronous analog-to-digital converter, pins of the multi-level isolated power supply architecture, MCU main control chip pads, and EtherCAT communication circuit pads. No digital signal traces are allowed to cross through any adjacent layers in the vertical three-dimensional space corresponding to the analog circuit area.

9. The PCB structure of the multi-channel synchronous acquisition isolation circuit according to claim 7, characterized in that, The components of the multi-channel analog differential signal conditioning circuit within the analog circuit area follow a homogeneous physical layout rule. Each channel of the multi-channel analog differential signal conditioning circuit has a complete physical signal link path through an RC anti-aliasing filter and an amplifier to the analog input pin of the synchronous analog-to-digital converter; In a multi-channel analog differential signal conditioning circuit, all physical packages of all devices and interconnecting copper traces in each channel are confined to the first layer. The absolute difference in physical trace length of the symmetrical differential signal path between each acquisition channel is controlled within 10 mil.

10. The PCB structure of the multi-channel synchronous acquisition isolation circuit according to claim 7, characterized in that, Define an independent power supply isolation zone within the digital circuit area; The digital circuit area is subdivided and independent local reference ground planes are established for each level of power module; The DC-DC module is placed in the power isolation area, and the positive network and ground network of the DC-DC module output are connected at a single point by a 0-ohm resistor connected across the output ground plane dividing line.

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