Bionic event-driven reconfigurable analog-to-digital converter and electronic device

Abstract

The application provides a bionic event-driven reconfigurable analog / digital converter and electronic equipment, which comprises an adjustable signal folding circuit, a dynamic comparator circuit and a bionic control logic circuit, and any two of the adjustable signal folding circuit, the dynamic comparator circuit and the bionic control logic circuit are connected; the adjustable signal folding circuit receives an externally transmitted first voltage signal, folds the first voltage signal to obtain a to-be-compared signal under the condition of triggering a folding action, and transmits the to-be-compared signal to the dynamic comparator circuit; the dynamic comparator circuit generates a comparison result according to the received to-be-compared signal, and transmits the comparison result to the bionic control logic circuit; the bionic control logic circuit generates a bionic clock signal according to the comparison result, and transmits the bionic clock signal to the dynamic comparator circuit; and the dynamic comparator circuit is opened / closed according to the bionic clock signal. The application can reduce the static power consumption generated by the analog / digital converter during operation.

Description

Technical Field

[0001] This application relates to the field of signal processing technology for electronic devices, and in particular to a biomimetic event-driven reconfigurable analog-to-digital converter and electronic device. Background Technology

[0002] In recent years, biosignal acquisition and processing systems for personal healthcare have developed rapidly. Traditional biosignal acquisition system architectures typically involve a pre-amplification stage after acquiring the biosignal. Following this, the amplified biosignal is filtered and sampled by a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for digitization. The generated digital signal is then sent to a wireless transmission module or signal processing module for disease detection. However, traditional system architectures using SAR ADCs and Nyquist sampling repeatedly sample sparse biosignal signals, even during periods of biosignal silence, leading to significant energy consumption issues.

[0003] Currently, Level-Crossing Analog-to-Digital Converters (LC-ADCs) utilize the sparsity of biological signals and achieve event-driven sampling at a lower average sampling rate. This means that biological signals are only sampled when they exceed a predetermined threshold, thus reducing ADC power consumption and achieving data compression during signal silence compared to Nyquist sampling. However, existing LC-ADC architectures, such as... Figure 1 and Figure 2 The architecture diagram shown indicates that the comparator generates high static power consumption during both active and silent input signal periods, resulting in high power consumption of the LC-ADC and wasted resources. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a biomimetic event-driven reconfigurable analog-to-digital converter and electronic device, which can solve the problem that the comparator in the prior art generates high static power consumption during the active or silent period of the input signal, resulting in high power consumption of LC-ADC and waste of resources, while realizing reconfigurable sampling function applicable to various biological signal processing.

[0005] In a first aspect, embodiments of this application provide an analog-to-digital converter, which includes an adjustable signal folding circuit, a dynamic comparator circuit, and a biomimetic control logic circuit, wherein any two of the adjustable signal folding circuit, the dynamic comparator circuit, and the biomimetic control logic circuit are connected together.

[0006] The adjustable signal folding circuit receives a first voltage signal transmitted from the outside. When the folding action is triggered, the first voltage signal is folded to obtain a signal to be compared, and the signal to be compared is transmitted to the dynamic comparator circuit.

[0007] The dynamic comparator circuit generates a comparison result based on the received signal to be compared, and transmits the comparison result to the bionic control logic circuit.

[0008] The bionic control logic circuit generates a bionic clock signal based on the comparison result, and transmits the bionic clock signal to the dynamic comparator circuit.

[0009] The dynamic comparator circuit is turned on / off according to the bionic clock signal.

[0010] In one possible implementation, the biomimetic control logic circuit also receives the second voltage signal transmitted externally; wherein the second voltage signal is adjustable.

[0011] The biomimetic control logic circuit generates different biomimetic clock signals and pulse sampling signals based on the second voltage signal.

[0012] In one possible implementation, the biomimetic control logic circuit transmits the biomimetic clock signal to the adjustable signal folding circuit.

[0013] The adjustable signal folding circuit determines whether to trigger the folding action based on the received bionic clock signal.

[0014] In one possible implementation, the adjustable signal folding circuit includes a first N-channel transistor and a second N-channel transistor;

[0015] The source of the first N-channel transistor and the source of the second N-channel transistor are both connected to an external circuit to receive a third voltage signal transmitted from the outside. This third voltage signal provides external charge for charge injection to the adjustable signal folding circuit.

[0016] The drains of the first N-channel transistor and the second N-channel transistor are both connected to the dynamic comparator circuit to transmit the signal to be compared to the dynamic comparator circuit.

[0017] In one possible implementation, the adjustable signal folding circuit further includes a first capacitor and a second capacitor;

[0018] The upper plate of the first capacitor is connected to the external circuit to receive the first voltage signal transmitted from the outside. The lower plate of the first capacitor is connected to the upper plate of the second capacitor, the drain of the first N-channel transistor, the drain of the second N-channel transistor, and the dynamic comparator circuit.

[0019] The lower plate of the second capacitor is grounded.

[0020] In one possible implementation, the dynamic comparator circuit includes a first P-channel transistor, a second P-channel transistor, a first-stage circuit, a second-stage circuit, and a third-stage circuit, all interconnected.

[0021] The source of the first P-channel transistor is connected to an external circuit, the gate of the first P-channel transistor is connected to the gate of the second P-channel transistor and the bionic control logic circuit, and the drain of the first P-channel transistor is connected to the first stage circuit.

[0022] The source of the second P-channel transistor is connected to the external circuit, and the drain of the second P-channel transistor is connected to the second stage circuit.

[0023] The third-level circuit is connected to the second-level circuit and the external circuit.

[0024] In one possible implementation, the first stage circuit is a differential amplifier circuit, the second stage circuit is a common-source amplifier circuit, and the third stage circuit is an inverter circuit.

[0025] In one possible implementation, the biomimetic control logic circuit includes a first inverter circuit, a second inverter circuit, a third inverter circuit, a control circuit, and a capacitor connected in sequence.

[0026] The first inverter circuit, the second inverter circuit, the third inverter circuit, and the control circuit are all composed of P-channel transistors and N-channel transistors.

[0027] On the other hand, embodiments of this application also provide an electronic device, which includes an external circuit and any of the analog-to-digital converters described above.

[0028] In one possible implementation, the external circuit provides a first voltage signal and a second voltage signal to the analog-to-digital converter, and the analog-to-digital converter generates a pulse sampling signal based on the first voltage signal and the second voltage signal.

[0029] The embodiments of this application can avoid the power consumption generated by the dynamic comparator circuit during signal folding by using an adjustable signal folding circuit, a dynamic comparator circuit, and a biomimetic control logic circuit, thereby reducing the static power consumption generated by the analog-to-digital converter during operation and thus achieving the purpose of avoiding resource waste; at the same time, by changing the second voltage signal to adjust the output rate of the pulse sampling signal, reconfigurable sampling is achieved.

[0030] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic diagram of an LC-ADC in the prior art is shown;

[0033] Figure 2 A schematic diagram of another LC-ADC in the prior art is shown;

[0034] Figure 3 A schematic diagram of an analog-to-digital converter provided in this application is shown;

[0035] Figure 4 A schematic diagram of the adjustable signal folding circuit in the analog-to-digital converter provided in this application is shown;

[0036] Figure 5 A schematic diagram of the dynamic comparator circuit in the analog-to-digital converter provided in this application is shown;

[0037] Figure 6 A schematic diagram of the biomimetic control logic circuit in the analog-to-digital converter provided in this application is shown.

[0038] Icon labels:

[0039] 1-Adjustable signal folding circuit; 11-First N-channel transistor; 12-Second N-channel transistor; 13-First capacitor; 14-Second capacitor; 2-Dynamic comparator circuit; 21-First P-channel transistor; 22-Second P-channel transistor; 23-First stage circuit; 24-Second stage circuit; 25-Third stage circuit; 231-First sub-P-channel transistor; 232-Second sub-P-channel transistor; 233-Third sub-P-channel transistor; 234-First sub-N-channel transistor; 235-Second sub-N-channel transistor; 241-Fourth sub-P-channel transistor; 242- 251-Third sub-N-channel transistor; 252-Fourth sub-N-channel transistor; 3-Bionic control logic circuit; 31-First inverter circuit; 311-Third P-channel transistor; 312-Third N-channel transistor; 32-Second inverter circuit; 321-Fourth P-channel transistor; 322-Fourth N-channel transistor; 33-Third inverter circuit; 331-Fifth P-channel transistor; 332-Fifth N-channel transistor; 34-Control circuit; 341-Sixth P-channel transistor; 342-Sixth N-channel transistor; 35-Capacitor. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0041] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0042] To keep the following description clear and concise, detailed descriptions of known functions and components are omitted. The analog-to-digital converter provided in this application will now be described in detail.

[0043] Figure 3 This application illustrates an embodiment of an analog-to-digital converter, which is provided by... Figure 3 It can be seen that the analog-to-digital converter includes an adjustable signal folding circuit 1, a dynamic comparator circuit 2, and a bionic control logic circuit 3, and any two of the adjustable signal folding circuit 1, the dynamic comparator circuit 2, and the bionic control logic circuit 3 are connected.

[0044] In specific implementation, the adjustable signal folding circuit 1 is connected to an external circuit. The external circuit transmits a first voltage signal to the adjustable signal folding circuit 1, that is, the external circuit provides voltage to the adjustable signal folding circuit 1. The adjustable signal folding circuit 1 receives the first voltage signal transmitted from the outside. This first voltage signal is the signal corresponding to the input voltage provided by the circuit where the analog-to-digital converter is located, and it changes in real time. Then, the first voltage signal is folded to obtain a signal to be compared, and the signal to be compared is transmitted to the dynamic comparator circuit 2. The signal to be compared includes the voltage to be compared. The voltage value of the folded signal to be compared falls within a preset voltage range, which is from 0 to the maximum supply voltage of the external circuit.

[0045] It is worth noting that the voltage difference between the maximum and minimum preset voltage values ​​included in this preset voltage range can have a certain impact on the accuracy of the analog-to-digital converter and even the sampling accuracy. Therefore, this preset voltage range can be adjusted according to actual needs.

[0046] After receiving the signal to be compared, the dynamic comparator circuit 2 generates a comparison result based on the received signal. Optionally, the dynamic comparator circuit 2 compares the voltage to be compared included in the received signal with the first comparison voltage and the second comparison voltage. In this embodiment, the first comparison voltage is a high threshold voltage and the second comparison voltage is a low threshold voltage. Of course, the first comparison voltage and the second comparison voltage can be adjusted according to actual needs.

[0047] After generating the comparison result, the dynamic comparator circuit 2 transmits the comparison result to the biomimetic control logic circuit 3. This comparison result can include 0 and 1; for example, the comparison result is 1 when the voltage to be compared is greater than a first comparison voltage, and 0 when the voltage to be compared is less than a second comparison voltage. Of course, the comparison result can also be set to include high and low levels, etc., but this embodiment does not specifically limit this.

[0048] After receiving the comparison result, the bionic control logic circuit 3 generates a bionic clock signal based on the comparison result and transmits the bionic clock signal to the dynamic comparator circuit 2. This causes the dynamic comparator circuit 2 to turn on / off according to the bionic clock signal. Optionally, when the bionic clock signal represents a low level, the dynamic comparator circuit 2 is turned on so that the analog-to-digital converter can generate a pulse sampling signal normally for sampling biological signals. When the bionic clock signal represents a high level, the dynamic comparator circuit 2 is turned off to avoid power consumption during signal folding, thereby reducing the static power consumption of the analog-to-digital converter during operation and thus avoiding resource waste.

[0049] In practical implementation, the bionic control logic circuit 3 also receives a second voltage signal transmitted externally, enabling it to generate different bionic clock signals and pulse sampling signals based on this second voltage signal. Here, the voltage value represented by the second voltage signal is adjustable. A higher voltage value results in a shorter time width for the bionic clock signal generated by the bionic control logic circuit 3 and a higher output rate for the pulse sampling signal. Conversely, a lower voltage value results in a longer time width for the bionic clock signal generated by the bionic control logic circuit 3 and a lower output rate for the pulse sampling signal. In other words, by controlling the second voltage signal transmitted to the bionic control logic circuit 3, the analog-to-digital converter can be adapted to various working scenarios, i.e., to collect various biological signals, thus improving its versatility for a wide range of biological signals.

[0050] Accordingly, by adjusting the time width of the bionic clock signal, the output rate of the pulse sampling signal of the analog-to-digital converter can be adjusted. At the same time, the folding speed of the adjustable signal folding circuit 1 can also be adjusted to achieve the purpose of reconfigurable sampling.

[0051] In a specific implementation, the bionic control logic circuit 3 also transmits the bionic clock signal to the adjustable signal folding circuit 1, so that the adjustable signal folding circuit 1 determines whether to trigger the folding action based on the received bionic clock signal. Optionally, the folding action is triggered when the bionic clock signal is a high-level signal, and the folding action is not triggered when the bionic clock signal is a low-level signal.

[0052] Figure 4 A schematic diagram of the adjustable signal folding circuit 1 is shown, with reference to... Figure 4 As can be seen, the adjustable signal folding circuit 1 shown in the embodiments of this application includes a first N-channel transistor 11, a second N-channel transistor 12, a first capacitor 13, and a second capacitor 14. Of course, those skilled in the art should know that... Figure 2As just one example, the first N-channel transistor 11 and the second N-channel transistor 12 can be interchanged, as can the first capacitor 13 and the second capacitor 14, and so on.

[0053] Combination Figure 3 and Figure 4 It is known that the gates of the first N-channel transistor 11 and the second N-channel transistor 12 are both connected to the bionic control logic circuit 3 to receive the bionic clock signal transmitted by the bionic control logic circuit 3 through the gates of the first N-channel transistor 11 and the second N-channel transistor 12. In this embodiment, the bionic clock signal is received / not received according to the comparison result type of the signal to be compared. When the bionic clock signal is a high-level signal, the bionic clock signal is received through the gate of the first N-channel transistor 11 or the gate of the second N-channel transistor 12. Optionally, when the voltage to be compared is greater than the first comparison voltage, the bionic clock signal is received through the gate of the first N-channel transistor 11, and when the voltage to be compared is less than the second comparison voltage, the bionic clock signal is received through the gate of the second N-channel transistor 12, etc. This embodiment does not specifically limit this.

[0054] Continue to refer to Figure 4 It is known that the source of the first N-channel transistor 11 and the source of the second N-channel transistor 12 are both connected to the external circuit to receive the third voltage signal transmitted from the outside. The third voltage signal provides the adjustable signal folding circuit 1 with external charge for charge injection. The drain of the first N-channel transistor 11, the drain of the second N-channel transistor 12, the lower plate of the first capacitor 13 and the upper plate of the second capacitor 14, and the dynamic comparator circuit 2 are connected. The upper plate of the first capacitor 13 is connected to the external circuit to receive the first voltage signal transmitted from the outside, and the lower plate of the second capacitor 14 is grounded.

[0055] Based on this, the upper plate of the first capacitor 13 receives the first voltage signal transmitted externally. After receiving the first voltage signal, it further determines whether the bionic clock signal received through the gate of the first N-channel transistor 11 or the gate of the second N-channel transistor 12 is a high-level signal. If the bionic clock signal is a high-level signal, based on the folding rule, the first voltage signal is folded using the first N-channel transistor 11, the second N-channel transistor 12, the first capacitor 13, and the second capacitor 14. The folding rule may include folding the voltage value included in the first voltage signal into a voltage to be compared, and making the voltage to be compared within a preset voltage range. At this time, the voltage of the first capacitor 13 and the second capacitor 14 is the same as the voltage value represented by the third voltage signal.

[0056] After obtaining the signal to be compared, the signal to be compared is transmitted to the dynamic comparator circuit 2.

[0057] Figure 5 A schematic diagram of dynamic comparator circuit 2 is shown, refer to... Figure 5 As can be seen, the dynamic comparator circuit 2 shown in the embodiments of this application includes a first P-channel transistor 21, a second P-channel transistor 22, a first-stage circuit 23, a second-stage circuit 24, and a third-stage circuit 25, all of which are interconnected. Specifically, the source of the first P-channel transistor 21 is connected to an external circuit to receive the power supplied by the external circuit to the dynamic comparator circuit 2. The gate of the first P-channel transistor 21 is connected to the gate of the second P-channel transistor 22 and the bionic control logic circuit 3. The drain of the first P-channel transistor 21 is connected to the first-stage circuit 23. The source of the second P-channel transistor 22 is connected to an external circuit. The drain of the second P-channel transistor 22 is connected to the second-stage circuit 24. The third-stage circuit 25 is connected to the second-stage circuit 24 and the external circuit.

[0058] As one example, the first-stage circuit 23 is a differential amplifier circuit, which includes a first sub-P-channel transistor 231, a second sub-P-channel transistor 232, a third sub-P-channel transistor 233, a first sub-N-channel transistor 234, and a second sub-N-channel transistor 235. The drain of the first sub-P-channel transistor 231 is connected to the source of the first sub-P-channel transistor 231, and the gate of the first sub-P-channel transistor 231 is connected to the external bias voltage of the second-stage circuit 24. The drain of the first sub-P-channel transistor 231 is connected to the source of the second sub-P-channel transistor 232 and the third sub-P-channel transistor 235. The source of transistor 233 is connected, the gate of the second sub-P-channel transistor 232 is connected to the adjustable signal folding circuit 1, the drain of the second sub-P-channel transistor 232 is connected to the drain and gate of the first sub-N-channel transistor 234 and the gate of the second sub-N-channel transistor 235; the gate of the third sub-P-channel transistor 233 is connected to the first comparison voltage, the drain of the third sub-P-channel transistor 233 is connected to the drain of the second sub-N-channel transistor 235 and the second stage circuit 24, and the sources of the first sub-N-channel transistor 234 and the second sub-N-channel transistor 235 are both grounded.

[0059] As one example, the second-stage circuit 24 is a common-source amplifier circuit, which includes a fourth sub-P-channel transistor 241 and a third sub-N-channel transistor 242. The source of the fourth sub-P-channel transistor 241 is connected to the drain of the second P-channel transistor 22, the gate of the fourth sub-P-channel transistor 241 is connected to the gate of the first sub-P-channel transistor 231, the drain of the fourth sub-P-channel transistor 241 is connected to the drain of the third sub-N-channel transistor 242 and the third-stage circuit 25, the gate of the third sub-N-channel transistor 242 is connected to the drain of the third sub-P-channel transistor 233 and the drain of the second sub-N-channel transistor 235, and the source of the third sub-N-channel transistor 242 is grounded.

[0060] As one example, the third-stage circuit 25 is an inverter circuit, which includes a fifth sub-P-channel transistor 251 and a fourth sub-N-channel transistor 252. The source of the fifth sub-P-channel transistor 251 is connected to an external circuit, and the gate of the fifth sub-P-channel transistor 251 is connected to the drain of the fourth sub-P-channel transistor 241, the drain of the third sub-N-channel transistor 242, and the gate of the fourth sub-N-channel transistor 252. The drain of the fifth sub-P-channel transistor 251 is connected to the drain of the fourth sub-N-channel transistor 252 and the output terminal of the comparison result. The source of the fourth sub-N-channel transistor 252 is grounded.

[0061] Figure 6 A schematic diagram of the biomimetic control logic circuit 3 is shown, with reference to... Figure 6 As can be seen, the biomimetic control logic circuit 3 shown in this embodiment includes a first inverter circuit 31, a second inverter circuit 32, a third inverter circuit 33, a control circuit 34, and a capacitor 35 connected in sequence, so as to improve the stability and circuit response speed of the biomimetic control logic circuit 3 through the first inverter circuit 31, the second inverter circuit 32, and the third inverter circuit 33. Optionally, the first inverter circuit 31, the second inverter circuit 32, the third inverter circuit 33, and the control circuit 34 are all composed of P-channel transistors and N-channel transistors.

[0062] As one example, the first inverter circuit 31 includes a third P-channel transistor 311 and a third N-channel transistor 312, the second inverter circuit 32 includes a fourth P-channel transistor 321 and a fourth N-channel transistor 322, the third inverter circuit 33 includes a fifth P-channel transistor 331 and a fifth N-channel transistor 332, and the control circuit 34 includes a sixth P-channel transistor 341 and a sixth N-channel transistor 342. The sources of the third P-channel transistor 311, the fourth P-channel transistor 321, the fifth P-channel transistor 331, and the sixth P-channel transistor 341 are all connected to external circuits. The gate of the third P-channel transistor 311 is connected to the dynamic comparator circuit 2 to receive the comparison result. The gate of the third P-channel transistor 311 is also connected to the gate of the third N-channel transistor 312. The drain of the third P-channel transistor 311 is connected to the drain of the third N-channel transistor 312, the gate of the fourth P-channel transistor 321, and the gate of the fourth N-channel transistor 322. The drain of the fourth P-channel transistor 321 is connected to the drain of the fourth N-channel transistor 322 and the fifth P-channel transistor 341. The gate of transistor 331, the gate of the fifth N-channel transistor 332, and the output terminal of the pulse sampling signal are connected. The drain of the fifth P-channel transistor 331 is connected to the drain of the fifth N-channel transistor 332 and the gate of the sixth P-channel transistor 341. The drain of the sixth P-channel transistor 341 is connected to the drain of the sixth N-channel transistor 342, the upper plate of capacitor 35, and the output terminal of the bionic clock signal. The gate of the sixth N-channel transistor 342 is connected to the external second voltage signal. The sources of the third N-channel transistor 312, the fourth N-channel transistor 322, the fifth N-channel transistor 332, the sixth N-channel transistor 342, and the lower plate of capacitor 35 are all grounded.

[0063] On the other hand, embodiments of this application also provide an electronic device, including an external circuit and any of the aforementioned analog-to-digital converters (ADCs). The external circuit provides a first voltage signal and a second voltage signal to the ADC. The ADC generates a pulse sampling signal based on the first and second voltage signals. Of course, the external circuit can also be used to provide a power supply voltage to power the ADC. Embodiments of this application, through the ADC, avoid the power consumption generated by the dynamic comparator circuit in the ADC during signal folding, thus reducing the power consumption generated by the ADC during operation and achieving the goal of avoiding resource waste. Simultaneously, by changing the second voltage signal to adjust the output rate of the pulse sampling signal, reconfigurable sampling is achieved.

[0064] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0065] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

[0066] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0067] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0068] The foregoing has described in detail several embodiments of this application, but this application is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications based on the concept of this application, and all such variations and modifications should fall within the scope of protection claimed in this application.

Claims

1. A biomimetic event-driven reconfigurable analog-to-digital converter, characterized in that, It includes an adjustable signal folding circuit, a dynamic comparator circuit, and a biomimetic control logic circuit, wherein any two of the adjustable signal folding circuit, the dynamic comparator circuit, and the biomimetic control logic circuit are connected. The adjustable signal folding circuit receives a first voltage signal transmitted from the outside. When the folding action is triggered, the first voltage signal is folded to obtain a signal to be compared, and the signal to be compared is transmitted to the dynamic comparator circuit. The dynamic comparator circuit generates a comparison result based on the received signal to be compared, and transmits the comparison result to the bionic control logic circuit. The bionic control logic circuit generates a bionic clock signal based on the comparison result, and transmits the bionic clock signal to the dynamic comparator circuit. The dynamic comparator circuit is turned on / off according to the bionic clock signal; The biomimetic control logic circuit also receives a second voltage signal transmitted from an external source; wherein the second voltage signal is adjustable. The biomimetic control logic circuit generates different biomimetic clock signals and pulse sampling signals based on the second voltage signal; The biomimetic control logic circuit transmits the biomimetic clock signal to the adjustable signal folding circuit. The adjustable signal folding circuit determines whether to trigger the folding action based on the received bionic clock signal.

2. The analog-to-digital converter according to claim 1, characterized in that, The adjustable signal folding circuit includes a first N-channel transistor and a second N-channel transistor. The source of the first N-channel transistor and the source of the second N-channel transistor are both connected to an external circuit to receive a third voltage signal transmitted from the outside. The third voltage signal provides the adjustable signal folding circuit with external charge for charge injection. The drains of the first N-channel transistor and the second N-channel transistor are both connected to the dynamic comparator circuit to transmit the signal to be compared to the dynamic comparator circuit.

3. The analog-to-digital converter according to claim 2, characterized in that, The adjustable signal folding circuit also includes a first capacitor and a second capacitor. The upper plate of the first capacitor is connected to the external circuit to receive the first voltage signal transmitted from the outside. The lower plate of the first capacitor is connected to the upper plate of the second capacitor, the drain of the first N-channel transistor, the drain of the second N-channel transistor, and the dynamic comparator circuit. The lower plate of the second capacitor is grounded.

4. The analog-to-digital converter according to claim 1, characterized in that, The dynamic comparator circuit includes a first P-channel transistor, a second P-channel transistor, a first-stage circuit, a second-stage circuit, and a third-stage circuit, all of which are interconnected. The source of the first P-channel transistor is connected to an external circuit, the gate of the first P-channel transistor is connected to the gate of the second P-channel transistor and the bionic control logic circuit, and the drain of the first P-channel transistor is connected to the first stage circuit. The source of the second P-channel transistor is connected to the external circuit, and the drain of the second P-channel transistor is connected to the second stage circuit. The third-level circuit is connected to the second-level circuit and the external circuit.

5. The analog-to-digital converter according to claim 4, characterized in that, The first stage circuit is a differential amplifier circuit, the second stage circuit is a common-source amplifier circuit, and the third stage circuit is an inverter circuit.

6. The analog-to-digital converter according to claim 1, characterized in that, The biomimetic control logic circuit includes a first inverter circuit, a second inverter circuit, a third inverter circuit, a control circuit, and a capacitor connected in sequence. The first inverter circuit, the second inverter circuit, the third inverter circuit, and the control circuit are all composed of P-channel transistors and N-channel transistors.

7. An electronic device, characterized in that, It includes external circuitry and an analog-to-digital converter as described in any one of claims 1-6.

8. The electronic device according to claim 7, characterized in that, The external circuit provides a first voltage signal and a second voltage signal to the analog-to-digital converter, and the analog-to-digital converter generates a pulse sampling signal based on the first voltage signal and the second voltage signal.

Images