Shift register, gate drive circuit and its driving method, display panel

Abstract

This application relates to a shift register, a gate driving circuit and its driving method, and a display panel. The shift register includes: an input module; a control module including a first switching unit, a second switching unit, and an energy storage unit, wherein the control terminal of the first switching unit receives a first control signal, the second terminal of the first switching unit is electrically connected to the first terminal of the energy storage unit and the second terminal of the second switching unit, the control terminal of the second switching unit receives a second control signal, and the first terminal of the second switching unit receives a second power supply signal; and an output module; in a first sub-stage of the holding phase, the first switching unit is turned off under the control of the first control signal, and the second switching unit is turned on under the control of the second control signal, so that the voltage levels of the first terminal and the third terminal of the energy storage unit remain consistent. Using the above-mentioned shift register, the energy storage unit can be controlled to not charge or discharge in the first sub-stage, thereby reducing power consumption.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register, a gate driving circuit and driving method, and a display panel. Background Technology

[0002] With the development of display technology, while pursuing higher resolutions, the power consumption of display devices has also increased. In order to reduce the power consumption of display devices, some products even operate at a driving frequency of less than 0.1Hz in standby mode.

[0003] In related technologies, during the low-frequency holding phase of the display panel, the shift register circuit is still in normal working condition, resulting in the same power consumption as in the high-frequency display mode. This causes the display panel to still have a large power consumption, thus failing to fully utilize the low power consumption advantage of the low-frequency display mode. Summary of the Invention

[0004] This application provides a shift register, a gate driving circuit and driving method, and a display panel to reduce the power consumption of the display device in low-frequency display mode.

[0005] In a first aspect, embodiments of this application provide a shift register, including:

[0006] An input module, wherein the control terminal of the input module is used to receive a first clock signal, and the multiple input terminals of the input module are respectively used to receive an input signal, the first clock signal and a first power signal;

[0007] The control module includes a first switching unit, a second switching unit, and an energy storage unit. The control terminal of the first switching unit is used to receive a first control signal. The first terminal of the first switching unit is electrically connected to the first output terminal of the input module. The second terminal of the first switching unit is electrically connected to the first terminal of the energy storage unit and the second terminal of the second switching unit. The control terminal of the second switching unit is used to receive a second control signal. The first terminal of the second switching unit is used to receive a second power signal. The second terminal of the energy storage unit is used to receive a second clock signal.

[0008] An output module, wherein multiple control terminals of the output module are electrically connected to the first power signal, the first output terminal of the input module, the second output terminal of the input module, and the third terminal of the energy storage unit, respectively; multiple input terminals of the output module are respectively used to receive the second clock signal, the first power signal, and the second power signal; and the output terminal of the output module is used to output a scan signal; wherein,

[0009] In the first sub-stage of the holding phase, the first switching unit is used to disconnect under the control of the first control signal, and the second switching unit is used to turn on under the control of the second control signal, so that the level states of the first terminal of the energy storage unit and the third terminal of the energy storage unit are consistent.

[0010] Secondly, embodiments of this application provide a gate driving circuit, including a first clock signal line, a second clock signal line, a first control signal line, a second control signal line, and a plurality of cascaded shift registers as described above; wherein,

[0011] The input terminal of the input module in the first-level shift register is used to receive a start signal. The control terminal of the first switch unit in each shift register is electrically connected to the first control signal line to receive the first control signal. The control terminal of the second switch unit in each shift register is electrically connected to the second control signal line to receive the second control signal.

[0012] The control terminal and the first input terminal of the input module in the i-th stage shift register are electrically connected to the first clock signal line to receive the first clock signal; the second terminal of the energy storage unit and the first input terminal of the output module in the i-th stage shift register are electrically connected to the second clock signal line to receive the second clock signal; where i is a positive integer greater than 1;

[0013] The control terminal and the first input terminal of the input module in the (i+1)th stage shift register are electrically connected to the second clock signal line to receive the second clock signal; the second terminal of the energy storage unit and the first input terminal of the output module in the i-th stage shift register are electrically connected to the first clock signal line to receive the first clock signal; the input terminal of the input module in the (i+1)th stage shift register is electrically connected to the output terminal of the output module in the i-th stage shift register.

[0014] Thirdly, embodiments of this application provide a driving method for a gate driving circuit, characterized in that it is applied to the gate driving circuit as described in the second aspect, the driving method for the gate driving circuit includes a data writing stage and a holding stage; wherein, in a first sub-stage of the holding stage, a first switching unit of the gate driving circuit is controlled to be turned off, and a second switching unit of the gate driving circuit is controlled to be turned on, so that the level states of the first terminal of the energy storage unit and the third terminal of the energy storage unit are consistent.

[0015] Fourthly, embodiments of this application provide a display panel, characterized in that it includes the gate driving circuit as described in the second aspect.

[0016] The shift register, gate driving circuit and driving method, and display panel provided in this application embodiment include an input module, a control module, and an output module. The control module includes a first switching unit, a second switching unit, and an energy storage unit. The control terminal of the first switching unit is used to receive a first control signal. The first terminal of the first switching unit is electrically connected to the first output terminal of the input module. The second terminal of the first switching unit is electrically connected to the first terminal of the energy storage unit and the second terminal of the second switching unit, respectively. The control terminal of the second switching unit is used to receive a second control signal. The first terminal of the second switching unit is used to receive a second power signal. The second terminal of the energy storage unit is used to receive a second clock signal. In the first sub-stage of the hold phase, the first switching unit is disconnected under the control of the first control signal, and the second switching unit is turned on under the control of the second control signal, so that the level states of the first terminal and the third terminal of the energy storage unit are consistent. This allows the energy storage unit to be controlled to not charge and discharge in the first sub-stage, avoiding power consumption caused by charging and discharging. For display panels with a long hold phase time, the power consumption of the display panel can be reduced to a large extent and the display performance can be improved by setting the time of the first sub-stage. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the schematic diagrams of a shift register provided in an embodiment of this application;

[0019] Figure 2 A signal timing diagram of a shift register provided in an embodiment of this application;

[0020] Figure 3 This is a signal timing diagram of another shift register provided in an embodiment of this application;

[0021] Figure 4 This is a second schematic diagram of a shift register provided in an embodiment of this application;

[0022] Figure 5 This is the third schematic diagram of a shift register provided in an embodiment of this application;

[0023] Figure 6 This is a signal timing diagram of another shift register provided in an embodiment of this application;

[0024] Figure 7This is the fourth schematic diagram of a shift register provided in an embodiment of this application;

[0025] Figure 8 Fifth schematic diagram of a shift register provided in the embodiments of this application;

[0026] Figure 9 This is the sixth schematic diagram of a shift register provided in an embodiment of this application;

[0027] Figure 10 This is the seventh schematic diagram of a shift register provided in an embodiment of this application;

[0028] Figure 11 This is the eighth schematic diagram of a shift register provided in an embodiment of this application;

[0029] Figure 12 This is the ninth schematic diagram of a shift register provided in an embodiment of this application;

[0030] Figure 13 This is the tenth schematic diagram of a shift register provided in an embodiment of this application;

[0031] Figure 14 This is eleventh of a schematic diagram of a shift register provided in an embodiment of this application;

[0032] Figure 15 This is the twelfth schematic diagram of a shift register provided in an embodiment of this application;

[0033] Figure 16 This is the thirteenth schematic diagram of a shift register provided in an embodiment of this application;

[0034] Figure 17 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0035] Figure 18 This is a schematic diagram of the structure of the first metal layer provided in an embodiment of this application;

[0036] Figure 19 This is a schematic diagram of the structure of the second metal layer provided in an embodiment of this application;

[0037] Figure 20 This is a schematic diagram of the structure of the third metal layer provided in an embodiment of this application;

[0038] Figure 21 This is a schematic diagram of the contact hole structure provided in an embodiment of this application;

[0039] Figure 22 This is a schematic diagram of the structure of the fourth metal layer provided in an embodiment of this application;

[0040] Figure 23 A schematic diagram of the structure formed by stacking the third metal layer, contact hole, and fourth metal layer from bottom to top according to an embodiment of this application;

[0041] Figure 24 This is a schematic diagram of the planar layout structure of the display panel provided in an embodiment of this application. Detailed Implementation

[0042] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0044] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0045] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0046] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0047] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0048] As mentioned in the background section, because shift registers contain active or passive components such as transistors and capacitors, the clock signal supplied to the shift register during its operation will repeatedly charge and discharge the components in the shift register. Especially during the low-frequency holding phase of the display panel, when the signal output terminal of the shift register outputs a fixed level for a long time, the clock signal continuously charges and discharges the components in the shift register repeatedly, which will result in wasted power consumption and is not conducive to the low power consumption of the shift register.

[0049] Based on the aforementioned technical problems, the inventors discovered that during the low-frequency hold phase, by controlling the potential of each terminal of the device in the shift register that is frequently charged and discharged due to the clock signal to remain consistent, frequent charging and discharging of the device can be avoided, thereby reducing power consumption. Based on this, the inventors further developed the technical solution of the embodiments of this application. Specifically, the embodiments of this application provide a shift register, including: an input module 10, a control module 20, and an output module 30; wherein, the control terminal of the input module 10 is used to receive a first clock signal CK, and multiple input terminals of the input module 10 are respectively used to receive an input signal IN, the first clock signal CK, and a first power signal VGL; the control module 20 includes a first switching unit 21, a second switching unit 22, and an energy storage unit 23, wherein the control terminal of the first switching unit 21 is used to receive a first control signal SW1, the first terminal of the first switching unit 21 is electrically connected to the first output terminal of the input module 10, the second terminal of the first switching unit 21 is electrically connected to the first terminal of the energy storage unit 23 and the second terminal of the second switching unit 22, the control terminal of the second switching unit 22 is used to receive a second control signal SW2, and the second switching unit 23... The first terminal of the energy storage unit 22 is used to receive the second power signal VGH, and the second terminal of the energy storage unit 23 is used to receive the second clock signal XCK. The multiple control terminals of the output module 30 are electrically connected to the first power signal VGL, the first output terminal of the input module 10, the second output terminal of the input module 10, and the third terminal of the energy storage unit, respectively. The multiple input terminals of the output module 30 are used to receive the second clock signal XCK, the first power signal VGL, and the second power signal VGH, respectively. The output terminal of the output module 30 is used to output the scan signal OUT. In the first sub-stage of the holding phase, the first switching unit 21 is used to disconnect under the control of the first control signal SW1, and the second switching unit 22 is used to turn on under the control of the second control signal SW2, so that the level states of the first terminal and the third terminal of the energy storage unit 23 are consistent.

[0050] By adopting the above technical solution, in the first sub-stage of the holding phase, the first switching unit 21 and the second switching unit 22 control the level states of the first and third terminals of the energy storage unit 23 to remain consistent, thereby avoiding frequent charging and discharging of the energy storage unit 23 in the first sub-stage and reducing power consumption.

[0051] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0052] Figure 1 This is a schematic diagram of a shift register provided in an embodiment of this application. See also... Figure 1 The shift register includes an input module 10, a control module 20, and an output module 30. The control terminal of the input module 10 receives a first clock signal CK, and multiple input terminals of the input module 10 receive an input signal IN, the first clock signal CK, and a first power signal VGL, respectively. The control module 20 includes a first switching unit 21, a second switching unit 22, and an energy storage unit 23. The control terminal of the first switching unit 21 receives a first control signal SW1, and its first terminal is electrically connected to the first output terminal of the input module 10. The second terminal of the first switching unit 21 is electrically connected to the first terminal of the energy storage unit 23 and the second terminal of the second switching unit 22, respectively. The control terminal of the second switching unit 22 receives a second control signal SW2, and its first terminal receives a second power signal VGH. The second terminal of the energy storage unit 23 receives a second clock signal XCK. The multiple control terminals of the output module 30 are electrically connected to the first power signal VGL, the first output terminal of the input module 10, the second output terminal of the input module 10, and the third terminal of the energy storage unit, respectively. The multiple input terminals of the output module 30 are used to receive the second clock signal XCK, the first power signal VGL, and the second power signal VGH, respectively. The output terminal of the output module 30 is used to output the scan signal OUT.

[0053] Figure 2 This is a signal timing diagram of a shift register provided in an embodiment of this application. Figure 2As shown, the shift register includes a data writing phase (Active frame) and a hold phase (Keep frame), wherein the hold phase includes a first sub-phase. In the first sub-phase of the hold phase, the first switching unit 21 is turned off under the control of the first control signal SW1, and the second switching unit 22 is turned on under the control of the second control signal SW2, so that the level states of the first terminal and the third terminal of the energy storage unit 23 are consistent. The hold phase may include only the first sub-phase, or it may include other phases, which is not limited here. Based on this, in the first sub-phase, the first switching unit 21 is in the off state and the second switching unit 22 is in the on state. That is, the first switching unit 21 cuts off the path between the input module 10 and the first terminal of the energy storage unit 23, and the second switching unit 22 turns on the path between the second power signal VGH and the first terminal of the energy storage unit 23. Therefore, the potential of the first terminal of the energy storage unit 23 is not affected by the first clock signal CK, and the potential states of the first terminal and the third terminal of the energy storage unit 23 are consistent. Therefore, the energy storage unit 23 will not charge or discharge, thereby reducing power consumption. For example, if the base frame of the display panel including the shift register is 60Hz, the data writing phase is 1Hz, and the first sub-phase is 59Hz, the energy storage unit 23 will not charge or discharge within the 59Hz time. Compared with the frequent charging and discharging within 59Hz in related technologies, this application can greatly reduce the power consumption of the display panel.

[0054] Figure 3 This is a signal timing diagram of a shift register provided in an embodiment of this application. Figure 3 As shown, the holding phase includes a first sub-phase and at least one second sub-phase. In the second sub-phase of the holding phase, the first switching unit 21 is turned on under the control of the first control signal SW1, and the second switching unit 22 is turned off under the control of the second control signal SW2, so that the energy storage unit 23 is charged and discharged according to the control signal output from the first output terminal of the input module 10 and the second power signal VGH under the control of the second clock signal XCK. Based on this, in the second sub-phase, the first switching unit 21 is in the on state and the second switching unit 22 is in the off state. That is, the first switching unit 21 connects the path between the input module 10 and the first terminal of the energy storage unit 23, and the second switching unit 22 disconnects the path between the second power signal VGH and the first terminal of the energy storage unit 23. In this case, the shift register can be restored to the state of the data writing phase, thereby preparing in advance for the next data writing to ensure the display effect of the display panel including the shift register.

[0055] Please continue reading. Figure 3The duration of the second sub-stage is greater than or equal to the period during which the first clock signal CK has an effective level. Based on this, it can be ensured that the potential of the first terminal of the energy storage unit 23 is restored to the state of the data writing stage in the second sub-stage, so that the shift register can be restored to the state of the data writing stage, so as to smoothly transition to the next display through the second sub-stage and improve the display performance of the display panel including the shift register.

[0056] Please continue reading. Figure 3 The first sub-stage precedes the second sub-stage. It can be understood that during the holding stage, the potentials of the first and third terminals of the energy storage unit 23 remain consistent in the first sub-stage, thus preventing the energy storage unit 23 from charging or discharging in the first sub-stage. Then, in the second sub-stage, by switching the on / off states of the first switching unit 21 and the second switching unit 22, the potential of the first terminal of the energy storage unit 23 is restored to the data writing stage state, thereby controlling the shift register to return to the data writing state, preparing for the next display, reducing power consumption, and ensuring display quality.

[0057] Please continue reading. Figure 2 and Figure 3 During the data writing phase, the first switching unit 21 is turned on under the control of the first control signal SW1, and the second switching unit 22 is turned off under the control of the second control signal SW2, so that the energy storage unit 23 is charged and discharged according to the control signal output from the first output terminal of the input module 10 and the second power signal VGH under the control of the second clock signal XCK. Based on this, the output module 30 can output a scan signal OUT according to the second clock signal XCK, the first power signal VGL, and the second power signal VGH under the action of the input module 10 and the control module 20, thus supporting the display function of the display panel.

[0058] Figure 4 and Figure 5 This is a schematic diagram of the shift register provided in an embodiment of this application. Figure 4 and Figure 5As shown, the first switching unit 21 includes a first transistor T1. The control terminal of the first transistor T1 is used to receive a first control signal SW1. The first terminal of the first transistor T1 is connected to the first output terminal of the input module 10, and the second terminal of the first transistor T1 is electrically connected to the first terminal of the energy storage unit 23 and the second terminal of the second switching unit 22, respectively. In the first sub-stage of the holding phase, the first transistor T1 is used to disconnect under the control of the first control signal SW1. Based on this, the path between the input module 10 and the first terminal of the energy storage unit 23 is cut off by the first transistor T1. As a result, the potential of the first terminal of the energy storage unit 23 is not affected by the input module 10, so that the potential of the first terminal of the energy storage unit 23 is not affected by the change of the first clock signal CK in the first sub-stage. This keeps the potential of the first terminal and the third terminal of the energy storage unit 23 consistent, so that the energy storage unit 23 will not charge or discharge in the first sub-stage, avoiding large power consumption due to the charging and discharging of the energy storage unit 23.

[0059] Please continue reading. Figure 4 and Figure 5 The first transistor T1 is either a P-type transistor or an N-type transistor. For example, the first transistor T1 can be a P-type field-effect transistor (FET), a P-type metal-oxide-semiconductor field-effect transistor (MOSFET / MOS), an NFET, or an NMOS. Figure 4 Taking the first transistor T1 as a P-type transistor as an example, in Figure 4 In the diagram, when the first control signal SW1 is low, the first transistor T1 is in the on state; when the first control signal SW1 is high, the first transistor T1 is in the off state. (See also...) Figure 2 and Figure 3 The timing sequence is shown. Figure 5 Taking the first transistor T1 as an N-type transistor as an example, in Figure 5 In the diagram, when the first control signal SW1 is high, the first transistor T1 is in the off state; when the first control signal SW1 is low, the first transistor T1 is in the on state. (See also...) Figure 6 The provided signal timing diagram is when the first transistor T1 is an N-type transistor.

[0060] In the embodiments of this application, when the shift register includes P-type transistors, the first terminal of each transistor is the source, and the second terminal of each transistor is the drain. When the shift register uses N-type transistors, the first terminal of each transistor is the drain, and the second terminal of each transistor is the source. The difference between using N-type transistors and using P-type transistors is that the signal level states are reversed, but the control principles are the same.

[0061] Figure 7 This is a schematic diagram of a shift register provided in an embodiment of this application. Figure 7 As shown, the first switching unit 21 further includes a second transistor T2. The control terminal of the second transistor T2 is used to receive the first power supply signal VGL. The first terminal of the second transistor T2 is electrically connected to the second terminal of the second switching unit 22 and the second terminal of the first transistor T1, respectively. The second terminal of the second transistor T2 is electrically connected to the first terminal of the energy storage unit 23. Optionally, the second transistor T2 can be a P-type transistor or an N-type transistor, and the type of the second transistor T2 is the same as that of the first transistor T1. Figure 7 Taking P-type transistors as an example, the first power signal VGL is a low-level signal. Under the control of the first power signal VGL, the second transistor T2 remains in the conducting state. Based on this, the first terminal of the energy storage unit 23 is connected to the second terminal of the first transistor T1 and the second terminal of the second switching unit 22 through the second transistor T2, thereby reducing the direct influence of the first clock signal CK on the potential of the first terminal of the energy storage unit 23 and stabilizing the potential of the energy storage unit 23, thereby improving the display performance of the display panel.

[0062] Please continue reading. Figure 4 , Figure 5 and Figure 7 The second switching unit 22 includes a third transistor T3. The control terminal of the third transistor T3 is used to receive the second control signal SW2, the first terminal of the third transistor T3 is used to receive the second clock signal XCK, and the second terminal of the third transistor T3 is electrically connected to the second terminal of the first switching unit 21 and the first terminal of the energy storage unit 23, respectively. In the first sub-stage of the holding phase, the third transistor T3 is turned on under the control of the second control signal SW2. Optionally, in the second sub-stage of the holding phase, the third transistor T3 is turned off under the control of the second control signal SW2. Based on this, the path for transmitting the first power signal VGL to the first terminal of the energy storage unit 23 is turned on through the third transistor T3, and the first switching unit 21 is in the off state. In this case, the potential of the first terminal of the energy storage unit 23 is not affected by the input module 10, so that the potential of the first terminal and the third terminal of the energy storage unit 23 are kept consistent, thereby controlling the energy storage unit 23 not to charge or discharge in the first sub-stage and reducing power consumption.

[0063] Please continue reading. Figures 2 to 7 The third transistor T3 is either a P-type transistor or an N-type transistor. For example, the third transistor T3 can be a PMOS, PFET, NMOS, or NFET. Figure 4 and Figure 7Taking the third transistor T3 as a P-type transistor as an example, when the second control signal SW2 is low, the third transistor T3 is in the on state; when the second control signal SW2 is high, the third transistor T3 is in the off state. (See [link to relevant documentation]). Figure 2 and Figure 3 The timing sequence is shown. Figure 5 Taking the third transistor T3 as an N-type transistor as an example, in Figure 5 In the diagram, when the second control signal SW2 is high, the third transistor T3 is off; when the second control signal SW2 is low, the third transistor T3 is on. (See also...) Figure 6 The timing sequence is shown.

[0064] Please continue reading. Figure 4 , Figure 5 and Figure 7 The energy storage unit 23 includes a first capacitor C1, a fourth transistor T4, and a fifth transistor T5. The first terminal of the first capacitor C1 is electrically connected to the second terminal of the first switching unit 21, the second terminal of the second switching unit 22, and the control terminal of the fourth transistor T4. The second terminal of the first capacitor C1 is electrically connected to the first terminal of the fourth transistor T4 and the first terminal of the fifth transistor T5. The second terminal of the fourth transistor T4 is connected to the control terminal of the fifth transistor T5, which receives the second clock signal XCK. The second terminal of the fifth transistor T5 is also electrically connected to the control terminal of the output module 30. Optionally, the fourth transistor T4 and the fifth transistor T5 can be P-type transistors, such as... Figure 4 and Figure 7 As shown, the fourth transistor T4 and the fifth transistor T5 can also be N-type transistors, such as... Figure 5 As shown.

[0065] Figure 8 This is a schematic diagram of a shift register provided in an embodiment of this application. Figure 8As shown, the output module 30 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2. The control terminal of the sixth transistor T6 is electrically connected to the second output terminal of the input module 10 and the first terminal of the seventh transistor T7. The first terminal of the sixth transistor T6 is electrically connected to the first terminal of the eighth transistor T8 and the first terminal of the second capacitor C2. The first terminal of the sixth transistor T6 is used to receive the second power signal VGH. The second terminal of the sixth transistor T6 is electrically connected to the control terminal of the eighth transistor T8, the second terminal of the second capacitor C2, the third terminal of the energy storage unit 23, and the first node N1. The control terminal of the seventh transistor T7 is used to receive the first power signal VGL. The second terminal of the seventh transistor T7 is electrically connected to the control terminal of the ninth transistor T9 and the second node N2. The first terminal of the eighth transistor T8 is used to receive the second power signal VGH. The second terminal of the eighth transistor T8 is electrically connected to the first terminal of the ninth transistor T9. The first terminal of the ninth transistor T9 serves as the output terminal of the output module 30 for outputting the scan signal OUT, and the second terminal of the ninth transistor T9 is used to receive the second power signal VGH.

[0066] Please continue reading. Figure 8 The output module 30 may further include a tenth transistor T10, an eleventh transistor T11, and a third capacitor C3. The control terminal of the tenth transistor T10 is electrically connected to the second output terminal of the input module 10. The first terminal of the tenth transistor T10 is used to receive the second power supply signal VGH. The second terminal of the tenth transistor T10 is electrically connected to the first terminal of the eleventh transistor T11 and the second terminal of the third capacitor C3. The control terminal of the eleventh transistor T11 is electrically connected to the second terminal of the seventh transistor T7 and the first terminal of the third capacitor C3. The second terminal of the eleventh transistor T11 is used to receive the second clock signal XCK.

[0067] Figure 9 This is a schematic diagram of a shift register provided in an embodiment of this application. Figure 9 As shown, the output module 30 may include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a second capacitor C2, and a fourth capacitor C4. The first terminal of the fourth capacitor C4 is electrically connected to the control terminal of the ninth transistor T9, and the second terminal of the fourth capacitor C4 is electrically connected to the first terminal of the ninth transistor T9. The fourth capacitor C4 can stabilize the potential of the first node N1, thereby improving the stability of the scan signal OUT and enhancing the display performance of the display panel.

[0068] Please continue reading. Figure 9The output module 30 may further include a fifteenth transistor T15, a sixteenth transistor T16, and a fifth capacitor C5. The control terminal of the fifteenth transistor T15 is electrically connected to the second output terminal of the input module 10. The first terminal of the fifteenth transistor T15 is used to receive the second power supply signal VGH. The second terminal of the fifteenth transistor T15 is electrically connected to the second terminal of the sixteenth transistor T16 and the first terminal of the fifth capacitor C5. The control terminal of the sixteenth transistor T16 is electrically connected to the second terminal of the thirteenth transistor T13 and the second terminal of the fifth capacitor C5. The first terminal of the sixteenth transistor T16 is used to receive the second clock signal XCK.

[0069] Please continue reading. Figure 9 The shift register may also include an adjustment module 40. Multiple control terminals of the adjustment module 40 are used to receive a first clock signal CK and a first power supply signal VGL, respectively. The first terminal of the adjustment module 40 is used to receive an input signal IN. The second terminal of the adjustment module 40 is electrically connected to the control terminal of the ninth transistor T9. The adjustment module 40 is used to adjust the output of the output module 30 to output a scan signal OUT during the data writing phase. Since the potential of the scan signal OUT does not change instantaneously... Figure 2 , Figure 3 and Figure 6 The scan signal OUT in the timing diagram represents the ideal situation. In actual output, there will be a certain delay. To address this, this embodiment uses the adjustment module 40 to control the on / off state of the ninth transistor T9, enabling the ninth transistor T9 to respond quickly when the scan signal OUT is output, thereby improving the signal delay output problem and enhancing display performance.

[0070] Please continue reading. Figure 9 The adjustment module 40 may include a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. The control terminal of the twelfth transistor T12 receives a first clock signal CK. The first terminal of the twelfth transistor T12 is electrically connected to the first terminal of the thirteenth transistor T13. The second terminal of the twelfth transistor T12 receives an input signal IN. The control terminal of the thirteenth transistor T13 receives a first power supply signal VGL. The second terminal of the thirteenth transistor T13 is electrically connected to both the control terminal and the first terminal of the fourteenth transistor T14. The second terminal of the fourteenth transistor T14 is electrically connected to the control terminal of the ninth transistor T9. The twelfth transistor T12, thirteenth transistor T13, and fourteenth transistor T14 can be P-type transistors or N-type transistors. The transistor types in the adjustment module 40 are the same as those in the output module 30. Figure 9 This is merely an illustrative example and is not intended to be limiting.

[0071] Please continue reading. Figure 9The shift register also includes a seventeenth transistor T17. The control terminal of the seventeenth transistor T17 receives the initial signal, its first terminal receives the second power supply signal VGH, and its second terminal is electrically connected to the second output terminal of the input module 10. The initial signal is active at the beginning of the shift register's operation, and the seventeenth transistor T7 initializes the shift register under the control of the initial signal. The initial signal is inactive during the data write and hold phases of the shift register, and does not affect its normal operation.

[0072] Figure 10 This is a schematic diagram of the shift register provided in an embodiment of this application. Figure 10 As shown, the input module 10 may include an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20. The control terminal of the eighteenth transistor T18 is electrically connected to the control terminal of the nineteenth transistor T19 and the second terminal of the twentieth transistor T20. The control terminal of the eighteenth transistor T18 is used to receive a first clock signal CK. The first terminal of the eighteenth transistor T18 is used to receive an input signal IN. The second terminal of the eighteenth transistor T18 is electrically connected to the control terminal of the twentieth transistor T20 and one control terminal of the output module 30. The first terminal of the nineteenth transistor T19 is electrically connected to the first terminal of the twentieth transistor T20, the first terminal of the first switching unit 21, and another control terminal of the output module 30. The second terminal of the nineteenth transistor T19 is used to receive a first power supply signal VGL. Optionally, the twentieth transistor T20 may be a dual-gate transistor.

[0073] Figures 11 to 16 The diagram illustrates the structures of several different shift registers provided in embodiments of this application. Figures 11 to 16 As shown, each shift register includes an input module 10, a control module 20, and an output module 30. The input module 10 includes an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20. The control module 20 includes a first switching unit 21, a second switching unit 22, and an energy storage unit 23.

[0074] exist Figure 11 In the middle, the input module 10 adopts Figure 10 The structure shown, and the control module 20 adopt Figure 4 The output module 30 adopts the structure shown in Figure 8. Figure 12 Compared to Figure 11 The structure shown. Figure 12 The twentieth transistor T20 is a dual-gate transistor, and the first switching unit 21 also includes a second transistor T2. Figure 13 Compared to Figure 12 The structure shown includes a shift register that also includes... Figure 9The adjustment module 40 shown has a first switching unit 21 that includes only the first transistor T1, and the output module 30 adopts... Figure 9 The structure shown. Figure 14 Compared to Figure 13 The structure shown includes a shift register that also includes... Figure 9 The seventeenth transistor T17 shown is... Figure 14 The output module 30 does not include the fourth capacitor C4.

[0075] Figure 15 Compared to Figure 12 The structure shown. Figure 15 The twentieth transistor, T20, is a dual-gate transistor. Figure 15 The output module 30 includes transistors T31~T34, capacitor C6, and capacitor C7. Figure 15 The shift register also includes transistors T35 and T36. The control terminal of transistor T31 is electrically connected to the second terminal of the eighteenth transistor T18, the second terminal of transistor T34, and the second terminal of capacitor C7. The first terminal of transistor T31 is electrically connected to the first terminal of capacitor C6, the first terminal of the third transistor T3, the first terminal of transistor T32, and the second terminal of transistor T36. The first terminal of transistor T31 is used to receive the second power supply signal VGH. The second terminal of transistor T31 is electrically connected to the second terminal of the fifth transistor T5, the control terminal of transistor T32, and the second terminal of capacitor C6. The second terminal of transistor T32 is electrically connected to the first terminal of transistor T33. The second terminal of transistor T32 is used to output the scan signal OUT. The control terminal of transistor T33 is electrically connected to the first terminal of transistor T34 and the first terminal of capacitor C7, respectively. The second terminal of transistor T33 is used to receive the first power supply signal VGL. The control terminal of transistor T34 is used to receive the first power supply signal VGL. The control terminal of transistor T35 is used to receive the second clock signal XCK. The first terminal of transistor T35 is electrically connected to the first terminal of transistor T36. The second terminal of transistor T35 is electrically connected to the second terminal of the eighteenth transistor T18 and the gate of the twentieth transistor T20, respectively. The control terminal of transistor T36 is electrically connected to the first terminal of the twentieth transistor T20, the first terminal of the nineteenth transistor T19, and the first terminal of the first transistor T1, respectively.

[0076] Figure 16 Compared to Figure 15 The structure shown. Figure 16 The output module 30 includes transistors T41~T43, capacitor C8, and capacitor C9. Figure 16The shift register also includes transistor T44 and capacitor C10. The control terminal of transistor T41 is electrically connected to the control terminal of transistor T43, the first terminal of transistor T44, and the second terminal of transistor T35. The first terminal of transistor T41 is electrically connected to the second terminal of the fifth transistor T5, the control terminal of transistor T42, and the second terminal of capacitor C8. The second terminal of transistor T41 is electrically connected to the second terminal of transistor T36, the first terminal of capacitor C10, the first terminal of the third transistor T3, the first terminal of capacitor C8, and the first terminal of transistor T42. The second terminal of transistor T41 is used to receive the second power supply signal VGH. The second terminal of transistor T42 is electrically connected to the first terminal of transistor T43. The second terminal of transistor T42 is used to output the scan signal OUT. The second terminal of transistor T43 is used to receive the first power supply signal VGL. The second terminal of capacitor C9 is electrically connected to the second terminal of the fourth transistor T4 and the control terminal of the fifth transistor T5, respectively. The second terminal of capacitor C10 is electrically connected to the control terminal of the twentieth transistor T20 and the second terminal of the eighteenth transistor T18, respectively. The control terminal of transistor T44 is electrically connected to the second terminal of the twentieth transistor T20, respectively. The control terminal of transistor T44 is used to receive the first clock signal CK. The second terminal of transistor T44 is used to receive the input signal IN. The control terminal of transistor T35 is used to receive the second clock signal XCK.

[0077] The above Figures 11 to 17 The shift register shown is illustrated using P-type transistors. For details on each module and unit, please refer to the relevant descriptions in the aforementioned embodiments; they will not be repeated here. It is understood that for... Figures 11 to 17 In the shift register shown, during the hold phase, the first node N1 needs to be maintained at a low level to ensure a stable output of the scan signal OUT. Therefore, the first clock signal CK and the second clock signal XCK need to continuously switch between high and low levels. In the absence of the first switching unit 21 and the second switching unit 22 in the shift register, the potential of the first terminal of the first capacitor C1 changes with the change of the first clock signal CK. That is, when the first clock signal CK is low, the potential of the first terminal of the first capacitor C1 also becomes low; when the first clock signal CK is high, the potential of the first terminal of the first capacitor C1 becomes high. Therefore, the first capacitor C1 continuously charges and discharges during the hold phase. To address this, this application adds a first switching unit 21 (first transistor T1, second transistor T2) and a second switching unit 22 (third transistor T3), and controls the on / off state of the first switching unit 21 through a first control signal SW1 and the on / off state of the second switching unit 22 through a second control signal SW2. This allows the first capacitor C1 to reduce the charging and discharging frequency during the hold phase, thereby reducing power consumption. Specifically, in conjunction with… Figure 2In terms of the timing shown, during the data writing phase, the first control signal SW1 remains low, the first transistor T1 is turned on under the action of the first control signal SW1, the second control signal SW2 remains high, and the third transistor T3 is turned off under the action of the second control signal SW2. The shift register outputs the scan signal OUT. During the holding phase, the first control signal SW1 remains high, the first transistor T1 is turned off under the action of the first control signal SW1, the second control signal SW2 remains low, and the third transistor T3 is turned on under the action of the second control signal SW2. The potential across the first capacitor C1 remains high. Therefore, the first capacitor C1 will not charge or discharge during the holding phase, thereby reducing the power consumption caused by the charging and discharging of the first capacitor C1.

[0078] Taking a round watch with a resolution of 390*450 as an example, the shift register provided in this application and the shift register of related technologies (excluding the first switching unit 21 and the second switching unit 22 of this application) are simulated. The power consumption comparison data of the two are shown in Table 1 below. VGH=6V and VGL=-6V are set. According to the simulation results, in the 5Hz black screen display mode, the power consumption of this application can be reduced by 8% compared with the related technologies. In the 5Hz 10% Pixel On 50nits screen display mode, the power consumption of the Driver IC can be reduced by 7%.

[0079] Table 1. Power Consumption Test Comparison Data

[0080]

[0081] Figure 17 This is a schematic diagram of a gate driving circuit provided in an embodiment of this application. Figure 17 As shown, the gate drive circuit includes a first clock signal line CK, a first clock signal line XCK, a first control signal line SW1, a second control signal line SW2, and multiple cascaded shift registers as provided in the above embodiments. Figure 17 The diagram shows four cascaded shift registers: 901, 902, 903, and 904.

[0082] The input terminal (IN terminal) of the input module 10 in the first-stage shift register is used to receive the start signal STV. The control terminal (SW1 terminal) of the first switch unit 21 in each shift register is electrically connected to the first control signal line SW1 to receive the first control signal SW1. The control terminal (SW2 terminal) of the second switch unit 22 in each shift register is electrically connected to the second control signal line SW2 to receive the second control signal SW2.

[0083] The i-th level shift register (e.g.) Figure 17In the shift registers 901 and 903 shown, the control terminal and the first input terminal of the input module 10 are electrically connected to the first clock signal line CK to receive the first clock signal CK; the second terminal of the energy storage unit 23 and the first input terminal of the output module 30 in the i-th stage shift register are electrically connected to the first clock signal line XCK to receive the second clock signal XCK. Here, i is a positive integer greater than 1.

[0084] The (i+1)th level shift register (e.g.) Figure 17 In the shift registers 902 and 904 shown, the control terminal and the first input terminal of the input module 10 are electrically connected to the first clock signal line XCK to receive the second clock signal XCK; the second terminal of the energy storage unit 23 and the first input terminal of the output module 30 in the i-th stage shift register are electrically connected to the first clock signal line CK to receive the first clock signal CK; the input terminal of the input module 10 in the (i+1)-th stage shift register is electrically connected to the output terminal of the output module 30 in the i-th stage shift register.

[0085] Each shift register in the aforementioned gate driving circuit can be connected to a corresponding pixel circuit, providing a scan signal OUT to the pixel circuit to drive the light-emitting element to emit light and realize the display function. Based on the gate driving circuit provided in this application, during the holding phase, the energy storage unit in each shift register can be controlled to prevent charging and discharging, thereby reducing power consumption.

[0086] In one embodiment, a driving method for a gate driving circuit is improved. This driving method can be applied to the gate driving circuit provided in the foregoing embodiments. The driving method includes a data writing stage and a holding stage. In the first sub-stage of the holding stage, the first switching unit 21 of the gate driving circuit is turned off, and the second switching unit 22 of the gate driving circuit is turned on, so that the voltage levels of the first terminal and the third terminal of the energy storage unit 23 are kept consistent. Based on this, by controlling the first switching unit 21 to turn off and the second switching unit 22 to turn on in the first sub-stage, the potentials of the first and third terminals of the energy storage unit 23 are kept consistent. Therefore, the energy storage unit 23 does not charge or discharge, avoiding power consumption caused by charging and discharging.

[0087] Optionally, in the second sub-stage of the data writing and holding stages, the first switching unit 21 is turned on and the second switching unit 22 is turned off, so that the energy storage unit 23 is charged and discharged according to the control signal output from the first output terminal of the input module 10 and the second power supply signal VGH under the control of the second clock signal XCK. Based on this, in the second sub-stage, by controlling the first switching unit 21 to turn on and the second switching unit 22 to turn off, the shift registers at each stage in the gate drive circuit can be restored to the state at the time of the data writing stage, so as to prepare for the next drive and ensure display performance.

[0088] In one embodiment, a display panel is provided, which includes the gate driving circuit provided in the above embodiment. The display panel provided in this application embodiment is applicable to display devices with display functions such as mobile phones, tablets, and wearable devices such as smartwatches. Taking a smartwatch as an example, smartwatches have a low refresh rate and a long hold phase. Based on the shift register provided in this application embodiment, its energy storage unit 23 will not charge or discharge during the hold phase, avoiding power consumption caused by charging and discharging, thereby reducing the power consumption of the display panel. It should be noted that the display panel provided in this application embodiment is applicable to low-temperature polysilicon (LTPS) products, and also to low-temperature polysilicon oxide (LTPO) products, and is not limited thereto.

[0089] Figure 18 This is a schematic diagram of the structure of the first metal layer provided in an embodiment of this application. Figure 19 This is a schematic diagram of the structure of the second metal layer provided in an embodiment of this application. Figure 20 This is a schematic diagram of the structure of the third metal layer provided in an embodiment of this application. Figure 21 This is a schematic diagram of the contact hole structure provided in an embodiment of this application. Figure 22 This is a schematic diagram of the structure of the fourth metal layer provided in an embodiment of this application. Figure 23 for Figures 20 to 22 A schematic diagram of the structure formed by stacking elements from bottom to top. Figure 24 This is a schematic diagram of the planar layout structure of the display panel provided in the embodiments of this application, and also... Figures 18 to 22 A schematic diagram of the structure formed by stacking elements from bottom to top. (Example) Figures 18 to 24As shown, the display panel includes a substrate and a first metal layer, a second metal layer (M1), a third metal layer (MC), and a fourth metal layer, sequentially located away from the substrate. In the shift register of the gate drive circuit, the first transistor T1 in the first switching unit 21 includes a first oxide active layer and a first gate, and the third transistor T3 in the second switching unit 22 includes a second oxide active layer and a second gate. The first oxide active layer includes a first terminal and a second terminal of the first transistor T1, and the second oxide active layer includes a first terminal and a second terminal of the second transistor T2. The first and second oxide active layers are located on the first metal layer, and the first and second gates are located on the second metal layer. The first plate of the first capacitor C1 in the energy storage unit 23 is located on the second metal layer, and the second plate of the first capacitor C1 in the energy storage unit 23 is located on the third metal layer. The first clock signal line CK, the first clock signal line XCK, the first control signal line SW1, and the second control signal line SW2 are located on the fourth metal layer. The contact holes are used to realize the electrical connection between the various structures. For example, the first gate of the first transistor T1 is electrically connected to the first control signal line SW1 through the contact hole, and the first gate of the second transistor T2 is electrically connected to the second control signal line SW2 through the contact hole. For other electrical connection structures, please refer to the relevant description of the shift register mentioned above.

[0090] The aforementioned shift register reuses the existing first, second, third, and fourth metal layers without requiring additional film layers, reducing the need for film layer design. This allows the potential across the first capacitor C1 of the energy storage unit 23 in the shift register to remain constant during the first sub-stage of the holding phase, thereby reducing the power consumption of the display panel. For example, when the base frame of the display panel is 60Hz, there is no charging or discharging within 59Hz when the display frequency is 1Hz, thus saving power consumption of the display panel and achieving a narrow bezel.

[0091] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A shift register, characterized in that, include: An input module, wherein the control terminal of the input module is used to receive a first clock signal, and the multiple input terminals of the input module are respectively used to receive an input signal, the first clock signal and a first power signal; The control module includes a first switching unit, a second switching unit, and an energy storage unit. The control terminal of the first switching unit is used to receive a first control signal. The first terminal of the first switching unit is electrically connected to the first output terminal of the input module. The second terminal of the first switching unit is electrically connected to the first terminal of the energy storage unit and the second terminal of the second switching unit. The control terminal of the second switching unit is used to receive a second control signal. The first terminal of the second switching unit is used to receive a second power signal. The second terminal of the energy storage unit is used to receive a second clock signal. An output module, wherein multiple control terminals of the output module are electrically connected to the first power signal, the first output terminal of the input module, the second output terminal of the input module, and the third terminal of the energy storage unit, respectively; multiple input terminals of the output module are respectively used to receive the second clock signal, the first power signal, and the second power signal; and the output terminal of the output module is used to output a scan signal; wherein, In the first sub-stage of the holding phase, the first switching unit is used to disconnect under the control of the first control signal, and the second switching unit is used to turn on under the control of the second control signal, so that the level states of the first terminal of the energy storage unit and the third terminal of the energy storage unit are consistent.

2. The shift register according to claim 1, characterized in that, In the second sub-stage of the holding phase, the first switching unit is turned on under the control of the first control signal, and the second switching unit is turned off under the control of the second control signal, so that the energy storage unit is charged and discharged according to the control signal output from the first output terminal of the input module and the second power signal under the control of the second clock signal.

3. The shift register according to claim 2, characterized in that, The duration of the second sub-phase is greater than or equal to the period during which the first clock signal has an effective level.

4. The shift register according to claim 2, characterized in that, The first sub-stage precedes the second sub-stage.

5. The shift register according to claim 1, characterized in that, During the data writing phase, the first switching unit is turned on under the control of the first control signal, and the second switching unit is turned off under the control of the second control signal, so that the energy storage unit is charged and discharged according to the control signal output from the first output terminal of the input module and the second power signal under the control of the second clock signal.

6. The shift register according to claim 1, characterized in that, The first switching unit includes a first transistor, the control terminal of the first transistor is used to receive the first control signal, the first terminal of the first transistor is connected to the first output terminal of the input module, and the second terminal of the first transistor is electrically connected to the first terminal of the energy storage unit and the second terminal of the second switching unit, respectively. In the first sub-stage of the holding phase, the first transistor is used to disconnect under the control of the first control signal.

7. The shift register according to claim 6, characterized in that, The first transistor is a P-type transistor or an N-type transistor.

8. The shift register according to claim 6, characterized in that, The first switching unit further includes a second transistor, the control terminal of the second transistor is used to receive the first power signal, the first terminal of the second transistor is electrically connected to the second terminal of the second switching unit and the second terminal of the first transistor, and the second terminal of the second transistor is electrically connected to the first terminal of the energy storage unit.

9. The shift register according to claim 1, characterized in that, The second switching unit includes a third transistor, the control terminal of which is used to receive the second control signal, the first terminal of which is used to receive the second clock signal, and the second terminal of which is electrically connected to the second terminal of the first switching unit and the first terminal of the energy storage unit, respectively. In the first sub-stage of the holding phase, the third transistor is turned on under the control of the second control signal.

10. The shift register according to claim 9, characterized in that, The third transistor is either a P-type transistor or an N-type transistor.

11. The shift register according to claim 1, characterized in that, The energy storage unit includes a first capacitor, a fourth transistor, and a fifth transistor. The first terminal of the first capacitor is electrically connected to the second terminal of the first switching unit, the second terminal of the second switching unit, and the control terminal of the fourth transistor. The second terminal of the first capacitor is electrically connected to the first terminal of the fourth transistor and the first terminal of the fifth transistor. The second terminal of the fourth transistor is connected to the control terminal of the fifth transistor. The control terminal of the fifth transistor is used to receive the second clock signal. The second terminal of the fifth transistor is electrically connected to the control terminal of the output module.

12. The shift register according to claim 1, characterized in that, The output module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a second capacitor; wherein, The control terminal of the sixth transistor is electrically connected to the second output terminal of the input module and the first terminal of the seventh transistor. The first terminal of the sixth transistor is electrically connected to the first terminal of the eighth transistor and the first terminal of the second capacitor. The first terminal of the sixth transistor is used to receive the second power signal. The second terminal of the sixth transistor is electrically connected to the control terminal of the eighth transistor, the second terminal of the second capacitor, and the third terminal of the energy storage unit. The control terminal of the seventh transistor is used to receive the first power signal. The second terminal of the seventh transistor is electrically connected to the control terminal of the ninth transistor. The first terminal of the eighth transistor is used to receive the second power signal. The second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor. The first terminal of the ninth transistor is used to output the scan signal. The second terminal of the ninth transistor is used to receive the second power signal.

13. The shift register according to claim 12, characterized in that, The output module further includes a tenth transistor, an eleventh transistor, and a third capacitor; wherein, the control terminal of the tenth transistor is electrically connected to the second output terminal of the input module, the first terminal of the tenth transistor is used to receive the second power signal, the second terminal of the tenth transistor is electrically connected to the first terminal of the eleventh transistor and the second terminal of the third capacitor, the control terminal of the eleventh transistor is electrically connected to the second terminal of the seventh transistor and the first terminal of the third capacitor, and the second terminal of the eleventh transistor is used to receive the second clock signal.

14. The shift register according to claim 12, characterized in that, The output module further includes a fourth capacitor, the first end of which is electrically connected to the control terminal of the ninth transistor, and the second end of which is electrically connected to the first end of the ninth transistor.

15. The shift register according to claim 12, characterized in that, The shift register also includes: The adjustment module has multiple control terminals for receiving the first clock signal and the first power signal, respectively. The first terminal of the adjustment module is used to receive the input signal, and the second terminal of the adjustment module is electrically connected to the control terminal of the ninth transistor. The adjustment module is used to adjust the output of the scan signal by the output module during the data writing stage.

16. The shift register according to claim 15, characterized in that, The adjustment module includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. The control terminal of the twelfth transistor is used to receive the first clock signal. The first terminal of the twelfth transistor is electrically connected to the first terminal of the thirteenth transistor. The second terminal of the twelfth transistor is used to receive the input signal. The control terminal of the thirteenth transistor is used to receive the first power signal. The second terminal of the thirteenth transistor is electrically connected to both the control terminal and the first terminal of the fourteenth transistor. The second terminal of the fourteenth transistor is electrically connected to the control terminal of the ninth transistor.

17. The shift register according to claim 16, characterized in that, The output module further includes a fifteenth transistor, a sixteenth transistor, and a fifth capacitor; wherein, the control terminal of the fifteenth transistor is electrically connected to the second output terminal of the input module, the first terminal of the fifteenth transistor is used to receive the second power signal, the second terminal of the fifteenth transistor is electrically connected to the second terminal of the sixteenth transistor and the first terminal of the fifth capacitor, the control terminal of the sixteenth transistor is electrically connected to the second terminal of the thirteenth transistor and the second terminal of the fifth capacitor, and the first terminal of the sixteenth transistor is used to receive the second clock signal.

18. The shift register according to claim 1, characterized in that, The shift register also includes a seventeenth transistor, the control terminal of which is used to receive an initial signal, the first terminal of which is used to receive a second power supply signal, and the second terminal of which is electrically connected to the second output terminal of the input module.

19. A gate driving circuit, characterized in that, It includes a first clock signal line, a second clock signal line, a first control signal line, a second control signal line, and multiple cascaded shift registers as described in any one of claims 1-18; wherein, The input terminal of the input module in the first-level shift register is used to receive a start signal. The control terminal of the first switch unit in each shift register is electrically connected to the first control signal line to receive the first control signal. The control terminal of the second switch unit in each shift register is electrically connected to the second control signal line to receive the second control signal. The control terminal and the first input terminal of the input module in the i-th stage shift register are electrically connected to the first clock signal line to receive the first clock signal; the second terminal of the energy storage unit and the first input terminal of the output module in the i-th stage shift register are electrically connected to the second clock signal line to receive the second clock signal; where i is a positive integer greater than 1; The control terminal and the first input terminal of the input module in the (i+1)th stage shift register are electrically connected to the second clock signal line to receive the second clock signal; the second terminal of the energy storage unit and the first input terminal of the output module in the i-th stage shift register are electrically connected to the first clock signal line to receive the first clock signal; the input terminal of the input module in the (i+1)th stage shift register is electrically connected to the output terminal of the output module in the i-th stage shift register.

20. A driving method for a gate driving circuit, characterized in that, Applied to the gate driving circuit as described in claim 19, the driving method of the gate driving circuit includes a data writing stage and a holding stage; wherein, in the first sub-stage of the holding stage, the first switching unit of the gate driving circuit is controlled to be turned off, and the second switching unit of the gate driving circuit is controlled to be turned on, so that the level states of the first terminal of the energy storage unit and the third terminal of the energy storage unit are consistent.

21. The method according to claim 20, characterized in that, In the second sub-stage of the data writing stage and the holding stage, the first switching unit is controlled to be turned on and the second switching unit is controlled to be turned off, so that the energy storage unit is charged and discharged according to the control signal output from the first output terminal of the input module and the second power signal under the control of the second clock signal.

22. A display panel, characterized in that, Includes the gate drive circuit as described in claim 19.

23. The display panel according to claim 22, characterized in that, The display panel includes a substrate and a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer sequentially disposed away from the substrate; wherein... In the shift register of the gate driving circuit, the first transistor in the first switching unit includes a first oxide active layer and a first gate, and the third transistor in the second switching unit includes a second oxide active layer and a second gate; wherein the first oxide active layer and the second oxide active layer are respectively located in the first metal layer, the first gate and the second gate are respectively located in the second metal layer, the first plate of the first capacitor in the energy storage unit is located in the second metal layer, and the second plate of the first capacitor in the energy storage unit is located in the third metal layer; The first clock signal line, the second clock signal line, the first control signal line, and the second control signal line are respectively located in the fourth metal layer.

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