A low-power long-distance downlink receiver circuit

Abstract

This invention relates to a low-power, long-distance downlink receiver circuit, comprising: a chirp despreading circuit for generating a despread difference frequency signal; an energy accumulation amplification circuit for accumulating signal energy to amplify the signal and generating the blank interval required to separate two adjacent signal segments; a normalization circuit that normalizes the amplified signal through a voltage comparator; a low-power decoding circuit that integrates the entire signal through an energy integrator to decode the signal; and a threshold detector that detects the signal level and sends it to a processor. This invention utilizes a chirp signal demodulation and despreading mechanism to suppress interference caused by environmental signals during long-distance transmission. Secondly, it accumulates the energy of the received signal using a resonator without consuming external energy, thereby achieving zero-power signal amplification. Finally, it implements the decoding function using energy integration.

Description

Technical Field

[0001] This invention relates to the field of Internet of Things (IoT) technology, and in particular to a low-power, long-distance downlink receiver circuit. Background Technology

[0002] When deploying Internet of Things (IoT) systems, communication connections need to be established between gateways and a large number of terminals. For weak terminals that require low power consumption and wide coverage, achieving a low-power, long-range, and reliable downlink is crucial. Traditional downlinks use high-performance superheterodyne receivers, which can achieve long-range reception. However, deploying such receivers on weak terminals significantly increases the overall power consumption of the terminal. For example, a typical superheterodyne receiver includes three energy-intensive signal processing stages: amplifying the received signal using a low-noise amplifier (LNA), generating a high-frequency carrier using a frequency synthesizer for signal demodulation, and decoding using high-speed sampling based on an ADC. These steps result in power consumption of tens of milliwatts (mW), which is tens of times the power consumption of other devices such as processors and sensors on weak terminals.

[0003] To achieve low-power and long-distance communication, many weak terminals have introduced Chirp Spread Spectrum (CSS) mechanisms in their uplink backscatter links in recent years, achieving uplink backscatter communication over distances of hundreds or even thousands of meters with microwatt-level power consumption. However, in downlink reception, these weak terminals use microwatt-level envelope detection circuits, resulting in very limited signal reception distance. These circuits do not use high-energy-consuming frequency synthesizers to generate carrier waves; instead, they use passive devices such as diodes to extract the signal envelope, thus enabling demodulation of amplitude shift keying (ASK) signals with microwatt-level power consumption. However, receivers based on envelope detection circuits have two limitations. First, envelope detection circuits themselves have low sensitivity, making it difficult to detect low-intensity signals. Furthermore, to reduce power consumption, receivers cannot use low-noise amplifiers with power consumption of tens of milliwatts to improve reception sensitivity. Second, envelope detection circuits cannot identify and eliminate the envelope of interfering signals, so they can only operate when the signal strength is much greater than the interference strength, such as when the SINR is higher than 10 dB. These limitations significantly reduce the receiving distance and reliability of envelope detector receivers. For example, conventional envelope detector circuits typically have a signal receiving distance of only 20-30 meters. Therefore, neither traditional superheterodyne receivers nor envelope detector receivers can simultaneously achieve long-distance, low-power, and interference-resistant signal reception.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-power long-distance downlink receiver circuit, which solves the contradiction that existing receivers cannot simultaneously achieve long-distance and low-power reception.

[0006] The objective of this invention is achieved through the following technical solution: a low-power long-distance downlink receiver circuit, comprising a receiving antenna, a Chirp despreading circuit, an energy accumulation amplifier circuit, a normalization circuit, a zero-power synchronization and low-power decoding circuit, a threshold detector, and a processor;

[0007] The Chirp despreading circuit is connected to the receiving antenna and is used to mix the two wideband Chirp signals simultaneously transmitted from the transmitter by the receiving antenna to achieve demodulation and despreading of the Chirp signals, generating a despread difference frequency signal.

[0008] The energy accumulation amplification circuit is connected to the Chirp despreading circuit to accumulate the energy of the signal to amplify the signal and generate the blank interval required to separate two adjacent signal segments.

[0009] The normalization circuit is connected to the energy accumulation amplifier circuit, and a voltage comparator is used to normalize the amplified signal, thereby converting the high level of the signal into a preset voltage value.

[0010] The low-power decoding circuit is connected to the normalization circuit and integrates the entire signal through an energy integrator, thereby achieving signal decoding.

[0011] The threshold detector detects the signal level and sends it to the processor;

[0012] The processor detects the first rising edge of the output signal of the normalization circuit to correct clock drift, calibrates its own synchronization clock, and controls the switching between synchronization and decoding functions in the zero-power synchronization and low-power decoding circuits.

[0013] The Chirp despreading circuit includes a mixer composed of two parallel RF diodes. The anode of one RF diode is connected to the receiver, and the anode of the other RF diode is grounded. This mixer is based on the nonlinear mixing principle of nonlinear devices such as diodes. For example, it can be implemented by connecting the anode of one RF diode to the receiver antenna and the anode of the other RF diode to ground. Alternatively, other circuit topologies that utilize the nonlinear mixing characteristics of diodes can be used. The mixer mixes the two Chirp signals to generate a difference frequency signal S. beat By measuring S beatThe duration of the signal determines the length of time the transmitter sends the two Chirp signals. By changing the duration of the transmitter sending the two Chirp signals, they are encoded into different binary symbols.

[0014] The energy accumulation amplification circuit includes an LC resonant circuit consisting of an inductor connected in series with the mixer and a grounded first capacitor. The energy in the circuit alternates between magnetic potential energy and electric potential energy under the influence of the first capacitor and the inductor, accumulating the signal energy to amplify the signal and obtain the amplified S. beat The signal is the resonant signal.

[0015] The encoding is represented by different binary symbols, including: the amplified S beat Long-duration signals are represented by the binary symbol 1. The amplified S... beat Signals with short durations are represented by the binary symbol 0;

[0016] Before the energy of the next symbol begins to accumulate in the LC resonant circuit, the energy of the previous symbol is released from the LC resonant circuit in advance, thus forming a period of time when the resonance stops before the arrival of the next symbol, namely the blank time interval, which is used to separate the two symbols.

[0017] The low-power decoding circuit includes a low-power energy integrator consisting of a resistor R connected in series with the normalization circuit and a second capacitor grounded. The energy integrator integrates the entire symbol to achieve symbol decoding.

[0018] An NMOS switch SW is connected in parallel with the second capacitor. After the previous symbol is fully charged, the processor controls the switch SW to close, which rapidly discharges the second capacitor, initializes it, and prevents residual energy from affecting the charging result of the next symbol.

[0019] A resistor R2 and an NMOS switch SW2 are connected in parallel across the two ends of the resistor R. A resistor R2 and an NMOS switch SW3 are connected in parallel at the connection point between the resistor R and the second capacitor. The other end of the switch SW3 is grounded.

[0020] When receiving a synchronization symbol, switches SW2 and SW3 are closed under the control of the processor, connecting resistors R2 and R3 into the circuit. This reduces the overall resistance of the RC circuit, thereby accelerating the charging speed of the RC circuit. Before the next symbol arrives, the energy in the second capacitor will be quickly released below the detection threshold, triggering a high-to-low transition in the threshold detector's output signal. After detecting the transition, the processor will control switch SW to close completely to release the energy in the second capacitor. During symbol synchronization, multiple consecutive symbols are used as synchronization symbols. When the processor detects the corresponding number of high levels in sequence, symbol synchronization can be achieved.

[0021] This invention offers the following advantages: First, a low-power, long-distance downlink receiver circuit, based on a passive device-based chirp signal demodulation and despreading mechanism, allows the receiver to operate at a negative SINR (signal-to-interference-plus-noise ratio), thereby suppressing interference caused by environmental signals during long-distance transmission. Second, without consuming external energy, the receiver uses a resonator to accumulate the energy of the received signal, achieving zero-power signal amplification. Finally, the receiver uses energy integration to implement the decoding function, avoiding the high power consumption caused by using high-power analog-to-digital converters (ADCs) for sampling in traditional decoding schemes. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the circuit principle of the present invention;

[0023] Figure 2 This diagram shows the downlink Chirp signal, its symbol, and the despreading circuit.

[0024] Figure 3 This is a schematic diagram of the energy accumulation amplifier circuit.

[0025] Figure 4 This is a schematic diagram of a low-power decoding circuit.

[0026] Figure 5 This is a schematic diagram of a decoding circuit with synchronization function;

[0027] Figure 6 This is a waveform diagram of a decoding circuit with synchronization function. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided below with reference to the accompanying drawings is not intended to limit the scope of protection of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The present invention will be further described below with reference to the accompanying drawings.

[0029] like Figure 1 As shown, this invention specifically relates to a receiver circuit with microwatt-level power consumption and a receiving distance of hundreds of meters. It can operate even when the interference strength is greater than the signal strength (i.e., SINR is less than 0). Based on the passive device's chirp signal demodulation and despreading mechanism, the receiver can operate at a negative SINR (signal-to-interference-plus-noise ratio), thereby suppressing interference caused by environmental signals during long-distance transmission. Secondly, without consuming external energy, the receiver uses a resonator to accumulate the energy of the received signal, thus achieving zero-power signal amplification. Finally, the receiver uses energy integration to implement the decoding function, avoiding the high power consumption caused by the use of high-power analog-to-digital converters (ADCs) for sampling in traditional decoding schemes.

[0030] Specifically, it includes a receiving antenna, a Chirp despreading circuit, an energy accumulation amplifier circuit, a normalization circuit, a zero-power synchronization and low-power decoding circuit, a threshold detector, and a processor;

[0031] The Chirp despreading circuit is connected to the receiving antenna and is used to mix the two broadband Chirp signals simultaneously transmitted from the transmitter to demodulate and despread the Chirp signals, generating a despread difference frequency signal. The energy accumulation amplifier circuit is connected to the Chirp despreading circuit and is used to accumulate the signal energy to amplify the signal and generate the blank interval required to separate the two adjacent signal segments. The normalization circuit is connected to the energy accumulation amplifier circuit and uses a voltage comparator to normalize the amplified signal, thereby converting the high level of the signal into a preset voltage value. The low-power decoding circuit is connected to the normalization circuit and integrates the entire signal through an energy integrator to achieve signal decoding. The threshold detector detects the high and low levels of the signal and sends them to the processor. The processor detects the first rising edge of the normalization circuit output signal to correct clock drift, calibrates its own synchronization clock, and controls the switching between synchronization and decoding functions in the zero-power synchronization and low-power decoding circuits.

[0032] Furthermore, such as Figure 2 As shown, this invention elevates the high-frequency carrier and down-chirp signal generation functions to the IoT gateway to reduce receiver power consumption. The gateway's transmitter simultaneously sends two wideband chirp signals. Upon receiving these two chirp signals, the receiver performs demodulation and despreading by mixing them, thereby generating a despread point-frequency signal. It can be understood that one of the two chirp signals transmitted by the gateway effectively functions as both a high-frequency carrier and a down-chirp signal, thus eliminating the need for the receiver to generate both separately.

[0033] Specifically Figure 2 The two chirp signals can be referred to as "Chirp 0" and "Chirp 1". They have the same modulation slope (i.e., frequency increase rate, measured in Hertz per second), and therefore, there is a constant frequency difference between them. Unlike narrowband signals such as amplitude shift keying (ASK) or frequency shift keying (FSK) signals, these two wideband chirp signals are not obscured by narrowband interference.

[0034] Two RF diodes are used as mixers to mix the two chirp signals. The positive and negative half-cycle RF signals received by the positive and negative terminals of the antenna, respectively, can both participate in the mixing, resulting in a high-frequency signal whose frequency is the sum of the frequencies of the two chirp signals, and a low-frequency difference signal (denoted as S). beat Using an LC resonant circuit to filter out high-frequency and harmonic signals, only the S signal is retained after filtering. beatIf the receiver detects S beat The presence of this signal allows it to infer that the gateway's transmitter is sending two Chirp signals. Furthermore, by measuring S... beat The receiver can determine the duration of the chirp signal transmitted by the transmitter by observing the signal's duration. Therefore, by varying the duration of the chirp signal, symbols representing different binary values ​​can be encoded.

[0035] Theoretically, the despreading mechanism of this invention will only be interfered with by Chirp spread spectrum signals that meet the following conditions: the Chirp signal needs to have the same frequency modulation slope as the two Chirp signals sent by the transmitter, and the frequency difference between it and the two Chirp signals needs to be 2n times f1-f0 (n=0,1,2,3...). The probability of this signal appearing in practical applications is also very small.

[0036] like Figure 3 As shown, this invention utilizes an LC resonant circuit to accumulate signal energy. The LC circuit is placed after the despreading circuit and consists of an inductor connected in series with a grounded capacitor. The energy in the circuit alternately converts between magnetic potential energy and electric potential energy under the influence of the capacitor and inductor. Specifically, the magnetic potential energy formed after energy enters the inductor can charge the capacitor, thereby creating electric potential energy between the two plates of the capacitor, and vice versa. The input signal of the LC circuit is S. beat That is, the difference frequency signal generated after the Chirp signal is despread. If S beat The frequency of the signal and the resonant frequency f of potential energy conversion res If the frequencies are equal, the energy will accumulate in the LC circuit in a resonant manner, and the resonant circuit will be the amplified signal. Therefore, the resonant circuit functions as both a filter and an amplifier, only absorbing signals with a frequency of f. res The signal is amplified.

[0037] This invention uses an enlarged S beat The duration of the signal (i.e., the resonant signal) represents a signal with a binary value of "1" or "0". Simultaneously, two adjacent S-wave intervals... beat The signals are separated by a blank interval. The S signals have different durations. beat The interval that follows is called symbol 1 or symbol 0, and S beat The duration in symbol 1 is longer than the duration in symbol 0, and symbol 1 contains more energy than symbol 0.

[0038] Furthermore, in order to generate the blank interval required to separate the symbols, in the resonant circuit, the energy of the previous symbol should be released from the LC circuit in advance before the energy of the next symbol begins to accumulate, thereby forming a period of resonant cessation before the arrival of the next symbol, i.e., the blank interval.

[0039] Higher symbol rates require shorter inter-symbol intervals, thus necessitating faster discharge speeds in LC circuits. The discharge speed of a resonant circuit depends on its quality factor Q, meaning a smaller Q value is needed to increase the discharge speed. However, a smaller Q value also implies weaker signal amplification capability in the LC circuit. Therefore, the receiver needs to strike a trade-off between amplification performance and communication rate.

[0040] The formula for defining quality factors is: Where P d揨ss E represents the average scattered power when energy is dissipated in the resistor during one resonant cycle. store Q represents the total energy stored in the LC circuit during one resonant cycle. This indicates that a higher Q value means that the LC circuit has a stronger ability to store energy, which means that it can accumulate more signal energy, but at the same time it means that it takes more time to release the energy in the circuit.

[0041] In order to select the most optimal resonant circuit, this invention uses a variety of commercially available inductors and capacitors to build multiple LC circuits suitable for different symbol rates, performs actual measurements on their discharge times, and calculates their Q values ​​using the following formula.

[0042]

[0043] Where R 揨nner It is the internal resistance of the LC resonant circuit.

[0044] Parameter table of selectable LC circuits at different symbol rates

[0045]

[0046] The table lists the circuit parameters, discharge time, and measured amplification performance of selectable LC resonant circuits at different symbol rates. In practical implementation, the appropriate circuit can be selected based on the data rate requirements. In the table, "V"... out / V in "Indicates that the resonant circuit amplifies S" beat The voltage amplification factor, T, when the signal is received. disThis is the measured discharge time. For example, for a symbol rate of 2 ksps, you can select the resonant circuit parameters in the third row of the table, whose discharge time is 100 microseconds. This means that within a total symbol length of 500 microseconds, a time interval of more than 100 microseconds is sufficient to distinguish between two consecutive symbols.

[0047] In this invention, the third resonant circuit scheme in the table is selected for prototypes with symbol rates of 1ksps and 2ksps, with a resonant frequency of 43kHz. In the 5ksps prototype, the fifth resonant circuit scheme is selected, with a resonant frequency of 32.8kHz.

[0048] In this invention, the magnified S beat The duration of a symbol is used to represent different binary information. For example, the symbol "1" has a longer duration than the symbol "0". beat The energy of a symbol "1" is higher than that of a symbol "0" because of the signal duration. If an integrator could integrate the symbol energy, symbols with different energy levels would produce different integration results, which could be used to distinguish symbols. Therefore, a low-power energy integrator could be designed to integrate the entire symbol, thus achieving symbol decoding. When decoding the same symbol, compared to an ADC requiring dozens of sampling, amplification, and integration operations, the energy integrator only needs to perform one integration operation, thus potentially significantly reducing decoding power consumption.

[0049] like Figure 4 As shown, S beat The high-level portion of the voltage can charge capacitor C1 through resistor R. Because S beat A longer signal duration allows the symbol "1" to charge the capacitor to a higher peak voltage, which can be detected by a threshold detector and converted into a high-level signal representing the binary value "1"; conversely, a shorter signal duration results in a lower peak voltage due to S. beat The signal duration is too short to raise the capacitor voltage to the detection threshold, so the threshold detector will output a low level representing the binary value "0". To reduce the power consumption of the integrator, the resistance value of R can be increased, thereby suppressing the internal current to only a few microamps, and the power consumption of the integrator can be reduced to about 10 microwatts.

[0050] In practical applications, the peak voltage that capacitor C1 can reach during charging depends not only on S. beat The duration also depends on S beat The signal amplitude. For example, when the receiver is placed close to the gateway transmitter, the Chirp signal received by the receiver is strong, which will ultimately result in a high amplitude Sbeat signal after amplification. beatThis will lead to a faster capacitor charging speed. In this case, although S in the symbol "0" beat The signal duration is short, but it can also rapidly charge the capacitor to the threshold voltage of the threshold detector. This can cause a symbol "0" to be incorrectly identified as a symbol "1". Conversely, when the receiver is placed far from the gateway transmitter, a symbol "1" may also be incorrectly identified as a symbol "0". To address this issue, this design normalizes the amplified Sbeat signal. Specifically, a voltage comparator is placed between the LC amplifier circuit and the RC integrator circuit to normalize the Sbeat signal. beat The high level of the signal is converted into a preset voltage value.

[0051] The threshold detector determines the binary value represented by each symbol based on the peak voltage reached during capacitor charging. Therefore, before the next symbol arrives, the capacitor needs to quickly and completely release its energy to prevent residual energy from affecting the charging result of the next symbol. Utilizing the capacitor's self-discharge effect is insufficient for energy release, as the self-discharge time is typically measured in seconds or even minutes, significantly reducing communication speed. To address this issue, this design incorporates an NMOS switch connected in parallel between the capacitor's two plates. Figure 4 As shown. At the end of each symbol, the switch will close, thus enabling rapid discharge.

[0052] To receive the decoding results, the processor needs to know the exact end time of each symbol and read the threshold detector's output at that time. Otherwise, if the processor reads the threshold detector's output at the wrong time (e.g., before integration is complete), it will receive an incorrect decoding result. In other words, the processor needs to synchronize with the symbols sent by the gateway. A common symbol synchronization method is to send a pre-agreed preamble symbol before communication; the processor can then identify the preamble symbol by sampling it with an ADC, thus achieving synchronization. However, the decoding circuit of this invention cannot use an ADC for sampling, and therefore it seems impossible to achieve synchronization and decoding of any single symbol.

[0053] To address this issue, the decoding circuit design incorporates a synchronization function, which can be switched between the circuit's synchronization and decoding functions via a program. For example... Figure 5 and Figure 6As shown, two NMOS switches and two resistors are added to the circuit to achieve synchronization. When receiving a synchronization symbol, switches SW2 and SW3 close under the processor's control, connecting resistors R2 and R3 into the circuit. At this time, the parallel resistors R and R2 form a smaller resistance, thus accelerating the charging speed of the RC circuit. With these resistors, even the symbol "0" can charge the capacitor to the threshold of the threshold detector, and due to the presence of R3, the energy in the capacitor can be quickly released below the detection threshold before the next symbol arrives, triggering a high-to-low transition in the threshold comparator's output signal. After detecting the transition, the processor closes SW to completely release the energy in the capacitor. Therefore, when the receiver performs symbol synchronization, it can use multiple consecutive symbols "0" as synchronization symbols. Symbol synchronization is achieved when the processor detects the corresponding number of high levels arriving sequentially. The reason why the symbol "1" is not used as the synchronization symbol in this paper is that the S in symbol "1"... beat If the signal duration is too long, the capacitor will charge to an excessively high voltage. In this case, even with R3 for discharging, the discharge time will be long, forcing the receiver to increase the interval between synchronization symbols, which increases the synchronization operation time.

[0054] like Figure 5 As shown, the terminal processor's clock will continuously drift during operation, causing deviations in the processor's synchronization state. As these deviations accumulate, signal decoding will eventually fail. To address this issue, the processor calibrates its own synchronization clock by detecting the first rising edge of each symbol.

[0055] This invention requires the participation of a processor. However, the processor only needs to participate in decoding for a brief period between the end of each symbol and the arrival of the next symbol. Specifically, the processor only needs to read the output of the threshold detector at the end of a symbol, briefly close the switch SW to initialize the capacitor, and detect the first rising edge of the next symbol to calibrate the clock. The processor can enter a sleep state at other times. In the sleep state, the processor only activates the timing and wake-up circuits, with power consumption at the nanowatt level.

[0056] This invention reduces power consumption by decreasing the charging current in the RC circuit. The charging current of the circuit can be expressed as:

[0057]

[0058] Where V ref This represents the charging voltage applied between the capacitor plates, equal to the reference voltage used in the normalization voltage comparator. I is suppressed by increasing resistor R and decreasing capacitor C2. chargeThis measure ensures that the product of capacitance and resistance, RC, and the charging speed of the circuit remain constant. For example, when the symbol rate is 5ksps, calculations show that suitable R and C values ​​should be 220kΩ and 330pF, respectively, at which point the power consumption of the RC circuit is 12 microwatts.

[0059] This invention achieves a receiving distance of hundreds of meters with microwatt-level power consumption. The first passive device-based chirp despreading mechanism is proposed, which successfully reduces the power consumption of chirp signal despreading from several milliwatts to zero by floating the high-power carrier and down-chirp signal generation functions to the gateway. Secondly, a novel zero-power amplification technique based on an LC resonant circuit and an encoding mechanism applicable to this LC resonant amplifier are proposed, effectively improving receiver sensitivity. Finally, an energy accumulation-based decoding mechanism is proposed to replace the high-power ADC sampling-based decoding mechanism. Extensive experimental evaluations of this design were conducted in various scenarios. Experimental results show that μMote can support a receiving distance of up to 400 meters with a power consumption of 62.07 microwatts at a communication bit rate of 2 kbps. Compared to existing low-power receivers, μMote increases the downlink communication distance by 8.65 times while reducing power consumption by 63.2%.

[0060] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A low-power, long-distance downlink receiver circuit, characterized in that: It includes a receiving antenna, a Chirp despreading circuit, an energy accumulation amplifier circuit, a normalization circuit, a low-power decoding circuit, a threshold detector, and a processor; The Chirp despreading circuit is connected to the receiving antenna and is used to mix the two wideband Chirp signals simultaneously transmitted from the transmitter by the receiving antenna to achieve demodulation and despreading of the Chirp signals, generating a despread difference frequency signal. The energy accumulation amplification circuit is connected to the Chirp despreading circuit to accumulate the energy of the signal to amplify the signal and generate the blank interval required to separate two adjacent signal segments. The normalization circuit is connected to the energy accumulation amplifier circuit, and a voltage comparator is used to normalize the amplified signal, thereby converting the high level of the signal into a preset voltage value. The low-power decoding circuit is connected to the normalization circuit and integrates the entire signal through an energy integrator, thereby achieving signal decoding. The threshold detector detects the signal level and sends it to the processor; The processor detects the first rising edge of the output signal of the normalization circuit to correct clock drift, calibrates its own synchronization clock, and controls the switching of synchronization and decoding functions in the zero-power synchronization and low-power decoding circuit. The Chirp despreading circuit includes a mixer composed of two parallel RF diodes. The anode of one RF diode is connected to the receiver, and the anode of the other RF diode is grounded. The mixer mixes the two Chirp signals to generate a difference frequency signal S. beat By measuring S beat The duration of the signal determines the duration of the two Chirp signals sent by the transmitter. By changing the duration of the two Chirp signals sent by the transmitter, they are encoded into different binary symbols. The energy accumulation amplification circuit includes an LC resonant circuit consisting of an inductor connected in series with the mixer and a grounded first capacitor. The energy in the circuit alternates between magnetic potential energy and electric potential energy under the influence of the first capacitor and the inductor, accumulating the signal energy to amplify the signal and obtain the amplified S. beat The signal is the resonant signal. The encoding is represented by different binary symbols, including: the amplified S beat Long-duration signals are represented by the binary symbol 1. The amplified S... beat Signals with short durations are represented by the binary symbol 0; Before the energy of the next symbol begins to accumulate in the LC resonant circuit, the energy of the previous symbol is released from the LC resonant circuit in advance, thus forming a period of time when the resonance stops before the arrival of the next symbol, namely the blank time interval, which is used to separate the two symbols.

2. The low-power long-distance downlink receiver circuit according to claim 1, characterized in that: The low-power decoding circuit includes a low-power energy integrator consisting of a resistor R connected in series with the normalization circuit and a second capacitor grounded. The energy integrator integrates the entire symbol to achieve symbol decoding.

3. The low-power long-distance downlink receiver circuit according to claim 2, characterized in that: An NMOS switch SW is connected in parallel with the second capacitor. After the previous symbol is fully charged, the processor controls the switch SW to close, which rapidly discharges the second capacitor, initializes it, and prevents residual energy from affecting the charging result of the next symbol.

4. The low-power long-distance downlink receiver circuit according to claim 3, characterized in that: A resistor R2 and an NMOS switch SW2 are connected in parallel across the two ends of the resistor R. A resistor R2 and an NMOS switch SW3 are connected in parallel at the connection point between the resistor R and the second capacitor. The other end of the switch SW3 is grounded. When receiving a synchronization symbol, switches SW2 and SW3 are closed under the control of the processor, connecting resistors R2 and R3 into the circuit. This reduces the overall resistance of the RC circuit, thereby accelerating the charging speed of the RC circuit. Before the next symbol arrives, the energy in the second capacitor will be quickly released below the detection threshold, triggering a high-to-low transition in the threshold detector's output signal. After detecting the transition, the processor will control switch SW to close completely to release the energy in the second capacitor. During symbol synchronization, multiple consecutive symbols are used as synchronization symbols. When the processor detects the corresponding number of high levels in sequence, symbol synchronization can be achieved.

Images