A resistor-capacitor hybrid analog-to-digital converter and a method of operating the same
By using a hybrid RC analog-to-digital converter, employing a segmented structure of an R-2R trapezoidal resistor network and a binary weighted capacitor array, the problems of numerous capacitors and mismatch in high-precision SAR ADCs are solved, achieving high-precision, low-power analog-to-digital conversion.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG UNIV
- Filing Date
- 2024-12-31
- Publication Date
- 2026-06-12
AI Technical Summary
Existing high-precision SAR ADCs require a large number of capacitors, occupy a large layout area, and capacitor mismatch affects linearity. Traditional calibration methods increase complexity and power consumption.
A hybrid RC analog-to-digital converter is adopted. The first stage uses RDAC to generate the active high bits, and the second stage uses CDAC to generate the active low bits. The segmented structure is realized through R-2R ladder resistor network and binary weighted capacitor array, which reduces the number of unit capacitors and resistors.
It effectively reduces circuit area, mitigates the impact of capacitor mismatch, improves linearity, achieves high-precision analog-to-digital conversion, and reduces power consumption.
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Figure CN119906429B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of mixed-signal integrated circuit design technology, and in particular to a resistor-capacitor hybrid analog-to-digital converter and its operating method. Background Technology
[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.
[0003] SAR ADCs have garnered significant attention in academia and are widely used in production due to their low power consumption, ease of achieving medium to high accuracy, and good compatibility with advanced processes. High-precision SAR ADCs typically employ charge redistribution structures. The number of capacitors required for this structure increases exponentially with resolution, resulting in a considerable number of capacitors needed for high-precision SAR ADCs, which occupies a very large layout area. Furthermore, large capacitors complicate the design of input and power buffers. In addition, the mismatch caused by an excessive number of capacitors can severely affect the ADC's linearity.
[0004] To reduce the number of unit capacitors in a CDAC, a segmented capacitor structure or a C-2C structure can be used. However, these structures are very sensitive to parasitic capacitance, limiting the overall accuracy of the ADC. In traditional binary weighted capacitor array structures, when the ADC accuracy is too high (greater than 12 bits), capacitor mismatch has a very serious impact. To achieve a sufficiently high Effective Number of Bits (ENOB) for the ADC, capacitor mismatch must be calibrated. Many effective calibration methods exist, such as Mismatch Error Shaping (MES), analog front-end calibration, and digital back-end calibration. However, while adding additional calibration circuitry can meet the requirements, it incurs additional area and power consumption overhead and increases design complexity. Summary of the Invention
[0005] To address the technical problems mentioned above, this invention provides a hybrid RC analog-to-digital converter and its operating method. The first stage uses an RDAC to generate the most significant bits (MSBs), and the second stage uses a CDAC to generate the least significant bits (LSBs). This segmented hybrid RC structure can effectively reduce the number of unit capacitors and mitigate the impact of capacitor mismatch.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] The first aspect of the present invention provides a hybrid RC analog-to-digital converter.
[0008] A hybrid analog-to-digital converter (ADC) includes: a SAR control logic circuit, and an RDAC resistor array, a CDAC capacitor array, a reference voltage sampling capacitor unit, and a comparator, all connected thereto. The CDAC capacitor array is connected to the positive and negative input terminals of the comparator, and the output terminal of the comparator is connected to the SAR control logic circuit.
[0009] The reference voltage sampling capacitor unit can be connected between the output terminal of the RDAC resistor array and ground to sample the output voltage of the RDAC resistor array, or connected between the input terminal of the CDAC capacitor array and the output terminal of the RDAC resistor array to provide a reference voltage for the CDAC capacitor array.
[0010] During the sampling phase, the input voltage is stored in the CDAC capacitor array, while the reference voltage sampling capacitor unit samples the output voltage of the RDAC resistor array. During the conversion phase, the comparator obtains the comparison result based on the output voltage of the CDAC capacitor array. Based on the comparison result, the SAR control logic circuit controls the switching of the RDAC resistor array and the CDAC capacitor array to complete the successive approximation analog-to-digital conversion process.
[0011] Furthermore, the RDAC resistor array includes ladder resistor networks RDACP and RDACN.
[0012] Furthermore, the RDACP / RDACN trapezoidal resistor network includes N+1 first series units, each first series unit including two first unit resistors Ru connected in series. One end of the 2nd to the N+1th first series units is sequentially designated as the first to the Nth nodes, and the other end serves as the N input terminals of the RDAC resistor array, sequentially designated as DP. M / DN M To DP M+N-1 / DN M+N-1 The first switch array selects whether to connect to ground voltage or reference voltage.
[0013] Furthermore, adjacent nodes from the first to the Nth node are connected by a second unit resistor. One end of the first series unit is directly connected to the first node, and the other end is fixedly connected to the common-mode reference voltage. The Nth node serves as the output terminal of the RDACP / RDACN ladder resistor network, which is ROUTP / ROUTN.
[0014] Furthermore, the CDAC capacitor array includes binary weighted capacitor arrays CDACP and CDACN, with the binary weighted capacitor array CDACP connected to the positive input terminal of the comparator and the binary weighted capacitor array CDACN connected to the negative input terminal of the comparator.
[0015] Furthermore, the binary weighted capacitor array CDACP / CDACN includes M capacitors, namely Cu, Cu, and 2. 1 Cu, 2 2 Cu、...、2 M-2 Cu; One end of each of the M capacitors is directly connected as the output node COUTP / COUTN of CDACP / CDACN, which is connected to the positive / negative input of the comparator. The other end serves as the M inputs of CDACP / CDACN, namely DP0 / DN0 to DP... M-1 / DN M-1 It can be connected to the differential input signal Vip / Vin, ROUTP / ROUTN or the reference voltage sampling capacitor unit via a switch array.
[0016] Furthermore, the reference voltage sampling capacitor array includes four capacitors Cpu, Cnu, Cpd, and Cnd. Cpu and Cpd are selectively connected between ROUTP and ground, or between the input switch array of the binary weighted capacitor array CDACP and ROUTP, through a switch controlled by a sampling signal. Cnu and Cnd are selectively connected between ROUTN and ground, or between the input switch array of the binary weighted capacitor array CDACN and ROUTN, through a switch controlled by a sampling signal.
[0017] A second aspect of the present invention provides a method for operating a hybrid RC analog-to-digital converter.
[0018] A method for operating a hybrid RC analog-to-digital converter, applied to the hybrid RC analog-to-digital converter described in the first aspect, includes:
[0019] During the sampling phase, the differential input signals Vip / Vin are connected to all input terminals of the CDAC capacitor array through a switch array to complete the sampling. At the same time, all input terminals of the RDAC resistor array are connected to GND. The reference voltage sampling capacitor unit is connected between the output terminal of the RDAC resistor array and ground to sample the output voltage of the RDAC resistor array.
[0020] During the conversion phase, the output terminal ROUT of the RDAC resistor array is connected to the input terminal of the CDAC capacitor array. The reference voltage sampling capacitor unit is connected between the switch array at the input terminal of the CDAC capacitor array and the output terminal of the RDAC resistor array, providing the reference voltage required for the conversion of the CDAC capacitor array during the conversion.
[0021] Furthermore, during the sampling phase, the voltage at points ROUTP / ROUTN is V. REF / 2 N+1The voltage is sampled onto Cpu / Cpd and Cnu / Cnd. During the conversion stage, the upper plate of Cpu / Cnu is connected to the input switch array of CDACP / CDACN, and the lower plate is connected to ROUTP / ROUTN. The upper plate of Cpd / Cnd is connected to ROUTP / ROUTN, and the lower plate is connected to the input switch array of CDACP / CDACN. The reference voltage required for conversion is provided to the CDAC capacitor array through the reference voltage sampling capacitor unit. The voltage of the upper plate of Cpu is V. REFPU =V ROUTP +V REF / 2 N+1 The voltage across the lower plate of Cpd is V. REFPD =V ROUTP -V REF / 2 N+1 The voltage across the upper plate of Cnu is V. REFNU =V ROUTN +V REF / 2 N+1 The voltage at the lower plate of Cnd is V. REFND =V ROUTN -V REF / 2 N+1 After the conversion begins, the voltage at the input terminals of the RDAC resistor array and CDAC capacitor array is switched by the logic control circuit according to the comparison result of the comparator, and the successive approximation process begins.
[0022] Furthermore, the successive approximation process is performed sequentially from the most significant bit to the least significant bit:
[0023] (1) Switching of the RDAC resistor array:
[0024] When the first comparator output is 1, the SAR control logic circuit controls the input terminal corresponding to RDACP / RDACN to switch to V. REF / GND, the voltage difference between the positive and negative input terminals of the comparator is
[0025] When the first comparator output is 0, the input terminals corresponding to RDACP / RDACN switch to GND / V. REF The voltage difference between the positive and negative input terminals of the comparator is
[0026] Similarly, after the resistor array comparison is complete, the voltage difference at the comparator input is: Where, when the comparator result is 1, B i =1, when the comparator result is 0, B i =-1;
[0027] (2) Then the switching of the CDAC capacitor array begins:
[0028] When the first comparator output is 1, the switch SP is activated. M-1 and SN M-1 Switch the most significant bit input of the binary weighted capacitor array CDACP from ROUTP to V. REFPU =V ROUTP +V REF / 2 N+1 This causes a change in the voltage at point COUTP. Switch the most significant bit input of the binary weighted capacitor array CDACN from ROUTN to V. REFND =V ROUTN -V REF / 2 N+1 This causes a change in the voltage at point COUTN. The change in voltage difference at the comparator input is:
[0029] When the first comparator output is 0, the most significant bit input of CDACP switches from ROUTP to V. REFPD =V ROUTP -V REF / 2 N+1 This causes a change in the voltage at point COUTP. Switch the highest bit input of CDACN from ROUTN to V. REFNU =V ROUTN +V REF / 2 N+1 This causes a change in the voltage at point COUTN. The change in voltage difference at the comparator input is:
[0030] And so on, after all bits have been compared, the voltage difference across the comparator is: Due to the final V COUTP -V COUTN ≈0, therefore: That is, the precision of the SAR control logic circuit has reached N+M bits.
[0031] Compared with the prior art, the beneficial effects of the present invention are:
[0032] This invention provides a hybrid RC analog-to-digital converter, in which the resistor array is implemented using an R-2R trapezoidal resistor network. This effectively reduces the number of unit resistors in the resistor array, reduces the circuit area, and thus allows for a larger area unit device with more area margin, reducing mismatch between devices and improving the linearity of the overall circuit.
[0033] This invention discloses an RC Hybrid (RC) Successive Approximation Register (SAR) analog-to-digital converter (ADC). It employs a resistive digital-to-analog converter (RDAC) to quantize the high N bits and a capacitive digital-to-analog converter (CDAC) to quantize the low M bits, ultimately obtaining an (N+M) bit output code. Due to the use of an RC segmented structure, this invention reduces the number of unit capacitors in the DAC, mitigating the impact of capacitor mismatch on ADC linearity. Traditional RC hybrid ADCs typically use a resistor string structure for the RDAC, while this invention uses an R-2R ladder resistor network, effectively reducing the number of unit resistors. By controlling the accuracy ratio of the RDAC and CDAC, this invention achieves a trade-off between linearity, area, and power consumption. Attached Figure Description
[0034] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.
[0035] Figure 1 This is a circuit schematic diagram of a conventional RC hybrid ADC with a resistor string structure shown in this invention;
[0036] Figure 2 This is a schematic diagram of the R-2R hybrid capacitive-resistive ADC shown in this invention;
[0037] Figure 3 This is a circuit schematic diagram of a resistor-capacitor hybrid analog-to-digital converter based on an R-2R structure, as shown in this invention.
[0038] Figure 4 This is a sampling schematic diagram of the reference voltage sampling unit shown in this invention;
[0039] Figure 5 This is a schematic diagram illustrating the generation of a reference voltage by a reference voltage sampling unit according to the present invention. Detailed Implementation
[0040] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0041] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.
[0042] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0043] Example 1
[0044] In traditional RC hybrid ADCs, the RDAC typically uses a resistor string structure. The schematic diagram of a traditional RC hybrid ADC is shown below. Figure 1 As shown, when the RDAC has an N-bit precision, the traditional structure requires 2 N The number of unit resistors increases exponentially with RDAC accuracy. In this invention, the RDAC of the RC hybrid ADC is implemented using an R-2R trapezoidal resistor network. With a differential structure, an N-bit RDAC requires only (6N+2) unit resistors, and the number of resistors increases linearly with RDAC accuracy. Therefore, this invention effectively reduces the number of unit resistors, thereby reducing the RDAC area. This increased area margin allows for larger unit capacitor values to reduce capacitor mismatch and avoids the need for calibration circuitry.
[0045] For a hybrid capacitive-resistive ADC using an R-2R structure, the schematic diagram of the hybrid capacitive-resistive ADC is as follows: Figure 2 As shown. The capacitive-resistive hybrid ADC uses a capacitor-based DAC to quantize the MSB bits and a resistor-based DAC to quantize the LSB bits. Because the matching between capacitors is better than that between resistors in current advanced processes, the capacitor-based DAC can achieve higher accuracy than the resistor-based DAC. In a SAR ADC, the accuracy of the LSB bits determines the overall accuracy of the ADC; therefore, compared to a capacitive-resistive ADC, this invention achieves higher accuracy by using a capacitive-resistive DAC to quantize the LSB bits, reducing the performance requirements of the comparator. Furthermore, the voltage variation range of the capacitor array in the capacitive-resistive ADC is V. REF In this invention, since the reference voltage of the capacitor array is generated by the resistor array and scaled by the resistor array, its variation range is... Where N is the precision of the resistor array, V REFU and V REFD The voltage provided by the reference voltage sampling capacitor unit. Since the power consumption generated during capacitor array switching is proportional to the square of the voltage change across the capacitor, the dynamic power consumption of the capacitor array in this invention is lower.
[0046] To illustrate the working principle and process of this invention, a hybrid RC analog-to-digital converter proposed in this invention is implemented using Vcm-based switching timing, as shown in the schematic diagram. Figure 3 As shown. The overall circuit includes a resistor array RDAC, a capacitor array CDAC, a reference voltage sampling capacitor unit, a comparator, control logic, and several switches.
[0047] The resistor array RDAC includes resistor arrays RDACP and RDACN. The resistor arrays employ an R-2R ladder network, with each array containing N+1 series-connected units. Each series-connected unit includes two unit resistors Ru connected in series, equivalent to a resistor arm with a resistance of 2Ru. One end of the 2nd to Nth series-connected units is connected via unit resistors Ru, forming N nodes at the connection points. The other end serves as the N input terminals of RDACP / RDACN, sequentially designated as DP. M / DN M To DP M+N-1 / DN M+N-1 Each through switch SP M / SN M To SP M+N-1 / SN M+N-1 Select grounding voltage GND, reference voltage V REF Or common-mode reference voltage V CM (V CM =V REF / 2); One end of the first series unit is directly connected to the first node, and the other end is fixedly connected to V. CM The Nth node serves as the output of RDACP / RDACN, which is ROUTP / ROUTN.
[0048] The CDAC capacitor array consists of two sets of binary weighted capacitor arrays, CDACP and CDACN. Each array contains M capacitors, which are Cu, Cu, and 2 in sequence. 1 Cu, 2 2 Cu、...、2 M-2 Cu; One end of each of the M capacitors is directly connected as the output node COUTP / COUTN of CDACP / CDACN, which is connected to the positive / negative input of the comparator; the other end serves as the M inputs of CDACP / CDACN, namely DP0 / DN0 to DP... M-1 / DN M-1 via switch array SP0 / SN0 to SP M-1 / SN M-1 Select the corresponding position to connect to the differential input signal Vip / Vin, ROUTP / ROUTN, or the reference voltage sampling capacitor unit.
[0049] The reference voltage sampling capacitor array contains four capacitors: Cpu, Cnu, Cpd, and Cnd. Cpu and Cpd are selectively connected between ROUTP and ground, or between the input switch array of CDACP and ROUTP, via a switch controlled by the sampling signal; Cnu and Cnd are selectively connected between ROUTN and ground, or between the input switch array of CDACN and ROUTN, via a switch controlled by the sampling signal.
[0050] The reference voltage sampling capacitor unit is not a bridge capacitor between the MSB and LSB. Its connection method and working principle are fundamentally different from the bridge capacitor in a traditional segmented capacitor array. The reference voltage sampling capacitor unit functions like a battery. During input signal sampling, it is charged by the RDAC. During CDAC conversion, it provides a reference voltage to the lower plate of the CDAC by switching its connection mode, enabling the overall analog-to-digital converter to achieve an N+M successive approximation process.
[0051] The specific workflow of the RC hybrid analog-to-digital converter described in this invention can be divided into two stages:
[0052] The first stage is the sampling stage: through the switch group SP0 / SN0 to SP M-1 / SN M-1 Connect all input terminals of CDACP and CDACN to Vip and Vin respectively to sample the input signal. At this time, both COUTP and COUTN nodes are connected to V. CM Therefore, the voltage difference between the upper and lower plates of CDACP and CDACN during sampling is V. CM -VIP, V CM -Vin; via switch group SP M / SN M To SP M+N-1 / SN M+N-1 Connect the inputs of RDACP and RDACN to GND, while connecting Cpu / Cpd and Cnu / Cnd between ROUTP / ROUTN and GND to sample and hold the output voltage of RDAC. Figure 4 The image shown is a simplified representation. Figure 4 Only one resistor array is displayed; the actual circuit has two arrays. The voltage V at point ROUTP / ROUTN is shown at this time. ROUTP0 / V ROUTN0 =V CM / 2 N =V REF / 2 N+1 V ROUTP0 and V ROUTN0 They were sampled onto Cpu / Cpd and Cnu / Cnd, respectively.
[0053] The second stage is the conversion stage: before the conversion begins, the switching group SP is used. M / SN M To SP M+N-1 / SN M+N-1 Connect both the inputs of RDACP and RDACN to V. CM Through switch group SP0 / SN0 to SP M-1 / SN M-1 Connect all input terminals of CDACP / CDACN to ROUTP / ROUTN. Since the voltage at points ROUTP and ROUTN is V at this time... ROUTP1 =V ROUTN1 =V CM (1 / 2+1 / 2 2 +…+1 / 2 N +1 / 2 N ) = V CM Therefore, the voltages at points COUTP and COUTN are 2V respectively. CM -VIP and 2V CM -Vin. Simultaneously connect the upper plate of Cpu / Cnu to the input switch array of CDACP / CDACN, and the lower plate to ROUTP / ROUTN; connect the upper plate of Cpd / Cnd to ROUTP / ROUTN, and the lower plate to the input switch array of CDACP / CDACN, such as... Figure 5 The image shown is a simplified representation. Figure 5 Only one resistor array is shown; the actual circuit has two arrays. During the conversion process, the reference voltage sampling capacitor unit provides the reference voltage required for the CDAC conversion. The CPU's upper plate voltage is V. REFPU =V ROUTP +V REF / 2 N+1 The voltage across the lower plate of Cpd is V. REFPD =V ROUTP -V REF / 2 N+1 The voltage across the upper plate of Cnu is V. REFNU =V ROUTN +V REF / 2 N+1 The voltage at the lower plate of Cnd is V. REFND =V ROUTN -V REF / 2 N+1 After the conversion begins, the voltage switching of the input terminals of RDAC and CDAC is controlled by the logic control circuit according to the comparison result of the comparator, and the successive approximation process begins.
[0054] By switch SP M+N-1 / SN M+N-1The input ends of the SP0 / SN0 control correspond to the (N+M)-th bit to the first bit of the ADC in sequence. The successive approximation process is carried out from the highest bit to the lowest bit in sequence.
[0055] When the result of the first comparison is 1, it indicates that V COUTP >V COUTN , that is, 2V CM -Vip>2V CM -Vin, that is, Vip<Vin. At this time, the logic control circuit controls the input ends corresponding to RDACP / RDACN to switch to V M+N-1 / SN M+N-1 to switch the input ends corresponding to RDACP / RDACN to V REF / GND. The change in the voltage of the highest-bit input end of RDACP is V REF -V CM =V CM , and the voltage at the ROUTP point rises by V CM / 2; the change in the voltage of the highest-bit input end of RDACN is GND-V CM =-V CM . The voltage at the ROUTN point drops by V CM / 2; since the input ends of CDACP and CDACN are respectively connected to ROUTP and RDACN during the RDAC conversion and the charges at the COUTP and COUTN points are conserved, the voltages at the COUTP and COUTN points respectively become 2V CM -Vip+V CM / 2 and 2V CM -Vin-V CM / 2, and the voltage difference between the positive and negative ends of the comparator is:
[0056]
[0057]
[0058] Similarly, when the result of the first comparison is 0, the input ends corresponding to RDACP / RDACN are switched to GND / V REF . The voltage changes at the COUTP and COUTN points are 2V CM- Vip-V CM / 2 and 2V CM -Vin+V CM / 2. The voltage difference at the input end of the comparator is:
[0059] And so on, when the comparison of the resistor array ends, the voltage difference at the input end of the comparator is:
[0060]
[0061] Where, when the comparator result is 1, B i =1, when the comparator result is 0, B i =-1.
[0062] Then the capacitor array switching begins. Similarly, when the comparator output is 1, the switch SP is activated. M-1 and SN M-1 Switch the highest bit input of CDACP from ROUTP to V. REFPU =V ROUTP +V REF / 2 N+1 This causes a change in the voltage at point COUTP. Switch the highest bit input of CDACN from ROUTN to V. REFND =V ROUTN -V REF / 2 N+1 This causes a change in the voltage at point COUTN. Therefore, the change in the voltage difference at the comparator input is:
[0063]
[0064] When the comparator output is 0, the most significant bit input of CDACP switches from ROUTP to V. REFPD =V ROUTP -V REF / 2 N +1 This causes a change in the voltage at point COUTP. Switch the highest bit input of CDACN from ROUTN to V. REFNU =V ROUTN +V REF / 2 N+1 This causes a change in the voltage at point COUTN. Therefore, the change in the voltage difference at the comparator input is:
[0065]
[0066] In summary, after the most significant bit of the CDAC has been compared, the voltage difference across the comparator is:
[0067]
[0068] Right now:
[0069]
[0070] And so on, after all bits have been compared, the voltage difference across the comparator is:
[0071]
[0072] Due to the final V COUTP -V COUTN ≈0, therefore:
[0073]
[0074] That is, the accuracy of the SAR ADC reaches N+M bits.
[0075] In summary, this invention proposes a hybrid RC analog-to-digital converter (ADC). Compared with traditional hybrid RC SAR ADCs, this invention can effectively reduce the area of the resistor array. By adjusting the accuracy ratio of the resistor array and capacitor array, this invention can better achieve a trade-off between linearity, area, and power consumption. It is worth noting that the ADC proposed in this invention is not limited to implementation using Vcm-based switching timing. By adjusting the number and connection method of the reference voltage sampling units, this invention can be applied to any switching timing, which will not be detailed here.
[0076] Example 2
[0077] This embodiment provides a method for operating a hybrid resistor-capacitor analog-to-digital converter.
[0078] A method for operating a hybrid RC analog-to-digital converter, applied to a hybrid RC analog-to-digital converter, includes:
[0079] During the sampling phase, the input voltage is stored on the capacitor array by sampling through the lower plate, while the reference voltage sampling capacitor unit samples the voltage output by the RDAC. During the conversion phase, the comparator obtains the comparison result based on the output voltage of the CDAC, and then controls the switching of the RDAC and CDAC through the logic control circuit according to the comparison result to complete the successive approximation analog-to-digital conversion process.
[0080] During the sampling phase, the differential input signals Vip / Vin are sampled by connecting to all input terminals of the capacitor arrays CDACP / CDACN via a switch array. Simultaneously, all input terminals of the resistor arrays RDACP and RDACN are connected to GND, and the reference voltage sampling capacitor is connected between the output terminal of the resistor array and ground to sample the output voltage of the RDAC.
[0081] During the conversion phase, the output terminals ROUTP / ROUTN of the resistor array are connected to the input terminals of the capacitor arrays CDACP / CDACN, respectively. The reference voltage sampling capacitor is connected between the switch array at the input terminal of CDAC and the output terminal of RDAC, providing the reference voltage required for the conversion of CDAC during the conversion.
[0082] In some embodiments, the RC hybrid analog-to-digital converter includes: an RDAC resistor array, a CDAC capacitor array, a reference voltage sampling capacitor unit, a comparator, and SAR control logic circuitry;
[0083] The RDAC resistor array comprises two sets of R-2R trapezoidal resistor networks, RDACP and RDACN. Each trapezoidal resistor network contains N+1 series-connected units, and each series-connected unit includes two unit resistors Ru connected in series. One end of the 2nd to N+1th series-connected units is sequentially designated as the first to Nth nodes, and the other end serves as the N input terminals of the RDAC, designated as DP. M / DN M To DP M+N-1 / DN M+N-1 The connection to ground voltage or reference voltage is selected via a switch array. Adjacent nodes from the first to the Nth node are connected by a unit resistor. One end of the first series unit is directly connected to the first node, and the other end is fixedly connected to the common-mode reference voltage. The Nth node serves as the output terminal of RDACP / RDACN, designated as ROUTP / ROUTN.
[0084] The reference voltage sampling capacitor unit can be connected between the output terminal of the RDAC resistor array and ground to sample the output voltage of the RDAC resistor array, or connected between the input terminal of the CDAC capacitor array and the output terminal of the RDAC resistor array to provide a reference voltage for the CDAC capacitor array.
[0085] The CDAC capacitor array comprises two sets of binary weighted capacitor arrays, CDACP and CDACN. Each set of capacitor arrays contains M capacitors, which are Cu, Cu, and 2 in sequence. 1 Cu, 2 2 Cu、...、2 M-2 Cu; One end of each of the M capacitors is directly connected as the output node COUTP / COUTN of CDACP / CDACN, which is connected to the positive / negative input of the comparator. The other end serves as the M inputs of CDACP / CDACN, namely DP0 / DN0 to DP... M-1 / DN M-1 It can be connected to the differential input signal Vip / Vin, ROUTP / ROUTN or the reference voltage sampling capacitor unit via a switch array.
[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A hybrid RC analog-to-digital converter, characterized in that, include: The SAR control logic circuit, and RDAC resistor array, CDAC capacitor array, reference voltage sampling capacitor unit and comparator are all connected to it. The CDAC capacitor array is connected to the positive input terminal and the negative input terminal of the comparator, and the output terminal of the comparator is connected to the SAR control logic circuit. The reference voltage sampling capacitor unit can be connected between the output terminal of the RDAC resistor array and ground to sample the output voltage of the RDAC resistor array, or connected between the input terminal of the CDAC capacitor array and the output terminal of the RDAC resistor array to provide a reference voltage for the CDAC capacitor array. When the reference voltage sampling capacitor unit is working, it is charged by the RDAC during the input signal sampling period. During the CDAC conversion, the reference voltage sampling capacitor unit provides a reference voltage to the lower plate of the CDAC by switching the connection mode. The RDAC resistor array includes ladder resistor networks RDACP and RDACN; The RDACP / RDACN trapezoidal resistor network includes N+1 first series units, and one end of the 2nd to N+1th first series units is sequentially denoted as the first to Nth nodes; The Nth node serves as the output of the RDACP / RDACN ladder resistor network, designated as ROUTP / ROUTN. The CDAC capacitor array includes binary weighted capacitor arrays CDACP and CDACN; The reference voltage sampling capacitor array includes four capacitors Cpu, Cnu, Cpd, and Cnd. Cpu and Cpd are selectively connected between ROUTP and ground, or between the input switch array of the binary weighted capacitor array CDACP and ROUTP, via a switch controlled by a sampling signal. Cnu and Cnd are selectively connected between ROUTN and ground, or between the input switch array of the binary weighted capacitor array CDACN and ROUTN, via a switch controlled by a sampling signal. During the sampling phase, the input voltage is stored in the CDAC capacitor array, while the reference voltage sampling capacitor unit samples the output voltage of the RDAC resistor array. During the conversion phase, the comparator obtains the comparison result based on the output voltage of the CDAC capacitor array. Based on the comparison result, the SAR control logic circuit controls the switching of the RDAC resistor array and the CDAC capacitor array to complete the successive approximation analog-to-digital conversion process.
2. The RC hybrid analog-to-digital converter according to claim 1, characterized in that, Each first series unit includes two first unit resistors Ru connected in series, and the other end serves as the N input terminals of the RDAC resistor array, which are DP in sequence. M / DN M To DP M+N-1 / DN M+N-1 The first switch array selects whether to connect to ground voltage or reference voltage.
3. The RC hybrid analog-to-digital converter according to claim 2, characterized in that, The adjacent nodes from the first to the Nth nodes are connected by a second unit resistor. One end of the first series unit is directly connected to the first node, and the other end is fixedly connected to the common-mode reference voltage.
4. The RC hybrid analog-to-digital converter according to claim 1, characterized in that, The binary weighted capacitor array CDACP is connected to the positive input terminal of the comparator, and the binary weighted capacitor array CDACN is connected to the negative input terminal of the comparator.
5. The RC hybrid analog-to-digital converter according to claim 4, characterized in that, The binary weighted capacitor array CDACP / CDACN includes M capacitors, namely Cu, Cu, and 2. 1 Cu, 2 2 Cu、...、2 M-2 Cu; One end of each of the M capacitors is directly connected as the output node COUTP / COUTN of CDACP / CDACN, which is connected to the positive / negative input of the comparator. The other end serves as the M inputs of CDACP / CDACN, namely DP0 / DN0 to DP... M-1 / DN M-1 It can be connected to the differential input signal Vip / Vin, ROUTP / ROUTN or the reference voltage sampling capacitor unit via a switch array.
6. A method for operating a hybrid RC analog-to-digital converter, characterized in that, Applied to the RC hybrid analog-to-digital converter according to any one of claims 1-5, comprising: During the sampling phase, the differential input signals Vip / Vin are connected to all input terminals of the CDAC capacitor array through a switch array to complete the sampling. At the same time, all input terminals of the RDAC resistor array are connected to GND. The reference voltage sampling capacitor unit is connected between the output terminal of the RDAC resistor array and ground to sample the output voltage of the RDAC resistor array. During the conversion phase, the output terminal ROUT of the RDAC resistor array is connected to the input terminal of the CDAC capacitor array. The reference voltage sampling capacitor unit is connected between the switch array at the input terminal of the CDAC capacitor array and the output terminal of the RDAC resistor array, providing the reference voltage required for the conversion of the CDAC capacitor array during the conversion.
7. The operating method of the RC hybrid analog-to-digital converter according to claim 6, characterized in that, During the sampling phase, the voltage at points ROUTP / ROUTN is V. REF / 2 N+1 It is sampled onto Cpu / Cpd and Cnu / Cnd; During the conversion phase, the upper plate of Cpu / Cnu is connected to the input switch array of CDACP / CDACN, and the lower plate is connected to ROUTP / ROUTN; the upper plate of Cpd / Cnd is connected to ROUTP / ROUTN, and the lower plate is connected to the input switch array of CDACP / CDACN. The reference voltage required for conversion is provided to the CDAC capacitor array through the reference voltage sampling capacitor unit; the voltage of the upper plate of Cpu is V. REFPU =V ROUTP +V REF / 2 N+1 The voltage across the lower plate of Cpd is V. REFPD =V ROUTP -V REF / 2 N+1 The voltage across the upper plate of Cnu is V. REFNU =V ROUTN +V REF / 2 N+1 The voltage at the lower plate of Cnd is V. REFND =V ROUTN -V REF / 2 N+1 After the conversion begins, the voltage at the input terminals of the RDAC resistor array and CDAC capacitor array is switched by the logic control circuit according to the comparison result of the comparator, and the successive approximation process begins.
8. The operating method of the RC hybrid analog-to-digital converter according to claim 7, characterized in that, The successive approximation process is performed sequentially from the most significant bit to the least significant bit: (1) Switching of the RDAC resistor array: When the first comparator output is 1, the SAR control logic circuit controls the input terminal corresponding to RDACP / RDACN to switch to V. REF / GND, the voltage difference between the positive and negative input terminals of the comparator is ; When the first comparator output is 0, the input terminals corresponding to RDACP / RDACN switch to GND / V. REF The voltage difference between the positive and negative input terminals of the comparator is Vin-Vip- ; Similarly, after the resistor array comparison is complete, the voltage difference at the comparator input is: ; where, when the comparator result is 1, B i =1, when the comparator result is 0, B i =-1; (2) Then the switching of the CDAC capacitor array begins: When the first comparator output is 1, the switch SP is activated. M-1 and SN M-1 Switch the most significant bit input of the binary weighted capacitor array CDACP from ROUTP to V. REFPU =V ROUTP +V REF / 2 N+1 This causes a change in the voltage at point COUTP. Switch the most significant bit input of the binary weighted capacitor array CDACN from ROUTN to V. REFND =V ROUTN -V REF / 2 N+1 This causes a change in the voltage at point COUTN. The change in voltage difference at the comparator input is: ; When the first comparator output is 0, the most significant bit input of CDACP switches from ROUTP to V. REFPD =V ROUTP -V REF / 2 N +1 This causes a change in the voltage at point COUTP. Switch the most significant bit input of CDACN from ROUTN to V. REFNU =V ROUTN +V REF / 2 N+1 This causes a change in the voltage at point COUTN. The change in voltage difference at the comparator input is: ; And so on, after all bits have been compared, the voltage difference across the comparator is: ; due to the final 0, therefore: This means that the precision of the SAR control logic circuit has reached N+M bits.