A method, network element and system for switching control in an SDH ring network

Abstract

A switching control method, network element and system in an SDH ring network, applied to a master processor of a network element in the SDH ring network, the network element comprising an eastward single board and a westward single board, and the total capacity of the panel ports in the eastward single board and the westward single board is greater than the total capacity of the backboard ports in the eastward single board and the westward single board respectively; the method comprises: obtaining virtual container (VC) cross corresponding information of the eastward single board and the westward single board, the VC cross corresponding information indicating the VC cross corresponding relationship between the panel ports and the backboard ports in the single board; when the optical fiber communication connection corresponding to the currently used single board in the eastward single board and the westward single board is disconnected, performing a multiplexing section protection switching operation of the network element according to the VC cross corresponding information, so as to improve the accuracy and reliability of the switching operation.

Description

Technical Field

[0001] This article relates to network communication technologies, particularly a switching control method, network elements, and system in an SDH ring network. Background Technology

[0002] Synchronous Digital Hierarchy (SDH) ring network protection switching technology is widely used in optical communication networks. In a ring network, network elements typically include the main control board, eastbound boards, westbound boards, and customer-side boards. When a fiber optic communication connection in the ring network is lost, the ring network protection switching mechanism should be able to switch services from the faulty path to the protected path to ensure rapid service recovery.

[0003] In practical applications, the following problems have been found in existing technologies: In existing SDH ring networks, some network elements adopt a segmented cross-connect architecture, and there is a situation of single-board capacity convergence, that is, the total capacity of the front panel ports of the eastbound and / or westbound single boards is greater than the total capacity of the backplane ports. See details. Figure 1 In such network elements, the cross-correspondence between the virtual containers (VCs) between the front panel ports and backplane ports of the eastbound or westbound boards is randomly configured, and the main control processor cannot know this cross-correspondence. Therefore, when the fiber optic communication connection corresponding to the currently used board in the eastbound or westbound board is disconnected, the main control processor needs to perform a multiplex section protection switching operation. However, because the main control processor lacks the aforementioned cross-correspondence, it cannot correctly complete the switching operation, resulting in prolonged service interruption time or even switching failure, affecting the network's reliability and self-healing capabilities. Summary of the Invention

[0004] This application provides a switching control method, network element, and system in an SDH ring network.

[0005] A switching control method in an SDH ring network is applied to the main control processor of a network element in the SDH ring network. The network element includes an eastbound board and a westbound board, and the total capacity of the front panel ports of the eastbound board and the westbound board is greater than the total capacity of their respective backplane ports. The method includes: Obtain the virtual container cross-correspondence information of the east-facing single board and the west-facing single board. The VC cross-correspondence information indicates the VC cross-correspondence relationship between the internal panel port and the back panel port of this single board. When the optical fiber communication connection corresponding to the currently used board in the east-facing board and the west-facing board is disconnected, the multiplex section protection switching operation of this network element is performed according to the VC cross-correspondence information.

[0006] A storage medium storing a computer program, wherein the computer program is configured to execute the method described above when run.

[0007] An electronic device includes a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the methods described above.

[0008] A network element in an SDH ring network includes: The main control board has a main control processor on it, which is used to execute the methods described above; The east-facing single board is equipped with a processing unit for synchronizing local VC cross-correspondence information with the main control processor. The west-facing single board is equipped with a processing unit for synchronizing local VC cross-correspondence information with the main control processor.

[0009] An SDH ring network protection switching system includes: The first network element, the second network element, and the third network element are connected end to end in sequence to form a ring topology; The first network element and the third network element are fault-adjacent nodes, and respectively adopt the network element structure described above; The second network element is a pass-through node, configured such that when the currently used optical fiber communication connection between the first network element and the second network element is disconnected, the backplane protection cross-connection of the east-facing single board of this network element is connected to the backplane protection cross-connection of the west-facing single board.

[0010] In this embodiment, the main control processor pre-acquires and stores the VC cross-correspondence information of the east-facing single board and the west-facing single board. When a fault occurs, the main control processor can perform a switchover operation based on the accurate cross-mapping relationship, thereby improving the accuracy and reliability of the switchover operation.

[0011] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0012] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0013] Figure 1 This is a schematic diagram illustrating the convergence of port capacity on a single board in related technologies. Figure 2 A flowchart illustrating the switching control method in an SDH ring network provided in this application embodiment; Figure 3 This is a schematic diagram of the structure of network elements in an SDH ring network provided in an embodiment of this application; Figure 4 for Figure 3 The diagram shows the interaction between the FPGA and the main control processor in the east-west direction board of the network element; Figure 5 This is a schematic diagram of the protection ring for the two-fiber bidirectional multiplexing section in an SDH ring network, as described in related technologies. Detailed Implementation

[0014] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0015] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0016] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0017] This embodiment provides a switching control method in an SDH ring network, applied to the main control processor of a network element in an SDH ring network. It aims to solve the technical problem that the main control processor cannot correctly perform switching operations in capacity convergence scenarios because it does not know the cross-correspondence relationship of the internal VCs of the single board.

[0018] The core of this method lies in proposing a switchover control mechanism based on the pre-synchronization of VC cross-correspondence information. Based on the active reporting or synchronization of the VC cross-correspondence relationship between the internal panel port and the backplane port by the single board, the main control processor pre-acquires and stores the VC cross-correspondence information of the east-facing single board and the west-facing single board. When a fault occurs, the main control processor can perform the switchover operation according to the accurate cross-mapping relationship, thereby improving the accuracy and reliability of the switchover operation.

[0019] Specifically, unlike existing technologies where the main control processor can only control the backplane port cross-connects without knowing the random mapping relationship inside the board, this method obtains the VC cross-connect corresponding information in advance, so that when the fiber optic disconnection event is triggered, the main control processor can directly use this information to locate the backplane cross-connect resource corresponding to the fault direction board, thereby correctly completing the switching of the customer-side board from the fault direction to the protection direction.

[0020] See Figure 2 The method includes steps A and B. Wherein: Step A: The main control processor obtains the VC cross-correspondence information of the east-facing single board and the west-facing single board; the VC cross-correspondence information indicates the VC cross-correspondence relationship between the internal panel port and the backplane port of this single board.

[0021] The purpose of this step is to enable the main control processor to know in advance the mapping relationship between the front panel ports and backplane ports within the east-facing and west-facing boards. Because the total capacity of the front panel ports is greater than the total capacity of the backplane ports in a capacity convergence scenario, virtual container cross-connections between front panel ports and backplane ports are randomly established within the board. This mapping relationship is unknown to the main control processor. By obtaining this information, the main control processor establishes the correspondence between the fault-direction ports and the backplane cross-connect resources.

[0022] Specifically, the eastbound and westbound boards proactively report their internal VC cross-connection information to the main control processor via an inter-board communication protocol (such as the IBC protocol). Upon receiving this information, the main control processor stores it in its local cross-connection mapping table. This retrieval operation can be performed during board initialization or dynamically updated when the cross-connection relationships within the board change.

[0023] This step no longer requires the assumption of a fixed correspondence between the front panel and the back panel; instead, it obtains a true dynamic mapping relationship through an information synchronization mechanism. Through these steps, the main control processor establishes a complete cross-mapping database, providing accurate routing information for subsequent switchover operations and laying the data foundation for their correct execution.

[0024] Step B: When the optical fiber communication connection corresponding to the currently used board in the east-facing board and the west-facing board is disconnected, the multiplex section protection switching operation of this network element is performed according to the VC cross-correspondence information.

[0025] This step serves to switch services from the faulty path to the protected path when a fiber optic fault occurs. The core of the multiplex section protection switching operation is to switch the backplane cross-working between the customer-side board and the faulty board to a backplane protection cross-working between the customer-side board and the board in the other direction.

[0026] The specific implementation is as follows: The main control processor learns that the fiber optic connection of a certain direction board (e.g., the east-facing board) is broken through an interrupt signal or polling. Then, the main control processor queries the locally stored VC cross-connection information to find the backplane port corresponding to the currently used panel port of the faulty direction board (east-facing board). Next, the main control processor controls the backplane cross-connection matrix to disconnect the working cross-connection between the customer-side board and the backplane port, and establishes a protection cross-connection between the customer-side board and the corresponding protection channel backplane port of the other direction board (west-facing board).

[0027] This step utilizes the VC cross-correspondence information pre-acquired in step A to achieve precise location of backplane resources in the fault direction. It can accurately and quickly complete the multiplex section protection switching operation using the pre-synchronized VC cross-correspondence information, thereby controlling the service interruption time within the standard requirement range (such as within 50ms), significantly improving the self-healing capability and reliability of the SDH ring network in capacity convergence equipment deployment scenarios.

[0028] By using the above-described switching control method, this embodiment solves the problem in the prior art where the main control processor is unaware of the random mapping relationship within the board by obtaining the VC cross-correspondence information of the east-facing and west-facing boards. By performing the switching operation based on this information when the fiber optic communication connection is disconnected, it solves the technical problem of not being able to correctly switch the customer-side cross-section in capacity convergence scenarios. It also achieves accurate execution of SDH ring network multiplex section protection switching under complex networking conditions where the panel port capacity is greater than the backplane port capacity, ensuring that the service recovery time meets industry standards.

[0029] In one specific embodiment, a back-switching mechanism after fault recovery is provided. That is, when the optical fiber communication connection corresponding to the previously used board in the east-facing board and the west-facing board is restored, the multiplex section protection back-switching operation of this network element is performed according to the VC cross-correspondence information.

[0030] After the fiber optic fault is repaired, when the fiber optic communication connection corresponding to the previously used board (i.e., the eastbound or westbound board that was switched off when the fault occurred) is restored, the main control processor executes the multiplex section protection revert operation for this network element based on the acquired VC cross-connect information. This revert operation refers to switching the service from the currently used protection path (the backplane protection cross-connect of the board in the other direction) back to the original working path (the backplane working cross-connect of the board in the fault direction).

[0031] The purpose of this step is to restore services to their normal operating path after the fault is cleared, thereby releasing protection resources and restoring the network's original topology to facilitate handling potential future faults. In standard multiplex section protection protocols, the switchback operation typically requires waiting for a configurable Wait To Restore (WTR) period to confirm line stability before execution.

[0032] The specific implementation method is as follows: The main control processor continuously monitors the line status information reported by the eastbound and westbound boards (e.g., alarm signals obtained via the fast overhead bus or recovery indications in bytes K1 / K2) to determine that the fiber optic communication connection corresponding to the previously faulty board has been restored. After confirming stable recovery (e.g., waiting for the WTR timer to time out), the main control processor queries the locally stored VC cross-connect information to find the mapping relationship between the corresponding panel port and backplane port in the board in the recovery direction (e.g., the previously faulty eastbound board). Then, the main control processor controls the backplane cross-connect matrix to disconnect the backplane protection cross-connect between the customer-side board and the board in the other direction (westbound board), and re-establish the backplane working cross-connect between the customer-side board and the board in the recovery direction (eastbound board). After the switchback is completed, the main control processor updates the switching information of the transmission direction (e.g., bytes K1 / K2) to notify adjacent network elements that the recovery is complete.

[0033] In scenarios involving capacity convergence and random mapping, the switchback also faces the problem that "the main control processor doesn't know which backplane port the original working path corresponds to." This step utilizes the VC cross-correspondence information already acquired and stored in step A, enabling the switchback operation to accurately locate the backplane port corresponding to the panel port of the original faulty board, avoiding the inability to switch back due to lost mapping relationships. Furthermore, by reusing the VC cross-correspondence information from step A, this step ensures that the same mapping table is used for both the switchover and the switchback, avoiding erroneous switchbacks due to inconsistent information (such as switching to the wrong port or switching to an idle port).

[0034] Through the above steps, this embodiment, after the fiber optic connection is restored, can accurately switch services back from the protection path to the original working path using the pre-synchronized VC cross-correspondence information, achieving a complete protection switching closed loop (fault switching → fault recovery → back-switching). Compared with the prior art where back-switching cannot be executed correctly in capacity convergence scenarios, this method ensures the reliability and accuracy of the back-switching operation, enabling the network to automatically recover to its initial working state and prepare for the next fault protection. Simultaneously, since back-switching and switching share the same VC cross-correspondence information, information redundancy and synchronization overhead are reduced, improving the overall efficiency and maintainability of the system.

[0035] In one specific embodiment, the status of the optical fiber communication connection corresponding to either the east-facing board or the west-facing board is obtained from the respective board via a fast overhead bus.

[0036] In SDH ring network protection switching, the International Telecommunication Union (ITU) requires switching times to be within 50ms, thus necessitating extremely low transmission latency for status information. Therefore, the main control processor obtains the status of the fiber optic communication connections for each board from both the eastbound and westbound boards via the fast overhead bus. This status indicates whether the fiber optic connection of the currently used board is functioning correctly (e.g., whether there are signal losses, frame synchronization issues, or other faults).

[0037] The purpose of this step is to provide the main control processor with real-time, low-latency line status information so that it can respond quickly and initiate a switchover operation when the fiber optic connection is lost.

[0038] The specific implementation method is as follows: Within the network element, FPGAs or dedicated overhead processing chips are installed on the eastbound and westbound boards, respectively. These chips extract alarm indications (such as LOS, LOF, K1 / K2 bytes, etc.) from the receiving direction of the SDH optical line interface in real time and encode this status information. The network element has an independent high-speed overhead bus, a high-speed channel dedicated to transmitting SDH overhead bytes (including line status, K1 / K2 bytes, etc.), physically separated from conventional slow management buses (such as I2C, UART, Ethernet, etc.). The FPGAs on the eastbound and westbound boards send real-time status information directly to the main control processor via this high-speed overhead bus. The main control processor can obtain the latest line status within microseconds without software polling.

[0039] Through the steps described above, the main control processor in this embodiment can obtain the fiber optic connection status of the eastbound or westbound board with extremely low latency (microseconds). This allows the main control processor to detect the fault the instant the fiber optic cable is disconnected, significantly reducing the response time compared to traditional slow bus polling or interrupt-based reading methods. In SDH ring networks with strict switching time requirements, this reduction in latency provides more time margin for subsequent switching operations (such as querying VC cross-connection information and configuring the backplane cross-connect matrix), thereby ensuring that the overall switching time consistently meets the standard requirement of less than 50ms. Simultaneously, the dedicated nature of the fast overhead bus avoids conflicts with management messages, improving the system's real-time performance and reliability.

[0040] In one specific embodiment, a method for obtaining VC cross-correspondence information is given, namely, synchronizing the respective VC cross-correspondence information with the eastbound and westbound single boards through the inter-board communication protocol.

[0041] Specifically, the main control processor synchronizes its respective VC cross-correspondence information with the eastbound and westbound single boards via an inter-board communication protocol. This synchronization process includes the main control processor receiving the VC cross-correspondence information from the single boards and ensuring that this information remains consistent between the main control side and the single board side.

[0042] The purpose of this step is to establish an information synchronization channel between the main control processor and the eastbound and westbound single boards, enabling the main control processor to obtain accurate and timely cross-correspondences between the virtual containers of the front panel ports and backplane ports within the single board. Since the cross-mapping within a single board may be randomly established or dynamically changing in a capacity convergence scenario, the main control processor cannot derive this mapping relationship through local configuration or preset rules; therefore, it must obtain it through active reporting from the single board.

[0043] The specific implementation method is as follows: The network element internally has an inter-board communication bus (such as an Ethernet backplane bus, PCIe bus, HDLC link, or dedicated IBC channel). Inter-board communication protocol stacks (such as the IBC protocol) run on the eastbound and westbound boards respectively, and the corresponding protocol stack also runs on the main control processor. The synchronization process can be performed as follows: Active reporting: During initialization, the board encapsulates the VC cross-correlation information between its currently active front panel ports and back panel ports into a message and sends it to the main control processor via the inter-board communication protocol. Upon receiving the message, the main control processor stores it in its local database.

[0044] Change reporting: When the cross-connection relationship of the VC within the single board changes (e.g., due to service reconfiguration, single board reset, cross-connection reconnection after protection switching, etc.), the single board actively reports the updated information again to ensure that the information of the main control processor is always consistent with the actual state of the single board.

[0045] Heartbeat or verification mechanism: The main control processor can periodically send query requests to the single board, or the single board can periodically report information summaries to detect whether the information is synchronized and prevent information inconsistency caused by communication packet loss.

[0046] In traditional SDH equipment, the main interaction between the main control processor and individual boards primarily involves configuration commands, alarm status, and performance statistics. The VC cross-mapping relationships within each board are typically managed locally by the board and not retrieved by the main control processor, as the mapping is one-to-one or fixed in non-capacity convergence scenarios. This step addresses the specific scenario of capacity convergence by designing a synchronization protocol for VC cross-mapping information. Furthermore, it supports proactive reporting of changes in cross-mapping relationships within individual boards, ensuring the main control processor can respond to board status changes in real time and preventing failover errors due to outdated information. The synchronization operation can be performed independently of the failover process (e.g., during system idle time), without increasing communication overhead during failover. When failover occurs, the main control processor directly uses the synchronized information without temporarily querying the board, thus shortening failover time.

[0047] Through the above steps, the main control processor in this embodiment can establish a reliable and real-time VC cross-correspondence information synchronization channel with the eastbound and westbound single boards. Compared with the complete lack of this information by the main control processor in the prior art, this method allows the main control processor to directly utilize the accurate mapping relationship stored locally when a switchover occurs, avoiding switchover failure due to missing information. The dynamic update mechanism ensures the timeliness of the main control processor's information, and the switchover operation can still be executed correctly even in scenarios where the single board cross-configuration changes frequently. At the same time, since the synchronization process is decoupled from the switchover process, it does not increase the communication latency on the switchover path, which helps to meet the 50ms switchover time requirement.

[0048] Figure 3 This is a schematic diagram of the network elements in the SDH ring network provided in this embodiment. Figure 3 As shown, this network element is suitable for SDH ring networks with capacity convergence scenarios and can execute the switching control method described in the aforementioned method embodiments. This network element includes a main control board, an eastbound board, and a westbound board.

[0049] The functions and connections of each component are explained below: a. Main control board: The main control board is equipped with a main control processor. This main control processor is used to execute the switching control method described above, specifically including: obtaining the VC cross-correspondence information of the eastbound and westbound boards; when the fiber optic communication connection corresponding to the currently used board is disconnected, performing multiplex section protection switching operation according to the VC cross-correspondence information; optionally, it also performs back-switching operation, obtains line status through the fast overhead bus, and synchronizes information through the inter-board communication protocol, etc.

[0050] The main control board is also responsible for the configuration management, performance monitoring, and alarm handling of the entire network element. In this solution, the core improvement of the main control processor is that it no longer assumes a fixed one-to-one correspondence between the front panel ports and the back panel ports. Instead, it actively receives the VC cross-correspondence information reported by the single board and establishes a dynamic mapping table, thereby correctly performing switchover in capacity convergence scenarios.

[0051] b. East-facing and west-facing veneers: The eastbound and westbound boards are used to connect fiber optic lines in two directions within the SDH ring network, respectively. Each board is equipped with a processing unit (e.g., an embedded CPU, MCU, or dedicated control processor). This processing unit is used to synchronize local VC cross-correspondence information with the main control processor.

[0052] Specifically: Local maintenance of VC cross-connection information: The eastbound / westbound boards contain cross-connect matrix chips or logic responsible for establishing virtual container cross-connections between panel ports (line ports facing optical fibers) and backplane ports (connecting to the internal backplane of network elements and communicating with customer-side boards or other boards). Since the total capacity of the board's panel ports is greater than the total capacity of its backplane ports, this cross-connection relationship is established randomly or dynamically by the board based on service configuration. The board's processing unit manages the local cross-connection table, recording the backplane port and virtual container level corresponding to each panel port.

[0053] Synchronization mechanism with the main control processor: Processing units proactively report their local VC cross-mapping information to the main control processor via inter-board communication protocols (such as the IBC protocol). Reporting occurs during: board initialization and startup, when cross-mapping relationships change (e.g., due to service reconfiguration or protection switching), and when the main control processor actively queries the system. In this way, the main control processor can obtain accurate internal board mapping relationships in real time, providing a basis for switchover decisions.

[0054] Fault Detection and Reporting: The eastbound and westbound boards are also responsible for monitoring the status of their respective fiber optic lines (such as signal loss (LOS), frame synchronization failure (LOF), etc.) and notifying the main control processor of status changes in real time via the fast overhead bus to trigger the switchover process. This function can be jointly performed by the FPGA or processing unit on the board, but it does not affect the synchronization of VC cross-corresponding information.

[0055] c. Communication channels within the network element: To achieve the above functions, the network element is configured with the following communication channels: Inter-board communication bus: Used to transmit VC cross-connection information, configuration commands, alarms, and other management data. This bus can use an Ethernet backplane, PCIe, HDLC, or a dedicated IBC channel. The main control processor and the processing units of the eastbound / westbound boards exchange messages through this bus.

[0056] Fast overhead bus: Used for real-time transmission of time-sensitive information such as line status and K1 / K2 bytes. This bus is independent of the inter-board communication bus, ensuring low latency and high real-time performance.

[0057] Based on the aforementioned method embodiments, the typical workflow of this network element in ring network protection switching is as follows: Initialization Phase: After the network element powers on, the main control processor starts. The processing units of the eastbound and westbound boards complete local initialization and establish the initial VC cross-mapping. The processing units actively report their respective VC cross-mapping information to the main control processor through the inter-board communication protocol. The main control processor receives and stores this information.

[0058] During normal operation: The main control processor continuously monitors the fiber optic line status of the eastbound and westbound boards via the fast overhead bus. Simultaneously, if the VC cross-mapping within a board changes (e.g., due to service adjustments), the processing unit will report the updated information again to maintain information synchronization between the main control side and the board side.

[0059] Fault Switching Phase: When an eastbound board detects a fiber optic cable disconnection (e.g., a LOS alarm), its FPGA or processing unit sends interrupt and status information to the main control processor via the fast overhead bus. Based on the received fault direction indication, the main control processor queries its locally stored VC cross-connect information to locate the backplane port corresponding to the faulty panel port on the eastbound board. Then, the main control processor controls the backplane cross-connect matrix to switch the working cross-connect between the customer-side board and that backplane port to a backplane protection cross-connect between the customer-side board and the corresponding protection channel on the westbound board. After the switchover is complete, the main control processor updates the status of the relevant boards via the inter-board communication protocol and sends new K1 / K2 bytes to neighboring network elements.

[0060] Fault recovery and switchback phase: After the fiber optic cable is repaired, the eastbound board detects the line recovery and notifies the main control processor via the fast overhead bus. After the WTR timer expires, the main control processor queries the VC cross-connect information again and switches the customer-side board back from the protection cross-connect of the westbound board to the working cross-connect of the eastbound board, restoring the original service path.

[0061] Compared with existing SDH network elements, the improvements of this network element are as follows: The VC cross-correspondence information synchronization mechanism between the main control processor and the single board: In traditional network elements, the main control processor does not care about the front-panel-back-panel mapping inside the single board, assuming that the mapping is fixed or one-to-one. This network element introduces an active reporting and dynamic update mechanism, enabling the main control processor to accurately grasp the random mapping relationship, thereby correctly performing switchover in capacity convergence scenarios.

[0062] Functional expansion of the single-board processing unit: Existing single-board processing units typically only handle local configuration and alarm reporting, without actively reporting VC cross-connect information. The eastbound / westbound single-board processing unit in this network element now includes a function for synchronous local cross-connect mapping, providing decision-making support for the master controller.

[0063] Overall architecture coordination: Through the coordinated work of the main control processor, the processing units of the eastbound / westbound single boards and two communication buses (inter-board communication bus + fast overhead bus), this network element realizes a complete protection switching closed loop in the capacity convergence scenario, including the entire process of fault detection, switching execution, and back-off recovery.

[0064] The SDH ring network using this network element can still achieve the standard requirement of 50ms ring network protection switching even under convergent networking conditions where the capacity of the front panel ports is greater than that of the back panel ports, significantly improving the flexibility and reliability of network deployment. Furthermore, since the synchronization of VC cross-connect information is independent of the switching path, it does not increase switching latency and supports dynamic updates. This allows the network element to adapt to frequent changes in service configurations, demonstrating strong practicality and commercial value.

[0065] In one specific embodiment, the east-facing and west-facing boards are further defined as follows: each board is equipped with an FPGA (Field Programmable Gate Array) to trigger an interrupt signal when the status of the fiber optic communication connection corresponding to the board changes, so that the main control processor can perform a switchover operation.

[0066] Figure 4 for Figure 3 The diagram shows the interaction between the FPGA and the main control processor in the east-west direction board of the network element. (See diagram for example.) Figure 3As shown, the FPGA works in collaboration with the processing unit (such as the CPU) on the single board, but performs different functions: the processing unit is responsible for management tasks such as synchronizing the corresponding information of VC cross-connection, while the FPGA is responsible for tasks with extremely high real-time requirements such as real-time line status monitoring, K1 / K2 byte extraction and detection, and interrupt triggering.

[0067] The specific functions and implementation methods of the FPGA include: a. Monitoring the status of fiber optic communication connections: The FPGAs on the east-facing and west-facing boards receive SDH frame signals in real time via optical line interfaces. The FPGAs integrate SDH frame synchronization and overhead processing modules, capable of extracting the following status information from the received optical signals: Physical layer alarms, such as Lost Signal (LOS), Lost Frame (LOF), and Alarm Indication Signal (AIS), directly reflect whether the fiber optic communication connection is normal.

[0068] Switching signaling in the overhead bytes: especially bytes K1 and K2. Bytes K1 / K2 are located in the section overhead of the SDH frame and are used to transmit Automatic Protection Switching (APS) protocol information between adjacent network elements, including switching request type, fault direction, bridging status, etc.

[0069] When a fiber optic communication connection is lost, the receiver will detect a LOS or LOF, and the contents of bytes K1 / K2 will also change (for example, a faulty neighbor node will send a specific failover request code). The FPGA needs to capture these changes in real time.

[0070] b. Three-frame detection mechanism: To avoid incorrect switching triggers due to single-frame errors or transient interference, the FPGA has an internal K1 / K2 byte change detection module. This module operates as follows: The FPGA continuously receives the K1 and K2 bytes in each SDH frame and compares the K1 / K2 content of the current frame with the historically saved K1 / K2 content.

[0071] The FPGA only considers a valid switchover request or line status change detected when the contents of the K1 / K2 bytes in three consecutive frames are different from the historical contents. This three-frame detection mechanism is a jitter prevention measure specified in the ITU-T G.841 standard, which can effectively filter out occasional transmission errors.

[0072] If three consecutive frames pass the detection, the FPGA records the currently received K1 / K2 bytes as valid switching information.

[0073] c. Triggering of interrupt signals: The FPGA also has an interrupt control module. After the detection and confirmation status changes for three consecutive frames, the interrupt control module performs the following operations: Triggering the main processor's interrupt pin: The FPGA sends an interrupt pulse or level change to the main processor via a hardware interrupt line (such as a dedicated IRQ signal line). This interrupt signal has the highest priority and can immediately interrupt the main processor's current task, causing it to enter the interrupt service routine.

[0074] Simultaneously, the FPGA sends the valid K1 / K2 bytes (and optional line status information) to the main control processor via the fast overhead bus. This allows the main control processor to directly read the switching information from a designated register or buffer on the fast overhead bus after responding to an interrupt, eliminating the need to query the board via the slow bus and saving time.

[0075] Update saved history: The FPGA saves the current K1 / K2 byte content as a new historical value for comparison in subsequent frames.

[0076] d. Collaboration with the main control processor: Upon receiving an interrupt signal, the main control processor immediately reads the contents of bytes K1 / K2 in the fast overhead bus, combines this with the synchronized VC cross-correspondence information, and performs a multiplex section protection switching operation (such as switching the customer-side board from the fault direction to the protection direction). After the switching is completed, the main control processor may generate new bytes K1 / K2 (used to notify adjacent network elements of the switching status) and send them to the FPGA of the eastbound / westbound board via the fast overhead bus. The FPGA then inserts these bytes into the SDH frame overhead in the transmission direction.

[0077] Through the dedicated FPGA design described above, this network element can notify the main control processor within microseconds when the fiber optic connection is broken or a switching request is received from an adjacent network element, ensuring an extremely short switching response time. Utilizing three consecutive frames of detection avoids false triggering and improves switching reliability. Parallel transmission of interrupts and data reduces the software overhead and bus wait time of the main control processor, ensuring a smooth overall switching time (5-10ms). Combined with the synchronization mechanism for VC cross-correspondence information, complete, efficient, and reliable ring network protection switching is achieved in capacity convergence scenarios.

[0078] This embodiment provides an SDH ring network protection switching system. The system comprises multiple network elements connected end-to-end to form a ring topology. Typically, the first, second, and third network elements are used as examples. The first and third network elements are fault-adjacent nodes, employing the network element structures described above; the second network element is a pass-through node. This system can complete ring network protection switching and recovery operations even in convergence scenarios where the total capacity of the front panel ports exceeds the total capacity of the back panel ports.

[0079] For ease of understanding, the following description uses the two-fiber bidirectional multiplex section protection ring as an example, and also refers to... Figure 5 The structure and specific implementation methods are shown.

[0080] In this system, the service crossover of each network element is logically divided into three segments: The first crossover: Intra-board crossover within the customer-side board. The customer-side board maps service signals from external devices (such as instruments) onto the backplane channel.

[0081] The second crossover: an intra-board crossover within either the east-facing or west-facing single board. This crossover is responsible for establishing connections between the backplane channels and the front panel ports (i.e., optical line ports). Due to capacity convergence (the total capacity of the front panel ports is greater than the total capacity of the backplane ports), the mapping relationship of this crossover is randomly established and cannot be predicted by the main control processor.

[0082] The third crossover: Backplane crossover between the customer-side board and the east / west board. This crossover is located on the backplane and is directly controlled by the main control processor. It is used to connect the customer-side board to the backplane port of the east or west board.

[0083] The core operation of ring network protection switching is to switch the third cross-connect: when a fiber optic cable fails in one direction, the main control processor switches the customer-side board from working cross-connect with the backplane of the board in the faulty direction to working cross-connect with the backplane of the board in the other direction.

[0084] exist Figure 5 The network element connection relationships in the system shown are as follows: the eastbound board of the first network element (network element 1) is connected to the westbound board of the second network element (network element 2) via optical fiber; the eastbound board of network element 2 is connected to the westbound board of the third network element (network element 3) via optical fiber; the eastbound board of network element 3 is connected to the westbound board of network element 1 via optical fiber, forming a closed loop. Each network element is equipped with a customer-side board for accessing services (for example, instrument 1 connects to the customer side of network element 1, and instrument 2 connects to the customer side of network element 3).

[0085] Initial working path: Under normal conditions, the service flows from Instrument 1 through the customer-side board of Network Element 1 → First cross-connect → Backplane → Third cross-connect (connected to the backplane port of the east-facing board) → Second cross-connect (internal mapping of the east-facing board to the panel port) → East-facing fiber optic cable → West-facing board panel port of Network Element 2 → Second cross-connect (internal mapping of the west-facing board to the backplane port) → Third cross-connect (through connection to the backplane port of the east-facing board) → Second cross-connect (internal mapping of the east-facing board to the panel port) → East-facing fiber optic cable → West-facing board panel port of Network Element 3 → Second cross-connect → Third cross-connect → Customer-side board → Instrument 2. The protection path is reserved along the other direction of the ring (Network Element 1 → Network Element 3 → Network Element 2).

[0086] Capacity Convergence Configuration: Assuming the total capacity of the eastbound single-board panel ports of network element 1 is greater than the total capacity of the backplane ports, the mapping relationship of the second cross section within it is randomly established. The main control processor of network element 1 has pre-obtained the VC cross section corresponding information (i.e., the mapping table of the second cross section) of the eastbound single board (and the westbound single board) through the inter-board communication protocol. The same applies to network element 3. Network element 2 is a pass-through node, and its main control processor has also synchronized the VC cross section information of the eastbound and westbound single boards.

[0087] The following explains the occurrence of the fault and the switchover operation: Fault scenario: The fiber optic line between network element 1 and network element 2 is disconnected (e.g., the fiber is broken). At this time, the eastbound board of network element 1 detects a loss of signal (LOS), and the westbound board of network element 2 also detects a LOS.

[0088] Operation of Network Element 1 (Fault Adjacent Node): The FPGA on the eastbound board of network element 1 detects no signal in the optical line receiving direction, and at the same time, the K1 / K2 bytes (from the peer network element 2) also show an anomaly. After confirming the state change according to the three-frame detection mechanism, the FPGA records the currently valid switching information (e.g., the K1 / K2 bytes indicate "signal failure" and the fault direction is eastbound), and pushes the switching information to the main control processor through the fast overhead bus, while triggering an interrupt in the main control processor.

[0089] The main control processor of network element 1 responds to the interrupt, reads the switching information, and obtains that the fault direction is eastward. The main control processor queries the locally stored VC cross-connection information (i.e., the second segment of the cross-connection mapping table for the eastward board) to determine the backplane port corresponding to the currently used eastward panel port. Then, the main control processor performs multiplex section protection switching, that is, switches the third segment cross-connection: the connection between the customer-side board and the eastward board backplane working cross-connection is switched to the connection between the customer-side board and the westward board backplane protection cross-connection.

[0090] After the switchover is completed, the main control processor of network element 1 generates new K1 / K2 bytes (e.g., indicating "bridging completed") according to the current ring network protection status (westward switchover status), and sends them to the westward board through the fast overhead bus. The FPGA of the westward board then inserts them into the optical line in the transmission direction to notify the adjacent network elements (network element 3 and network element 2).

[0091] Operation of network element 3 (another faulty adjacent node): Element 3 is not a direct fiber break point, but its westbound board will receive a switchover request forwarded from Element 2 (K1 / K2 byte change). The FPGA of Element 3 detects three consecutive frames of K1 / K2 byte change, triggers an interrupt, and the main control processor reads the switchover information, realizing that the fault occurred at a remote end (between Element 1 and Element 2), and a switchover needs to be performed.

[0092] The main control processor of network element 3 queries the locally stored VC cross-connect information to determine the mapping relationship between the panel ports and backplane ports of the westward board. Then, it switches the third cross-connect: the working cross-connect between the customer-side board and the westward board is switched to the protection cross-connect between the customer-side board and the eastward board. The ring network protection status of network element 3 changes to the eastward switching status.

[0093] Operations of Network Element 2 (Through-through Node): Network element 2 is not a fault-adjacent node; its eastbound and westbound boards receive K1 / K2 bytes from network element 3 and network element 1, respectively. The FPGA triggers an interrupt upon detecting the change in K1 / K2, and the main control processor reads the switchover information.

[0094] The main control processor of network element 2 determines that it is in a pass-through state based on the received switching information, and there is no need to switch the third cross-connect of the customer-side board (because there is no service uploading or downloading on the customer side). Its core operation is to connect the backplane protection cross-connect of the eastbound board with the backplane protection cross-connect of the westbound board. Specifically, the main control processor controls the backplane cross-connect matrix to directly connect the backplane ports used for protection channels on the eastbound board with the backplane ports used for protection channels on the westbound board. This allows protection services from network element 3 to be forwarded to network element 1 via network element 2, and vice versa. This operation essentially establishes a pass-through connection on the protection path.

[0095] The service path after the switchover is as follows: The service starts from Instrument 1, passes through the customer side of Network Element 1 → the third protection cross-connect of Network Element 1 (connected to the west-facing board) → the second cross-connect of the west-facing board of Network Element 1 → west-facing fiber optic cable → the east-facing board of Network Element 3 → the second cross-connect of Network Element 3 → the third protection cross-connect of Network Element 3 (connected to the customer side) → Instrument 2. The protection cross-connect of Network Element 2 is in a connected state, but the service does not actually pass through Network Element 2 (because the fiber between Network Element 1 and Network Element 2 is broken, the service detours in another direction). However, the through-connection provides a channel for possible bidirectional services.

[0096] The following explains the fault recovery and switchback operation: After the fiber optic fault is repaired, the eastbound board of network element 1 detects that the line has been restored (LOS disappears), and the K1 / K2 bytes return to the normal idle code. The FPGA detects the status change (three consecutive frames), triggers an interrupt, and the main control processor learns that the fault has been restored.

[0097] The main control processor of network element 1 starts the WTR (Wait for Recovery) timer. After waiting for a period of time to confirm that the line is stable, it performs a back-switch operation: switching the backplane protection cross-connection of the customer-side board and the west-facing board back to the working cross-connection of the east-facing board. That is, the third cross-connection is restored to its initial working connection. After the back-switch is completed, network element 1 updates the K1 / K2 bytes in the transmission direction and notifies the adjacent network elements.

[0098] Network element 3 also performs a back-switching operation, switching the third cross section from the protection side back to the working side.

[0099] As a pass-through node, after receiving the recovery instruction, network element 2 needs to disconnect the previously connected east-facing backplane protection cross and west-facing backplane protection cross, release the protection resources, and restore the network to its initial idle state.

[0100] Compared to existing systems: In capacity convergence scenarios, existing SDH ring network protection systems often fail to switch over to the third cross-connect segment correctly because the main control processor of adjacent fault nodes is unaware of the mapping relationship of the second cross-connect segment within the board. This results in a switchover failure. This system, by pre-synchronizing the VC cross-connect correspondence information, enables the main control processor to accurately determine the mapping of the second cross-connect segment, thus successfully completing the switchover of the third cross-connect segment. Existing through-nodes typically only connect the protection cross-connect segment during switchover, but may lack a clear disconnection mechanism during back-off, preventing the release of protection resources. This system configures both connection and disconnection operations at through-nodes, achieving complete lifecycle management of protection resources.

[0101] In a typical three-network-element scenario, the measured switching time for the two-fiber bidirectional multiplex section protection is 5-10ms, far exceeding the ITU-T requirement of 50ms, and it still meets the standard when the number of network elements increases. By using FPGA hardware to detect three consecutive frames of K1 / K2 changes, fast overhead bus transmission, and the main control processor combining VC cross-connect information to execute the third-stage cross-connect switching, highly reliable and low-latency ring network self-healing is achieved. The coordinated connection / disconnection operations of through-nodes and the switching / return-back of faulty adjacent nodes ensure the correctness of the system throughout the fault and recovery process, fully adapting to the complex networking requirements of capacity convergence scenarios.

[0102] In addition, this application also provides a storage medium storing a computer program, wherein the computer program is configured to execute the method described above when running.

[0103] This application also provides an electronic device including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the methods described above.

[0104] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A switching control method in an SDH ring network, characterized in that, A main control processor applied to network elements in an SDH ring network, wherein the network element includes an eastbound board and a westbound board, and the total capacity of the front panel ports of the eastbound board and the westbound board is greater than the total capacity of their respective backplane ports; the method includes: Obtain the virtual container VC cross-correspondence information of the east-facing single board and the west-facing single board. The VC cross-correspondence information indicates the VC cross-correspondence relationship between the internal panel port and the back panel port of this single board. When the optical fiber communication connection corresponding to the currently used board in the east-facing board and the west-facing board is disconnected, the multiplex section protection switching operation of this network element is performed according to the VC cross-correspondence information.

2. The method according to claim 1, characterized in that, The method further includes: Once the fiber optic communication connection corresponding to the previously used boards in the east-facing and west-facing boards is restored, the multiplex section protection reswitching operation of this network element is performed according to the VC cross-connection information.

3. The method according to claim 1 or 2, characterized in that: The status of the fiber optic communication connection corresponding to either the east-facing board or the west-facing board is obtained from the respective board via a fast overhead bus transmission.

4. The method according to claim 1 or 2, characterized in that: The VC cross-correspondence information is synchronized with the eastbound and westbound single boards through the inter-board communication protocol.

5. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 4 when it is run.

6. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 4.

7. A network element in an SDH ring network, characterized in that, include: A main control board, on which a main control processor is provided, for executing the method as described in any one of claims 1 to 4; The east-facing single board is equipped with a processing unit for synchronizing local VC cross-correspondence information with the main control processor. The west-facing single board is equipped with a processing unit for synchronizing local VC cross-correspondence information with the main control processor.

8. The network element according to claim 7, characterized in that: The main control processor synchronizes its respective VC cross-correspondence information with the eastbound single board and the westbound single board respectively through the inter-board communication protocol.

9. The network element according to claim 7 or 8, characterized in that: The east-facing and west-facing single boards are equipped with FPGAs, which are used to trigger an interrupt signal when the status of the optical fiber communication connection corresponding to the single board changes, so that the main control processor can perform a switchover operation.

10. An SDH ring network protection switching system, characterized in that, include: The first network element, the second network element, and the third network element are connected end to end in sequence to form a ring topology; The first network element and the third network element are fault-adjacent nodes, and each adopts the structure of the network element as described in any one of claims 7 to 9; The second network element is a pass-through node, configured such that when the currently used optical fiber communication connection between the first network element and the second network element is disconnected, the backplane protection cross-connection of the east-facing single board of this network element is connected to the backplane protection cross-connection of the west-facing single board.

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