Three-dimensional multi-core particle optoelectronic integrated structure based on silicon photoelectric conversion substrate interconnection and preparation method thereof
By growing micro-metal bumps in situ on a silicon photoelectric conversion substrate to achieve vertical electrical interconnection between the functional chip and the silicon photoelectric conversion substrate, the problems of complex optical signal coupling structure and long electrical interconnection path in the existing CPO scheme are solved, realizing high-density, low-latency and high-reliability three-dimensional optoelectronic integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 上海曜感科技有限公司
- Filing Date
- 2026-02-09
- Publication Date
- 2026-06-16
AI Technical Summary
Existing CPO solutions have complex optical signal coupling structures, long electrical interconnect paths, low integration density, and high-temperature processes may damage heterogeneous optoelectronic devices.
In-situ self-grown micro-metal bumps are used to achieve vertical electrical interconnection between functional cores and silicon photoelectric conversion substrates. A three-dimensional interconnect framework is constructed through interconnection transfer cores, and bonding and metal growth are carried out using low-temperature processes.
It achieves ultra-high density interconnection, shortens the electrical signal transmission path, reduces transmission delay and parasitic effects, improves integration reliability and yield, and has good process compatibility.
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Figure CN122228012A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor optoelectronic integration and advanced packaging technology, specifically to a three-dimensional heterogeneous integrated structure for optoelectronic co-packaging and its manufacturing method, particularly a scheme that utilizes a silicon optoelectronic conversion substrate with a complete internal electrical interconnect network as a system-level transfer platform and achieves ultra-high density, low temperature, and high precision three-dimensional interconnection through a "bonding-then-growth" process. Background Technology
[0002] With the explosive growth in computing bandwidth demands for AI training and inference, tight integration (CPO) of high-performance computing units such as GPUs (Graphics Processing Units) and optical interconnect engines has become an inevitable trend. Existing CPO solutions, especially those involving 2.5D integration, typically face the following challenges: 1) When optical signals are coupled from external optical fibers to the PIC (Photonic Integrated Circuit) within the package, additional, bulky silicon carriers or interposers are often required to fix and calibrate the fiber array, increasing packaging complexity and vertical space occupation; 2) System-level electrical inputs / outputs (I / O) usually require separate interposers or complex redistribution layers to achieve fan-out, increasing interconnect length and design complexity; 3) There is still room for optimization in the integration methods of EIC (Electrical Integrated Circuit), DRV (Driving Vehicle), TIA (Transceiver Array), and PIC to pursue lower signal latency and higher integration density.
[0003] Therefore, there is an urgent need for a CPO solution that can simplify the optical coupling structure, shorten the electrical interconnect path, and achieve higher integration density. Summary of the Invention
[0004] This invention aims to overcome the shortcomings of existing technologies and provide a high-density, high-performance, and process-compatible three-dimensional multi-core optoelectronic integrated structure and its fabrication method. Its core lies in using "in-situ self-grown micro-metal bumps" to achieve vertical electrical interconnection between functional cores and silicon optoelectronic conversion substrates, and introducing "interconnection transition cores" as intermediaries to construct a three-dimensional interconnect framework.
[0005] To achieve the above objectives, the first aspect of the present invention provides a method for fabricating a three-dimensional multi-core optoelectronic integrated structure based on silicon optoelectronic conversion substrate interconnection, comprising the steps of: S1: Provides a silicon photoelectric conversion substrate, which integrates a silicon optical waveguide. A first interconnect pad and a second interconnect pad are formed on its upper surface, and a bottom interconnect pad is formed on its lower surface. It has several through-silicon vias that electrically connect the first interconnect pad and the bottom interconnect pad, and electrically connect the second interconnect pad and the bottom interconnect pad. It also has horizontal interconnect lines that electrically interconnect the first interconnect pad and the second interconnect pad. S2: Provide functional chips that include at least: electrical functional chips, silicon photonic chips and laser chips; S3: The electrical functional chip, the silicon photonic chip, and the laser chip are aligned and bonded to the upper surface of the silicon photoelectric conversion substrate with their active surfaces facing down through the bonding layer, so that a gap is formed between each electrode and the corresponding pad. S4: Perform in-situ self-growing interconnect process to selectively grow metal in the gap to form micro-metal bumps and achieve electrical connection.
[0006] Further, step S3 includes: A non-conductive bonding layer is formed on the upper surface of the silicon photoelectric conversion substrate and / or the active surface of the functional chip. The functional chip is aligned and pressed onto the upper surface of the silicon photoelectric conversion substrate with its active surface facing down through the bonding layer, and the bonding layer is cured at a temperature below 250°C to form a mechanical bond; wherein the electrode of the functional chip is separated from the corresponding interconnect pad of the silicon photoelectric conversion substrate by the bonding layer.
[0007] Furthermore, in step S3, an interconnecting adapter chip is also bonded to the gap region on the upper surface of the silicon photoelectric conversion substrate.
[0008] Furthermore, in step S3, the material of the bonding layer is aluminum nitride or high-density silicon oxide, and the method of forming it is spin-coating a sol-gel precursor and then heat-curing it.
[0009] Further, in step S4, the in-situ self-grown metal interconnect process is chemical plating or electroplating, using a mask or the bonding layer as an insulating mask to achieve selective growth of metal in the gap. The self-grown metals include copper, aluminum, tungsten, titanium, cobalt, molybdenum, tin and their alloys, and the process is carried out at a solution temperature of 40°C to 80°C.
[0010] Further, in step S4, the interconnect adapter chip is bonded to the silicon photoelectric conversion substrate together with the functional chip through the bonding layer with its lower surface facing down; the metal is also selectively grown in the gap between the bottom interconnect pad of the interconnect adapter chip and the corresponding interconnect pad of the silicon photoelectric conversion substrate to form micro metal bumps.
[0011] Furthermore, following step S4, the following step is also included: The back side of the bonded functional chip is thinned and polished to make it coplanar with other structures on the upper surface of the silicon photoelectric conversion substrate; Fabricate system-level interconnect structures containing redistribution layers on coplanar surfaces.
[0012] Furthermore, following step S4, the following step is also included: The back side of the bonded silicon photoelectric conversion substrate is thinned and polished; Fabricate a system-level interconnect structure containing a rewiring layer on the surface.
[0013] Furthermore, the method for forming the silicon photoelectric conversion substrate includes: It provides PIC cores, through-silicon via cores and carriers. The PIC cores are SOI substrates and the through-silicon via cores include through-silicon via arrays. The electrode pads of the PIC core and the through-silicon via core are bonded to the substrate, and the surfaces and gaps of the PIC core and the through-silicon via core are filled with insulating medium. The electrode pads of the exposed PIC chip and through-silicon via chip are unbonded and used as the first interconnect pad and the second interconnect pad.
[0014] Furthermore, it also includes: The PIC chip includes a silicon optoelectronics adapter board, which includes a silicon optical waveguide, a silicon-based optical modulator, and a grating coupler.
[0015] Furthermore, the method for forming the silicon photoelectric conversion substrate includes: providing an SOI silicon wafer; forming a PIC chip therein, including a silicon photoelectric adapter board, comprising a silicon optical waveguide, a silicon-based optical modulator, and a grating coupler; and forming through-silicon vias in non-transparent areas.
[0016] A three-dimensional multi-core optoelectronic integrated structure obtained according to any one of the above-described preparation methods, comprising: A silicon photoelectric conversion substrate integrates a silicon waveguide, with a first interconnect pad and a second interconnect pad formed on its upper surface and a bottom interconnect pad formed on its lower surface. It has several through-silicon vias that electrically connect the first interconnect pad and the bottom interconnect pad, and electrically connect the second interconnect pad and the bottom interconnect pad. It also has horizontal interconnect lines that electrically interconnect the first interconnect pad and the second interconnect pad. The electrical functional chip and the silicon photonic chip are directly bonded to the first region on the upper surface of the silicon photoelectric conversion substrate through a bonding layer with their active surfaces facing down. The laser chip is directly bonded to the second region on the upper surface of the silicon photoelectric conversion substrate with its active surface facing down via a bonding layer; In this process, in-situ self-grown micro-metal bumps are formed between the active surface electrodes of the electrical functional chip and the silicon photonic chip and the corresponding first interconnect pads of the silicon photoelectric conversion substrate, and between the active surface electrodes of the laser chip and the corresponding second interconnect pads of the silicon photoelectric conversion substrate, to achieve vertical electrical interconnection.
[0017] Furthermore, the bonding layer is aluminum nitride or high-density silicon oxide.
[0018] Furthermore, the silicon photoelectric conversion substrate is an SOI silicon wafer.
[0019] Furthermore, the laser chip is a vertical cavity surface-emitting laser chip, and its output port is optically coupled to the silicon waveguide through an optical coupling structure on the silicon photoelectric conversion substrate.
[0020] Furthermore, the vertical cavity surface-emitting laser chip is inverted bonded, with its front annular electrode connected through the micro-metal bump, and its back electrode interconnected with the silicon photoelectric conversion substrate through a through-silicon via.
[0021] Furthermore, it also includes a silicon beam deflector bonded to the surface of the silicon photoelectric conversion substrate; the laser chip is a horizontal cavity surface-emitting laser chip, and its output port is deflected by the beam deflector and coupled to the silicon optical waveguide.
[0022] Furthermore, the silicon photonics core integrates a photodetector core.
[0023] Furthermore, the gaps between the functional cores, the gaps between the functional cores and the silicon photoelectric conversion substrate, and the surface of the functional cores are filled with an insulating dielectric layer, the material of which is aluminum nitride.
[0024] The beneficial effects of this invention are as follows: 1. System-level integration with extremely short paths: The silicon photoelectric conversion substrate integrates TSVs and horizontal interconnects to become a system adapter board, enabling high-speed electrical signals to be transmitted from the functional chip to the system I / O within the substrate via the shortest path, greatly reducing transmission delay and parasitic effects.
[0025] 2. Revolutionary improvement in interconnect density: The micro-metal bumps formed by the "bonding before growth" process have their size defined by the thickness of the bonding layer (submicron level), which can achieve 1-5μm pitch interconnects that are unattainable by traditional processes, meeting the demand for ultra-high I / O density in future Exascale computing.
[0026] 3. Low temperature throughout the process to ensure reliability: The core bonding and metal growth processes are all completed below 250°C, which completely avoids thermal damage to heterogeneous optoelectronic devices caused by high temperature, and significantly improves the reliability and yield of integration.
[0027] 4. Excellent optoelectronic compatibility: The non-conductive bonding layer naturally isolates the optical path area from the electrical interconnection area, and the position of the bumps grown in situ is precisely controllable, effectively eliminating the interference of the metal structure on the light field and realizing optoelectronic co-design.
[0028] 5. Flexible and scalable process: This method is insensitive to differences in chip thickness and can integrate multiple heterogeneous chips at once. The process is compatible with existing CMOS and silicon photonics production lines, supports wafer-level mass production, and lays the foundation for more complex SoP (system-on-chip optoelectronics). Attached Figure Description
[0029] Figure 1 This is a flowchart of the fabrication method of the three-dimensional multi-core optoelectronic integrated structure based on silicon optoelectronic conversion substrate interconnection of the present invention; Figure 2 This is a cross-sectional schematic diagram of the three-dimensional multi-core optoelectronic integrated structure based on silicon optoelectronic conversion substrate interconnection of the present invention; Figure 3 This is a cross-sectional schematic diagram of the three-dimensional multi-core optoelectronic integrated structure based on silicon optoelectronic conversion substrate interconnection of the present invention.
[0030] Explanation of the labels in the diagram: 10-Silicon photoelectric conversion substrate; 105-Through silicon via; 13-First interconnect pad; 14-Second interconnect pad; 15-Bottom interconnect pad; 16-Horizontal interconnect line; 19-Bonding layer; 20-Electrically functional chip; 30-Laser chip; 40-Silicon photoelectric chip; 50-Silicon-based beam deflector; 60-Metal microbump. Detailed Implementation
[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention. Obviously, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
[0033] This invention also provides a method for fabricating a three-dimensional multi-core optoelectronic integrated structure, see attached figure. Figure 1 The preparation method is illustrated with a flowchart.
[0034] Step S1: Provide a silicon photoelectric conversion substrate 10, which integrates a silicon optical waveguide. A first interconnect pad 13 and a second interconnect pad 14 are formed on its upper surface, and a bottom interconnect pad 15 is formed on its lower surface. The substrate has a plurality of through-silicon vias 105 that electrically connect the first interconnect pad 13 and the bottom interconnect pad 15, and electrically connect the second interconnect pad 14 and the bottom interconnect pad 15. The substrate also has horizontal interconnect lines 16 that electrically interconnect the first interconnect pad 13 and the second interconnect pad 14.
[0035] Specifically, an SOI silicon wafer is provided as a silicon photoelectric conversion substrate 10. A silicon photoelectric adapter layer is defined and formed in the top silicon layer of the SOI silicon wafer, and silicon optical waveguides, silicon-based optical modulators, and grating couplers are etched therein. All photonic devices, such as silicon optical waveguides, mirrors, and gratings, are fabricated on the wafer; through-silicon vias are formed in the non-transparent areas.
[0036] On the silicon optoelectronics interposer, a 1 μm thick layer of aluminum nitride is deposited as an interlayer dielectric using plasma-enhanced PECVD (chemical vapor deposition). Vias leading to the modulator electrodes and predetermined interconnect nodes are then photolithographically etched and etched. Subsequently, a titanium / copper seed layer is sputtered using PVD (physical vapor deposition), and the vias are filled using electroplating to form TSVs (Through Silicon Vias 105), thus forming a redistribution layer RDL with a first copper horizontal interconnect line 16 approximately 1 μm thick. This interconnect layer is used to directly electrically connect the subsequently formed upper surface pads located in different regions (e.g., connecting the EIC region of the electrical chip, the silicon photonics region, and the laser driver region), enabling ultra-short-distance, high-speed electrical signal communication between chips.
[0037] The aluminum nitride passivation layer is deposited, and pad windows are created through photolithography and etching. A PVD sputtering adhesion layer and a copper seed layer are then sequentially deposited, followed by copper electroplating to a thickness of 2 μm. Planarization is then performed using CMP (Chemical Mechanical Polishing) to form patterned upper surface first interconnect pads 13 and upper surface second interconnect pads 14. On the lower surface of the wafer, an array of bottom interconnect pads 15 is formed using a similar process; these can be subsequently ball-mounted as system I / O.
[0038] Step S2: Provide functional chips including at least: EIC (Electrical Functional Chip 20), silicon photonic chip 40 and laser chip 30.
[0039] In this embodiment, the silicon photonics chip 40 integrates a Ge germanium (advanced packaging and chiplet) detector array, and the electrical functional chip 20 integrates a master control chip. In this embodiment, the laser chip 30 is a horizontal cavity surface-emitting laser (VCSEL) chip 30, such as an In / GaAs horizontal laser, and also includes a silicon-based beam deflector 50. Specifically, EIC wafers, silicon photonics chip wafers, and horizontal laser wafers are fabricated on separate production lines. The EIC, silicon photonics chip, and VCSEL wafers are thinned to expose the back electrode on the back side, and then diced from the wafers to obtain individual electrical functional chips 20, silicon photonics chip 40, and horizontal laser chips 30. The silicon photonics chip 40 also integrates a photodetector chip.
[0040] Step S3: Align and bond the electrical functional chip 20, silicon photonic chip 40 and laser chip 30 with their active surfaces facing down to the upper surface of the silicon photoelectric conversion substrate 1 via the bonding layer 19, so that a gap is formed between each electrode and the corresponding pad.
[0041] Specifically, an AlN (aluminum nitride) sol-gel precursor is uniformly coated onto the entire surface of the silicon photoelectric conversion substrate 10 wafer and / or the EIC core, silicon photoelectric core, and laser core 30 using a spin-coating process. After pre-baking on a hot plate (150°C, 2 minutes), a bonding layer 19 with a thickness of approximately 800 nm is formed. In one embodiment, the bonding layer may surround the electrode pads to be interconnected.
[0042] Using a high-precision flip-chip bonding machine, silicon photonics core 40, EIC core 20, and horizontal laser core 30 are sequentially picked up and transferred to predetermined positions on the silicon photoelectric conversion substrate 10 wafer. In the bonding machine, a certain pressure and appropriate temperature are applied to the cores for bonding. The functional cores are aligned and pressed onto the upper surface of the silicon photoelectric conversion substrate 10 with their active surfaces facing down through the bonding layer 19. The bonding layer 19 is then cured at a temperature below 250°C to form a mechanical bond. The electrodes of the functional cores are separated from their corresponding interconnect pads on the silicon photoelectric conversion substrate 1 by the bonding layer, thereby forming interconnected gaps around the electrode pads to be interconnected.
[0043] Step S4: Perform in-situ self-grown interconnect process, selectively grow metal in the gap to form micro metal bumps, and realize electrical connection.
[0044] Specifically, the electrode pads of the functional chip and the electrode pads of the silicon photoelectric conversion substrate 1 typically have exposed copper or gold on their surfaces. These metals are catalytically active for electroless copper plating. On the catalytically active surfaces, copper ions in the solution are reduced to metallic copper and deposited. Deposition begins on the upper and lower electrode surfaces and grows into the gap. Due to the narrow gap, solution exchange is limited, but metal ions can be continuously supplied through diffusion. After approximately 30-60 minutes, the copper grown on the upper and lower electrode surfaces meets and merges at the center of the gap, forming a solid, completely gap-filling metal microbump. This process is performed at low temperatures, between 40°C and 80°C, for example, 60°C, with minimal thermal impact on the device. The grown bump perfectly conforms to the gap shape, achieving ultra-high density truly conformal interconnects and exhibiting strong adaptability to minute height differences after bonding.
[0045] Self-grown metals include any one of copper, aluminum, tungsten, titanium, cobalt, molybdenum, tin, and their alloys.
[0046] Optional features also include: back-side processing and system interconnect.
[0047] In one embodiment, the back side of the bonded silicon photoelectric conversion substrate 10 is thinned and polished; a system-level interconnect structure including a redistribution layer is fabricated on the surface. The silicon photoelectric conversion substrate 10 wafer integrates silicon waveguides, modulators, horizontal interconnects 16, and vertical through-silicon vias 105. Electrical functional chips 20, silicon photoelectric chips 40, and VCSEL laser chips 30 are flip-chip integrated onto the silicon photoelectric conversion substrate wafer 10 via aluminum nitride bonding layers 19 and in-situ grown metal microbumps 60. Light emitted from the VCSEL laser chip 30 is coupled vertically downwards through an opening at the center of a ring electrode into a grating coupler and silicon waveguide within a transition plate. All high-speed electrical signals are transmitted via the metal microbumps 60 and the interconnect network within the silicon photoelectric conversion substrate 10 wafer using the shortest path; system-level I / O is led out through solder balls on the back side of the transition plate.
[0048] In one embodiment, in step S3, an interconnecting adapter chip is also bonded to the gap region on the upper surface of the photonic integrated circuit substrate silicon photoelectric conversion substrate 10.
[0049] In one embodiment, in step S4, the in-situ self-grown metal interconnect process is chemical plating or electroplating, which uses a mask or the bonding layer as an insulating mask to achieve selective growth of metal in the gap. The self-grown metal includes copper, aluminum, tungsten, titanium, cobalt, molybdenum, tin and their alloys, and the process is carried out at a solution temperature of 40°C to 80°C.
[0050] In one embodiment, in step S4, the interconnect adapter chip is bonded together with the functional chip to the photonic integrated circuit substrate silicon photoelectric conversion substrate 10 through the bonding layer with its lower surface facing down; the metal is also selectively grown in the gap between the bottom interconnect pad 15 of the interconnect adapter chip and the corresponding interconnect pad of the photonic integrated circuit substrate silicon photoelectric conversion substrate 10 to form micro metal bumps.
[0051] In one embodiment, such as Figure 3 As shown, after step S4, the method further includes the following steps: thinning and polishing the back side of the bonded functional chip so that it is coplanar with other structures on the upper surface of the silicon photoelectric conversion substrate 10; and fabricating a system-level interconnect structure containing a redistribution layer on the eutectic surface formed after thinning and polishing.
[0052] In another embodiment, the method for forming a silicon photoelectric conversion substrate includes: We provide PIC (Photonic Integrated Circuit) chips, through-silicon via (TSV) chips, and carrier wafers. The PIC chips are SOI substrates, and the TSV chips include TSV arrays. The electrode pads of the PIC core and the through-silicon via core are bonded to the substrate, and the surfaces and gaps of the PIC core and the through-silicon via core are filled with insulating medium. The electrode pads of the PIC chip and through-silicon via chip are unbonded and exposed, and the exposed electrode pads serve as the first interconnect pad 13 and the second interconnect pad 14.
[0053] The PIC chip includes a silicon optoelectronics adapter board, which includes a silicon waveguide, a silicon-based optical modulator, and a grating coupler.
[0054] Accordingly, the present invention also provides a three-dimensional multi-core optoelectronic integrated structure obtained by a manufacturing method thereof, comprising: The silicon photoelectric conversion substrate 10 integrates a silicon waveguide inside. A first interconnect pad 13 and a second interconnect pad 14 are formed on its upper surface, and a bottom interconnect pad 15 is formed on its lower surface. It has a plurality of silicon vias 105 that electrically connect the first interconnect pad and the bottom interconnect pad 15 and electrically connect the second interconnect pad 14 and the bottom interconnect pad 15. It also has horizontal interconnect lines 16 that electrically interconnect the first interconnect pad 13 and the second interconnect pad 14. The electrical functional chip 20 and the silicon photonic chip 40 are directly bonded to the first region of the upper surface of the silicon photoelectric conversion substrate 10 through the bonding layer 19 with their active surfaces facing down. The laser chip 30 is directly bonded to the second region of the upper surface of the silicon photoelectric conversion substrate 10 via the bonding layer 19 with its active surface facing down. In this process, in-situ self-grown micro-metal bumps 60 are formed between the active surface electrodes of the electrical functional chip 20 and the silicon photonic chip 40 and the corresponding first interconnect pads 13 of the silicon photoelectric conversion substrate 10, and between the active surface electrode of the laser chip 30 and the corresponding second interconnect pads 14 of the silicon photoelectric conversion substrate 10, to achieve vertical electrical interconnection.
[0055] In one embodiment, the bonding layer 19 is aluminum nitride or high-density silicon oxide.
[0056] In one embodiment, the silicon photoelectric conversion substrate 10 is an SOI silicon wafer.
[0057] In one embodiment, such as Figure 2 As shown, it also includes a silicon beam deflector 50 bonded to the upper surface of the silicon photoelectric conversion substrate 1; the laser chip 30 is a horizontal cavity surface-emitting laser chip 30, such as an In / GaAs (indium gallium arsenide) horizontal laser, whose output port is deflected by the beam deflector and coupled to the silicon optical waveguide.
[0058] In one embodiment, such as Figure 3 As shown, the laser chip 30 is a VCSEL (Vertical-Cavity Surface-Emitting Laser) chip, and its output port is optically coupled to the silicon waveguide through an optical coupling structure on the silicon photoelectric conversion substrate 10. The VCSEL chip is inverted bonded, with its front annular electrode connected through the micro-metal bump 60, and its back electrode interconnected with the silicon photoelectric conversion substrate 10 through a through-silicon via 105.
[0059] In one embodiment, the thickness of the interconnecting adapter core is matched with the thickness of the functional core after bonding, so that their upper surfaces are coplanar.
[0060] Since aluminum nitride is a transparent material and has excellent thermal conductivity, the insulating dielectric layer, filling layer, passivation layer and bonding layer in this invention are preferably made of aluminum nitride, which can fully meet the requirements of CPO devices for light transmission and heat dissipation performance.
[0061] In one embodiment, the gaps between the functional chips, the gaps between the functional chips and the upper surface of the silicon photoelectric conversion substrate, and the surface of the functional chips are filled with an insulating dielectric layer, the insulating dielectric layer being made of aluminum nitride. Many modifications and other embodiments of the invention set forth herein will occur to those skilled in the art, taking advantage of the teachings presented in the foregoing description and the accompanying drawings. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, such specific terminology is used only in a general and descriptive sense and is not intended to be limiting.
Claims
1. A method for fabricating a three-dimensional multi-core optoelectronic integrated structure based on silicon optoelectronic conversion substrate interconnection, characterized in that, Including the following steps: S1: Provides a silicon photoelectric conversion substrate, which integrates a silicon optical waveguide. A first interconnect pad and a second interconnect pad are formed on its upper surface, and a bottom interconnect pad is formed on its lower surface. It has several through-silicon vias that electrically connect the first interconnect pad and the bottom interconnect pad, and electrically connect the second interconnect pad and the bottom interconnect pad. It also has horizontal interconnect lines that electrically interconnect the first interconnect pad and the second interconnect pad. S2: Provide functional chips that include at least: electrical functional chips, silicon photonic chips and laser chips; S3: The electrical functional chip, the silicon photonic chip, and the laser chip are aligned and bonded to the upper surface of the silicon photoelectric conversion substrate with their active surfaces facing down through the bonding layer, so that a gap is formed between each electrode and the corresponding pad. S4: Perform in-situ self-growing interconnect process to selectively grow metal in the gap to form micro-metal bumps and achieve electrical connection.
2. The preparation method according to claim 1, characterized in that, Step S3 includes: A non-conductive bonding layer is formed on the upper surface of the silicon photoelectric conversion substrate and / or the active surface of the functional chip. The functional chip is aligned and pressed onto the upper surface of the silicon photoelectric conversion substrate with its active surface facing down through the bonding layer, and the bonding layer is cured at a temperature below 250°C to form a mechanical bond; wherein the electrode of the functional chip is separated from the corresponding interconnect pad of the silicon photoelectric conversion substrate by the bonding layer.
3. The preparation method according to claim 1, characterized in that, In step S3, an interconnecting adapter chip is also bonded to the gap region on the upper surface of the silicon photoelectric conversion substrate.
4. The preparation method according to claim 2, characterized in that, In step S3, the bonding layer is made of aluminum nitride or high-density silicon oxide, and is formed by spin-coating a sol-gel precursor and then heat-curing it.
5. The preparation method according to claim 2, characterized in that, In step S4, the in-situ self-grown metal interconnect process is chemical plating or electroplating. By using a mask or the bonding layer as an insulating mask, selective growth of metal in the gap is achieved. The self-grown metals include copper, aluminum, tungsten, titanium, cobalt, molybdenum, tin and their alloys. The process is carried out at a solution temperature of 40°C to 80°C.
6. The preparation method according to claim 3, characterized in that, In step S4, the interconnecting adapter chip is bonded to the silicon photoelectric conversion substrate together with the functional chip through the bonding layer with its lower surface facing down; The metal is selectively grown in the gap between the bottom interconnect pad of the interconnect adapter chip and the corresponding interconnect pad of the silicon photoelectric conversion substrate to form micro metal bumps.
7. The preparation method according to claim 3, characterized in that, Following step S4, the following steps are also included: The back side of the bonded functional chip is thinned and polished to make it coplanar with other structures on the upper surface of the silicon photoelectric conversion substrate; Fabricate system-level interconnect structures containing redistribution layers on coplanar surfaces.
8. The preparation method according to claim 2, characterized in that, Following step S4, the following steps are also included: The back side of the bonded silicon photoelectric conversion substrate is thinned and polished; Fabricate system-level interconnect structures containing rewiring layers on the surface.
9. The preparation method according to claim 2, characterized in that, Methods for forming silicon photoelectric conversion substrates include: It provides PIC cores, through-silicon via cores and carriers. The PIC cores are SOI substrates and the through-silicon via cores include through-silicon via arrays. The electrode pads of the PIC core and the through-silicon via core are bonded to the substrate, and the surfaces and gaps of the PIC core and the through-silicon via core are filled with insulating medium. The electrode pads of the exposed PIC chip and through-silicon via chip are unbonded and used as the first interconnect pad and the second interconnect pad.
10. The preparation method according to claim 9, characterized in that, Also includes: The PIC chip includes a silicon optoelectronics adapter board, which includes silicon optical waveguides, silicon-based optical modulators, and grating couplers.
11. The preparation method according to claim 2, characterized in that, A method for forming a silicon photoelectric conversion substrate includes: providing an SOI silicon wafer; forming a PIC chip therein, including a silicon photoelectric adapter board, which includes a silicon optical waveguide, a silicon-based optical modulator, and a grating coupler; and forming through-silicon vias in non-transparent areas.
12. A three-dimensional multi-core optoelectronic integrated structure obtained by any one of the preparation methods according to claims 1-11, characterized in that, include: A silicon photoelectric conversion substrate integrates a silicon waveguide, with a first interconnect pad and a second interconnect pad formed on its upper surface and a bottom interconnect pad formed on its lower surface. It has several through-silicon vias that electrically connect the first interconnect pad and the bottom interconnect pad, and electrically connect the second interconnect pad and the bottom interconnect pad. It also has horizontal interconnect lines that electrically interconnect the first interconnect pad and the second interconnect pad. The electrical functional chip and the silicon photonic chip are directly bonded to the first region on the upper surface of the silicon photoelectric conversion substrate through a bonding layer with their active surfaces facing down. The laser chip is directly bonded to the second region on the upper surface of the silicon photoelectric conversion substrate with its active surface facing down via a bonding layer; In this process, in-situ self-grown micro-metal bumps are formed between the active surface electrodes of the electrical functional chip and the silicon photonic chip and the corresponding first interconnect pads of the silicon photoelectric conversion substrate, and between the active surface electrodes of the laser chip and the corresponding second interconnect pads of the silicon photoelectric conversion substrate, to achieve vertical electrical interconnection.
13. The three-dimensional multi-core optoelectronic integrated structure according to claim 12, characterized in that, The bonding layer is aluminum nitride or high-density silicon oxide.
14. The three-dimensional multi-core optoelectronic integrated structure according to claim 12, characterized in that, The silicon photoelectric conversion substrate is an SOI silicon wafer.
15. The three-dimensional multi-core optoelectronic integrated structure according to claim 12, characterized in that, The laser chip is a vertical cavity surface-emitting laser chip, and its output port is optically coupled to the silicon waveguide through an optical coupling structure on the silicon photoelectric conversion substrate.
16. The three-dimensional multi-core optoelectronic integrated structure according to claim 12, characterized in that, The vertical cavity surface-emitting laser chip is inverted bonded, with its front annular electrode connected through the micro-metal bump, and its back electrode interconnected with the silicon photoelectric conversion substrate through through-silicon vias.
17. The three-dimensional multi-core optoelectronic integrated structure according to claim 12, characterized in that, It also includes a silicon beam deflector bonded to the surface of the silicon photoelectric conversion substrate; the laser chip is a horizontal cavity surface-emitting laser chip, and its output port is deflected by the beam deflector and coupled to the silicon optical waveguide.
18. The three-dimensional multi-core optoelectronic integrated structure according to claim 12, characterized in that, The silicon photonics core integrates a photodetector core.
19. The three-dimensional multi-core optoelectronic integrated structure according to claim 12, characterized in that, The gaps between the functional cores, the gaps between the functional cores and the silicon photoelectric conversion substrate, and the surface of the functional cores are filled with an insulating dielectric layer, the material of which is aluminum nitride.