Three-dimensional multi-core particle optoelectronic integrated structure based on self-grown micro-bumps and preparation method thereof

Abstract

The application discloses a three-dimensional multi-core particle optoelectronic integrated structure based on self-growth micro-bumps and a preparation method thereof. The structure comprises: a photonic integrated circuit substrate, an upper surface of which is formed with an electrode pad; a plurality of functional core particles, including at least one electronic integrated control core particle and at least one laser core particle, the plurality of functional core particles being directly bonded to different regions of the upper surface of the photonic integrated circuit substrate in a manner that the active surfaces thereof face downwards through a bonding layer; an interconnection transfer core particle, a lower surface of which is directly bonded to the upper surface of the photonic integrated circuit substrate through the bonding layer and located in a gap region between the plurality of functional core particles; and a through silicon via array arranged in the interconnection transfer core particle. The application realizes high-density, low-loss, low-temperature and optical path compatible heterogeneous three-dimensional integration, and significantly improves the performance, reliability and expansibility of an optoelectronic integrated system.

Description

Technical Field

[0001] This invention relates to the fields of ultra-large-scale integrated circuits, semiconductor optoelectronic integration and advanced packaging technology, and in particular to a three-dimensional multi-core optoelectronic integrated structure based on self-grown microbumps and its fabrication method. Background Technology

[0002] With the explosive growth in computing bandwidth demands for AI training and inference, the tight integration of high-performance computing units such as GPUs (Graphics Processing Units) with optical interconnect engines (i.e., Co-Packaging) has become an inevitable trend. Existing Co-Packaging solutions, especially those involving 2.5D integration, typically face the following challenges: 1. When optical signals are coupled from external optical fibers to photonic integrated circuits (PICs) within the package, additional, bulky silicon carriers or interposers are often required to fix and calibrate the fiber array, increasing packaging complexity and vertical space occupation. 2. System-level electrical inputs / outputs (I / O) typically require a separate interposer layer or complex rerouting layer to achieve fan-out, increasing interconnect length and design complexity; 3. There is still room for optimization in the integration of the electronic control chip (EIC), driver chip (DRV), receiver chip (TIA), and PIC in order to achieve lower signal delay and higher integration density.

[0003] Therefore, there is an urgent need for a CPO solution that can simplify the optical coupling structure, shorten the electrical interconnect path, and achieve higher integration density. Summary of the Invention

[0004] This invention aims to overcome the shortcomings of existing technologies and provide a high-density, high-performance, and process-compatible three-dimensional multi-core optoelectronic integrated structure and its fabrication method. Its core lies in using "in-situ self-grown micro-metal bumps" to achieve vertical electrical interconnection between functional cores and photonic substrates, and introducing "interconnection transition cores" as intermediaries to construct a three-dimensional interconnect framework.

[0005] To achieve the above objectives, the first aspect of the present invention provides a three-dimensional multi-core optoelectronic integrated structure based on self-grown microbumps, comprising: A photonic integrated circuit substrate, on the upper surface of which electrode pads are formed; Multiple functional chips, including at least one electronic integrated control chip and at least one laser chip, are directly bonded to different regions on the upper surface of the photonic integrated circuit substrate via a bonding layer with their active surfaces facing down. The interconnecting adapter chip is directly bonded to the upper surface of the photonic integrated circuit substrate via a bonding layer, and is located in the gap region between the multiple functional chips; the interconnecting adapter chip has a through-silicon via array inside; The interconnect adapter chip has a top interconnect pad on its upper surface and a bottom interconnect pad on its lower surface. The through-silicon via array electrically connects the top interconnect pad and the bottom interconnect pad. In this process, in-situ self-grown micro-metal bumps are formed between the active surface electrode of each functional chip and the corresponding electrode pad of the photonic integrated circuit substrate, and between the bottom interconnect pad of the interconnect transition chip and the corresponding electrode pad of the photonic integrated circuit substrate, to achieve vertical electrical interconnection between the functional chip, the interconnect transition chip and the photonic integrated circuit substrate.

[0006] Furthermore, the bonding layer is aluminum nitride.

[0007] Furthermore, it also includes a system-level interconnect layer located on the back of the functional core, comprising an insulating layer and a metal redistribution layer stacked sequentially.

[0008] Furthermore, the insulating layer is aluminum nitride.

[0009] Furthermore, the photonic integrated circuit substrate is an SOI substrate.

[0010] Furthermore, the photonic integrated circuit substrate integrates an optical waveguide and an optical modulator; the laser chip is a vertical cavity surface-emitting laser chip, and its output port is optically coupled to the optical waveguide through an optical coupling structure on the photonic integrated circuit substrate.

[0011] Furthermore, the vertical cavity surface-emitting laser chip is upside down on the upper surface of the photonic integrated circuit substrate, and the front side of the vertical cavity surface-emitting laser chip has an annular electrode pad. An in-situ self-grown micro-metal bump is formed between the annular electrode pad and the electrode pad on the upper surface of the photonic integrated circuit substrate. The back side of the vertical cavity surface-emitting laser chip has a bottom electrode, the exposed surface of which faces the upper surface of the photonic integrated circuit substrate and is interconnected with the electrode pads on the upper surface of the photonic integrated circuit substrate through through-silicon vias.

[0012] Furthermore, it also includes a silicon-based beam deflector bonded to the upper surface of a photonic integrated circuit substrate, wherein an optical waveguide and an optical modulator are integrated within the photonic integrated circuit substrate; the laser chip is a horizontal cavity surface-emitting laser chip, with its output port facing the silicon-based beam deflector, and the silicon-based beam deflector directs the beam to an optical coupling structure on the photonic integrated circuit substrate for optical coupling with the optical waveguide.

[0013] A method for fabricating a three-dimensional multi-core optoelectronic integrated structure as described above includes the following steps: S1: Provides a photonic integrated circuit substrate, on which electrode pads are formed on the upper surface; S2: Provides multiple functional chips and interconnect transition chips; the active surface of the functional chips has electrodes, and the interconnect transition chips have a through-silicon via array and interconnect pads on the upper and lower surfaces; S3: The plurality of functional chips and the interconnect transition chips are aligned and bonded to predetermined positions on the upper surface of the photonic integrated circuit substrate with their active surfaces or lower surfaces facing down via a bonding layer; wherein, there are gaps between the electrodes of the functional chips and the electrode pads of the photonic integrated circuit substrate, and between the bottom interconnect pads of the interconnect transition chips and the corresponding pads of the photonic integrated circuit substrate; S4: Perform in-situ self-grown interconnect process, selectively grow metal in the gap between the electrode of the functional chip and the electrode pad of the photonic integrated circuit substrate, and in the gap between the bottom interconnect pad of the interconnect transition chip and the electrode pad of the photonic integrated circuit substrate, to form micro metal bumps and realize the electrical connection between the two.

[0014] Furthermore, the steps include: S5: A system-level interconnect layer is formed on the back side of the plurality of functional cores and on the upper surface of the interconnect adapter core; S6: System input / output pads are formed on the system-level interconnect layer.

[0015] Furthermore, the in-situ self-grown micro-metal bumps are formed in situ in the gap between the electrodes of the functional core and the photonic integrated circuit substrate after the functional core is bonded to the substrate by chemical plating, electroplating or gas plating processes.

[0016] Furthermore, the plurality of functional chips include at least one CMOS master control chip and one PIC chip, and also include a silicon-based beam deflector bonded to the upper surface of the photonic integrated circuit substrate. The photonic integrated circuit substrate integrates an optical waveguide and an optical modulator. The laser chip is a horizontal cavity surface-emitting laser chip, and its light outlet faces the silicon-based beam deflector. The silicon-based beam deflector directs the light beam to an optical coupling structure on the photonic integrated circuit substrate and optically couples it with the optical waveguide.

[0017] The beneficial effects of this invention are: 1. High-density interconnect: The size of the in-situ self-grown micro-metal bumps is controllable, which can achieve an interconnect density far exceeding that of traditional solder balls, meeting the requirements of high-speed electrical signal transmission.

[0018] 2. Low loss and optical compatibility: The self-grown bumps are formed after bonding, with precise positioning and their morphology can be controlled through the process, effectively reducing the obstruction or light scattering disturbance of the metal structure on adjacent optical paths (especially VCSEL flip-chip structures).

[0019] 3. Low-temperature process: The entire integration process mainly uses low-temperature bonding and growth processes to avoid thermal damage to the performance of the prepared lasers, modulators and other optoelectronic devices caused by high temperatures.

[0020] 4. Strong three-dimensional scalability: The "embedded" layout and coplanar design of interconnect adapter cores and functional cores provide perfect support for building multi-layer interconnects (rewiring layers) in the vertical direction, making it easier to achieve more complex system-level integration and heterogeneous integration.

[0021] 5. High flexibility: This structure is compatible with the integration of various light sources such as VCSELs (vertical cavity surface-emitting lasers) and edge-emitting lasers, and has wide applicability. Attached Figure Description

[0022] Figure 1 This is a cross-sectional schematic diagram of a three-dimensional multi-core optoelectronic integrated structure based on VCSEL according to an embodiment of the present invention.

[0023] Figure 2 This is a cross-sectional schematic diagram of a three-dimensional multi-core optoelectronic integrated structure based on a side-emitting laser and a beam deflector provided in an embodiment of the present invention.

[0024] Figure 3 This is a flowchart of the main steps of the preparation method of the present invention.

[0025] Icon labels: Photonic integrated circuit substrate 10; PIC silicon photonic chip assembly 11; mirror 12; grating 13; electrode pad 14; electronic integrated control chip 20; microelectrode 21; vertical cavity surface emission laser chip 30; P-type electrode 31; bottom electrode 32; bonding layer; interconnect adapter chip 50; through silicon via 51; bottom interconnect pad 52; top interconnect pad 53; micro metal bump 60. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention. Obviously, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0028] Example 1

[0029] Please see Figure 1 This embodiment provides a three-dimensional multi-core optoelectronic integrated structure based on VCSEL, including: Photonic integrated circuit substrate 10. In this embodiment, it is an SOI substrate, and a PIC silicon photonic chip assembly 11, including an optical waveguide, a modulator, and a detector, is integrated in the silicon device layer on top of it using semiconductor processes. It also includes a tilting mirror 12 for directing the reflection of horizontal waveguide light, or a grating 13 for vertical laser input for grating coupling and reflection coupling. On the upper surface of the substrate 10, electrode pads 14 made of aluminum or copper are fabricated, and the electrode pads 14 are divided into a first electrode pad and a second electrode pad.

[0030] In this embodiment, multiple functional chips include an electronic integrated control (EIC) chip 20 and a vertical-cavity surface-emitting laser (VCSEL) chip 30. The VCSEL chip is inverted and placed on the upper surface of the photonic integrated circuit substrate 10. The front side of the VCSEL chip has an annular electrode pad, and an in-situ self-grown micro-metal bump 60 is formed between the annular electrode pad and the electrode pad on the upper surface of the photonic integrated circuit substrate. The back side of the VCSEL chip has a bottom electrode 32, the exposed surface of which faces the upper surface of the photonic integrated circuit substrate 10, and is interconnected with the electrode pad 14 on the surface of the photonic integrated circuit substrate 10 through a through-silicon via 51.

[0031] The electronic integrated control chip 20 and the vertical-cavity surface-emitting laser chip 30, as functional chips, are both bonded directly to the upper surface of the photonic integrated circuit substrate 10 with their active surfaces facing down via a bonding layer 41. In this embodiment, the bonding layer 41 is aluminum nitride with a thickness of approximately 500 nm. The active surface of the electronic integrated control chip 20 contains CMOS logic circuitry, serving as a CMOS main control chip, and has multiple copper microelectrodes 21 on its bottom. The active surface of the vertical-cavity surface-emitting laser chip 30 contains an InGaAs (indium gallium arsenide) multi-quantum-well light-emitting structure, with a ring-shaped P-type electrode 31 on its front side and a bottom electrode 32 on its back side. After bonding, the microelectrodes 21 are aligned with the first electrode pad, and the P-type electrode 31 is aligned with the second electrode pad.

[0032] Interconnect adapter chip 50. In this embodiment, it is preferably a high-resistivity silicon substrate with a dense array of through-silicon vias (TSVs) 51 inside, filled with electroplated copper. The lower surface of the interconnect adapter chip 50 has copper bottom interconnect pads 52, and the upper surface has copper top interconnect pads 53, which are electrically connected by the TSVs 51. The interconnect adapter chip 50 is bonded to the photonic integrated circuit substrate 10 via a bonding layer 41 and is precisely located in the gap between the electronic integrated control chip 20 and the vertical-cavity surface-emitting laser chip 30. Its thickness is designed so that after bonding, its upper surface is substantially coplanar with the back surfaces of the two functional chips.

[0033] In another embodiment, the photonic integrated circuit substrate 10 is also bonded with a photodetector, such as a Ge / InGaAs (germanium gallium arsenide) photodetector, in the same manner as described above, and an interconnection adapter chip 50 is also bonded in the gap between the EIC chip and the photodetector chip.

[0034] In-situ self-grown micro-metallic bumps 60, such as Figure 1 As shown, micro-metallic bumps 60 made of pure copper are filled between the microelectrode 21 of the EIC chip and the first electrode pad of the photonic substrate 10, and between the P-type electrode 31 of the VCSEL chip and the second electrode pad. These bumps are grown in situ using a chemical plating process after bonding, and their shape matches the gap cavity, completely connecting the upper and lower electrodes. Typical dimensions of the bumps 60 are: height 200 nm-1 μm, diameter 1-5 μm.

[0035] Optionally, a system-level interconnect layer located on the back of the functional chip may also be included, comprising an insulating layer and a metal redistribution layer stacked sequentially. Alternatively, a system-level interconnect layer may also be included. This layer covers the back of the EIC chip, the VCSEL chip, and the top surface of the interconnect adapter chip 50. This layer comprises a 5μm thick aluminum nitride layer and a copper redistribution layer fabricated thereon. The redistribution layer is connected to the back electrode of the EIC chip, the back electrode of the VCSEL chip, and the top copper pad 53 of the interconnect adapter chip 50 via copper plugs located in the aluminum nitride, thereby enabling system-level power, ground, and low-speed signal distribution.

[0036] In one embodiment, both the junction insulation and the dielectric layer in the above structure are made of aluminum nitride. Aluminum nitride has excellent insulation and thermal conductivity, and is compatible with semiconductor processes, thereby increasing the heat dissipation of the entire structure.

[0037] The working mechanism of this structure is as follows: The vertical-cavity surface-emitting laser (VCSEL) chip 30, driven by the electronically integrated control chip 20, emits a vertically downward laser beam. The laser beam passes through the transparent region inside its annular P-type electrode 31, enters the photonic integrated circuit substrate 10, and is coupled into the optical waveguide by the grating 13 therein. The modulator performs high-speed modulation of the light in the optical waveguide. The modulated optical signal can be output (e.g., coupled into an optical fiber). All high-speed electrical signals are transmitted between the EIC chip, the VCSEL chip, and the photonic modulator via an ultra-short path (micro-metal bumps 60). The power, ground, and control signals required by the system can be efficiently distributed to the various functional chips via the TSV channels of the interconnect adapter chip 50, located on top of the interconnect adapter chip 50, through the back-side system interconnect.

[0038] Example 2

[0039] Please see Figure 2 This embodiment provides a three-dimensional multi-core optoelectronic integrated structure based on a side-emitting laser and a beam deflector. It includes: Photonic integrated circuit substrate: An SOI (silicon-on-insulator) substrate is used, which integrates a silicon optical waveguide network (including single-mode waveguides, multimode interference couplers, etc.) and silicon-based optical modulators (such as carrier depletion Mach-Zehnder interferometers and MZI modulators). A fine pattern of copper electrode pads (minimum feature size 5 μm) is fabricated on the substrate surface for electrical interconnection, as well as a grating coupler array (630 nm period, 50% duty cycle) for vertical optical input / output.

[0040] Functional chips include CMOS master control chips: manufactured using 40nm or more advanced process nodes, approximately 3mm x 3mm in size, with an active surface containing numerous aluminum I / O pads. This chip is responsible for driving the laser, controlling the optical modulator, and processing detector signals. Horizontal cavity surface-emitting laser (HCSEL) chips: using InP (indium phosphide) or GaAs (gallium arsenide) material systems, with emission wavelengths such as 1310nm or 1550nm. This functional chip is bonded with its active surface facing down. Its key feature is that the light-emitting port is located on the side of the chip, and after bonding, the light-emitting port remains horizontally aligned with the photonic substrate surface. The electrodes on its active surface (typically P-type and N-type contact pads) are used to receive high-voltage pulse drive signals.

[0041] Silicon-based beam deflector: This is a freestanding single-crystal silicon microstructure with a height of approximately 200-300 μm. Its core feature is a precisely machined 54.7° reflective bevel, obtained, for example, through anisotropic etching of the silicon crystal surface. A highly reflective metal film, such as gold or aluminum, is deposited on the surface of this bevel. This beam deflector is fixed to a predetermined position on the upper surface of the photonic integrated circuit substrate via a bonding layer, such as aluminum nitride, precisely in front of the optical path of the HCSEL chip's light exit port.

[0042] Interconnect chip 50: Made of high-resistivity silicon, approximately 150 μm thick, with an integrated array of copper-filled through-silicon vias 51. Top interconnect pads 53 and bottom interconnect pads 52 are formed on its upper and lower surfaces, respectively. Its thickness is designed so that, after bonding, its upper surface is substantially coplanar with the back surface of the CMOS main control chip and detector assembly chip. This chip is bonded to the gap region between other functional chips.

[0043] Micro-metal bumps 60: In-situ self-grown micro-metal bumps 60, such as columnar copper bumps, are formed between the aluminum electrodes of the CMOS chip, the electrodes of the detector chip and the corresponding copper pads of the photonic substrate, and between the bottom copper pads of the interconnect chip and the corresponding copper pads of the photonic substrate. These bumps are approximately 1-2 μm high and 5-10 μm in diameter. After low-temperature bonding, these bumps are selectively grown in the electrode gaps through chemical plating or electroplating processes, achieving high-density, low-parasitic vertical electrical interconnects between all chips and the photonic substrate.

[0044] Optionally, a system-level interconnect layer may also be included: a system-level interconnect consisting of a SiO2 (silicon dioxide) dielectric layer and a copper redistribution layer is sequentially constructed on the back side of the coplanar functional core and the upper surface of the interconnect transition core 50. The outermost layer forms a solder ball array as system I / O.

[0045] In this embodiment, after the integrated structure is powered on, the generated laser beam is emitted horizontally from its side exit port. This horizontal beam travels approximately 10-50 μm in the air before incident on the 54.7° reflecting slope of the silicon-based beam deflector. Due to the incident angle of 54.7°, according to the law of reflection, the beam is precisely deflected by 90°, becoming vertically downward propagating. The vertically downward beam then precisely incidents on the grating coupler integrated on the surface of the photonic integrated circuit substrate 10. The grating coupler efficiently couples the vertically incident light into the horizontally propagating silicon optical waveguide inside the substrate, thus completing the optical coupling from the edge-emitting laser to the planar optical waveguide. This approach avoids directly fabricating complex micro-optical structures on the laser chip, simplifies laser manufacturing processes, and achieves efficient and stable optical coupling.

[0046] Accordingly, the present invention also provides a method for a three-dimensional multi-core optoelectronic integrated structure, as shown in the attached figure. Figure 3 The preparation method is illustrated with a flowchart.

[0047] Step S1: Provide a photonic integrated circuit substrate 10, on which electrode pads 14 are formed.

[0048] An SOI wafer is provided as the photonic substrate wafer 10. All photonic devices, such as PIC silicon photonic chip components, mirrors 12, and gratings 13, are fabricated on the wafer. Subsequently, electrode pads 14, including a first electrode pad and a second electrode pad, are deposited and photolithographically formed on the surface of the device region. Finally, an aluminum nitride layer approximately 500 nm thick is spin-coated across the entire wafer surface as the material for the first bonding layer 41 and the second bonding layer 42.

[0049] Step S2: Provide multiple functional chips and interconnect transition chips 50; the active surface of the functional chips has electrodes, and the interconnect transition chips 50 have an array of through silicon vias 51 and interconnect pads on the upper and lower surfaces.

[0050] EIC wafers, VCSEL wafers, and interconnect wafers containing TSV arrays 51 are fabricated on separate production lines. The EIC and VCSEL wafers are thinned to expose the back electrodes on the back side, and then diced to obtain individual EIC and VCSEL cores. The interconnect wafers are thinned to a target thickness, such as 100 μm, and then diced.

[0051] Step S3: Align and bond the plurality of functional chips and the interconnect transition chips to predetermined positions on the upper surface of the photonic integrated circuit substrate 10 with their active surfaces or lower surfaces facing down via the bonding layer 41; wherein, there are gaps between the electrodes of the functional chips and the electrode pads 14 of the photonic integrated circuit substrate, and between the bottom interconnect pads of the interconnect transition chips 50 and the corresponding pads of the photonic integrated circuit substrate.

[0052] Using a high-precision flip-chip bonding machine, interconnect adapter cores 50, EIC cores, and VCSEL cores are sequentially picked up and transferred to predetermined positions on the photonic substrate wafer. Bonding is performed in the bonding machine by applying specific pressure and appropriate temperature to the cores.

[0053] Step S4: Perform in-situ self-grown interconnect process, selectively grow metal in the gap between the electrode of the functional chip and the electrode pad 14 of the photonic integrated circuit substrate, and in the gap between the bottom interconnect pad 52 of the interconnect transition chip 50 and the electrode pad 14 of the photonic integrated circuit substrate, to form micro metal bumps and realize the electrical connection between the two.

[0054] The electrodes of the functional chip and the pads of the photonic substrate typically have exposed copper or gold. These metals are catalytically active for electroless copper plating. On the catalytically active surfaces, copper ions in the solution are reduced to metallic copper and deposited. Deposition begins on the upper and lower electrode surfaces and grows into the gap. Due to the narrow gap, solution exchange is limited, but metal ions can be continuously supplied through diffusion. After approximately 30-60 minutes, the copper grown on the upper and lower electrode surfaces meets and merges at the center of the gap, forming a solid, completely gap-filling copper micro-bump 60. This process is performed at a low temperature, such as 60°C, with minimal thermal impact on the device. The grown bump perfectly conforms to the gap shape, achieving ultra-high density truly conformal interconnects and exhibiting strong adaptability to minute height differences after bonding.

[0055] Preferably, it may also include: back-side system-level interconnect and packaging.

[0056] The beneficial effects of the present invention are fully demonstrated in this embodiment: The micro-copper bump interconnect, which is bonded first and then grown, achieves submicron pitch, low resistance, and high reliability vertical interconnect, breaking through the density limit of traditional bump technology.

[0057] 1. The core interconnect process is completed below 60°C, and the temporary bonding temperature is only 150°C, which protects the heterogeneous material device to the greatest extent.

[0058] 2. EIC, VCSEL, PIC and TSV adapter chips are tightly integrated in three-dimensional space, resulting in extremely short signal paths and a significant reduction in system size.

[0059] 4. The process flow is clear, with most steps completed at the wafer level. It has good compatibility with existing packaging production lines and has the potential for large-scale mass production.

[0060] Benefiting from the teachings presented in the foregoing description and the accompanying drawings, those skilled in the art will conceive of many modifications and other embodiments of the invention set forth herein. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in a general and descriptive sense and is not intended to be limiting.

Claims

1. A three-dimensional multi-core optoelectronic integrated structure based on self-grown microbumps, characterized in that, include: A photonic integrated circuit substrate, on the upper surface of which electrode pads are formed; Multiple functional chips, including at least one electronic integrated control chip and at least one laser chip, are directly bonded to different regions on the upper surface of the photonic integrated circuit substrate via a bonding layer with their active surfaces facing down. The interconnecting adapter chip is directly bonded to the upper surface of the photonic integrated circuit substrate via a bonding layer, and is located in the gap region between the multiple functional chips; the interconnecting adapter chip has a through-silicon via array inside; The interconnect adapter chip has a top interconnect pad on its upper surface and a bottom interconnect pad on its lower surface. The through-silicon via array electrically connects the top interconnect pad and the bottom interconnect pad. In this process, in-situ self-grown micro-metal bumps are formed between the active surface electrode of each functional chip and the corresponding electrode pad of the photonic integrated circuit substrate, and between the bottom interconnect pad of the interconnect transition chip and the corresponding electrode pad of the photonic integrated circuit substrate, to achieve vertical electrical interconnection between the functional chip, the interconnect transition chip and the photonic integrated circuit substrate.

2. The three-dimensional multi-core optoelectronic integrated structure according to claim 1, characterized in that, The bonding layer is aluminum nitride.

3. The three-dimensional multi-core optoelectronic integrated structure according to claim 1, characterized in that, It also includes a system-level interconnect layer located on the back of the functional core, comprising an insulating layer and a metal redistribution layer stacked sequentially.

4. The three-dimensional multi-core optoelectronic integrated structure according to claim 3, characterized in that, The insulating layer is aluminum nitride.

5. The three-dimensional multi-core optoelectronic integrated structure according to claim 1, characterized in that, The photonic integrated circuit substrate is an SOI substrate.

6. The three-dimensional multi-core optoelectronic integrated structure according to claim 1, characterized in that, The photonic integrated circuit substrate integrates an optical waveguide and an optical modulator; the laser chip is a vertical cavity surface-emitting laser chip, and its light outlet is optically coupled to the optical waveguide through an optical coupling structure on the photonic integrated circuit substrate.

7. In the three-dimensional multi-core optoelectronic integrated structure according to claim 6, the vertical cavity surface-emitting laser core is upside down on the upper surface of the photonic integrated circuit substrate, the front side of the vertical cavity surface-emitting laser core has an annular electrode pad, and an in-situ self-grown micro-metal bump is formed between the annular electrode pad and the electrode pad on the upper surface of the photonic integrated circuit substrate. The back side of the vertical cavity surface-emitting laser chip has a bottom electrode, the exposed surface of which faces the upper surface of the photonic integrated circuit substrate and is interconnected with the electrode pads on the upper surface of the photonic integrated circuit substrate through through-silicon vias.

8. The three-dimensional multi-core optoelectronic integrated structure according to claim 1, characterized in that, It also includes a silicon-based beam deflector bonded to the surface of a photonic integrated circuit substrate, wherein an optical waveguide and an optical modulator are integrated within the photonic integrated circuit substrate; the laser chip is a horizontal cavity surface-emitting laser chip, with its output port facing the silicon-based beam deflector, and the silicon-based beam deflector directs the beam to an optical coupling structure on the photonic integrated circuit substrate for optical coupling with the optical waveguide.

9. A method for preparing a three-dimensional multi-core optoelectronic integrated structure as described in any one of claims 1 to 8, characterized in that, Including the following steps: S1: Provides a photonic integrated circuit substrate, on which electrode pads are formed on the upper surface; S2: Provides multiple functional chips and interconnect transition chips; the active surface of the functional chips has electrodes, and the interconnect transition chips have a through-silicon via array and interconnect pads on the upper and lower surfaces; S3: The plurality of functional chips and the interconnect transition chips are aligned and bonded to predetermined positions on the upper surface of the photonic integrated circuit substrate with their active surfaces or lower surfaces facing down via a bonding layer; wherein, there are gaps between the electrodes of the functional chips and the electrode pads of the photonic integrated circuit substrate, and between the bottom interconnect pads of the interconnect transition chips and the corresponding pads of the photonic integrated circuit substrate; S4: Perform in-situ self-grown interconnect process, selectively grow metal in the gap between the electrode of the functional chip and the electrode pad of the photonic integrated circuit substrate, and in the gap between the bottom interconnect pad of the interconnect transition chip and the electrode pad of the photonic integrated circuit substrate, to form micro metal bumps and realize the electrical connection between the two.

10. The method according to claim 9, characterized in that, It also includes the following steps: S5: A system-level interconnect layer is formed on the back side of the plurality of functional cores and on the upper surface of the interconnect adapter core; S6: System input / output pads are formed on the system-level interconnect layer.

11. The method according to claim 10, characterized in that, The in-situ self-grown micro-metal bumps are formed in situ in the gap between the electrodes of the functional core and the photonic integrated circuit substrate after the functional core is bonded to the substrate by chemical plating, electroplating or gas plating processes.

12. The method according to claim 9, characterized in that, The plurality of functional chips include at least one CMOS master control chip and one PIC chip, and also include a silicon beam deflector bonded to the upper surface of the photonic integrated circuit substrate. The photonic integrated circuit substrate integrates an optical waveguide and an optical modulator. The laser chip is a horizontal cavity surface emitter laser chip, and its light outlet faces the silicon beam deflector. The silicon beam deflector directs the light beam to an optical coupling structure on the photonic integrated circuit substrate and optically couples it with the optical waveguide.

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